CY24292LFXIT [CYPRESS]
Clock Generator, 100MHz, CMOS, QFN-32;
| 型号： | CY24292LFXIT |
| 厂家： | 
CYPRESS |
| 描述： | Clock Generator, 100MHz, CMOS, QFN-32 时钟 外围集成电路 晶体 |
| 文件： | 总20页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY24292
Four Outputs PCI-Express Clock Generator
Four Outputs PCI-Express Clock Generator
Features
Functional Description
■ 25 MHz Crystal or Clock Input
CY24292 is a clock generator device intended for PCI-Express
applications. The device includes: four 100 MHz differential
clocks with HCSL Compatible outputs for PCI-Express, and one
single-ended 25 MHz output.
■ Four Differential 100 MHz PCI-Express Clocks
■ Supports HCSL Compatible Output Levels
■ One Single-ended 25 MHz Output
Using a serially programmable SMBus interface, the CY24292
incorporates spread spectrum modulation on all four 100 MHz
■ Spread Spectrum Capability on all 100 MHz PCI-Express Clock
Outputs
outputs. The device incorporates a Lexmark Spread Spectrum
profile for maximum electromagnetic interference (EMI)
reduction. The spread feature or individual outputs can also be
disabled using the SMBus interface.
■ SMBus Interface with Read Back Capability
■ 32-pin QFN Package
For a complete list of related documentation, click here.
■ Operating Voltage 3.3 V
■ Commercial and Industrial Operating Temperature Range
Logic Block Diagram
VDD
PCIE0P
PCIE0N
(100 MHz)
(100 MHz)
XIN/EXCLKIN
Clock Buffer/
(25 MHz)
Crystal
Oscillator
XOUT
PCIE1P
PCIE1N
PLL Clock
Synthesizer,
Dividers, Buffers
and
PCIE2P
PCIE2N
(100 MHz)
(100 MHz)
SCLK
Configuration
Logic
PCIE3P
PCIE3N
SDATA
PD_RESET#
25M (25 MHz)
IREF
RREF = 475 Ohms 1%
GND
Cypress Semiconductor Corporation
Document Number: 001-46142 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 27, 2017
CY24292
Contents
Pin Configuration .............................................................3
Pin Definitions ..................................................................3
Functional Overview ........................................................4
SMBus Serial Data Interface .......................................4
Data Protocol ...............................................................4
Control Registers .........................................................6
Application Information ...................................................8
Crystal Recommendations ..........................................8
Crystal Loading ...........................................................8
Calculating Load Capacitors .......................................8
Current Source (Iref) Reference Resistor ....................8
Output Termination ......................................................8
PCB Layout Recommendations ..................................9
Decoupling Capacitors ................................................9
PCI-Express Layout Guidelines ......................................9
HCSL Compatible Layout Guidelines ..........................9
Absolute Maximum Ratings ..........................................10
Recommended Operation Conditions ..........................10
DC Electrical Characteristics ........................................11
Thermal Resistance ........................................................11
AC Electrical Characteristics ........................................12
Test and Measurement Setup ........................................14
Single-ended Signals ................................................14
Differential Signals ....................................................14
Ordering Information ......................................................15
Ordering Code Definitions .........................................15
Package Diagram ............................................................16
Acronyms ........................................................................17
Document Conventions .................................................17
Units of Measure .......................................................17
Document History Page .................................................18
Sales, Solutions, and Legal Information ......................20
Worldwide Sales and Design Support .......................20
Products ....................................................................20
PSoC® Solutions ......................................................20
Cypress Developer Community .................................20
Technical Support .....................................................20
Document Number: 001-46142 Rev. *G
Page 2 of 20
CY24292
Pin Configuration
Figure 1. 32-pin QFN Pinout CY24292
32
31
30
29
28
27
26
25
PCIE1P
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VDD
PCIE1N
GND
XOUT
XIN/EXCLKIN
CY24292
IREF
VDD
32 Pin QFN
PCIE2N
PD_RESET#
PCIE2P
GND
GND
VDD
GND
VDD
9
10
11
12
13
14
15
16
Pin Definitions
Pin Number
Pin Name
Pin Type
Description
1
PCIE1P
Output
Differential 100 MHz PCI-Express true clock output. High impedance when disabled.
Differential 100 MHz PCI-Express complementary clock output. High impedance when
disabled.
2
PCIE1N
Output
3
4
GND
IREF
Power
Output
Ground
Current set for all differential clock drivers. Connect 475 resistor to ground.
Differential 100 MHz PCI-Express complementary clock output. High impedance when
disabled.
5
PCIE2N
Output
6
7
8
PCIE2P
GND
Output
Power
Power
Differential 100 MHz PCI-Express true clock output. High impedance when disabled.
Ground
VDD
3.3 V Power supply
Differential 100 MHz PCI-Express complementary clock output. High impedance when
disabled.
9
PCIE3N
Output
10
11
12
PCIE3P
VDD
Output
Power
Output
Differential 100 MHz PCI-Express true clock output. High impedance when disabled.
3.3 V Power supply
PCIE0P
Differential 100 MHz PCI-Express true clock output. High impedance when disabled.
Differential 100 MHz PCI-Express complementary clock output. High impedance when
disabled.
13
PCIE0N
Output
14
15
16
17
SCLK
SDATA
VDD
Input
SMBus clock input
SMBus data input
3.3 V Power supply
Ground
Input
Power
Power
GND
Document Number: 001-46142 Rev. *G
Page 3 of 20
CY24292
Pin Definitions (continued)
Pin Number
Pin Name
VDD
GND
Pin Type
Power
Description
18
19
3.3 V Power supply
Ground
Power
Global reset pin. Powers down PLLs, disables outputs and sets the SMBus tables to their
default state when pulled low. Has internal weak pull up.
20
PD_RESET# Input
21
22
23
24
25
VDD
Power
3.3 V Power supply
XIN/EXCLKIN Input
Crystal or clock input. Connect to 25 MHz fundamental mode crystal or clock.
Crystal output. Connect to 25 MHz fundamental mode crystal. Float for clock input.
3.3 V Power supply
XOUT
VDD
NC
Output
Power
–
No connect. Pin has no internal connection.
25 MHz Single-ended LVCMOS output. Pull-down when disabled by PD_RESET#. Driv-
en low when individually disabled (via SMBus byte 0, bit 0).
26
25M
Output
27
28
29
30
31
32
GND
VDD
GND
VDD
GND
VDD
Power
Power
Power
Power
Power
Power
Ground
3.3 V Power supply
Ground
3.3 V Power supply
Ground
3.3 V Power supply
Data Protocol
Functional Overview
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
SMBus Serial Data Interface
block write and read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant bit
first) with the ability to stop after any complete byte is transferred.
For byte write and byte read operations, the system controller
can access individually indexed bytes. The offset of the indexed
byte is encoded in the command code, as described in Table 1.
A two-signal serial interface is provided to enhance the flexibility
and function of the clock synthesizer. Through the serial data
interface, various device functions such as clock output buffers
can be individually enabled or disabled. The registers associated
with the serial data interface initialize to their default setting upon
power up, and therefore this interface is optional. Clock device
register changes are normally made upon system initialization, if
required. This is a RAM-based technology which does not keep
its value when power is off or during a power transition.
The block write and block read protocol is outlined in Table 2 on
page 5, while Table 3 on page 5 outlines the corresponding byte
write and byte read protocol. The slave receiver address is
11010010 (D2h) for write and 11010011 (D3h) for read.
Table 1. Command Code Definition
Bit
Description
7
0 = block read or block write operation, 1 = byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be '0000000'
(6:0)
Document Number: 001-46142 Rev. *G
Page 4 of 20
CY24292
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
2:8
9
Slave address – 7 bits
Write
2:8
9
Slave address – 7 bits
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command code – 8-bit ‘00000000’ stands for block
operation
11:18
Command code – 8-bit ‘00000000’ stands for block
operation
19
20:27
28
Acknowledge from slave
Byte count – 8 bits
19
20
Acknowledge from slave
Repeat start
Acknowledge from slave
Data byte 0 – 8 bits
21:27
28
Slave address – 7 bits
Read
29:36
37
Acknowledge from slave
Data byte 1 – 8 bits
29
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge
38:45
46
30:37
38
Acknowledge from slave
Data byte N/Slave acknowledge
Data byte N – 8 bits
Acknowledge from slave
Stop
39:46
47
Data byte from slave – 8 bits
Acknowledge
48:55
56
Data byte from slave – 8 bits
Acknowledge
Data bytes from slave/acknowledge
Data byte N from slave – 8 bits
Not acknowledge
Stop
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
2:8
9
Slave address – 7 bits
Write = 0
2:8
9
Slave address – 7 bits
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command code – 8 bits ‘1xxxxxxx’ stands for byte
operation, bits[6:0] of bits[6:0] the command code
represents the offset of the byte to be accessed
11:18
Command code – 8 bits ‘1xxxxxxx’ stands for byte
operation, of the command code represents the
offset of the byte to be accessed
19
20:27
28
Acknowledge from slave
Data byte from master – 8 bits
Acknowledge from slave
Stop
19
20
Acknowledge from slave
Repeat start
21:27
28
Slave address – 7 bits
Read = 1
29
29
Acknowledge from slave
Data byte from slave – 8 bits
Not acknowledge
Stop
30:37
38
39
Document Number: 001-46142 Rev. *G
Page 5 of 20
CY24292
Control Registers
Table 4. Byte 0: Spread Spectrum Control Register
Bit
7
Type At Power up
Outputs Affected
Description
Notes
0 = spread off
1 = –0.5% down
R/W
R
1
All 100 MHz PCI-Express outputs Spread select for 100 MHz PCI-Express clocks
6
Undefined Not applicable
All outputs
Not used
0 = disabled
1 = enabled
5
R/W
1
Global OE bit. Enables or disables all outputs.
4
3
2
1
R
R
R
R
Undefined Not applicable
Undefined Not applicable
Undefined Not applicable
Undefined Not applicable
Not used
Not used
Not used
Not used
Single-ended 25 MHz output,
25M
OE for single-ended 25 MHz output, 25M.
Output driven low when disabled.
0 = disabled
1 = enabled
0
R/W
1
Table 5. Byte 1: Control Register
Bit
Type At Power up
Outputs Affected
Outputs Affected
Outputs Affected
Description
Notes
Notes
Notes
0 to 7
R
Undefined Not applicable
Not used
Table 6. Byte 2: Control Register
Bit
Type At Power up
Description
0 to 7
R
Undefined Not applicable
Not used
Table 7. Byte 3: Control Register
Bit
Type At Power up
Description
6,7
R
0
Not applicable
Not used
100 MHz PCI-Express output
PCIE3
0 = disabled
1 = enabled
5
R/W
1
OE for 100 MHz PCI-Express output PCIE3
100 MHz PCI-Express output
PCIE2
0 = disabled
1 = enabled
4
3
2
R/W
R
1
0
1
OE for 100 MHz PCI-Express output PCIE2
Not used
Not applicable
100 MHz PCI-Express output
PCIE1
0 = disabled
1 = enabled
R/W
OE for 100 MHz PCI-Express output PCIE1
100 MHz PCI-Express output
PCIE0
0 = disabled
1 = enabled
1
0
R/W
R
1
OE for 100 MHz PCI-Express output PCIE0
Not used
Undefined Not applicable
Table 8. Byte 4: Control Register
Bit
Type At Power up
Outputs Affected
Description
Notes
0 to 7
R
Undefined Not applicable
Not used
Document Number: 001-46142 Rev. *G
Page 6 of 20
CY24292
Table 9. Byte 5: Control Register
Bit
7
Type At Power up
Outputs Affected
Not applicable
Description
Notes
R
R
R
R
R
R
R
R
0
0
0
1
1
0
0
0
Revision ID bit 3
Revision ID bit 2
Revision ID bit 1
Revision ID bit 0
Vendor ID bit 3
Vendor ID bit 2
Vendor ID bit 1
Vendor ID bit 0
6
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
5
4
3
2
1
0
Table 10. Byte 6: Control Register
Bit
Type At Power up
Outputs Affected
Description
Notes
0 to 7
R
Undefined Not applicable
Not used
The state of the clock outputs upon assertion of the PD_RESET# signal from input pin or Global OE control bit from byte 0, bit 5 of
the SMBus is shown in the following table.
Table 11. Power Down Reset Table
H/W PD_RESET# (pin 24)
S/W PD_RESET# (Byte 0 bit 5)
All Clock Outputs
Disabled, Hi-Z. 25M has weak pull-down.
Disabled, Hi-Z. 25M has weak pull-down.
Disabled, Hi-Z. 25M has weak pull-down.
Enabled
0
0
1
1
0
1
0
1
Document Number: 001-46142 Rev. *G
Page 7 of 20
CY24292
Application Information
Crystal Recommendations
The CY24292 requires a parallel resonance crystal. Substituting a series resonance crystal causes the CY24292 to operate at the
wrong frequency and violate the ppm specification. For most applications there is a 300 ppm frequency shift between the series and
parallel crystals due to incorrect loading.
Table 12. Crystal Recommendations
Frequency
Cut
Load Cap (max) Eff Series Rest (max) Drive (max) Tolerance (max) Stability (max) Aging (max)
16 pF 30 1.0 mW 30 ppm 10 ppm 5 ppm/yr
25.00 MHz Parallel
Use the following formulas to calculate the trim capacitor values
for Ce1 and Ce2.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm
performance. To realize low ppm performance, consider the total
capacitance the crystal sees to calculate the appropriate
capacitive loading (CL).
Load capacitance (each side)
Ce = 2 * CL – (Cs + Ci)
Figure 2 shows a typical crystal configuration using two trim
capacitors. It is important to note that the trim capacitors in series
with the crystal are not parallel. It is a common misconception
that load capacitors are in parallel with the crystal and are
approximately equal to the load capacitance of the crystal. This
is not true.
Total capacitance (as seen by the crystal)
1
CLe
=
1
1
(
)
+
Ce2 + Cs2 + Ci2
Ce1 + Cs1 + Ci1
Calculating Load Capacitors
CL .................................................. Crystal load capacitance
In addition to the standard external trim capacitors, the trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading.
CLe ........................................Actual loading seen by crystal
using standard value trim capacitors
Ce ....................................................External trim capacitors
Cs .............................................Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
As mentioned in the previous section, the capacitance on each
side of the crystal is in series with the crystal. This means the
total capacitance on each side of the crystal must be twice the
specified crystal load capacitance (CL). While the capacitance
on each side of the crystal is in series with the crystal, the trim
capacitors (Ce1, Ce2) must be calculated to provide equal
capacitive loading on both sides.
Current Source (Iref) Reference Resistor
If the board target trace impedance (Z) is 50 , then for
RREF = 475 (1%) provides IREF of 2.32 mA. The output
current (IOH) is equal to 6 × IREF.
Figure 2. Crystal Loading Example
Output Termination
Clock
Chip
The PCI-Express differential clock outputs of CY24292 are open
source drivers and require an external series resistor and a
resistor to ground. These resistor values and their allowable
locations are explained in detail in the section PCI-Express
Layout Guidelines on page 9.
Ci
1
Ci2
Pin
3 to 6 pF
X2
X1
Cs2
Cs1
Trace
2.8 pF
XTAL
Ce1
Ce2
Trim
26 pF
Document Number: 001-46142 Rev. *G
Page 8 of 20
CY24292
4. An optimum layout is one with all components on the same
side of the board, minimizing vias through other signal layers
(any ferrite beads and bulk decoupling capacitors can be
mounted on the back). Other signal traces must be routed
away from the CY24292. This includes signal traces just
underneath the device, or on layers adjacent to the ground
plane layer used by the device.
PCB Layout Recommendations
For optimum device performance and lowest phase noise, the
following guidelines must be observed.
1. Each 0.01 µF decoupling capacitor must be mounted on the
component side of the board as close to the VDD pin as
possible.
2. No vias must be used between the decoupling capacitor and
the VDD pin.
Decoupling Capacitors
Decoupling capacitors of 0.01 µF must be connected between
VDD and GND as close to the device as possible. Do not share
ground vias between components. Route power from power
source through the capacitor pad, and then into the CY24292
pin.
3. The PCB trace to the VDD pin and the ground via must be
kept as short as possible. The distance of the ferrite bead and
bulk decoupling from the device is less critical.
PCI-Express Layout Guidelines
HCSL Compatible Layout Guidelines
Table 13. Common Recommendations for Differential Routing
Differential Routing[1]
L1 length, route as non-coupled 50 trace
L2 length, route as non-coupled 50 trace
L3 length, route as non-coupled 50 trace
RS
Dimension or Value
Unit
inch
inch
inch
0.5 max
0.2 max
0.2 max
33
RT
49.9
Table 14. Differential Routing for PCI-Express Load or Connector
Differential Routing [1]
Dimension or Value
2 to 32
Unit
inch
inch
L4 length, route as coupled microstrip 100 differential trace
L4 length, route as coupled stripline 100 differential trace
1.8 to 30
Figure 3. PCI-Express Device Routing
Rs
L4
L4
L1
L1
L2
L2
RS
RT
RT
Output Buffer
L3
L3
PCI Express Load or
Connector
Note
1. Refer to Figure 3.
Document Number: 001-46142 Rev. *G
Page 9 of 20
CY24292
Absolute Maximum Ratings
Parameter
VDD
Description
Supply voltage
Condition
Min
–0.5
–0.5
–65
–
Max
4.6
Unit
V
VIN
Input voltage
Relative to VSS
Non Operating
VDD + 0.5
150
V
TS
Temperature, Storage
Temperature, Junction
°C
°C
V
TJ
125
–
ESDHBM
ESD Protection (Human Body
Model)
JEDEC EIA/JESD22-A114-E
2000
UL-94
MSL
Flammability rating
V-0 at 1/8 in.
3
Moisture sensitivity level
Recommended Operation Conditions
Parameter
Description
Min
3.0
0
Typ
–
Max
3.6
70
Unit
V
V
Supply voltage
DD
T
Commercial ambient temperature
Industrial ambient temperature
–
°C
°C
AC
T
–40
–
85
AI
PU
PD
Power up time for all VDD to reach minimum specified voltage (power
ramps must be monotonic)
t
0.05
–
500
ms
t
Minimum pulse width of PD_RESET# input
SMBus Voltage
100
3.0
–
–
–
ns
V
V
3.6
SMB
Tolerance on the 475RREF resistor that sets output currents on
100MHz ports
R
–
–
1
%
REFTOL
Document Number: 001-46142 Rev. *G
Page 10 of 20
CY24292
DC Electrical Characteristics
Unless otherwise stated, VDD = 3.3 V ± 0.3 V, ambient temperature = –40 °C to 85 °C Industrial, 0 °C to 70 °C Commercial, RREF = 475
Parameter[2]
Description
Condition
Min
Typ
Max
Unit
Low level output voltage of 25M
clock
VOL1
IOL = 8 mA
–
–
0.4
V
High level output voltage of 25M
clock
VOH1
VOL2
IOH = –8 mA
VDD – 0.4
–0.2
–
0
–
V
V
Low level output voltage of 100M HCSL termination
clocks
0.05
(RS = 33 , RT = 49.9 )
High level output voltageof 100M HCSL termination
VOH2
VOL3
IOH
0.65
–
0.71
–
0.95
0.4
V
V
clocks
(RS = 33 RT49.9
Low level output voltage SDATA IOL = 4 mA
Outputhighcurrentfordifferential
IOH = 6 × IREF
–13
–15.2
–17
mA
clocks
Low level input voltage of SCLK,
SDATA
VIL1
VIH1
VIL2
VIH2
–0.3
2.1
–
–
–
–
0.8
VDD + 0.3
0.8
V
V
V
V
High level input voltage of SCLK,
SDATA
Low level input voltage of
XIN/EXCLKIN, PD_RESET# pins
–0.3
2.0
High level input voltage of
XIN/EXCLKIN, PD_RESET# pins
VDD + 0.3
No load, PD_RESET# pin = 1
–
–
50
135
250
5
70
170
350
–
mA
mA
A
pF
IDD
Operating supply current
Full load, PD_RESET# pin = 1
PD_RESET# pin = 0
All input pins
IDDPD
CIN
Power down current
–
Input capacitance
–
RPU
RPD
Pull up resistor, PD_RESET#
Pull down resistor, 25M output
–
90
–
–
k
k
PD_RESET# = 0
50
150
Thermal Resistance
Parameter[3]
Description
Test Conditions
32-pin QFN
Unit
Thermal resistance
(junction to ambient)
θJA
22
°C/W
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
Thermal resistance
(junction to case)
θJC
19.5
°C/W
Notes
2. Parameters are guaranteed by design and characterization. Not 100% tested in production.
3. These parameters are guaranteed by design and are not tested.
Document Number: 001-46142 Rev. *G
Page 11 of 20
CY24292
AC Electrical Characteristics
Unless otherwise stated, VDD = 3.3 V ± 0.3 V, ambient temperature = –40 °C to 85 °C Industrial, 0°C to 70°C Commercial, RREF = 475
Table 15. Single-Ended 25 MHz Output
Parameter[4]
Description
Condition
Min
Typ
Max
Unit
Input clock frequency (crystal or
external clock)
–
FIN
–
25
–
MHz
TINDC
FOUT
Input clock duty cycle
40
–
–
60
–
%
–
–
Output clock frequency, 25M
25
MHz
TR
Output rise time[5]
Output fall time[5]
Output clock duty cycle[5]
20% to 80% of VDD
–
–
0.5
0.5
50
1
1
ns
ns
%
TF
80% to 20% of VDD
Measured at VDD/2
TDC
TCCJ
45
55
Cycle-to-cycle jitter[5]
–
–
–
–
200
2
ps
–
TOEPD
TLOCK
Output enable from power down PD_RESET# going high to 99% of final
reset
ms
frequency
Measured from 90% of the applied power
supply level
Clock stabilization from power up
–
1
2
ms
Notes
4. Parameters are guaranteed by design and characterization. Not 100% tested in production.
5. Measured with Cload = 15 pF lumped load.
Document Number: 001-46142 Rev. *G
Page 12 of 20
CY24292
Table 16. Differential 100 MHz, HCSL Terminated Outputs
Parameter [6]
FOUT
Description
Output frequency
Test Condition
Min
–
Typ
–
Max
100
Unit
MHz
type
kHz
ps
Lexmark
33
SPPROFILE
SPMOD
Spread modulation profile
–
–
Spread modulation frequency
30
–
32
–
Cycle-to-cycle jitter[7]
TCCJ
90
86
Peak-to-peak phase jitter[7, 8]
Output clock duty cycle[7]
Rising edge rate[7, 9]
TPHJ
TDC
ERR
ERF
–
–
50
–
ps
%
45
0.6
0.6
55
See notes 7 and 9
4.0
4.0
V/ns
V/ns
Falling edge rate[7, 9]
See notes 7 and 9
–
Absolute crossing point
voltage [10, 11, 12]
VCROSS
VXdelta
See notes 10, 11, and 12
0.25
–
0.35
–
0.55
140
V
Variation of VCROSS over all rising
clock edges[10, 11, 13]
See notes 10, 11, and 13
mV
Average clock period
accuracy[7, 14]
Absolute clock period[7, 15]
TPERIOD AVG
TPERIOD ABS
TOSKEW ALL
See notes 7 and 14
See notes 7 and 15
–300
9.847
–
–
–
–
2800
10.203
100
ppm
ns
Measured at VCROSS point
See note 16
Output skew, all pairs[16]
ps
PCIE0P/N to PCIE3P/N skew
and PCIE1P/N to PCIE2P/N
skew[16]
Measured at VCROSS point
See note 16
TOSKEW P-P
–
–
50
ps
Output enable from power down PD_RESET# going high to 99% of
TOEPD
TLOCK
–
–
–
1
2
2
ms
ms
reset
final frequency
Measured from 90% of the applied
power supply level
Clock stabilization from power up
Notes
6. Parameters are guaranteed by design and characterization. Not 100% tested in production.
7. Measurement taken from differential waveform (PCIEP minus PCIEN). Either single ended probes with math or a differential probe can be used.
8. Phase jitter is determined using data captured on an oscilloscope at a sample rate of 20 GS/sec, for a minimum 100,000 continuous clock periods. This data is then
processed using the ClockJitter 1.3.0 software from PCISIG, using the PCI_E_1_1 template.
9. Measured from -150 mV to +150 mV on the differential waveform (derived from PCIEP minus PCIEN). The signal must be monotonic through the measurement region
for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing.
10. Measurement taken from a single-ended waveform.
11. Measured at crossing point where the instantaneous voltage value of the rising edge of PCIEP equals the falling edge of PCIEN.
12. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement.
13. Defined as the total variation of all crossing voltages of Rising PCIEP and Falling PCIEN. This is the maximum allowed variance in V
for any particular system.
CROSS
14. PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100.000000 MHz exactly, or 100 Hz. For 300 PPM then
we have an error budget of 30 kHz. The period is to be measured with a frequency counter with measurement window set to 100 ms or greater. The ±300 PPM applies
to systems that do not employ Spread Spectrum or that use common clock source. For systems employing Spread Spectrum, there is an additional 2500 PPM nominal
shift in maximum period resulting from the 0.5% down spread, resulting in a maximum average period specification of +2800 PPM.
15. Defined as the absolute minimum or maximum instantaneous period. This includes cycle-to-cycle jitter, relative PPM tolerance, and spread spectrum modulation.
16. Measured at the rising 0 V point of the differential signal. Skew is the time difference of the rising 0 V point between any two differential signal pairs. The measurement
is taken over 1000 samples, and the average value is used.
Document Number: 001-46142 Rev. *G
Page 13 of 20
CY24292
Test and Measurement Setup
Single-ended Signals
Figure 4. Test Load Configuration for Single-ended Output Signal
453 Ohm
CLoad
50 Ohm
Differential Signals
Figure 5. Test Load Configuration for Differential Output Signal
33 Ohm
PCIEP
CLoad
CLoad
50 Ohm
50 Ohm
33 Ohm
PCIEN
475
Ohm
Document Number: 001-46142 Rev. *G
Page 14 of 20
CY24292
Ordering Information
Ordering Code
Pb-free
Package Type
Production Flow
CY24292LFXC
CY24292LFXCT
CY24292LFXI
32-pin QFN
Commercial, 0 °C to 70 °C
Commercial, 0 °C to 70 °C
Industrial, –40 °C to 85 °C
Industrial, –40 °C to 85 °C
32-pin QFN – Tape and Reel
32-pin QFN
CY24292LFXIT
32-pin QFN – Tape and Reel
Ordering Code Definitions
CY 24292
L
X -xxx
T
X
X
T = Tape and Reel, blank = tube
Configuration specific identifier (Factory Programmed)
Temperature Range: X = C or I
C = Commercial = 0 °C to 70 °C; I = Industrial = –40 °C to 85 °C
Pb-free
X = F or blank
F = Field Programmable; blank = Factory Programmed
Package:
L = 32-pin QFN
Part Identifier
Company ID: CY = Cypress
Document Number: 001-46142 Rev. *G
Page 15 of 20
CY24292
Package Diagram
Figure 6. 32-pin QFN (5 × 5 × 0.55 mm) LQ32 3.5 × 3.5 E-Pad (Sawn) Package Outline, 001-42168
SEE NOTE 1
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NOTES:
1.
HATCH AREA IS SOLDERABLE EXPOSED PAD
2. BASED ON REF JEDEC # MO-248
3. PACKAGE WEIGHT: 0.0388g
4. DIMENSIONS ARE IN MILLIMETERS
001-42168 *F
Document Number: 001-46142 Rev. *G
Page 16 of 20
CY24292
Acronyms
Document Conventions
Table 17. Acronyms Used in this Document
Units of Measure
Acronym
EIA
Description
electronic industries alliance
electromagnetic interference
electrostatic discharge
Table 18. Units of Measure
Symbol
°C
Unit of Measure
EMI
degree Celsius
kilohertz
kHz
k
MHz
F
mA
ms
mV
ns
ESD
kilohm
HCSL
JEDEC
host clock signal level
megahertz
microfarad
milliampere
millisecond
millivolt
joint electron devices engineering council
low voltage complementary metal oxide
semiconductor
LVCMOS
OE
output enable
PCI
peripheral component interconnect
phase-locked loop
nanosecond
ohm
PLL
QFN
RAM
quad-flat no-leads
%
percent
random access memory
pF
picofarad
parts per million
picosecond
volt
ppm
ps
V
Document Number: 001-46142 Rev. *G
Page 17 of 20
CY24292
Document History Page
Document Title: CY24292, Four Outputs PCI-Express Clock Generator
Document Number: 001-46142
Orig. of
Change
Submission
Date
Rev.
ECN
Description of Change
PYG / DPF
/ AESA
**
2490167
See ECN New data sheet.
Updated Pin Configuration (Changed pinout based on PCIE_Bonding_Rev G).
Updated DC Electrical Characteristics (Added Note 2 and referred the same
note in parameter column, added HCSL termination in Condition column for
VOL2, VOH2).
DPF /
AESA
*A
2507681
05/23/2008 Updated AC Electrical Characteristics (updated Note 5, added Note 11 and
referred the same note in TDC parameter in Table 16, changed Cload from 2
pF to 4 pF in a Note below, added maximum value of VXdelta (140 mV) in the
Table 16).
Updated to new template.
Changed status from Preliminary to Final.
Updated Pin Definitions (Added explanation of 25M output disable feature).
Updated Control Registers (Changed default setting (At Power up column) for
bit 7 in Table 4 to ‘1’, changed description of bit 5 in Table 4 to ‘Global OE bit’,
added explanation of 25M output disable feature in Table 4, changed unused
bits (Type Column) from R/W to R in Table 7, changed default setting (At Power
up column) for bit 4 in Table 9 to ‘1’, added explanation of 25M output disable
feature in Table 11).
Updated the sub-section Crystal Recommendations under the main section
Application Information (Added “max” to Load Cap and Eff Series Rest columns
in Table 12).
Updated sub-section “LVDS Compatible Layout Guidelines” under the main
section PCI-Express Layout Guidelines (changed “LVDS Down Device” to
“LVDS Device” in all instances).
Updated Absolute Maximum Ratings (Changed maximum value of TJ
parameter to 125 °C).
Updated Recommended Operation Conditions (Added V
parameters and its details).
and R
REFTOL
SMB
Updated DC Electrical Characteristics (added RREF value to conditions at top,
removed VOHSD and VOLSD parameters and their details, changed maximum
12/03/2009 value of VOH2 parameter from 0.85 V to 0.95 V, added VOL3 parameter and its
details, changed typical value of IOH parameter from –14.2 mA to –15.2 mA,
added minimum value of VIL1 parameter, changed maximum value of VIL1
parameter from 1 V to 0.8 V, changed minimum value of VIH1 parameter from
2.2 V to 2.1 V, added typical and maximum values for IDD no load and full load
parameters, changed typical value of IDDPD parameter from TBD to 250 µA,
changed maximum value of IDDPD parameter from TBD to 350 µA, added RPU
parameter and its details, changed RPD parameter to apply to 25M output only).
Updated AC Electrical Characteristics (added RREF value to conditions at top,
removed FERR parameter and its details in Table 15, added SPPROFILE
parameter and its details in Table 16, added minimum and maximum values for
SPMOD parameter, changed maximum value of TCCJ parameter from 100 ps to
90 ps in Table 16, added TPHJ parameter and its details in Table 16, changed
TR and TF parameters and its details into ERR and ERF parameters in Table 16,
removed TRFMATCH parameter and its details in Table 16, splitted TOSKEW
parameter into two parameters namely TOSKEW ALL and TOSKEW P-P parameter
and also changed their details in Table 16, added minimum value of VCROSS
parameter and also changed the description of the same parameter in Table 16,
changed description of VXdelta parameter in Table 16).
*B
2811340
CXQ
Updated Package Diagram (to spec 001-42168 Rev *C).
Fixed various typos.
*C
2901711
KVM
05/14/10
Updated Package Diagram.
Document Number: 001-46142 Rev. *G
Page 18 of 20
CY24292
Document History Page (continued)
Document Title: CY24292, Four Outputs PCI-Express Clock Generator
Document Number: 001-46142
Orig. of
Change
Submission
Date
Rev.
ECN
Description of Change
Updated Features (Removed LVDS related information).
Updated Functional Description (Removed LVDS related information).
Updated Output Termination under Application Information (Removed LVDS
related information).
*D
3448896
PURU
11/28/2011 Removed the sub-section “LVDS Compatible Layout Guidelines” under the
main section PCI-Express Layout Guidelines.
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Updated to new template.
Updated Functional Description:
12/05/2014 Added “For a complete list of related documentation, click here.” at the end.
*E
4580588
TAVA
Updated Package Diagram.
Added Thermal Resistance.
04/26/2017
*F
5281281
5784045
PSR
PSR
Updated to new template.
Updated AC Electrical Characteristics: Added FIN and TINDC parameters.
06/27/2017
*G
Updated Figure 6 in Package Diagram (spec 001-42168 *E to *F).
Document Number: 001-46142 Rev. *G
Page 19 of 20
CY24292
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
ARM® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
cypress.com/mcu
cypress.com/support
Microcontrollers
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2008–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-46142 Rev. *G
Revised June 27, 2017
Page 20 of 20
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