CY24293ZXCT [CYPRESS]
Two Outputs PCI-Express Clock Generator; 两路输出的PCI-Express时钟发生器
| 型号： | CY24293ZXCT |
| 厂家： | 
CYPRESS |
| 描述： | Two Outputs PCI-Express Clock Generator |
| 文件： | 总10页 (文件大小：449K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY24293
Two Outputs PCI-Express Clock Generator
Features
Functional Description
■ 25 MHz Crystal or Clock Input
CY24293 is a two output PCI-Express clock generator device
intended for networking applications. The device takes 25 MHz
crystal or clock input and provides two pairs of differential outputs
at 25 MHz, 100 MHz, 125 MHz, or 200 MHz for HCSL, and
25 MHz or 100 MHz for the LVDS signaling standard.
■ Two sets of Differential PCI-Express Clocks
■ Pin Selectable Output Frequencies
■ Supports HCSL or LVDS Compatible Output Levels
The device incorporates Lexmark Spread Spectrum profile for
maximum electromagnetic interference (EMI) reduction. The
spread type and amount can be selected using select pins.
■ Spread Spectrum Capability on all Output Clocks with Pin
Selectable Spread Range
■ 16-pin TSSOP Package
■ Operating Voltage 3.3V
■ Commercial and Industrial Operating Temperature Range
Logic Block Diagram
VDDX
VDDO
XIN/EXCLKIN
Clock Buffer/
PCIE0P
Crystal
Oscillator
(25 MHz)
PCIE0N
XOUT
PLL Clock
Synthesizer
SS0
PCIE1P
PCIE1N
SS1
Control
Logic
S0
S1
IREF
OE
= 475 Ohms 1%
R REF
GNDX
GNDO
Cypress Semiconductor Corporation
Document Number: 001-46117 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 02, 2009
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CY24293
Pinouts
Figure 1. Pin Diagram - CY24293 16-Pin TSSOP
1
2
3
4
5
6
7
8
VDDX
S0
S1
16
15
14
13
12
11
10
9
PCIE0P
PCIE0N
GNDO
VDDO
PCIE1P
PCIE1N
IREF
SS0
XIN/EXCLKIN
XOUT
TSSOP
OE
GNDX
SS1
Table 1. Pin Definitions - CY24293 16-Pin TSSOP
Pin Number
Pin Name Pin Type
Description
1
2
3
4
5
S0
Input
Input
Input
Frequency select pin. Has internal weak pull up. Refer to Table 2.
Frequency select pin. Has internal weak pull up. Refer to Table 2.
Spread Spectrum Select pin 0. Has internal weak pull up. Refer to Table 3.
Crystal or clock input. 25 MHz fundamental mode crystal or clock input.
S1
SS0
XIN/EXCLKIN Input
XOUT
OE
Output
Crystal output. 25 MHz fundamental mode crystal input. Float for clock input.
Input
High true output enable pin. When set low, PCI-E outputs are tri-stated. Has internal weak
pull up.
6
7
GNDX
SS1
Power
Input
Ground
8
Spread Spectrum Select pin 1. Has internal weak pull up. Refer to Table 3.
Current set for all differential clock drivers. Connect 475Ω resistor to ground.
Differential PCI-Express complementary clock output. Tristated when disabled.
Differential PCI-Express true clock output. Tristated when disabled.
3.3V Power supply for output driver and analog circuits.
Ground
9
IREF
Output
Output
Output
Input
10
11
12
13
14
15
16
PCIE1N
PCIE1P
VDDO
GNDO
PCIE0N
PCIE0P
VDDX
Power
Output
Output
Input
Differential PCI-Express complementary clock output. Tristated when disabled.
Differential PCI-Express true clock output. Tristated when disabled.
3.3V Power supply for oscillator and digital circuits.
Table 2. Output Selection Table
S1
0
S0
0
PCIE0[N,P], PCIE1[N,P]
25 MHz
0
1
100 MHz
1
0
125 MHz
1
1
200 MHz
Table 3. Spread Selection Table
SS1
0
SS0
0
Spread%
No Spread
-0.5%
0
1
1
0
-0.75%
1
1
No Spread
Document Number: 001-46117 Rev. *C
Page 2 of 10
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CY24293
Application Information
Crystal Recommendations
CY24293 requires a parallel resonance crystal. Substituting a series resonance crystal causes the CY24293 to operate at the wrong
frequency and violate the ppm specification. For most applications, there is a 300 ppm frequency shift between series and parallel
crystals due to incorrect loading.
Table 4. Crystal Recommendations
Frequency
Cut
Load Cap
Eff Series Rest
(max)
Drive (max) Tolerance (max) Stability (max) Aging (max)
1.0 mW 30 ppm 10 ppm 5 ppm/yr.
25.00 MHz
Parallel
16 pF
30 Ω
Use the following formulas to calculate the trim capacitor values
for Ce1 and Ce2:
Crystal Loading
Crystal loading plays a critical role in achieving low ppm
performance. To realize low ppm performance, consider the total
capacitance the crystal sees to calculate the appropriate
capacitive loading (CL).
Load capacitance (each side)
Ce = 2 * CL – (Cs + Ci)
Figure 2 shows a typical crystal configuration using two trim
capacitors. It is important to note that the trim capacitors in series
with the crystal are not parallel. It is a common misconception
that load capacitors are in parallel with the crystal and must be
approximately equal to the load capacitance of the crystal. This
is not true.
Total capacitance (as seen by the crystal)
1
CLe
=
1
1
(
)
+
Ce2 + Cs2 + Ci2
Ce1 + Cs1 + Ci1
CL................................................... Crystal load capacitance
CLe.........................................Actual loading seen by crystal
using standard value trim capacitors
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading.
Ce.....................................................External trim capacitors
Cs..............................................Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
As mentioned in the previous section, the capacitance on each
side of the crystal is in series with the crystal. This means the
total capacitance on each side of the crystal must be twice the
specified crystal load capacitance (CL). While the capacitance
on each side of the crystal is in series with the crystal, trim
capacitors (Ce1, Ce2) must be calculated to provide equal
capacitive loading on both sides.
Current Source (Iref) Reference Resistor
If the board target trace impedance (Z) is 50Ω, then for
RREF = 475Ω (1%), provides IREF of 2.32 mA. The output
current (IOH) is equal to 6*IREF.
Output Termination
Figure 2. Crystal Loading Example
The PCI-Express differential clock outputs of the CY24293 are
open source drivers and require an external series resistor and
a resistor to ground. These resistor values and their allowable
locations are explained in the section PCI-Express Layout
Guidelines on page 4. The CY24293 can also be configured for
LVDS compatible voltage levels. Refer to the section LVDS
Compatible Layout Guidelines on page 5.
ClockChip
Ci2
Ci1
Pin
3 to 6p
X2
X1
Cs2
Cs1
Trace
2.8 pF
XTAL
Ce1
Ce2
Trim
26 pF
Document Number: 001-46117 Rev. *C
Page 3 of 10
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CY24293
4. An optimum layout is one with all components on the same
side of the board, minimizing vias through other signal layers
(any ferrite beads and bulk decoupling capacitors can be
mounted on the back). Other signal traces must be routed
away from the CY24293. This includes signal traces just
underneath the device, or on layers adjacent to the ground
plane layer used by the device.
PCB Layout Recommendations
For optimum device performance and the lowest phase noise,
the following guidelines must be observed:
1. Each 0.01 µF decoupling capacitor must be mounted on the
component side of the board as close to the VDD pin as
possible.
2. No vias must be used between the decoupling capacitor and
the VDD pin.
Decoupling Capacitors
The decoupling capacitors of 0.01 µF must be connected
between VDD and GND as close to the device as possible. Do
not share ground vias between components. Route power from
the power source through the capacitor pad and then into the
CY24293 pin.
3. The PCB trace to the VDD pin and the ground via must be
kept as short as possible. Distance of the ferrite bead and bulk
decoupling from the device is less critical.
PCI-Express Layout Guidelines
HCSL Compatible Layout Guidelines
Table 5. Common Recommendations for Differential Routing
Differential Routing[1]
L1 length, route as non-coupled 50Ω trace
L2 length, route as non-coupled 50Ω trace
L3 length, route as non-coupled 50Ω trace
RS
Dimension or Value
Unit
inch
inch
inch
Ω
0.5 max
0.2 max
0.2 max
33
RT
49.9
Ω
Table 6. Differential Routing for PCI-Express Load or Connector
Differential Routing[1]
Dimension or Value
2 to 32
Unit
inch
inch
L4 length, route as coupled microstrip 100Ω differential trace
L4 length, route as coupled stripline 100Ω differential trace
1.8 to 30
Figure 3. PCI-Express Device Routing
Rs
L4
L4
L1
L1
L2
L2
RS
RT
RT
Output Buffer
L3
L3
PCI Express Load or
Connector
Note
1. Refer to Figure 3.
Document Number: 001-46117 Rev. *C
Page 4 of 10
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CY24293
LVDS Compatible Layout Guidelines
Table 7. Common Recommendations for Differential Routing
Differential Routing[2]
Dimension or Value
Unit
inch
inch
inch
Ω
L1 length, route as noncoupled 50Ω trace
0.5 max
0.2 max
0.2 max
100
L2 length, route as noncoupled 50Ω trace
L3 length, route as noncoupled 50Ω trace
RP
RQ
RS
RT
150
Ω
33
Ω
49.9
Ω
Table 8. LVDS Device Differential Routing
Differential Routing[2]
Dimension or Value
2 to 32
Unit
inch
inch
L4 length, route as coupled microstrip 100Ω differential trace
L4 length, route as coupled stripline 100Ω differential trace
1.8 to 30
Figure 4. LVDS Device Routing
Rs
L4
L4
L1
L1
L2
L2
RQ
RP
Rs
RT
RT
Output Buffer
L3
L3
LVDS Device Input
Note
2. Refer to Figure 4.
Document Number: 001-46117 Rev. *C
Page 5 of 10
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CY24293
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 9. Absolute Maximum Ratings
Parameter
VDD
Description
Condition
Relative to VSS
Min
–0.5
–0.5
–65
Max
Unit
V
Supply voltage
Input voltage
4.6
VIN
VDD+0.5
V
TS
Temperature, Storage
Non Functional
+150
°C
°C
V
TJ
Temperature, Junction
Non Functional
–65
+150
ESDHBM
UL-94
MSL
ESD Protection (Human Body Model)
Flammability rating
JEDEC EIA/JESD22-A114-E
2000
–
V-0 at 1/8 in.
3
Moisture sensitivity level
Recommended Operation Conditions
Parameter
Description
Min
Typ
–
Max
3.6
Unit
V
V
3.0
0
Supply voltage
DD
T
Commercial ambient temperature
Industrial ambient temperature
–
+70
+85
500
°C
AC
T
–40
0.05
–
°C
AI
t
Power up time for all V to reach minimum specified voltage (power ramps must
–
ms
PU
DD
be monotonic)
DC Electrical Characteristics
Unless otherwise stated, VDD = 3.3V ±0.3V, ambient temperature = -40°C to +85°C Industrial, 0°C to +70°C Commercial
Parameter[3]
Description
Input low voltage
Condition
Min
-0.3
2.0
Typ
–
Max
0.8
Unit
V
VIL
VIH
VOL
Input high voltage
–
VDD+0.3
0.05
V
Output low voltage of PCIE0[P/N],
PCIE1[P/N]
HCSL termination
(RS = 33Ω, RT = 49.9Ω)
-0.2
0
V
VOH
Output high voltage of PCIE0[P/N],
PCIE1[P/N]
HCSL termination
(RS = 33Ω, RT = 49.9Ω)
0.65
0.71
0.85
V
IDD
Operating supply current
Output disabled current
Input capacitance
No load, OE = 1
OE = 0
–
–
–
–
45
–
60
50
–
mA
mA
pF
Ω
IDDOD
CIN
All input pins
5
RPU
Pull up resistance
S0, S1, SS0, SS1, OE
70k
–
Note
3. Parameters are guaranteed by design and characterization. Not 100% tested in production
Document Number: 001-46117 Rev. *C
Page 6 of 10
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CY24293
,
AC Electrical Characteristics
Unless otherwise stated: VDD = 3.3V ±0.3V, ambient temperature = -40°C to +85°C Industrial, 0°C to +70°C Commercial, Outputs
HCSL terminated.
Parameter[3]
Description
Condition
Min
Typ
Max
Unit
FIN
Input clock frequency (crystal or
external clock)
–
25
–
MHz
FOUT
Output frequency
HCSL Termination
–
–
–
–
–
–
0
–
200
100
–
MHz
MHz
ppm
ps
LVDS Termination
FERR
TCCJ
Frequency synthesis error
Cycle-to-cycle jitter[4]
75
SPMOD
TDC
Spread modulation frequency
–
32
50
–
kHz
%
Output clock duty cycle[4,6]
Output enable time
45
55
TOEH
OE going high to differential outputs
becoming valid
–
–
–
–
–
1
200
200
2
ns
TOEL
Output disable time
OE going low to differential outputs
becoming invalid
ns
TLOCK
Clock stabilization from power up
Measured from 90% of the applied power
supply level
ms
Output rise time[4,5]
TR
Measured from 0.175V to 0.525V
Measured from 0.525V to 0.175V
For a given frequency, Max(TR) - Min (TR)
For a given frequency, Max(TF) - Min (TF)
Measured at VCROSS point
130
130
–
–
–
700
700
125
125
50
ps
ps
ps
ps
ps
V
Output fall time[4,5]
TF
Rise time variation[4,5]
Fall time variation[4,5]
Output skew[6]
DTR
–
DTF
–
–
TOSKEW
VCROSS
VXdelta
–
–
Absolute crossing point voltage[6,7]
0.25
–
0.35
–
0.55
140
Variation of VCROSS over all clock
edges[6,8]
mV
Test and Measurement Setup
Figure 5. Test Load Configuration for Differential Output Signals
33 Ohm
PCIEP
CLoad
CLoad
50 Ohm
50 Ohm
33 Ohm
PCIEN
475
Ohm
Notes
4. Measured with Cload = 4 pF max. (scope probe + trace load)
5. Measurement taken from a differential waveform.
6. Measured at crossing point where the instantaneous voltage value of the rising edge of PCIEP equals the falling edge of PCIEN.
7. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement.
8. Refers to the difference between the PCIEP rising edge VCROSS average value and the PCIEN rising edge VCROSS average value.
Document Number: 001-46117 Rev. *C
Page 7 of 10
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CY24293
Ordering Information
Part Number
Pb-free
Type
Production Flow
CY24293ZXC
CY24293ZXCT
CY24293ZXI
CY24293ZXIT
16-pin TSSOP
16-pin TSSOP tape & reel
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Industrial, -40°C to 85°C
Industrial, -40°C to 85°C
16-pin TSSOP
16-pin TSSOP tape & reel
Package Dimensions
Figure 6. 16-Pin TSSOP 4.40 mm Body Package
PIN 1 ID
DIMENSIONS IN MM[INCHES] MIN.
MAX.
1
REFERENCE JEDEC MO-153
PACKAGE WEIGHT 0.05gms
6.25[0.246]
6.50[0.256]
4.30[0.169]
4.50[0.177]
PART #
Z16.173 STANDARD PKG.
ZZ16.173 LEAD FREE PKG.
16
0.65[0.025]
BSC.
0.25[0.010]
BSC
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
GAUGE
PLANE
0°-8°
0.076[0.003]
0.50[0.020]
0.70[0.027]
0.05[0.002]
0.15[0.006]
0.85[0.033]
0.09[[0.003]
0.20[0.008]
SEATING
PLANE
0.95[0.037]
4.90[0.193]
5.10[0.200]
51-85091 *A
Document Number: 001-46117 Rev. *C
Page 8 of 10
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CY24293
Document History Page
Document Title: CY24293 Two Outputs PCI-Express Clock Generator
Document Number: 001-46117
Submission
REV.
ECN NO. Orig. of Change
Description of Change
Date
**
2490167 PYG/DPF/AESA See ECN New Data Sheet
*A
2507681
DPF/AESA
05/23/2008 Added Note 1: Parameters are guaranteed by design and characterization.
Not 100% tested in production.
Added Note 2 for Duty cycle spec in the AC Elect. Characteristics.
Added HCSL termination in Condition for VOL, VOH DC Elect. Char.
Added VXdelta value of 140 mV in the Differential 100 MHz HCSL output.
Changed Cload from 2 pF to 4 pF in Note 2.
Added internal weak Pull ups for S0, S1, SS0, SS1 and OE pins.
Updated TOEH and TOEL to 200 ns (max.).
Updated data sheet template
*B
*C
2621901
2683343
CXQ/AESA
CXQ/PYRS
12/19/2008 Updated IDD spec in DC Electrical Characteristics.
Added max spec for IDDOD DC Electrical Characteristics.
Added RPU in DC Electrical Characteristics.
Replaced TRFVAR with DTR and DTF in AC Electrical Characteristics.
Added definitions for rise and fall time variation, crossing point variation in
AC Electrical Characteristics.
Reduced cycle-to-cycle jitter spec to 75ps in AC Electrical Characteristics.
04/03/2009 Removed “Preliminary” from datasheet title and headings
Added “max” to crystal ESR spec.
Changed “LVDS Down Device” to “LVDS Device” in Table 8 and Figure 4.
Document Number: 001-46117 Rev. *C
Page 9 of 10
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CY24293
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
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© Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-46117 Rev. *C
Revised April 02, 2009
Page 10 of 10
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