CY29942AXIT [CYPRESS]
Low Skew Clock Driver, 29942 Series, 18 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, LQFP-32;
| 型号： | CY29942AXIT |
| 厂家： | 
CYPRESS |
| 描述： | Low Skew Clock Driver, 29942 Series, 18 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总7页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY29942
2.5V or 3.3V, 200 MHz, 1:18 Clock
Distribution Buffer
Features
Description
■ 200 MHz Clock Support
The CY29942 is a low voltage 200 MHz clock distribution buffer
with an LVCMOS or LVTTL compatible input clock. All other
control inputs are LVCMOS/LVTTL compatible. The eighteen
outputs are 2.5V or 3.3V LVCMOS or LVTTL compatible and can
drive 50Ω series or parallel terminated transmission lines. For
series terminated transmission lines, each output can drive one
or two traces giving the devices an effective fanout of 1:36. Low
output-to-output skews make the CY29942 an ideal clock distri-
bution buffer for nested clock trees in the most demanding of
synchronous systems.
■ 2.5V or 3.3V Operation
■ LVCMOS/LVTTL Clock Input
■ LVCMOS-/LVTTL-Compatible Inputs
■ 18 Clock Outputs: Drive up to 36 Clock Lines
■ 110 ps Typical Output-to-output Skew
■ Output Enable Control
■ Pin Compatible with MPC942C
■ Available in Industrial and Commercial
■ 32-pin LQFP package
Logic Block Diagram
VDD
18
TCLK
OE
Q0-Q17
Cypress Semiconductor Corporation
Document #: 38-07284 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 10, 2009
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CY29942
Pinouts
Figure 1. Pin Configuration
VSS
VSS
TCLK
NC
OE
NC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Q6
Q7
Q8
VDD
Q9
Q10
Q11
VSS
CY29942
VDD
VDD
Table 1. Pin Description[1]
Pin
3
Name
TCLK
OE
I/O
Description
Input, PD External Reference/Test Clock Input
5
Input, PU Output Enable. When HIGH, all outputs are enabled. When set LOW,
the outputs are at high impedance.
9, 10, 11, 13, 14, 15, 18, 19, 20,
22, 23, 24, 26, 27, 28, 30, 31, 32
Q(17:0)
Output
Clock Outputs
7, 8, 16, 21, 29
1, 2, 12, 17, 25
4, 6
VDD
VSS
NC
3.3V or 2.5V Power Supply
Common Ground
No Connection
Note
1. PD = Internal Pull-Down, PU = Internal Pull-up.
Document #: 38-07284 Rev. *D
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CY29942
Maximum Ratings[2]
Maximum Input Voltage Relative to VSS:............. VSS – 0.3V
Maximum Input Voltage Relative to VDD:............. VDD + 0.3V
Storage Temperature:......................................–65° to 150°C
Operating Temperature:.....................................–40° to 85°C
Maximum ESD protection............................................... 2 kV
Maximum Power Supply:................................................ 5.5V
Maximum Input Current:............................................ ±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For proper
operation, Vin and Vout should be constrained to the range:
VSS < (Vin or Vout) < VDD
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
DC Parameters
VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, Over the specified temperature range.
Parameter
Description
Input Low Voltage
Input High Voltage
Input Low Current[3]
Input High Current[3]
Output Low Voltage[4]
Conditions
Min
VSS
2.0
Typ
Max
0.8
Unit
V
VIL
VIH
IIL
VDD
–200
200
0.5
V
µA
µA
V
IIH
VOL
VOH
IOL = 20 mA
Output High Voltage[4] IOH = –20 mA, VDDC = 3.3V
2.4
2.0
V
I
OH = –16 mA, VDDC = 2.5V
IDDQ
IDD
Quiescent Supply
Current
5
7
mA
mA
Dynamic Supply
Current
VDD = 3.3V, Outputs at 150 MHz,
CL = 15 pF
285
335
200
240
VDD = 3.3V, Outputs at 200 MHz,
CL = 15 pF
VDD = 2.5V, Outputs at 150 MHz,
CL = 15 pF
VDD = 2.5V, Outputs at 200 MHz,
CL = 15 pF
Zout
Output Impedance
Input Capacitance
VDD = 3.3V
8
12
15
4
16
20
Ω
VDD = 2.5V
10
Cin
pF
Notes
2. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. Driving series or parallel terminated 50Ω (or 50Ω to V /2) transmission lines.
DD
Document #: 38-07284 Rev. *D
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CY29942
AC Parameters
VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, Over the specified temperature range[5]
Parameter
Fmax
Description
Input Frequency
TTL_CLK to Q Delay[6, 7]
Conditions
Min
Typ
Max
200
3.8
4.4
55
Unit
MHz
ns
Tpd
VDD = 3.3V
1.8
2.3
45
3.3
3.8
VDD = 2.5V
FoutDC
Tskew
Output Duty Cycle[6, 7, 8]
Output-to-Output Skew[6, 7]
Part-to-Part Skew[9]
Measured at VDD/2
%
ps
ns
110
200
1.0
1.3
600
1.1
Tskew(pp)
VDD = 3.3V
V
DD = 2.5V
Tskew(pp)
Tr/Tf
Part-to-Part Skew[10]
Output Clocks Rise/Fall Time[6, 7] 0.8V to 2.0V, VDD = 3.3V
ps
ns
0.2
0.5V to 1.8V, VDD = 2.5V
Notes
5. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
6. Outputs driving 50Ω transmission lines.
7. See Figure 2.
8. 50% input duty cycle.
9. Across temperature and voltage ranges, includes output skew.
10. For a specific temperature and voltage, includes output skew.
Figure 2. LVCMOS_CLK CY29942 Test Reference for VCC = 3.3V and VCC = 2.5V
CY29942 DUT
Zo = 50 ohm
Zo = 50 ohm
Pulse
Generator
Z = 50 ohm
RT = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 3. LVCMOS Propagation Delay (TPD) Test Reference
VCC
LVCMOS_CLK
VCC /2
GND
VCC
Q
VCC /2
tPD
GND
Document #: 38-07284 Rev. *D
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CY29942
Figure 4. Output Duty Cycle (FoutDC)
VCC
VCC /2
GND
tP
T0
DC = tP / T0 x 100%
Figure 5.
Figure 6. Output-to-Output Skew tsk(0)
VCC
VCC /2
GND
VCC
VCC /2
GND
tSK(0)
Figure 7.
Ordering Information
Part Number
CY29942AI
Package Type
Production Flow
32-Pin LQFP
Industrial,–40° to 85°C
Industrial, –40° to 85°C
Commercial, 0° to 70°C
CY29942AIT
CY29942AC
32-Pin LQFP – Tape and Reel
32-Pin LQFP
Pb-free
CY29942AXI
CY29942AXIT
CY29942AXC
CY29942AXCT
32-Pin LQFP
Industrial, –40° to 85°C
Industrial, –40° to 85°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
32-Pin LQFP – Tape and Reel
32-Pin LQFP
32-Pin LQFP – Tape and Reel
Document #: 38-07284 Rev. *D
Page 5 of 7
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CY29942
Package Drawing and Dimensions
32-Pin Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14
51-85088-*B
Document #: 38-07284 Rev. *D
Page 6 of 7
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CY29942
Document History Page
Document Title: CY29942 2.5V or 3.3V, 200 MHz, 1:18 Clock Distribution Buffer
Document Number: 38-07284
Orig. of Submission
Revision
ECN
Description of Change
Change
Date
**
111095
116777
122876
334117
BRK
02/07/02 New datasheet
*A
*B
*C
HWT
RBI
08/14/02 Added a Commercial Temp. Range in the Ordering Information
12/21/02 Add power up requirements to maximum rating information.
RGL
See ECN Added Lead-free devices
Added typical value for output-output skew
*D
2761988
KVM
09/10/09 Ordering Information table: fixed typo and removed obsolete CY29942ACT.
Changed Lead-free to Pb-free.
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2002-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07284 Rev. *D
Revised September 10, 2009
Page 7 of 7
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