CY29942 [CYPRESS]
2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer; 2.5V或3.3V ， 200MHz的， 1:18时钟分配缓冲器
| 型号： | CY29942 |
| 厂家： | 
CYPRESS |
| 描述： | 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer |
| 文件： | 总7页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
42
CY29942
2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
Features
Description
• 200-MHz clock support
• 2.5V or 3.3V operation
The CY29942 is a low-voltage 200-MHz clock distribution buff-
er with an LVCMOS or LVTTL compatible input clock. All other
control inputs are LVCMOS/LVTTL compatible. The eighteen
outputs are 2.5V or 3.3V LVCMOS or LVTTL compatible and
can drive 50 Ω series or parallel terminated transmission lines.
For series terminated transmission lines, each output can
drive one or two traces giving the devices an effective fanout
of 1:36. Low output-to-output skews make the CY29942 an
ideal clock distribution buffer for nested clock trees in the most
demanding of synchronous systems.
• LVCMOS/LVTTL clock input
• LVCMOS-/LVTTL-compatible inputs
• 18 clock outputs: drive up to 36 clock lines
• 200 ps max. output-to-output skew
• Output Enable control
• Pin compatible with MPC942C
• Available in Industrial and Commercial
• 32-pin LQFP package
Block Diagram
Pin Configuration
VDD
VSS
VSS
TCLK
NC
OE
NC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Q6
Q7
Q8
VDD
Q9
Q10
Q11
VSS
18
TCLK
Q0-Q17
CY29942
OE
VDD
VDD
Cypress Semiconductor Corporation
Document #: 38-07284 Rev. *B
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised December 21, 2002
CY29942
Pin Description[1]
Pin
3
Name
PWR
I/O
Description
TCLK
OE
I, PD External Reference/Test Clock Input
5
I, PU Output Enable. When HIGH, all the outputs are enabled. When set
LOW, the outputs are at high impedance.
9, 10, 11, 13,
14,15,18,19,
20,22,23,24,
26,27,28,30,
31, 32
Q(17:0)
VDD
O
Clock Outputs
7, 8, 16, 21,
29
VDD
VSS
NC
3.3V or 2.5V Power Supply
Common Ground
1, 2, 12, 17,
25
4, 6
No Connection
Note:
1. PD = Internal Pull-Down, PU = Internal Pull-up.
Document #: 38-07284 Rev. *B
Page 2 of 7
CY29942
Maximum Ratings[2]
Maximum Input Voltage Relative to VSS: ............. VSS – 0.3V
Maximum Input Voltage Relative to VDD:............. VDD + 0.3V
Storage Temperature: ................................–65°C to + 150°C
Operating Temperature:................................–40°C to +85°C
Maximum ESD protection ...............................................2 kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current: ............................................±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any volt-
age higher than the maximum rated voltages to this circuit. For
proper operation, Vin and Vout should be constrained to the
range:
VSS < (Vin or Vout) < VDD
Unused inputs must always be tied to an appropriate logic volt-
age level (either VSS or VDD).
DC Parameters: VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, Over the specified temperature range.
Parameter
Description
Input Low Voltage
Input High Voltage
Input Low Current[3]
Input High Current[3]
Output Low Voltage[4]
Conditions
Min.
VSS
2.0
Typ.
Max.
0.8
Unit
V
VIL
VIH
IIL
VDD
–200
200
V
µA
µA
V
IIH
VOL
IOL = 20 mA
0.5
VOH
Output High Voltage[4] IOH = –20 mA, VDDC = 3.3V
2.4
2.0
V
IOH = –16 mA, VDDC = 2.5V
IDDQ
IDD
Quiescent Supply
Current
5
7
mA
mA
Dynamic Supply
Current
VDD = 3.3V, Outputs @ 150 MHz,
CL = 15 pF
285
335
200
240
VDD = 3.3V, Outputs @ 200 MHz,
CL = 15 pF
VDD = 2.5V, Outputs @ 150 MHz,
CL = 15pF
VDD = 2.5V, Outputs @ 200 MHz,
CL = 15pF
Zout
Output Impedance
Input Capacitance
VDD = 3.3V
VDD = 2.5V
8
12
15
4
16
20
Ω
10
Cin
pF
Notes:
2. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines.
Document #: 38-07284 Rev. *B
Page 3 of 7
CY29942
AC Parameters[5]: VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, Over the specified temperature range
Parameter
Fmax
Description
Input Frequency
TTL_CLK to Q Delay[6, 7]
Conditions
Min.
Typ.
Max.
200
3.8
Unit
MHz
ns
Tpd
VDD = 3.3V
DD = 2.5V
1.8
2.3
45
3.3
3.8
V
4.4
FoutDC
Tskew
Output Duty Cycle[6, 7, 8]
Output-to-Output Skew[6, 7]
Part-to-Part Skew[9]
Measured at VDD/2
55
%
ps
ns
200
1.0
Tskew(pp)
VDD = 3.3V
VDD = 2.5V
1.3
Tskew(pp)
Tr/Tf
Part-to-Part Skew[10]
600
1.1
ps
ns
Output Clocks Rise/Fall
Time[6, 7]
0.8V to 2.0V, VDD = 3.3V
0.5V to 1.8V, VDD = 2.5V
0.2
Notes:
5. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
6. Outputs driving 50Ω transmission lines.
7. See Figure 1.
8. 50% input duty cycle.
9. Across temperature and voltage ranges, includes output skew.
10. For a specific temperature and voltage, includes output skew.
CY29942 DUT
Zo = 50 ohm
Zo = 50 ohm
Pulse
Generator
Z = 50 ohm
RT = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 1. LVCMOS_CLK CY29942 Test Reference for VCC = 3.3V and VCC = 2.5V
VCC
LVCMOS_CLK
VCC /2
GND
VCC
Q
VCC /2
tPD
GND
Figure 2. LVCMOS Propagation Delay (TPD) Test Reference
VCC
VCC /2
tP
GND
T0
DC = tP / T0 x 100%
Figure 3. Output Duty Cycle (FoutDC)
Document #: 38-07284 Rev. *B
Page 4 of 7
CY29942
VCC
VCC /2
GND
VCC
VCC /2
GND
tSK(0)
Figure 4. Output-to-Output Skew tsk(0)
Document #: 38-07284 Rev. *B
Page 5 of 7
CY29942
Ordering Information
Part Number
CY29942AI
Package Type
32 Pin LQFP
Production Flow
Industrial, -40°C to +85°C
Industrial, -40°C to +85°C
Commercial, 0°C to +70°C
Commercial, 0°C to +70°C
CY29942AIT
CY29942AC
CY29942ACT
32 Pin LQFP - Tape and Reel
32 Pin LQFP
32 Pin LQFP - Tape and Reel
Package Drawing and Dimensions
32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14
51-85088-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07284 Rev. *B
Page 6 of 7
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY29942
Revision History
Document Title: CY29942 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
Document Number: 38-07284
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
111095
116777
122876
Description of Change
02/07/02
08/14/02
12/21/02
BRK
HWT
RBI
New data sheet
*A
Added a Commercial Temp. Range in the Ordering Information
Add power up requirements to maximum rating information.
*B
Document #: 38-07284 Rev. *B
Page 7 of 7
相关型号：
CY29942AXIT
Low Skew Clock Driver, 29942 Series, 18 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, LQFP-32
CYPRESS
©2020 ICPDF网 联系我们和版权申明