CY2PP3210AI [CYPRESS]
Dual 1:5 Differential Clock / Data Fanout Buffer; 双1 ： 5差分时钟/数据扇出缓冲器
| 型号： | CY2PP3210AI |
| 厂家： | 
CYPRESS |
| 描述： | Dual 1:5 Differential Clock / Data Fanout Buffer |
| 文件： | 总9页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FastEdge™ Series
CY2PP3210
Dual 1:5 Differential Clock/Data Fanout Buffer
Features
Functional Description
The CY2PP3210 is a low-skew, low propagation delay dual
• Dual sets of five ECL/PECL differential outputs
• Two ECL/PECL differential inputs
• Hot-swappable/-insertable
• 50 ps output-to-output skew
• 150 ps device-to-device skew
1-to-5 differential fanout buffer targeted to meet the require-
ments of high-performance clock and data distribution applica-
tions. The device is implemented on SiGe technology and has
a fully differential internal architecture that is optimized to
achieve low signal skews at operating frequencies of up to 1.5
GHz.
The device features two differential input paths that are differ-
ential internally. The CY2PP3210 may function not only as a
differential clock buffer but also as a signal-level translator and
fanout distributing a single-ended signal. An external bias pin,
VBB, is provided for this purpose. In such an application, the
VBB pin should be connected to either one of the CLKA# or
CLKB# inputs and bypassed to ground via a 0.01-µF capacitor.
Traditionally, in ECL, it is used to provide the reference level
to a receiving single-ended input that might have a differential
bias point.
Since the CY2PP3210 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in
communication systems. Furthermore, advanced circuit
design schemes, such as internal temperature compensation,
ensure that the CY2PP3210 delivers consistent performance
over various platforms.
• 500 ps propagation delay (typical)
• 0.8 ps RMS period jitter (max.)
• 1.5 GHz Operation (2.2 GHz max. toggle frequency)
• PECL mode supply range: VCC = 2.5V± 5% to 3.3V±5%
with VEE = 0V
• ECL mode supply range: VE E = –2.5V± 5% to –3.3V±5%
with VCC = 0V
• Industrial temperature range: –40°C to 85°C
• 32-pin 1.4-mm TQFP package
• Temperature compensation like 100K ECL
• Pin compatible with MC100ES6210
Block Diagram
Pin Configuration
QA0
QA0#
QA1
QA1#
VCC
CLKA
QA2
QA2#
CLKA#
VEE
QA3
1
2
3
4
5
6
7
8
VCC
NC
CLKA
CLKA#
VBB
CLKB
CLKB#
VEE
QA3
QA3#
QA4
QA4#
QB0
QB0#
QB1
QB1#
24
23
22
21
20
19
18
17
QA3#
QA4
QA4#
CY2PP3210
QB0
QB0#
QB1
VCC
QB1#
CLKB
QB2
QB2#
CLKB#
VEE
QB3
QB3#
QB4
QB4#
VBB
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-07508 Rev.*C
Revised July 28, 2004
FastEdge™ Series
CY2PP3210
Pin Definitions[1, 2, 3]
Pin
Name
NC
I/O[1]
Type
Description
2
No connect.
ECL/PECL ECL/PECL Differential Input Clocks.
3
CLKA,
I,PD
4
5
6
CLKA# I,PD/PU ECL/PECL ECL/PECL Differential Input Clocks.
VBB[3]
CLKB,
O
Bias
Reference Voltage Output.
I,PD
ECL/PECL ECL/PECL Differential Input Clocks.
7
8
CLKB# I,PD/PU ECL/PECL ECL/PECL Differential Input Clocks.
VEE[2]
VCC
–PWR
+PWR
Power
Power
Negative Supply.
Positive Supply.
1,9,16,25,32
31,29,27,24,22
30,28,26,23,21
20,18,15,13,11
19,17,14,12,10
QA(0:4)
QA#(0:4)
QB(0:4)
QB#(0:4)
O
O
O
O
ECL/PECL True output
ECL/PECL Complement output
ECL/PECL True output
ECL/PECL Complement output
Governing Agencies
The following agencies provide specifications that apply to the
CY2PP3210. The agency name and relevant specification is
listed below in Table 2.
Table 1.
Agency Name
JEDEC
Specification
JESD 020B (MSL)
JESD 51 (Theta JA)
JESD 8–2 (ECL)
JESD 65–B (skew,jitter)
Mil-Spec
883E Method 1012.1 (Thermal Theta JC)
Notes:
1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power
2. In ECL mode (negative power supply mode), V is either –3.3V or –2.5V and V is connected to GND (0V). In PECL mode (positive power supply mode),
EE
CC
V
is connected to GND (0V) and V is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (V
)
EE
CC
CC
and are between V and V
.
EE
CC
3. V is available for use for single-ended bias mode for |3.3V| supplies (not |2.5V|).
BB
Document #: 38-07508 Rev.*C
Page 2 of 9
FastEdge™ Series
CY2PP3210
Absolute Maximum Ratings
Parameter
VCC
VEE
TS
TJ
ESDh
MSL
Description
Condition
Non-Functional
Non-Functional
Non-Functional
Non-Functional
Human Body Model
Min.
–0.3
-4.6
–65
Max.
4.6
0.3
+150
150
Unit
V
V
°C
°C
V
N.A.
gates
Positive Supply Voltage
Negative Supply Voltage
Temperature, Storage
Temperature, Junction
ESD Protection
2000
3
50
Moisture Sensitivity Level
Gate Count Total Number of Used Gates
Assembled Die
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Operating Conditions
Parameter
IBB
LUI
TA
ØJc
ØJa
IEE
CIN
LIN
Description
Output Reference Current
Latch Up Immunity
Temperature, Operating Ambient
Dissipation, Junction to Case
Dissipation, Junction to Ambient
Maximum Quiescent Supply Current
Input pin capacitance
Condition
Relative to VBB
Functional, typical
Functional
Min.
–
Max.
|200|
Unit
uA
mA
°C
°C/W
°C/W
mA
pF
nH
V
100
–40
+85
Functional
29[4]
76[4]
Functional
VEE pin[5]
–
–
130
3
1
Pin Inductance
Input Voltage
[6]
VIN
Relative to VCC
Relative to VCC
Relative to VCC
–0.3
–0.3
VCC + 0.3
VCC – 2
VCC + 0.3
[6]
VTT
VOUT
IIN
Output Termination Voltage
Output Voltage
V
V
uA
[6]
Input Current[7]
VIN = VIL, or VIN = VIH
l150l
PECL DC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
VCC
Operating Voltage
2.5V ± 5%, VEE = 0.0V
2.375
2.625
V
3.3V ± 5%, VEE = 0.0V
3.135
3.465
V
VCMR
VOH
VOL
Differential Cross Point Voltage[8]
Output High Voltage
Differential operation
IOH = –30 mA[9]
1.2
VCC – 1.25
VCC
VCC – 0.7
V
V
Output Low Voltage
I
OL = –5 mA[9]
V
CC = 3.3V ± 5%
CC = 2.5V ± 5%
VCC – 1.995
VCC – 1.5
V
V
V
V
V
V
V
CC –1.995
VCC – 1.3
VIH
VIL
VBB
Input Voltage, High
Input Voltage, Low
Output Reference Voltage
Single-ended operation
Single-ended operation
VCC – 1.165
VCC – 1.945 [10] VCC – 1.625
VCC – 1.620 VCC – 1.220
VCC – 0.880 [10]
[3]
[6]
Relative to VCC
Notes:
4. Theta JA EIA JEDEC 51 test board conditions (typical value); Theta JC 883E Method 1012.1
5. Power Calculation: V * I +0.5 (I + I ) (V – V ) (number of differential outputs used); I does not include current going off chip.
CC
EE
OH
OL
OH
OL
EE
6. where V is 3.3V±5% or 2.5V±5%
CC
7. Inputs have internal pull-up/pull-down or biasing resistors which affect the input current.
8. Refer to Figure 1
9. Equivalent to a termination of 50Ω to VTT. I
=(V
-V )/50; I
=(V
-V )/50; I
=(V
-V )/50; I
=(V
-V )/50;
OLMAX TT
OHMIN
OHMIN TT
OHMAX
OHMAX TT
OLMIN
OLMIN TT
OLMAX
10. V will operate down to V ; V will operate up to V
CC
IL
EE
IH
Document #: 38-07508 Rev.*C
Page 3 of 9
FastEdge™ Series
CY2PP3210
ECL DC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
VEE
Negative Power Supply
–2.5V ± 5%, VCC = 0.0V
–2.625
–2.375
V
–3.3V ± 5%, VCC = 0.0V
–3.465
–3.135
VCMR
VOH
VOL
Differential cross point voltage[8]
Output High Voltage
Differential operation
IOH = –30 mA[9]
VEE + 1.2
–1.25
0V
–0.7
V
V
Output Low Voltage
I
OL = –5 mA[9]
V
EE = –3.3V ± 5%
–1.995
–1.995
–1.165
–1.945 [10]
– 1.620
–1.5
–1.3
V
V
EE = –2.5V ± 5%
VIH
VIL
VBB
Input Voltage, High
Input Voltage, Low
Output Reference Voltage
Single-ended operation
Single-ended operation
–0.880 [10]
–1.625
V
V
V
[3]
– 1.220
AC Electrical Specifications
Parameter
VPP
FCLK
TPD
Description
Condition
Differential operation
50% duty cycle Standard load
660 MHz [11]
Min.
0.1
Max.
1.3
1.5
Unit
V
GHz
ps
Differential Input Voltage[8]
Input Frequency
Propagation Delay CLKA or CLKB to
280
750
Output pair
Vo
Output Voltage (peak-to-peak; see
Figure 2)
–
< 1 GHz
0.375
V
VCMRO
tsk(0)
tsk(PP)
TPER
Output Common Voltage Range (typ.)
Output-to-output Skew
Part-to-Part Output Skew
Output Period Jitter (rms)[12]
Output Pulse Skew[13]
VCC – 1.425
V
660 MHz [11], See Figure 3
660 MHz [11]
–
–
–
–
50
150
0.8
50
ps
ps
ps
ps
660 MHz [11]
tsk(P)
660 MHz [11], See Figure 3
TR,TF
Output Rise/Fall Time (see Figure 2)
660 MHz 50% duty cycle
Differential 20% to 80%
0.08
0.3
ns
Timing Definitions
VCC
VIH
VCMR Max = VCC
VPP range
0.1V - 1.3V
VPP
VCMR
VIL
VCMR Min = VEE + 1.2
VEE
Figure 1. PECL/ECL Input Waveform Definitions
Notes:
11. 50% duty cycle; standard load; differential operation
12. For 3.3V supplies. Jitter measured differentially using an Agilent 8133A Pulse Generator with an 8500A LeCroy Wavemaster Oscilloscope using at least 10,000
data points
13. Output pulse skew is the absolute difference of the propagation delay times: | t
– t
|.
PHL
PLH
Document #: 38-07508 Rev.*C
Page 4 of 9
FastEdge™ Series
CY2PP3210
tr, tf,
VO
20-80%
Figure 2. ECL/LVPECL Output
I n p u t
C l o c k
V P P
T P L H ,
T P D
T P H L
O u t p u t
C l o c k
V O
t S K ( O )
A n o t h e r
O u t p u t
C l o c k
Figure3. PropagationDelay(TPD), outputpulseskew(|tPLH-tPHL|), andoutput-to-outputskew(tSK(O)
)
for both CLKA or CLKB to Output Pair, PECL/ECL to PECL/ECL
Test Configuration
Standard test load using a differential pulse generator and
differential measurement instrument.
V T T
V T T
R T = 50 ohm
R T = 50 ohm
5 "
P ulse
G enerator
Z o = 50 ohm
Z o = 50 ohm
Z = 50 ohm
5 "
D U T
R T = 50 ohm
C Y 2P P 3210
R T = 50 ohm
V T T
V T T
Figure 4. CY2PP318 AC Test Reference
Document #: 38-07508 Rev.*C
Page 5 of 9
FastEdge™ Series
CY2PP3210
Applications Information
Termination Examples
V T T
C Y 2 P P 3 2 1 0
V C C
R T = 5 0 o h m
5 "
Z o = 50 o hm
5 "
R T = 5 0 o h m
V T T
V E E
Figure 5. Standard LVPECL – PECL Output Termination
V T T
C Y 2 P P 3 2 1 0
R T = 5 0 o h m
V C C
5 "
Z o = 5 0 o h m
5 "
V T T
R T = 5 0 o h m
V B B (3 .3 V )
V E E
Figure 6. Driving a PECL/ECL Single-ended Input
3 .3 V
C Y 2 P P 3 2 1 0
V C C = 3 .3 V
1 2 0 o h m
L V D S
5 "
3 3 o h m
Z o = 5 0 o h m
(2 p la c e s )
5 "
1 2 0 o h m
5 1 o h m
(2 p la c e s )
3 .3 V
L V P E C L to
L V D S
V E E = 0 V
Figure 7. Low-voltage Positive Emitter-coupled Logic (LVPECL) to a Low-voltage Differential Sig-
naling (LVDS) Interface
Document #: 38-07508 Rev.*C
Page 6 of 9
FastEdge™ Series
CY2PP3210
VDD-2
X
VCC
Y
Z
One output is shown for clarity
Figure 8. Termination for LVPECL to HTSL interface for VCC=2.5V would use X=50 Ohms, Y=2300 Ohms, and Z=1000
Ohms. See application note titled, “PECL Translation, SAW Oscillators, and Specs” for other signalling standards
and supplies.
Ordering Information
Part Number
CY2PP3210AI
CY2PP3210AIT
Package Type
Product Flow
Industrial, –40° to 85°C
Industrial, –40° to 85°C
32-pin TQFP
32-pin TQFP – Tape and Reel
Document #: 38-07508 Rev.*C
Page 7 of 9
FastEdge™ Series
CY2PP3210
Package Drawing and Dimension
32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14
Dimensions are in mm
51-85088-*B
FastEdge is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
Document #: 38-07508 Rev.*C
Page 8 of 9
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
FastEdge™ Series
CY2PP3210
Document History Page
Document Title: CY2PP3210 FastEdge™ Series Dual 1:5 Differential Clock/Data Fanout Buffer
Document Number: 38-07508
Issue
Date
02/12/03
Orig. of
Change
RGL
REV.
**
*A
ECN NO.
122396
125458
Description of Change
New Data Sheet
04/17/03
RGL
Corrected pins 26 to 31 from Q2#, Q2, Q1#, Q1, Q0#, Q0 to QA2#, QA2,
QA1#, QA1,QA0#, QA0 in the Pin Configuration diagram
Changed pins 9, 16, 25, 32 from VCC to VCCO
Changed the title to FastEdge™ Series Dual 1:5 Differential Clock/Data
Fanout Buffer
*B
*C
229370
247616
See ECN
RGL
Supplied data to all the TBD’s to match the device
See ECN RGL/GGK Changed VOH and VOL to match the Char Data
Document #: 38-07508 Rev.*C
Page 9 of 9
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