CY2XP22ZXC [CYPRESS]
Crystal to LVPECL Clock Generator; 水晶LVPECL时钟发生器
| 型号： | CY2XP22ZXC |
| 厂家： | 
CYPRESS |
| 描述： | Crystal to LVPECL Clock Generator |
| 文件： | 总8页 (文件大小：234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
CY2XP22
Crystal to LVPECL Clock Generator
Features
■
■
■
■
■
One LVPECL Output Pair
■
■
■
Pb-free 8-Pin TSSOP Package
Selectable Frequency Multiplication: x2.5 or x5
External Crystal Frequency: 25.0 MHz
Output Frequency: 62.5 MHz or 125 MHz
Supply Voltage: 3.3V or 2.5V
Commercial and Industrial Temperature Ranges
Functional Description
Low RMS Phase Jitter at 125 MHz, using 25 MHz Crystal
(1.875 MHz to 20 MHz): 0.4 ps (Typical)
The CY2XP22 is a PLL (Phase Locked Loop) based high
performance clock generator that uses an external reference
crystal. It is specifically targeted at FibreChannel and Gigabit
Ethernet applications. It produces a selectable output frequency
that is 2.5 or 5 times the crystal frequency. With a 25 MHz crystal,
the user can select either a 62.5 MHz or 125 MHz output. It uses
Cypress’s low noise VCO technology to achieve less than 1 ps
typical RMS phase jitter. The CY2XP22 has a crystal oscillator
interface input and one LVPECL output pair.
■
Phase Noise at 125 MHz:
Offset
1 kHz
Noise Power
–117 dBc/Hz
–126 dBc/Hz
–131 dBc/Hz
–131 dBc/Hz
10 kHz
100 kHz
1 MHz
Logic Block Diagram
XIN
External
Crystal
CLK
CRYSTAL
OSCILLATOR
LOW -N OISE
PLL
OUTPUT
DIVIDER
CLK#
XOUT
F_SEL
Pinouts
Figure 1. Pin Diagram - 8-Pin TSSOP
VDD
VSS
XOUT
XIN
1
2
3
4
8
7
6
5
VDD
CLK
CLK#
F_SEL
Table 1. Pin Definition - 8-Pin TSSOP
Pin Number
Pin Name
VDD
I/O Type
Description
1, 8
2
Power
Power
3.3V or 2.5V power supply
Ground
VSS
3, 4
5
XOUT, XIN
F_SEL
XTAL output and input
CMOS input
Parallel resonant crystal interface
Frequency Select: see Frequency Table
Differential Clock Output
6,7
CLK#, CLK
LVPECL output
Cypress Semiconductor Corporation
Document #: 001-10229 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 15, 2009
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PRELIMINARY
CY2XP22
Frequency Table
Inputs
PLL Multiplier Value
Output Frequency (MHz)
Crystal Frequency (MHz)
F_SEL
25
0
1
5
125
2.5
62.5
Absolute Maximum Conditions
Parameter
Description
Conditions
Min
–0.5
–0.5
–65
Max
Unit
V
VDD
Supply Voltage
4.4
VDD + 0.5
150
[1]
VIN
Input Voltage, DC
Relative to VSS
V
TS
Temperature, Storage
Temperature, Junction
Non operating
°C
°C
V
TJ
135
ESDHBM
UL–94
ESD Protection, Human Body Model
Flammability Rating
JEDEC STD 22-A114-B
At 1/8 in.
2000
V–0
[2]
ΘJA
Thermal Resistance, Junction to Ambient 0 m/s airflow
100
91
°C/W
1 m/s airflow
2.5 m/s airflow
87
Operating Conditions
Parameter
Description
Min
3.135
2.375
0
Max
3.465
2.625
70
Unit
V
VDD
TA
3.3V Supply Voltage
2.5V Supply Voltage
V
Ambient Temperature, Commercial
Ambient Temperature, Industrial
°C
°C
ms
–40
85
TPU
Power up time for all VDD to reach minimum specified voltage (ensure power ramps
is monotonic)
0.05
500
DC Electrical Characteristics
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
[3]
IDD
Operating Supply Current with
output terminated
VDD = 3.465V, FOUT = 125 MHz,
output terminated
–
–
150
mA
VDD = 2.625V, FOUT = 125 MHz,
output terminated
–
–
–
–
–
–
145
mA
V
VOH
LVPECL Output High Voltage
LVPECL Output Low Voltage
VDD = 3.3V or 2.5V, RTERM = 50Ω to VDD –1.15
DD – 2.0V
VDD –0.75
VDD –1.625
1000
V
VOL
VDD = 3.3V or 2.5V, RTERM = 50Ω to VDD –2.0
DD – 2.0V
V
V
VOD1
VOD2
LVPECL Peak-to-Peak Output
Voltage Swing
VDD = 3.3V or 2.5V, RTERM = 50Ω to
600
mV
mV
V
DD – 2.0V
LVPECL Output Voltage Swing
V
1.5V
DD = 2.5V, RTERM = 50Ω to VDD
–
500
1000
(VOH - VOL
)
Notes
1. The voltage on any input or IO pin cannot exceed the power pin during power up.
2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of
copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
3.
I
includes approximately 24 mA of current that is dissipated externally in the output termination resistors.
DD
Document #: 001-10229 Rev. *C
Page 2 of 8
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PRELIMINARY
CY2XP22
DC Electrical Characteristics (continued)
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VOCM
LVPECL Output Common Mode VDD = 2.5V, RTERM = 50Ω to VDD
–
1.2
–
–
V
Voltage (VOH + VOL)/2
1.5V
VIH
VIL
IIH
Input High Voltage, F_SEL
Input Low Voltage, F_SEL
Input High Current, F_SEL
Input Low Current, F_SEL
Input Capacitance, F_SEL
Pin Capacitance, XIN & XOUT
0.7*VDD
–0.3
–
–
–
VDD + 0.3
0.3*VDD
115
V
V
F_SEL = VDD
F_SEL = VSS
–
µA
µA
pF
pF
IIL
–50
–
–
CIN
CINX
15
4.5
AC Electrical Characteristics[4]
Parameter
FOUT
Description
Output Frequency
Conditions
Min
62.5
–
Typ
–
Max
125
–
Unit
MHz
ps
TR, TF
TJitter(φ)
TDC
Output Rise or Fall Time
RMS Phase Jitter (Random)
Output Duty Cycle
20% to 80% of full output swing
125 MHz, (1.875–20 MHz)
500
0.4
50
–
–
–
ps
Measured at zero crossing point
Time for CLK to reach valid
48
–
52
10
%
TLOCK
Startup Time
ms
frequency measured from the time
VDD = VDD(min.) or from F_SEL
changing
Recommended Crystal Specifications[5]
Parameter
Description
Min
Max
Unit
Mode
F
Mode of Oscillation
Frequency
Fundamental
25
–
25
50
7
MHz
Ω
ESR
C0
Equivalent Series Resistance
Shunt Capacitance
–
pF
Notes
4. Not 100% tested, guaranteed by design and characterization.
5. Characterized using an 18 pF parallel resonant crystal.
Document #: 001-10229 Rev. *C
Page 3 of 8
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PRELIMINARY
CY2XP22
Parameter Measurements
Figure 2. 3.3V Output Load AC Test Circuit
2V
SCOPE
Z = 50Ω
Z = 50Ω
VDD
LVPECL
CLK
50Ω
50Ω
CLK#
VSS
-1.3V +/- 0.165V
Figure 3. 2.5V Output Load AC Test Circuit
2V
SCOPE
Z = 50Ω
Z = 50Ω
VDD
LVPECL
CLK
50Ω
50Ω
CLK#
VSS
-0.5V +/- 0.125V
Figure 4. Output DC Parameters
VA
CLK
VOD
VOCM = (VA + VB)/2
CLK#
VB
Figure 5. Output Rise and Fall Time
CLK#
80% 80%
20%
20%
CLK
TR
TF
Document #: 001-10229 Rev. *C
Page 4 of 8
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PRELIMINARY
CY2XP22
Figure 6. RMS Phase Jitter
Phase noise
Noise
Power
Phase noise mask
Offset Frequency
f2
f1
Area Under the Masked Phase Noise Plot
RMS Jitter =
Figure 7. Output Duty Cycle
CLK
TPW
TDC
=
TPERIOD
CLK#
TPW
TPERIOD
Document #: 001-10229 Rev. *C
Page 5 of 8
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PRELIMINARY
CY2XP22
Application Information
Figure 9. LVPECL Output Termination
Power Supply Filtering Techniques
As in any high speed analog circuitry, noise at the power supply
pins can degrade performance. To achieve optimum jitter perfor-
mance, use good power supply isolation practices. Figure 8 illus-
trates a typical filtering scheme. Since all the current flows
through pin 1, the resistance and inductance between this pin
and the supply is minimized. A 0.01 or 0.1 µF ceramic chip
capacitor is also located close to this pin to provide a short and
low impedance AC path to ground. A 1 to 10 µF ceramic or
tantalum capacitor is located in the general vicinity of this device
and may be shared with other devices.
3.3V
125Ω
125Ω
Z0 = 50Ω
CLK
IN
Z0 = 50Ω
CLK#
84Ω
84Ω
Figure 8. Power Supply Filtering
Crystal Interface
V
DD
(Pin 8)
The CY2XP22 is characterized with 18 pF parallel resonant
crystals. The capacitor values shown in Figure 10 are deter-
mined using a 25 MHz 18 pF parallel resonant crystal and are
chosen to minimize the ppm error. Note that the optimal values
for C1 and C2 depend on the parasitic trace capacitance and are
thus layout dependent.
3.3V
10µ
V
DD
(Pin 1)
.μ
0.01 µF
F
Figure 10. Crystal Input Interface
XIN
Termination for LVPECL Output
C1
30 pF
The CY2XP22 implements its LVPECL driver with a current
steering design. For proper operation, it requires a 50 ohm dc
termination on each of the two output signals. For 3.3V
operation, this data sheet specifies output levels for termination
to VDD–2.0V. This same termination voltage can also be used for
X1
Device
18 pF Parallel
Crystal
XOUT
V
DD = 2.5V operation, or it can be terminated to VDD-1.5V. Note
C2
that it is also possible to terminate with 50 ohms to ground (VSS),
but the high and low signal levels differ from the data sheet
values. Termination resistors are best located close to the desti-
nation device. To avoid reflections, trace characteristic
impedance (Z0) should match the termination impedance.
Figure 9 shows a standard termination scheme.
27 pF
Document #: 001-10229 Rev. *C
Page 6 of 8
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PRELIMINARY
CY2XP22
Ordering Information
Part Number
CY2XP22ZXC
Package Type
Product Flow
Commercial, 0°C to 70°C
8-pin TSSOP
CY2XP22ZXCT
CY2XP22ZXI
8-pin TSSOP - Tape and Reel
8-pin TSSOP
Commercial, 0°C to 70°C
Industrial, -40°C to 85°C
Industrial, -40°C to 85°C
CY2XP22ZXIT
8-pin TSSOP - Tape and Reel
Package Drawing and Dimensions
Figure 11. 8-Pin Thin Shrunk Small Outline Package (4.40 MM Body) Z8
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN.
MAX.
6.25[0.246]
6.50[0.256]
4.30[0.169]
4.50[0.177]
8
0.65[0.025]
BSC.
0.25[0.010]
BSC
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
GAUGE
PLANE
0°-8°
0.076[0.003]
0.85[0.033]
0.95[0.037]
0.50[0.020]
0.70[0.027]
0.05[0.002]
0.15[0.006]
0.09[[0.003]
0.20[0.008]
SEATING
PLANE
2.90[0.114]
3.10[0.122]
51-85093-*A
Document #: 001-10229 Rev. *C
Page 7 of 8
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PRELIMINARY
CY2XP22
Document History Page
Document Title: CY2XP22 Crystal to LVPECL Clock Generator
Document Number: 001-10229
Submission
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
*A
*B
506262
838060
2700242
See ECN
See ECN
RGL
RGL
New Data Sheet
Changed status from Advance to Preliminary
04/30/2009 KVM/PYRS Reformatted
Revised phase noise values
Replaced VCC with VDD; VEE with VSS; updated pin names
Removed pull-up resistor on F_SEL
Corrected temperature range, added industrial temperature range
Increased IDD from 120 / 100 mA to 150 / 140 mA
Added CINX parameter, revised CIN parameter
Revised LVPECL output specs
Added thermal resistance information
Changed VIL, VIH, IIL & IIH specs
Revised suggested crystal load capacitor values
*C
2718898
06/15/09
WWZ
Minor ECN to post data sheet to external web
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© Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-10229 Rev. *C
Revised June 15, 2009
Page 8 of 8
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