CY62126EV30LL-55ZSXET [CYPRESS]
Standard SRAM, 64KX16, 55ns, CMOS, PDSO44, LEAD FREE, TSOP2-44;
| 型号： | CY62126EV30LL-55ZSXET |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 64KX16, 55ns, CMOS, PDSO44, LEAD FREE, TSOP2-44 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总16页 (文件大小：300K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62126EV30 MoBL
1-Mbit (64K x 16) Static RAM
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life(MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device in standby mode reduces power consumption by more
than 99 percent when deselected (CE HIGH). The input and
output pins (I/O0 through I/O15) are placed in a high impedance
state when the device is deselected (CE HIGH), the outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH) or during a write
operation (CE LOW and WE LOW).
Features
■ High speed: 45 ns
■ Temperature ranges
❐ Industrial: –40 °C to +85 °C
❐ Automotive: –40 °C to +125 °C
■ Wide voltage range: 2.2 V to 3.6 V
■ Pin compatible with CY62126DV30
■ Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 4 A
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A15). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A15).
■ Ultra low active power
❐ Typical active current: 1.3 mA at f = 1 MHz
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the “Truth Table” on page 11 for a
complete description of read and write modes.
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ OfferedinPb-free48-ballveryfinepitchballgridarray(VFBGA)
and 44-pin thin small outline package (TSOP) II packages
Functional Description
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
The CY62126EV30 is a high performance CMOS static RAM
organized as 64K words by 16 bits. This device features
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
64K x 16
I/O0–I/O7
RAM Array
I/O8–I/O15
A2
A1
A0
COLUMN DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document #: 38-05486 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 17, 2010
CY62126EV30 MoBL
Contents
Pin Configuration ............................................................. 3
Maximum Ratings............................................................. 4
Operating Range............................................................... 4
Electrical Characteristics................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance.......................................................... 5
Data Retention Characteristics ....................................... 6
Switching Characteristics................................................ 7
Switching Waveforms ...................................................... 8
Truth Table...................................................................... 11
Ordering Information...................................................... 12
Ordering Code Definitions......................................... 12
Package Diagrams.......................................................... 13
Acronyms........................................................................ 14
Document History Page................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support....................... 16
Products.................................................................... 16
PSoC Solutions......................................................... 16
Document #: 38-05486 Rev. *H
Page 2 of 16
CY62126EV30 MoBL
Pin Configuration
Figure 1. 48-Ball VFBGA (Top View)
Figure 2. 44-Pin TSOP II (Top View) [1]
1
4
2
5
3
6
NC
I/O
A
A
A
A
A
7
OE
BHE
BLE
I/O
15
I/O
I/O
13
I/O
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
4
3
5
6
A
A
A
A
A
A
OE
2
1
BLE
0
1
2
A
B
C
0
A
A
I/O BHE
CE
I/O
4
3
0
8
CE
I/O
I/O
I/O
I/O
0
A
A
6
I/O
I/O
2
I/O
1
2
3
14
5
10
1
9
9
10
11
12
13
14
15
16
12
V
A
V
I/O
I/O
3
NC
NC
cc
D
E
F
SS
7
11
V
V
SS
CC
V
SS
I/O
I/O
I/O
I/O
V
CC
I/O
I/O
I/O
I/O
Vss
NC
V
4
I/O
I/O
CC
11
10
12
4
5
6
7
9
A
A
15
I/O
I/O
5
I/O
I/O
14
13
14
6
8
WE 17
NC
A
A
15
A
14
A
13
A
12
18
19
20
21
22
8
A
A
G
H
I/O
NC
WE
I/O
7
13
12
15
A
9
A
10
A
A
A
A
NC
A
11
NC
NC
10
9
11
8
NC
Table 1. Product Portfolio
Power Dissipation
Operating, ICC (mA)
VCC Range (V)
Speed
(ns)
Product
Range
Standby, ISB2 (A)
f = 1 MHz
f = fmax
Min
Typ[2]
3.0
Max
3.6
Typ[2] Max Typ[2] Max
Typ[2]
Max
4
CY62126EV30LL Industrial
CY62126EV30LL Automotive
2.2
2.2
45
55
1.3
1.3
2
4
11
11
16
35
1
1
3.0
3.6
30
Notes
1. NC pins are not connected on the die.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
Document #: 38-05486 Rev. *H
Page 3 of 16
CY62126EV30 MoBL
DC input voltage[3, 4] 0.3 V to 3.6 V (VCCmax + 0.3 V)
Maximum Ratings
Output current into outputs (LOW) .............................. 20 mA
Exceeding maximum ratings may shorten the battery life of the
device. These user guidelines are not tested.
Static discharge voltage.......................................... > 2001 V
(MIL-STD-883, Method 3015)
Storage temperature ................................ –65 °C to +150 °C
Latch up current..................................................... > 200 mA
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Operating Range
Supply voltage to ground
Ambient
potential..............................–0.3 V to 3.6 V (VCCmax + 0.3 V)
[5]
Device
Range
VCC
Temperature
DC voltage applied to outputs
in High Z state[3, 4] ..............–0.3 V to 3.6 V (VCCmax + 0.3 V)
CY62126EV30LL
Industrial –40 °C to +85 °C 2.2 V to
3.6 V
Automotive –40 °C to +125 °C
Electrical Characteristics
(Over the Operating Range)
45 ns (Industrial)
55 ns (Automotive)
Parameter
Description
Test Conditions
IOH = –0.1 mA
Unit
Min Typ[6]
Max
–
Min Typ[6]
Max
VOH
Output high voltage
2.0
2.4
–
–
–
2.0
2.4
–
–
–
–
–
V
V
IOH = –1.0 mA, VCC > 2.70V
IOL = 0.1 mA
–
VOL
VIH
VIL
Output low voltage
Input high voltage
Input low voltage
–
0.4
0.4
0.4
V
IOL = 2.1mA, VCC > 2.70V
VCC = 2.2 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.2 V to 2.7 V
VCC = 2.7 V to 3.6 V
–
–
–
–
–
0.4
V
1.8
2.2
–0.3
–0.3
–1
–
VCC + 0.3 1.8
VCC + 0.3 2.2
VCC + 0.3
VCC + 0.3
0.6
V
–
–
V
–
0.6
0.8
+1
–0.3
–0.3
–4
–4
–
–
V
–
–
0.8
V
IIX
Input leakage current GND < VI < VCC
–
–
+4
A
A
mA
IOZ
ICC
Output leakage current GND < VO < VCC, Output Disabled –1
VCC operating supply f = fmax = 1/tRC VCC = VCCmax
–
+1
–
+4
11
1.3
16
11
1.3
35
current
IOUT = 0 mA
CMOS levels
f = 1 MHz
–
2.0
–
4.0
ISB1
Automatic CE power CE > VCC 0.2 V,
–
1
4
–
1
35
A
down current —CMOS
inputs
VIN > VCC – 0.2 V, VIN < 0.2 V)
f = fmax (Address and Data Only),
f = 0 (OE, BHE, BLE and WE),
VCC = 3.60V
[7]
ISB2
Automatic CE power CE > VCC – 0.2 V,
–
1
4
–
1
30
A
down current —CMOS
inputs
V
IN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60V
Notes
3.
4.
V
= –2.0 V for pulse durations less than 20 ns.
IL(min)
V
= V +0.75 V for pulse durations less than 20 ns.
IH(max)
CC
5. Full device AC operation assumes a 100 s ramp time from 0 to V (min) and 200 s wait time after V stabilization.
cc
cc
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
7. Chip enable (CE) needs to be tied to CMOS levels to meet the I
/ I
spec. Other inputs can be left floating.
SB2 CCDR
Document #: 38-05486 Rev. *H
Page 4 of 16
CY62126EV30 MoBL
Capacitance
For all packages. Tested initially and after any design or process changes that may affect these parameters.
Parameter
CIN
COUT
Description
Input capacitance
Output capacitance
Test Conditions
Max
10
Unit
pF
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
10
pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
VFBGA
TSOP II
Parameter
JA
Description
Test Conditions
Unit
Package Package
Thermal resistance
(Junction to ambient)
Still Air, soldered on a 4.25 × 1.125 inch,
two-layer printed circuit board
58.85
17.01
28.2
3.4
°C/W
°C/W
JC
Thermal resistance
(Junction to case)
Figure 3. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
90%
10%
VCC
OUTPUT
VCC
GND
90%
10%
R2
30 pF
Rise Time = 1 V/ns
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.2 V - 2.7 V
16600
15400
8000
2.7 V - 3.6 V
1103
Unit
R1
R2
1554
RTH
VTH
645
1.2
1.75
V
Document #: 38-05486 Rev. *H
Page 5 of 16
CY62126EV30 MoBL
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min
1.5
–
Typ[8]
Max
–
Unit
V
VDR
VCC for data retention
Data retention current
–
–
–
–
[9]
ICCDR
VCC= VDR, CE > VCC – 0.2 V,
IN > VCC – 0.2 V or VIN < 0.2 V
Industrial
3
A
A
ns
V
Automotive
–
30
–
[10]
tCDR
Chip deselect to data
retention time
0
[10]
tR
Operation recovery time
tRC
–
–
ns
Figure 4. Data Retention Waveform
DATA RETENTION MODE
VCC(min)
VCC(min)
V
> 1.5 V
VCC
DR
t
t
CDR
R
CE
Notes
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
9. Tested initially and after any design or process changes that may affect these parameters.
10. Full device AC operation requires linear V ramp from V to V > 100 s.
CC
DR
CC(min)
Document #: 38-05486 Rev. *H
Page 6 of 16
CY62126EV30 MoBL
Switching Characteristics
Over the Operating Range [11, 12]
45 ns (Industrial)
55 ns (Automotive)
Parameter
Description
Unit
Min
Max
Min
Max
Read Cycle
tRC
Read cycle time
45
–
–
45
–
55
–
–
55
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
tOHA
Data hold from address change
CE LOW to data valid
10
–
10
–
tACE
45
22
–
55
25
–
–
–
tDOE
OE LOW to data valid
OE LOW to Low Z [13]
OE HIGH to High Z [13, 14]
CE LOW to Low Z [13]
CE HIGH to High Z [13, 14]
tLZOE
tHZOE
tLZCE
tHZCE
tPU
5
–
5
–
18
–
20
–
10
–
10
–
18
–
20
–
CE LOW to power up
0
–
–
0
–
–
tPD
CE HIGH to power down
BHE / BLE LOW to data valid
BHE / BLE LOW to Low Z [13]
BHE / BLE HIGH to High Z [13, 14]
45
22
–
55
25
–
tDBE
tLZBE
tHZBE
Write Cycle [15]
tWC
5
–
5
–
18
20
Write cycle time
45
–
–
–
–
–
–
–
–
–
55
–
–
–
–
–
–
–
–
–
ns
tSCE
tAW
tHA
CE LOW to write end
35
35
0
40
40
0
ns
ns
ns
ns
Address setup to write end
Address hold from write end
Address setup to write start
tSA
0
0
tPWE
tBW
tSD
WE pulse width
35
35
25
0
40
40
25
0
ns
ns
ns
ns
BHE / BLE pulse width
Data setup to write end
Data hold from write end
tHD
WE LOW to High Z [13, 14]
WE HIGH to Low Z [13]
18
–
20
–
ns
ns
–
–
tHZWE
tLZWE
10
10
Notes
11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of V
/2, input pulse levels of 0 to V
, and output loading of the specified
CC(typ)
CC(typ)
I
/I and 30-pF load capacitance.
OL OH
12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
13. At any temperature and voltage condition, t is less than t , t is less than t , t is less than t , and t is less than t for any device.
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
14. t
, t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
HZOE HZCE HZBE
HZWE
15. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE or both = V . All signals must be active to initiate a write and any of these
IL
IL
signals can terminate a write by going inactive. The data input setup and hold timing must refer to the edge of signal that terminates write.
Document #: 38-05486 Rev. *H
Page 7 of 16
CY62126EV30 MoBL
Switching Waveforms
Figure 5. Read Cycle No. 1(Address transition controlled)[16, 17]
tRC
ADDRESS
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
DATA OUT
[17, 18]
Figure 6. Read Cycle No. 2 (OE controlled)
ADDRESS
CE
t
RC
t
PD
HZCE
t
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
BHE/BLE
t
HZBE
t
DBE
t
LZBE
HIGH
IMPEDANCE
HIGHIMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PU
V
50%
50%
CC
I
SUPPLY
SB
CURRENT
Notes
16. The device is continuously selected. OE, CE = V , BHE, BLE, or both = V
.
IL
IL
17. WE is high for read cycle.
18. Address valid before or similar to CE and BHE, BLE transition LOW.
Document #: 38-05486 Rev. *H
Page 8 of 16
CY62126EV30 MoBL
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (WE controlled)[19, 20, 21]
t
WC
ADDRESS
CE
tSCE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
HD
t
SD
NOTE 22
DATAIN
DATA I/O
t
HZOE
[
, 20, 21]
Figure 8. Write Cycle No. 2 (CE controlled) 19
t
WC
ADDRESS
CE
t
SCE
tSA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
DATAIN
DATA I/O
NOTE 22
t
HZOE
Notes
19. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE or both = V . All signals must be active to initiate a write and any of
IL
IL
these signals can terminate a write by going inactive. The data input setup and hold timing must refer to the edge of signal that terminates write.
20. Data I/O is high impedance if OE = V
.
IH
21. If CE goes high simultaneously with WE = V , the output remains in a high impedance state.
IH
22. During this period, the I/Os are in output state. Do not apply input signals.
Document #: 38-05486 Rev. *H
Page 9 of 16
CY62126EV30 MoBL
Switching Waveforms (continued)
[23]
Figure 9. Write Cycle No. 3 (WE controlled, OE LOW
t
WC
ADDRESS
CE
t
SCE
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
HD
t
SD
DATA I/O
NOTE 24
DATAIN
t
LZWE
t
HZWE
[23]
Figure 10. Write Cycle No. 4 (BHE/BLE controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
tBW
BHE/BLE
WE
t
SA
tPWE
tHZWE
t
HD
t
SD
NOTE 24
DATAIN
DATA I/O
tLZWE
Note
23. If CE goes high simultaneously with WE = V , the output remains in a high impedance state.
IH
24. During this period, the I/Os are in output state. Do not apply input signals.
Document #: 38-05486 Rev. *H
Page 10 of 16
CY62126EV30 MoBL
Truth Table
CE[25]
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
High Z
Mode
Power
H
L
L
L
Deselect/power down
Output disabled
Read
Standby (ISB)
X
X
H
H
High Z
Active (ICC
Active (ICC
Active (ICC
)
)
)
H
L
L
L
Data out (I/O0–I/O15)
H
L
H
L
Data out (I/O0–I/O7);
I/O8–I/O15 in High Z
Read
L
H
L
L
H
Data out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC
)
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z
High Z
High Z
Output disabled
Output disabled
Output disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
L
Data in (I/O0–I/O15)
L
H
Data in (I/O0–I/O7);
I/O8–I/O15 in High Z
Write
L
L
X
L
H
Data in (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC
)
Note
25. Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted.
Document #: 38-05486 Rev. *H
Page 11 of 16
CY62126EV30 MoBL
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Package Type
Ordering Code
45
CY62126EV30LL-45BVXI
CY62126EV30LL-45ZSXI
CY62126EV30LL-45ZSXA
CY62126EV30LL-55BVXE
CY62126EV30LL-55ZSXE
51-85150 48-ball VFBGA (Pb-free)
51-85087 44-pin TSOP II (Pb-free)
51-85087 44-pin TSOP II (Pb-free)
51-85150 48-ball VFBGA (Pb-free)
51-85087 44-pin TSOP II (Pb-free)
Industrial
Industrial
Automotive-A
Automotive-E
Automotive-E
55
Contact your local Cypress sales representative for availability of other parts.
Ordering Code Definitions
Temperature Grades:
I = Industrial
45/55 XXX
V30 LL
E
X
CY 621 2
6
A = Auto-A
E = Auto-E
Package type:
BVX: VFBGA (Pb-free)
ZSX: TSOP II (Pb-free)
Speed grade
Low Power
Voltage Range = 3 V Typical
E = Process Technology 90 nm
Bus Width = x16
Density = 1 Mbit
621 = MoBL SRAM Family
Cypress
CY =
Company ID:
Document #: 38-05486 Rev. *H
Page 12 of 16
CY62126EV30 MoBL
Package Diagrams
Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
51-85150 *F
Document #: 38-05486 Rev. *H
Page 13 of 16
CY62126EV30 MoBL
Figure 12. 44-Pin TSOP II, 51-85087
PIN 1 I.D.
22
1
Z
Z
Z
Z
Z
X
AA
EJECTOR MARK
(OPTIONAL)
23
44
CAN BE LOCATED
ANYWHERE IN THE
BOTTOM PKG
BOTTOM VIEW
TOP VIEW
0.400(0.016)
0.300 (0.012)
0.800 BSC
(0.0315)
BASE PLANE
10.262 (0.404)
10.058 (0.396)
0.10 (.004)
0°-5°
0.210 (0.0083)
0.120 (0.0047)
18.517 (0.729)
18.313 (0.721)
SEATING
PLANE
0.597 (0.0235)
0.406 (0.0160)
DIMENSION IN MM (INCH)
MAX
MIN.
51-85087-*C
Acronyms
Acronym
BHE
Description
byte high enable
BLE
byte low enable
CMOS
CE
complementary metal oxide semiconductor
chip enable
I/O
input/output
OE
output enable
SRAM
TSOP
VFBGA
WE
static random access memory
thin small outline package
very fine ball gird array
write enable
Document #: 38-05486 Rev. *H
Page 14 of 16
CY62126EV30 MoBL
Document History Page
Document Title: CY62126EV30 MoBL®, 1-Mbit (64K x 16) Static RAM
Document Number: 38-05486
Submission
Date
Orig. of
Change
Rev.
ECN No.
Description of Change
**
202760
300835
See ECN
See ECN
AJU
SYT
New data sheet
*A
Converted from Advance Information to Preliminary
Specified Typical standby power in the Features Section
Changed E3 ball from DNU to NC in the Pin Configuration for the FBGA Package
and removed the footnote associated with it on page #2
Changed tOHA from 6 ns to 10 ns for both 35- and 45-ns speed bins, respectively
Changed tDOE, tSD from 15 to 18 ns for 35-ns speed bin
Changed tHZOE, tHZBE, tHZWE from 12 and 15 ns to 15 and 18 ns for the 35- and
45-ns speed bins, respectively
Changed tHZCE from 12 and 15 ns to 18 and 22 ns for the 35- and 45-ns speed
bins, respectively
Changed tSCE,tBW from 25 and 40 ns to 30 and 35 ns for the 35- and 45-ns speed
bins, respectively
Changed tAW from 25 to 30 ns and 40 to 35 ns for 35 and 45-ns speed bins respec-
tively
Changed tDBE from 35 and 45 ns to 18 and 22 ns for the 35 and 45 ns speed bins
respectively
Removed footnote that read “BHE.BLE is the AND of both BHE and BLE. Chip can
be deselected by either disabling the chip enable signals or by disabling both BHE
and BLE” on page # 4
Removed footnote that read “If both BHE and BLE are toggled together, then tLZBE
is 10 ns” on page # 5
Added Pb-free package information
*B
461631
See ECN
NXR
Converted from Preliminary to Final
Removed 35 ns Speed Bin
Removed “L” version of CY62126EV30
Changed ICC (Typ) from 8 mA to 11 mA and ICC (max) from 12 mA to 16 mA for f = fmax
Changed ICC (max) from 1.5 mA to 2.0 mA for f = 1 MHz, ISB1, ISB2 (max) from 1 A
to 4 A, ISB1, ISB2 (Typ) from 0.5 A to 1 A, ICCDR (max) from 1.5 A to 3 A, AC Test
load Capacitance value from 50 pF to 30 pF, tLZOE from 3 to 5 ns, tLZCE from 6 to
10 ns, tHZCE from 22 to 18 ns, tLZBE from 6 to 5 ns, tPWE from 30 to 35 ns, tSD from
22 to 25 ns, tLZWE from 6 to 10 ns, and updated the Ordering Information table.
*C
*D
*E
*F
925501
1045260
2631771
See ECN
See ECN
01/07/09
VKN
VKN
Added footnote #7 related to ISB2 and ICCDR
Added footnote #11 related AC timing parameters
Added Automotive information
Updated Ordering Information table
NXR/PYRS Changed CE condition from X to L in Truth table for Output Disable mode
Updated template
2944332 06/04/2010
VKN
Added Contents
Removed byte enable from footnote #2 in Electrical Characteristics
Added footnote related to chip enable in Truth Table
Updated Package Diagrams
Updated links in Sales, Solutions, and Legal Information
*G
*H
2996166 07/29/2010
3113864 12/17/2010
AJU
Added CY62126EV30LL-45ZSXA part in Ordering Information.
Added Ordering Code Definitions.
Modified table footnote format.
PRAS
Updated Figure 1 and Package Diagram, and fixed Typo in Figure 3..
Document #: 38-05486 Rev. *H
Page 15 of 16
CY62126EV30 MoBL
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC Solutions
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2008-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05486 Rev. *H
Revised December 17, 2010
Page 16 of 16
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective
holders.
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