CY62127BVLL-55ZIT [CYPRESS]
Standard SRAM, 64KX16, 55ns, CMOS, PDSO44, TSOP2-44;
| 型号： | CY62127BVLL-55ZIT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 64KX16, 55ns, CMOS, PDSO44, TSOP2-44 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总10页 (文件大小：189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62127BV
64K x 16 Static RAM
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
Features
• 2.7V–3.6V operation
(BLE) is LOW, then data from I/O pins (I/O through I/O ), is
1
8
written into the location specified on the address pins (A
• CMOS for optimum speed/power
• Low active power (70 ns, LL version)
— 54 mW (max.) (15 mA)
0
through A ). If Byte High Enable (BHE) is LOW, then data
15
from I/O pins (I/O through I/O ) is written into the location
9
16
specified on the address pins (A through A ).
0
15
• Low standby power (70 ns, LL version)
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
— 54 W (max.) (15 A)
µ
µ
• Automatic power-down when deselected
Power down either with CE or BHE and BLE HIGH
—
pins will appear on I/O to I/O . If Byte High Enable (BHE) is
1
8
• Independent control of Upper and Lower Bytes
• Available in 44-pin TSOP II (forward) and fBGA
LOW, then data from memory will appear on I/O to I/O . See
9
16
the truth table at the back of this data sheet for a complete
description of read and write modes.
Functional Description
The input/output pins (I/O through I/O ) are placed in a
1
16
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY62127BV is a high-performance CMOS Static RAM
organized as 65,536 words by 16 bits. This device has an au-
tomatic power-down feature that significantly reduces power
consumption by 99% when deselected. The device enters
power-down mode when CE is HIGH or when CE is LOW and
both BLE and BHE are HIGH.
The CY62127BV is available in standard 44-pin TSOP Type II
(forward pinout) and fBGA packages.
Logic Block Diagram
Pin
Configurations
TSOP II (Forward)
Top View
DATA IN DRIVERS
44
1
A
4
A
5
43
42
41
40
39
38
A
A
2
3
4
5
6
3
6
A12
A11
A10
A9
A
A
2
7
OE
A
1
BHE
BLE
I/O
A
0
CE
A7
A6
A3
A2
A1
64K x 16
I/O
7
1
16
I/O1–I/O8
37
36
35
34
33
RAM Array
1024 X 1024
I/O
I/O
8
I/O
I/O
2
3
15
14
13
9
I/O9–I/O16
10
11
12
13
I/O
V
I/O
4
V
SS
CC
V
V
SS
CC
A0
I/O
32
I/O
I/O
5
6
7
8
12
11
I/O
I/O
I/O
31
30
29
28
14
15
16
I/O
I/O
10
9
COLUMN DECODER
WE 17
NC
18
27
26
25
A
A
8
15
19
A
A
14
13
9
10
11
A
20
21
22
A
A
BHE
A
12
WE
CE
OE
24
23
NC
NC
BLE
62127BV–1
62127BV–2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
June 14, 2000
CY62127BV
Pin Configurations (continued)
fBGA
4
1
2
3
5
6
A
A
A
1
BLE
OE
NC
2
0
3
A
B
C
A
4
A
I/O
9
I/O
1
BHE
CE
I/O
A
6
I/O
11
A
5
I/O
10
I/O
3
2
I/O
12
V
V
A
7
NC
NC
I/O
4
SS
CC
D
E
F
I/O
V
CC
I/O
13
V
SS
NC
5
I/O
14
A
I/O
7
I/O
15
A
I/O
15
14
6
I/O
16
A
I/O
8
A
NC
WE
G
H
12
13
A
8
A
A
A
9
NC
NC
10
11
62127BV–3
Selection Guide
62127BV-55
62127BV-70
Units
ns
Maximum Access Time
55
20
15
70
15
15
Maximum Operating Current
Maximum CMOS Standby Current
mA
µA
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Ambient
[1]
[2]
Supply Voltage on V to Relative GND .... –0.5V to +4.6V
Range
Industrial
Temperature
V
CC
CC
DC Voltage Applied to Outputs
–40°C to +85°C
2.7V–3.6V
[1]
in High Z State ....................................–0.5V to V + 0.5V
CC
[1]
DC Input Voltage .................................–0.5V to V + 0.5V
CC
Notes:
1.
VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “Instant On” case temperature.
2
CY62127BV
Electrical Characteristics Over the Operating Range
62127BV–55, 70
[3]
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
= Min., I = –1.0 mA
Min.
Typ.
Max.
Unit
V
V
V
V
2.2
OH
CC
CC
OH
V
= Min., I = 2.1 mA
0.4
V
OL
OL
V
2.0
V
+
CC
V
IH
0.3
0.4
+1
[1]
V
Input LOW Voltage
–0.3
–1
V
IL
I
I
Input Load Current
GND ≤ V ≤ V
CC
µA
µA
IX
I
Output Leakage Current
GND ≤ V ≤ V ,
CC
–1
+1
OZ
I
Output Disabled
I
I
I
V
Operating
V
= Max.,
= 0 mA,
55 ns
70 ns
20
15
mA
mA
CC
CC
CC
Supply Current
I
OUT
f = f
= 1/t
MAX
RC
Automatic CE
Power-Down Current
—TTL Inputs
Max. V , CE ≥ V
V
V
2
mA
SB1
SB2
CC
IH
≥ V or
IN
IN
IH
≤ V , f = f
IL
MAX
Automatic CE
Max. V
,
0.5
15
µA
CC
Power-Down Current
—CMOS Inputs
CE ≥ V – 0.3V,
CC
V
≥ V – 0.3V,
CC
IN
or V ≤ 0.3V, f=0
IN
Capacitance[4]
Parameter
Description
Test Conditions
Max.
Unit
C
C
Input Capacitance
Output Capacitance
T = 25°C, f = 1 MHz,
9
9
pF
pF
IN
A
V
= 3.3V
CC
OUT
AC Test Loads and Waveforms
R1 1076
R1 1076
Ω
Ω
ALL INPUT PULSES
90%
3.0V
3.0V
VCC
90%
10%
OUTPUT
OUTPUT
10%
R2
1262
R2
1262
30 pF
5 pF
GND
Ω
Ω
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
Rise Time:
1 V/ns
Fall Time
1 V/ns
(b)
(a)
581
Ω
1.62V
OUTPUT
Equivalent to:
THÉVENIN
EQUIVALENT
62127BV-4
Notes:
3. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal
conditions (TA = 25°C, VCC=3.0V). Parameters are guaranteed by design and characterization, and not 100% tested.
4. Tested initially and after any design or process changes that may affect these parameters.
3
CY62127BV
Switching Characteristics[5] Over the Operating Range
62127BV–55
62127BV–70
Parameter
Description
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
55
70
AA
Data Hold from Address Change
CE LOW to Data Valid
10
10
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
55
25
70
35
OE LOW to Data Valid
[7]
OE LOW to Low Z
5
10
0
5
10
0
[6, 7]
OE HIGH to High Z
20
20
25
25
[7]
CE LOW to Low Z
[6, 7]
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
55
55
70
70
PD
DBE
LZBE
[7]
Byte Enable to LOW Z
5
5
[6, 7]
t
Byte Disable to HIGH Z
20
25
HZBE
[8]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
55
45
45
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
SCE
AW
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
HA
0
0
SA
40
25
0
50
30
0
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
HD
[7]
WE HIGH to Low Z
5
5
LZWE
HZWE
BW
[6, 7]
WE LOW to High Z
25
25
Byte Enable to End of Write
45
60
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL/IOH and 30 pF load capacitance.
6.
t
HZOE, tHZCE, tHZWE, and tHZBE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE islessthan tLZCE,tHZOE is less thantLZOE, tHZWE islessthan tLZWE,and tHZBE is less than tLZBE,foranygiven device.
8. The internal write time of the memory is defined by the overlap of CELOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. Refer to truth table for
further conditions from BHE and BLE.
4
CY62127BV
Data Retention Characteristics (Over the Operating Range for “L” and “LL” version only)
[9]
Parameter
Description
Conditions
Min.
Typ
Max.
3.6
Unit
V
V
V
for Data Retention
CC
2.0
DR
I
t
t
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
V
= V = 2.0V,
0.5
15
µA
ns
CCDR
CC
DR
CE > V -0.3V,
[4]
CC
0
CDR
R
V
> V - 0.3V or,
IN
CC
V
< 0.3V.
t
ns
IN
RC
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
VCC
CE
DR
t
t
R
CDR
62127BV–5
Switching Waveforms
[10, 11]
Read Cycle No.1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
62127BV-6
Notes:
9. No input may exceed VCC + 0.3V.
10. Device is continuously selected. OE, CE, BHE, BLE = VIL.
11. WE is HIGH for read cycle.
5
CY62127BV
Switching Waveforms (continued)
[11, 12, 13]
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
t
RC
t
ACE
OE
BHE, BLE
t
DBE
t
HZBE
t
LZBE
t
t
HZOE
DOE
t
t
HZCE
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
t
PU
VCC
SUPPLY
CURRENT
50%
50%
ISB
62127BV-7
[13, 14]
Write Cycle No. 1 (CE Controlled)
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
BHE, BLE
t
BW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
62127BV-8
Notes:
12. Address valid prior to or coincident with CE transition LOW.
13. Data I/O is high impedance if OE = VIH or BHE and BLE = VIH
.
14. If CE, BHE, or BLE go HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
6
CY62127BV
Switching Waveforms (continued)
[13, 14]
WC
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
t
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE, BLE
OE
t
t
SD
t
HD
HZOE
DATA VALID
DATA I/O
IN
NOTE 15
62127BV-9
[13, 14]
Write Cycle No.3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HD
t
t
SD
HZWE
NOTE 15
DATAI/O
DATA VALID
t
LZWE
62127BV-10
Note:
15. During this period the I/Os are in the output state and input signals should not be applied.
7
CY62127BV
Truth Table
CE
H
L
OE WE BLE
BHE
X
I/O –I/O
I/O –I/O
16
Mode
Power
1
8
9
X
L
X
H
H
H
L
X
L
High Z
High Z
Power Down
Read All Bits
Standby (I
)
SB
L
Data Out
Data Out
High Z
Data Out
High Z
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
)
)
)
)
)
)
)
CC
CC
CC
CC
CC
CC
CC
L
L
L
H
L
Read Lower Bits Only
Read Upper Bits Only
Write All Bits
L
L
H
L
Data Out
Data In
High Z
L
X
X
X
H
X
L
Data In
Data In
High Z
L
L
L
H
L
Write Lower Bits Only
Write Upper Bits Only
Selected, Outputs Disabled
Power Down
L
L
H
L
Data In
High Z
L
H
X
L
High Z
L
H
H
High Z
High Z
Standby (I
)
SB
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY62127BVLL-55ZI
CY62127BVLL-55BAI
CY62127BVLL-70ZI
CY62127BVLL-70BAI
Package Type
55
Z44
BA48
Z44
44-Lead TSOP II
Industrial
48-Ball Fine Pitch Ball Grid Array (fBGA)
44-Lead TSOP II
70
BA48
48-Ball Fine Pitch Ball Grid Array (fBGA)
Document #: 38-01018-**
8
CY62127BV
Package Diagrams
48-Ball (7.00 mm x 7.00 mm) Fine Pitch BGA BA48
51-85096-C
9
CY62127BV
Package Diagrams (continued)
44-Pin TSOP II Z44
51-85087-A
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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