CY62138FLL [CYPRESS]
2-Mbit (256K x 8) Static RAM; 2兆位（ 256K ×8 ）静态RAM
| 型号： | CY62138FLL |
| 厂家： | 
CYPRESS |
| 描述： | 2-Mbit (256K x 8) Static RAM |
| 文件： | 总14页 (文件大小：574K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62138F MoBL®
2-Mbit (256K x 8) Static RAM
Features
Functional Description [1]
■ High speed: 45 ns
The CY62138F is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE1 HIGH or CE2 LOW).
■ Wide voltage range: 4.5 V – 5.5 V
■ Pin compatible with CY62138V
■ Ultra low standby power
— Typical standby current: 1 A
— Maximum standby current: 5 A
■ Ultra low active power
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified
on the address pins (A0 through A17).
— Typical active current: 1.6 mA @ f = 1 MHz
■ Easy memory expansion with CE1, CE2, and OE features
■ Automatic power down when deselected
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and output enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
■ complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free 32-pin SOIC and 32-pin thin small outline
package (TSOP) II packages
The eight input and output pins (I/O0 through I/O7) are placed in
a high impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW and CE2 HIGH and WE
LOW).
Logic Block Diagram
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-13194 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 15, 2010
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CY62138F MoBL®
Contents
Pin Configuration .............................................................3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics (Over the Operating Range) ...4
Capacitance ......................................................................4
Thermal Resistance ..........................................................4
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics ........................................5
Data Retention Waveform.................................................5
Switching Characteristics (Over the Operating Range) ..6
Read Cycle 1 (Address transition controlled)...............7
Read Cycle No. 2 (OE controlled)................................7
Write Cycle No. 1 (WE controlled)................................7
Write Cycle No. 2 (CE1 or CE2 controlled) ..................8
Write Cycle No. 3 (WE controlled, OE LOW) ...............8
Truth Table ........................................................................9
Ordering Information ......................................................10
Ordering Code Definition ...........................................10
Package Diagrams ..........................................................11
Acronyms ........................................................................12
Documents Conventions ...............................................12
Units of Measure .......................................................12
Document History Page .................................................13
Sales, Solutions, and Legal Information ......................14
Worldwide Sales and Design Support .......................14
Products ....................................................................14
PSoC Solutions .........................................................14
Document #: 001-13194 Rev. *C
Page 2 of 14
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CY62138F MoBL®
Pin Configuration
32-Pin SOIC/TSOP II Pinout
Top View
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
A17
A16
A14
A12
A7
1
2
32
31
30
29
28
27
26
25
24
23
22
3
4
5
A6
6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
7
8
9
10
11
12
13
14
15
16
CE1
21
20
19
18
17
I/O7
I/O6
I/O5
I/O4
I/O3
Product Portfolio
Power Dissipation
Operating ICC (mA)
f = 1MHz f = fmax
VCC Range (V)
Speed
(ns)
Product
Standby ISB2 (A)
Min
Typ [2]
Max
5.5 V
Typ [2]
1.6
Max
Typ [2]
13
Max
Typ [2]
Max
CY62138FLL
4.5 V
5.0 V
45
2.5
18
1
5
Notes
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
Document #: 001-13194 Rev. *C
Page 3 of 14
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CY62138F MoBL®
DC Input Voltage [3, 4]......... –0.5 V to 6.0 V (VCCmax + 0.5 V)
Output Current into Outputs (LOW) ............................ 20 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage ........................................ > 2001 V
(MIL–STD–883, Method 3015)
Storage temperature ............................... –65 °C to + 150 °C
Latch-up Current ....................................................> 200 mA
Ambient temperature with
power applied ......................................... –55 °C to + 125 °C
Operating Range
Supply voltage to ground
Ambient
potential .............................–0.5 V to 6.0 V (VCCmax + 0.5 V)
[5]
Device
Range
VCC
Temperature
DC voltage applied to outputs
in High-Z state [3, 4].............–0.5 V to 6.0 V (VCCmax + 0.5 V)
CY62138FLL
Industrial –40°Cto+85°C 4.5 V to 5.5 V
Electrical Characteristics (Over the Operating Range)
45 ns
Typ [6]
Parameter
Description
Test Conditions
Unit
Min
2.4
–
Max
–
VOH
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
IOH = –1.0 mA
–
–
V
V
VOL
VIH
VIL
IIX
IOL = 2.1 mA
0.4
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
GND < VI < VCC
2.2
–0.5
–1
–1
–
–
VCC + 0.5
0.8
V
–
V
Input leakage current
Outputcleakage Current
–
+1
A
A
mA
IOZ
ICC
GND < VO < VCC, Output disabled
–
+1
VCC operating supply
Current
f = fmax = 1/tRC
f = 1 MHz
VCC = VCC(max)
IOUT = 0 mA
CMOS levels
13
1.6
18
–
2.5
[7]
ISB2
Automatic CE Power-down CE1 > VCC – 0.2 V or CE2 < 0.2 V
current CMOS inputs
–
1
5
A
V
IN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
Capacitance
Parameter[8]
Description
Input capacitance
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz,
CC = VCC(typ)
Max
Unit
pF
CIN
10
10
V
COUT
pF
Thermal Resistance
Parameter[8]
Description
Test Conditions
SOIC
TSOP II
Unit
JA
Thermal resistance
(Junction to Ambient)
Still air, soldered on a 3 × 4.5 inch two-layer printed
circuit board
44.53
44.16
C / W
JC
Thermal resistance
(Junction to Case)
24.05
11.97
C / W
Notes
3.
V
= –2.0 V for pulse durations less than 20 ns.
IL(min)
4.
V
= V +0.75 V for pulse durations less than 20 ns.
IH(max)
CC
5. Full device AC operation assumes a 100 s ramp time from 0 to V (min) and 200 s wait time after V stabilization.
CC
CC
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C
A
CC
CC(typ)
7. Chip enables (CE and CE ) must be at CMOS level to meet the I
/ I
spec. Other inputs can be left floating.
1
2
SB2 CCDR
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-13194 Rev. *C
Page 4 of 14
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CY62138F MoBL®
AC Test Loads and Waveforms
R1
ALL INPUT PULSES
90%
VCC
3.0V
GND
OUTPUT
90%
10%
10%
R2
30 pF
Rise Time = 1 V/ns
Fall Time = 1 V/ns
INCLUDING
JIG AND
Equivalent to:
THEVENIN EQUIVALENT
SCOPE
RTH
OUTPUT
V
Parameters
5.0 V
1800
990
Unit
R1
R2
RTH
VTH
639
1.77
V
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
Description
VCC for Data retention
Data retention current
Conditions
Min
2.0
–
Typ [9]
Max
–
Unit
V
–
1
[10]
ICCDR
VCC= VDR, CE1 > VCC 0.2V or CE2 < 0.2V,
IN > VCC - 0.2V or VIN < 0.2V
5
A
V
[9]
tCDR
Chip deselect to data
retention time
0
–
–
–
–
ns
ns
[11]
tR
Operation recovery time
45
[12]
Data Retention Waveform
DATA RETENTION MODE
> 2.0V
VCC(min)
VCC(min)
V
VCC
CE
DR
t
t
R
CDR
Notes:
9. Tested initially and after any design or process changes that may affect these parameters.Typical values are included for reference only and are not guaranteed
or tested. Typical values are measured at V = V , T = 25 °C
CC
CC(typ)
A
10. Chip enables (CE and CE ) must be at CMOS level to meet the I
/ I
spec. Other inputs can be left floating.
1
2
SB2 CCDR
11. Full device AC operation requires linear V ramp from V to V
> 100 s or stable at V
> 100 s.
CC
DR
CC(min)
CC(min)
12. CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW, CE is HIGH.
1
2
1
2
1
2
Document #: 001-13194 Rev. *C
Page 5 of 14
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CY62138F MoBL®
Switching Characteristics (Over the Operating Range)
45 ns
Parameter[13]
Description
Unit
Max
Min
Read Cycle
tRC
Read cycle time
45
–
–
45
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data hold from address change
10
–
45
22
–
CE1 LOW and CE2 HIGH to data valid
OE LOW to data valid
–
OE LOW to Low-Z [14]
5
OE HIGH to High-Z [14, 15]
–
18
–
CE1 LOW and CE2 HIGH to Low Z [14]
CE1 HIGH or CE2 LOW to High-Z [14, 15]
10
–
18
–
to power-up
0
CE1 LOW and CE2 HIGH
tPD
to power-down
–
45
CE1 HIGH or CE2 LOW
Write Cycle [16]
tWC
Write cycle time
45
35
35
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
to write end
CE1 LOW and CE2 HIGH
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
–
tHA
–
tSA
0
–
tPWE
tSD
35
25
0
–
Data setup to write end
Data hold from write end
WE LOW to High-Z [14, 15]
WE HIGH to Low-Z [14]
–
tHD
–
tHZWE
tLZWE
–
18
–
10
Notes
13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V
/2, input
CC(typ)
pulse levels of 0 to V
, and output loading of the specified I /I as shown in the AC Test Loads and Waveforms on page 5.
CC(typ)
OL OH
14. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
15. t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
HZWE
HZOE HZCE
16. The internal write time of the memory is defined by the overlap of WE, CE = V , and CE = V . All signals must be ACTIVE to initiate a write and any of these
1
IL
2
IH
signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document #: 001-13194 Rev. *C
Page 6 of 14
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CY62138F MoBL®
Switching Waveforms
Read Cycle 1 (Address transition controlled) [17, 18]
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE controlled) [18, 19, 22]
ADDRESS
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PD
ICC
t
V
CC
PU
50%
SUPPLY
CURRENT
50%
ISB
Write Cycle No. 1 (WE controlled) [16, 20, 21, 22]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
23
DATA I/O
NOTE
DATA VALID
t
HZOE
Notes:
17. The device is continuously selected. OE, CE = V , CE = V
.
1
IL
2
IH
18. WE is HIGH for read cycle.
19. Address valid before or similar to CE transition LOW and CE transition HIGH.
1
2
20. Data I/O is high impedance if OE = V
.
IH
21. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
1
2
22. CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW, CE is HIGH
1
2
1
2
1
2
23. During this period, the I/Os are in output state. Do not apply input signals
Document #: 001-13194 Rev. *C
Page 7 of 14
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CY62138F MoBL®
Switching Waveforms (continued)
Write Cycle No. 2 (CE1 or CE2 controlled) [24, 25, 26, 27]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
AW
HA
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Write Cycle No. 3 (WE controlled, OE LOW) [24, 27]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
28
NOTE
DATA VALID
DATA I/O
t
t
LZWE
HZWE
Notes
24. CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW, CE is HIGH
1
2
1
2
1
2
25. The internal write time of the memory is defined by the overlap of WE, CE = V , and CE = V . All signals must be ACTIVE to initiate a write and any of these
1
IL
2
IH
signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write
26. Data I/O is high impedance if OE = V
.
IH
27. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
1
2
28. During this period, the I/Os are in output state. Do not apply input signals.
Document #: 001-13194 Rev. *C
Page 8 of 14
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CY62138F MoBL®
Truth Table
CE1
H
X[29]
CE2
X[29]
WE
X
OE
X
Inputs/Outputs
Mode
Deselect / Power-down
Deselect/Power-down
Read
Power
High Z
High-Z
Data out
High-Z
Data in
Standby (ISB
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
L
X
X
)
L
H
H
L
)
L
H
H
H
X
Output disabled
Write
)
L
H
L
)
Note
29. The ‘X’ (Don’t care) state for the Chip enables (CE and CE ) in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins
1
2
is not permitted
Document #: 001-13194 Rev. *C
Page 9 of 14
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CY62138F MoBL®
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Package Type
Ordering Code
45
CY62138FLL-45SXI
CY62138FLL-45ZSXI
51-85081 32-pin Small Outline Integrated Circuit (Pb-free)
51-85095 32-pin Thin Small Outline Package II (Pb-free)
Industrial
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definition
LL
45
XXX
X
CY
621
3
8F
Temperature Grades
I = Industrial
Package Type = SX : SOIC (Pb-free)
ZSX : TSOP II (Pb-free)
Speed Grade
Low Power
Bus Width = X8
F = 90nm Technology
Density = 2 Mbit
MoBL SRAM Family
Coimpany ID: CY = Cypress
Document #: 001-13194 Rev. *C
Page 10 of 14
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CY62138F MoBL®
Package Diagrams
Figure 1. 32-pin (450 Mil) Molded SOIC, 51-85081
51-85081-*C
Document #: 001-13194 Rev. *C
Page 11 of 14
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CY62138F MoBL®
Package Diagrams (continued)
Figure 2. 32-Pin TSOP II, 51-85095
51-85095-*A
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their
respective holders.
Acronyms
Documents Conventions
Units of Measure
Acronym
CMOS
I/O
Description
complementary metal oxide semiconductor
input/output
Symbol
°C
Unit of Measure
degrees Celsius
microamperes
milliampere
megahertz
nanoseconds
picofarads
volts
SRAM
VFBGA
TSOP
static random access memory
very fine ball grid array
A
mA
MHz
ns
thin small outline package
small outline integrated circuit
SOIC
pF
V
ohms
W
watts
Document #: 001-13194 Rev. *C
Page 12 of 14
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CY62138F MoBL®
Document History Page
Document Title: CY62138F MoBL® 2-Mbit (256K x 8) Static RAM
Document Number: 001-13194
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
**
797956
940341
See ECN
See ECN
VKN
New Data Sheet
*A
*B
VKN
Added footnote #7 related to ISB2 and ICCDR
3055174 13/10/2010
RAME
Updated As per new template
Added Acronyms and Units of Measure table.
Added Ordering Code Definition.
Footnotes updated
Updated Package Diagram Figure 1 and Figure 2.
*C
3061313 15/10/2010
RAME
Minor change: Corrected “IO” to “I/O”
Document #: 001-13194 Rev. *C
Page 13 of 14
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CY62138F MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-13194 Rev. *C
Revised October 15, 2010
Page 14 of 14
All products and company names mentioned in this document may be the trademarks of their respective holders.
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相关型号：
CY62138FV30LL-45SXIT
Standard SRAM, 256KX8, 45ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32
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CY62138FV30LL-45ZAXIT
Standard SRAM, 256KX8, 45ns, CMOS, PDSO32, 8 X 13.40 MM, 1.20 MM HEIGHT, LEAD FREE, STSOP-32
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