CY7C09579V-100BBXC [CYPRESS]
Dual-Port SRAM, 32KX36, 12.5ns, CMOS, PBGA172, 15 X 15 MM, 1.25 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, FBGA-172;
| 型号： | CY7C09579V-100BBXC |
| 厂家： | 
CYPRESS |
| 描述： | Dual-Port SRAM, 32KX36, 12.5ns, CMOS, PBGA172, 15 X 15 MM, 1.25 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, FBGA-172 静态存储器 内存集成电路 |
| 文件： | 总33页 (文件大小：866K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C09569V CY7C09579V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3
Synchronous Dual-Port Static RAM
V 16 K / 32 K × 36 FLEx36®
CY7C09569V
CY7C09579V
3.3 V 16 K / 32 K × 36 FLEx36®
Synchronous Dual-Port Static RAM
3.3
V 16 K / 32 K × 36 FLEx36® Synchronous Dual-Port Static RAM
Features
Functional Description
■ True dual-ported memory cells which allow simultaneous
access of the same memory location
The CY7C09569V and CY7C09579V are high-speed 3.3 V
synchronous CMOS 16 K and 32 K × 36 dual-port static RAMs.
Two ports are provided, permitting independent, simultaneous
access for reads and writes to any location in memory. Registers
on control, address, and data lines allow for minimal set-up and
hold times. In pipelined output mode, data is registered for
decreased cycle time. Clock to data valid tCD2 = 5 ns (pipelined).
Flow-through mode can also be used to bypass the pipelined
output register to eliminate access latency. In flow-through mode
data will be available tCD1 = 12.5 ns after the address is clocked
into the device. Pipelined output or flow-through mode is
selected via the FT/Pipe pin.
■ Two flow-through/pipelined devices
❐ 16 K × 36 organization (CY7C09569V)
❐ 32 K × 36 organization (CY7C09579V)
■ 0.25-micron CMOS for optimum speed/power
■ Three modes
❐ Flow-through
❐ Pipelined
❐ Burst
Each port contains a burst counter on the input address register.
The internal write pulse width is independent of the external R/W
LOW duration. The internal write pulse is self-timed to allow the
shortest possible cycle times.
■ Bus-matching capabilities on right port (× 36 to × 18 or × 9)
■ Byte-select capabilities on left port
■ 100-MHz pipelined operation
A HIGH on CE for one clock cycle will power down the internal
circuitry to reduce the static power consumption. In the pipelined
mode, one cycle is required with CE LOW to reactivate the
outputs.
■ High-speed clock to data access 5/6 ns
■ 3.3 V low operating power
❐ Active = 250 mA (typical)
❐ Standby = 10 A (typical)
Counter Enable Inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted, the
address counter will increment on each LOW-to-HIGH transition
of that port’s clock signal. This will read/write one word from/into
each successive address location until CNTEN is deasserted.
The counter can address the entire memory array and will loop
back to the start. Counter Reset (CNTRST) is used to reset the
burst counter.
■ Fully synchronous interface for ease of use
■ Burst counters increment addresses internally
❐ Shorten cycle times
❐ Minimize bus noise
❐ Supported in flow-through and pipelined modes
■ Counter address read back via I/O lines
■ Single chip enable
Parts are available in 144-pin Thin Quad Plastic Flatpack
(TQFP), 144-pin Pb-free Thin Quad Plastic Flatpack (TQFP) and
172-ball Ball Grid Array (BGA) packages.
■ Automatic power-down
■ Commercial and industrial temperature ranges
■ Compact package
❐ 144-pin TQFP (20 × 20 × 1.4 mm)
❐ 144-pin Pb-free TQFP (20 × 20 × 1.4 mm)
❐ 172-ball BGA (1.0-mm pitch) (15 × 15 × 0.51 mm)
Selection Guide
CY7C09569V / CY7C09579V
Unit
Description
-100
100
5
-83
83
6
fMAX2 (pipelined)
MHz
ns
Maximum access time (clock to data, pipelined)
Typical operating current ICC
250
30
240
25
10
mA
mA
A
Typical standby current for ISB1 (both ports TTL level)
Typical standby current for ISB3 (both ports CMOS level)
10
Cypress Semiconductor Corporation
Document Number: 38-06054 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 7, 2013
CY7C09569V
CY7C09579V
Logic Block Diagram
R/WL
OEL
R/WR
OER
Left
Port
Control
Logic
Right
Port
Control
Logic
B0–B3
CEL
CER
FT/PipeR
FT/PipeL
BE
9
9
9
9
9
9
9
9
I/O0L–I/O8L
9/18/36
I/O9L–I/O17L
I/O18L–I/O26L
I/O27L–I/O35L
I/O
Control
Bus
Match
I/O
Control
I/OR
BM
SIZE
[1]
14/15
14/15
[1]
A0–A13/14R
A0–A13/14L
Counter/
Address
Register
Decode
Counter/
CLKL
CLKR
ADSR
True Dual-Ported
RAM Array
Address
Register
Decode
ADSL
CNTENL
CNTRSTL
CNTENR
CNTRSTR
Note
1. A –A for 16K; A –A for 32 K devices.
0
13
0
14
Document Number: 38-06054 Rev. *H
Page 2 of 33
CY7C09569V
CY7C09579V
Contents
Pin Configurations ...........................................................4
Pin Definitions ..................................................................6
Maximum Ratings .............................................................7
Operating Range ...............................................................7
Electrical Characteristics .................................................7
Capacitance ......................................................................7
AC Test Load and Waveforms .........................................8
Switching Characteristics ................................................9
Switching Waveforms ....................................................11
Read/Write and Enable Operation .................................24
Address Counter Control Operation .............................24
Right Port Configuration ................................................25
Right Port Operation ......................................................25
Readout of Internal Address Counter ...........................25
Left Port Operation .........................................................25
Counter Operation ..........................................................26
Bus Match Operation .....................................................26
Long-Word (36-bit) Operation ...................................26
Word (18-bit) Operation .............................................27
Byte (9-bit) Operation ................................................27
Ordering Information ......................................................28
16 K × 36 3.3 V Synchronous Dual-Port SRAM ........28
32K × 36 3.3 V Synchronous Dual-Port SRAM .........28
Ordering Code Definitions .........................................28
Package Diagrams ..........................................................29
Acronyms ........................................................................31
Document Conventions .................................................31
Units of Measure .......................................................31
Document History Page .................................................32
Sales, Solutions, and Legal Information ......................33
Worldwide Sales and Design Support .......................33
Products ....................................................................33
PSoC Solutions .........................................................33
Document Number: 38-06054 Rev. *H
Page 3 of 33
CY7C09569V
CY7C09579V
Pin Configurations
Figure 1. 144-pin TQFP (20 × 20 × 1.4 mm) pinout (Top View)
I/O33L
I/O34L
1
2
108
I/O33R
I/O34R
107
106
I/O35L
A0L
I/O35R
A0R
3
4
105
104
103
102
A1L
5
6
7
8
A1R
A2R
A2L
A3R
A4R
A3L
A4L
101
100
A5R
A6R
A7R
A5L
A6L
A7L
9
10
99
98
97
96
11
12
13
BM
SIZE
B0
B1
BE
B2
B3
14
15
95
94
vss
OER
R/WR
16
17
18
19
93
92
91
90
OEL
R/WL
VDD
VSS
VSS
VDD
VSS
CY7C09569V (16 K × 36)
CY7C09579V (32 K × 36)
VSS
20
21
89
88
CEL
CER
CLKL
22
23
24
25
87
86
85
84
83
82
CLKR
ADSR
ADSL
CNTRSTL
CNTENL
FT/PIPEL
A8L
CNTRSTR
CNTENR
FT/PIPER
A8R
26
27
28
29
30
31
A9R
A9L
81
80
A10R
A10L
79
78
77
A11R
A12R
A11L
A12L
A13R
A13L
32
33
[3]
[2]
NC
NC
76
75
I/O26L
I/O25L
I/O24L
34
35
36
I/O26R
74
73
I/O25R
I/O24R
Notes
2. This pin is A14L for CY7C09579V.
3. This pin is A14R for CY7C09579V.
Document Number: 38-06054 Rev. *H
Page 4 of 33
CY7C09569V
CY7C09579V
Pin Configurations
Figure 2. 172-ball BGA (15 × 15 × 1.25 mm) pinout (Top View)
1
2
3
NC
4
VSS
5
6
7
8
9
10
11
12
13
14
I/O32L I/O30L
I/O13L VDD I/O11L I/O11R VDD I/O13R
VSS
NC
I/O30R I/O32R
A
B
C
D
E
F
A0L
NC
I/O33L
A1L
I/O29
I/O31L
I/O35L
NC
I/O17L
I/O27L
I/O34L
B0L
I/O14L I/O12L I/O9L I/O9R I/O12R I/O14R I/O17R
I/O29R I/O33R
A0R
NC
NC
I/O15L I/O10L I/O10R I/O15R NC
I/O27R
I/O31R
I/O35R
NC
A1R
A3R
A2L
A4L
VDD
OEL
VSS
A9L
A11L
A3L
I/O28L I/O16L VSS
VSS I/O16R I/O28R I/O34R
A2R
A4R
VDD
OER
VSS
A9R
A11R
A5L
NC
NC
NC
NC
NC
NC
BM
A5R
A6L
A7L
B1L
SIZE
CER
A7R
A6R
B2L
B3L
CEL
VSS
A8R
VSS
NC
BE
G
H
J
R/WL
A10L
A12L
A8L
CLKL
ADSL
CNTRSTL
I/O26L
I/O18L
I/O6L
VSS
CLKR
ADSR
R/WR
A10R
A12R
VSS
NC
NC
NC
NC
NC
NC
NC CNTRSTR
K
L
FT/PIPEL A13L CNTENL
I/O25L I/O19L VSS
VSS I/O19R I/O25R I/O26R
CNTENR A13R FT/PIPER
I/O22R NC
NC[5]
I/O8R I/O20R I/O24R
NC I/O21R I/O23R
NC
NC[4]
I/O22L
I/O8L
NC
NC
I/O7L I/O2L I/O2R I/O7R
NC
I/O18R
I/O6R
VSS
M
N
P
I/O24L I/O20L
I/O23L I/O21L
I/O5L I/O3L I/O0L I/O0R
I/3R
I/O5R
I/O4L VDD I/O1L I/O1R VDD I/O4R
Notes
4. This pin is A14L for CY7C09579V.
5. This pin is A14R for CY7C09579V.
Document Number: 38-06054 Rev. *H
Page 5 of 33
CY7C09569V
CY7C09579V
Pin Definitions
Left Port
Right Port
Description
A0L–A13/14L A0R–A13/14R Address Inputs (A0–A13 for 16 K, A0–A14 for 32 K devices).
ADSL
ADSR
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to assert
the part using the externally supplied address on Address Pins. To load this address into the Burst
Address Counter both ADS and CNTEN have to be LOW. ADS is disabled if CNTRST is asserted
LOW.
CEL
CER
Chip Enable Input.
CLKL
CLKR
Clock Signal. This input can be free-running or strobed. Maximum clock input rate is fMAX.
CNTENL
CNTENR
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if CNTRST is asserted LOW.
CNTRSTL
CNTRSTR
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective
port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O0L–I/O35L I/O0R–I/O35R Data Bus Input/Output
OEL
OER
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
R/WL
R/WR
FT/PIPER
–
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For
read operations, assert this pin HIGH.
FT/PIPEL
B0L–B3L
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For
pipelined mode operation, assert this pin HIGH.
Byte Select Inputs. Asserting these signals enable read and write operations to the corresponding
bytes of the memory array.
–
BM, SIZE
BE
Select Pins for Bus Matching. See Bus Matching for details.
Big Endian Pin. See Bus Matching for details.
Ground Input.
–
VSS
VDD
Power Input.
Document Number: 38-06054 Rev. *H
Page 6 of 33
CY7C09569V
CY7C09579V
DC input voltage ..............................–0.5 V to VDD + 0.5 V[7]
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage ..........................................> 2001 V
Latch-up current ....................................................> 200 mA
Maximum Ratings
Exceeding maximum ratings[6] may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Operating Range
Range
Ambient Temperature
VDD
Supply voltage to ground potential ..............–0.5 V to +4.6 V
Commercial
0 °C to +70 °C
3.3 V 165 mV
DC voltage applied to
outputs in High Z state ........................–0.5 V to VDD + 0.5 V
Electrical Characteristics
Over the Operating Range
CY7C09569V / CY7C09579V
Parameter
Description
-100
Typ
–
-83
Typ
–
Unit
Min
Max
Min
Max
VOH
Output HIGH Voltage
(VDD = Min., IOH = –4.0 mA)
2.4
–
2.4
–
V
V
VOL
Output LOW Voltage
–
–
0.4
–
–
0.4
(VDD = Min., IOL= +4.0 mA)
VIH
VIL
IOZ
ICC
Input HIGH Voltage
Input LOW Voltage
2.0
–
–
–
–
2.0
–
–
–
–
V
V
0.8
10
0.8
10
Output Leakage Current
–10
–
–
–10
–
–
A
mA
Operating Current
(VDD = Max., IOUT = 0 mA)
250
385
240
360
Outputs Disabled
ISB1
ISB2
ISB3
Standby Current (Both Ports TTL Level)
CEL & CER VIH, f = fMAX
–
–
–
30
75
220
1
–
–
–
25
70
210
1
mA
mA
mA
Standby Current (One Port TTL Level)
CEL | CER VIH, f = fMAX
170
0.01
160
0.01
Standby Current
(Both Ports CMOS Level)
CEL & CER VDD – 0.2 V, f = 0
ISB4
Standby Current
(One Port CMOS Level)
CEL | CER VIH, f = fMAX
–
150
200
–
140
190
mA
Capacitance
Parameter
CIN
Description
Test Conditions
TA = 25 °C, f = 1 MHz, VDD = 3.3 V
Max
Unit
pF
Input capacitance
10
10
COUT
Output capacitance
pF
Notes
6. The voltage on any input or I/O pin can not exceed the power pin during power-up.
7. Pulse width < 20 ns.
Document Number: 38-06054 Rev. *H
Page 7 of 33
CY7C09569V
CY7C09579V
AC Test Load and Waveforms
Figure 3. AC Test Load and Waveforms
3.3 V
Z0 = 50
R = 50
Output
R1 = 590
[8]
C
Output
V
TH
= 1.5 V
C = 5 pF
R2 = 435
(b) Three-State Delay (Load 2)
(a) Normal Load (Load 1)
3.0 V
VSS
90%
10%
90%
10%
3 ns
All Input Pulses
3 ns
7
6
5
4
3
2
1
20[9]
30 60 80 100
200
Capacitance (pF)
(b) Load Derating Curve
Notes
8. External AC Test Load Capacitance = 10 pF.
9. (Internal I/O pad Capacitance = 10 pF + AC Test Load.
Document Number: 38-06054 Rev. *H
Page 8 of 33
CY7C09569V
CY7C09579V
Switching Characteristics
Over the Operating Range
CY7C09569V/CY7C09579V
-100 -83
Parameter
Description
Unit
Min
–
Max
67
100
–
Min
–
Max
45
83
–
fMAX1
fMAX2
tCYC1
tCYC2
tCH1
tCL1
tCH2
tCL2
tR
fMax Flow-Through
fMax Pipelined
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
Clock Cycle Time – Flow-Through
Clock Cycle Time – Pipelined
Clock HIGH Time – Flow-Through
Clock LOW Time – Flow-Through
Clock HIGH Time – Pipelined
Clock LOW Time – Pipelined
Clock Rise Time
15
10
6.5
6.5
4
22
12
7.5
7.5
5
–
–
–
–
–
–
–
–
4
–
5
–
–
3
–
3
tF
Clock Fall Time
–
3
–
3
tSA
Address Set-Up Time
3.5
0.5
3.5
0.5
3.5
0.5
3.5
0.5
3.5
0.5
3.5
0.5
3.5
0.5
3.5
0.5
–
–
4
–
tHA
Address Hold Time
–
0.5
4
–
tSB
Byte Select Set-Up Time
Byte Select Hold Time
–
–
tHB
–
0.5
4
–
tSC
Chip Enable Set-Up Time
Chip Enable Hold Time
R/W Set-Up Time
–
–
tHC
–
0.5
4
–
tSW
–
–
tHW
tSD
R/W Hold Time
–
0.5
4
–
Input Data Set-Up Time
Input Data Hold Time
–
–
tHD
–
0.5
4
–
tSAD
tHAD
tSCN
tHCN
tSRST
tHRST
tOE
ADS Set-Up Time
–
–
ADS Hold Time
–
0.5
4
–
CNTEN Set-Up Time
–
–
CNTEN Hold Time
–
0.5
4
–
CNTRST Set-Up Time
–
–
CNTRST Hold Time
–
0.5
–
–
Output Enable to Data Valid
OE to Low Z
8
9
[10, 11]
tOLZ
tOHZ
tCD1
tCD2
tCA1
tCA2
tDC
2
–
2
–
[10, 11]
OE to High Z
1
7
1
7
Clock to Data Valid – Flow-Through
Clock to Data Valid – Pipelined
Clock to Counter Address Valid – Flow-Through
Clock to Counter Address Valid – Pipelined
Data Output Hold After Clock HIGH
Clock HIGH to Output High Z
Clock HIGH to Output Low Z
–
12.5
5
–
18
6
–
–
–
12.5
9
–
18
10
–
–
–
2
–
2
[10, 11]
tCKHZ
2
6
2
7
[10, 11]
tCKLZ
2
–
2
–
Notes
10. This parameter is guaranteed by design, but it is not production tested.
11. Test conditions used are Load 2.
Document Number: 38-06054 Rev. *H
Page 9 of 33
CY7C09569V
CY7C09579V
Switching Characteristics (continued)
Over the Operating Range
CY7C09569V/CY7C09579V
-100 -83
Parameter
Description
Unit
Min
Max
Min
Max
Port to Port Delays
tCWDD
tCCS
Write Port Clock HIGH to Read Data Delay
Clock to Clock Set-Up Time
–
–
30
9
–
–
35
10
ns
ns
Document Number: 38-06054 Rev. *H
Page 10 of 33
CY7C09569V
CY7C09579V
Switching Waveforms
Figure 4. Read Cycle for Flow-Through Output (FT/PIPE = VIL) [12, 13, 14, 15]
tCYC1
tCH1
tCL1
CLK
CE
tSC
tHC
tSC
tHC
tSB
tHB
B0-3
R/W
tSW
tSA
tHW
tHA
An
An+1
An+2
An+3
Address
DataOUT
tCKHZ
Qn+2
tDC
tDC
Qn
tCD1
Qn+1
tCKLZ
tOHZ
tOLZ
OE
tOE
Figure 5. Read Cycle for Pipelined Operation (FT/PIPE = VIH) [12, 13, 14, 15]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tSC
tHC
tSB
tHB
B0-3
R/W
tSW
tSA
tHW
tHA
Address
DataOUT
An
An+1
An+2
An+3
tDC
1 Latency
tCD2
Qn
Qn+1
Qn+2
tOHZ
tCKLZ
tOLZ
OE
t
OE
Notes
12. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
13. ADS = V , CNTEN = V and CNTRST = V
.
IH
IL
IL
14. The output is disabled (high-impedance state) by CE=V following the next rising edge of the clock.
IH
15. Addresses do not have to be accessed sequentially since ADS = V constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
IL
Document Number: 38-06054 Rev. *H
Page 11 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 6. Bus Match Read Cycle for Flow-Through Output (FT/PIPE = VIL) [16, 17, 18, 19, 20]
tCYC1
tCH1
tCL1
CLK
CE
tSC
tHC
ADS
R/W
tSW
tSA
tHW
tHA
An
An
An+1
An+1
Address
DataOUT
tDC
Qn
tCD1
Qn
Qn+1
1st
Cycle
Qn+1
2nd
Cycle
1st
Cycle
2nd
Cycle
tCKLZ
tDC
LOW
OE
Figure 7. Bus Match Read Cycle for Pipelined Operation (FT/PIPE = VIH) [16, 17, 18, 19, 20]
tCYC2
tCL2
tCH2
CLK
CE
tHC
tSC
R/W
tSW tHW
ADS
Address
An+1
An
An
An+1
tSA tHA
t
tCD2
tCD2
CD2
tCLKZ
DataOUT
Qn
Qn
Qn+1
1 Latency
tDC
1st Cycle
tDC
2nd Cycle
tDC
1st Cycle
OE
LOW
Notes
16. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
17. The output is disabled (high-impedance state) by CE=V following the next rising edge of the clock.
IH
18. Timing shown is for x18 bus matching; x9 bus matching is similar with 4 cycles between address inputs.
19. See table “Right Port Operation“ for data output on first and subsequent cycles.
20. CNTEN = V . In x9 and x18 Bus Matching Burst Mode operations (Write or Read), ADS can toggle on the rising edge of every clock cycle or it can be at V level all
IL
IH
the time except when loading the initial external address (i.e. ADS = V only required when reading or writing the first Byte or Word).
IL
Document Number: 38-06054 Rev. *H
Page 12 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 8. Bank Select Pipelined Read [21, 22]
tCYC2
tCH2
tCL2
CLKL
tHA
tSA
A3
A4
Address(B1)
A5
A0
A1
A2
tHC
tSC
CE(B1)
tCD2
tCD2
tCD2
tCKHZ
tHC
tCKHZ
tSC
Q0
Q3
Q1
DataOUT(B1)
Address(B2)
tHA
tSA
tDC
A2
tDC
A3
tCKLZ
A4
A5
A0
A1
tHC
tSC
CE(B2)
tCD2
tCKHZ
tCD2
tSC
tHC
DataOUT(B2)
Q4
Q2
tCKLZ
tCKLZ
Figure 9. Left Port Write to Flow-Through Right Port Read [22, 23, 24, 25, 26]
CLKL
R/WL
tHW
tSW
tHA
tSA
No
Match
AddressL
DataINL
Match
tHD
tSD
Valid
tCCS
CLKR
R/WR
tCD1
tSW tHW
tSA
tHA
No
Match
Match
AddressR
tCWDD
tCD1
DataOUTR
Valid
Valid
tDC
tDC
Notes
21. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this data sheet.
ADDRESS = ADDRESS
.
(B2)
(B1)
22. B0 = B1 = B2 = B3 = BM = SIZE = ADS = CNTEN = V , CNTRST = V
.
IL
IH
23. The same waveforms apply for a right port write to flow-through left port read.
24. CE = B0 = B1 = B2 = B3 = ADS = CNTEN=V ; CNTRST= V
.
IH
IL
25. OE = V for the right port, which is being read from. OE = V for the left port, which is being written to.
IL
IH
26. If t
maximum specified, then data from right port READ is not valid until the maximum specified for t
. If t > maximum specified, then data is not valid
CCS
CCS
CWDD
until t
+ t
(t
does not apply in this case).
CCS
CD1 CWDD
Document Number: 38-06054 Rev. *H
Page 13 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 10. Pipelined Read-to-Write-to-Read (OE = VIL) [27, 28, 29, 30]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tSW
tHW
R/W
tSW
tHW
An
An+1
An+2
An+2
An+3
An+4
Address
DataIN
tSD tHD
tSA
tHA
Dn+2
tCD2
tCD2
tCKHZ
tCKLZ
Qn
Qn+3
DataOUT
Read
No Operation
Write
Read
Notes
27. Addresses do not have to be accessed sequentially since ADS = V constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
IL
28. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
29. CE = ADS = CNTEN = V ; CNTRST = V
.
IL
IH
30. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
Document Number: 38-06054 Rev. *H
Page 14 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 11. Pipelined Read-to-Write-to-Read (OE Controlled) [31, 32, 33, 34]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tHW
tSW
R/W
tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
Address
DataIN
tSA
tHA
tSD tHD
Dn+2
Dn+3
tCD2
tCKLZ
tCD2
DataOUT
Qn
Qn+4
tOHZ
OE
Read
Write
Read
Notes
31. Test conditions used are Load 2.
32. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
33. CE = ADS = CNTEN = V ; CNTRST = V
.
IH
IL
34. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
Document Number: 38-06054 Rev. *H
Page 15 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 12. Bus Match Pipelined Read-to-Write-to-Read (OE = VIL) [35, 36, 37, 38, 39, 40, 41]
tCYC2
CLK
CE
tCL2
tCH2
tSC
tHC
R/W
tSW
tHW
Address
An+3
An+2
An+4
An+1
An+2
An+4
An
An+3
An
An+1
tSA
tHA
ADS
tCKLZ
2nd Word
Qn
1st Word
Qn+3
2nd Word
Qn+3
1st Word
Qn
DataOUT
tCKHZ
tCD2
tCD2
tCD2
2nd Word
Dn+2
1st Word
Dn+2
tDC
DataIN
tHD
tSD
No
Operation 1st Cycle
Read
1st Cycle
Read
1st Cycle
Read
Read
2nd Cycle
Write
2nd Cycle
Read
Read
2nd Cycle
Write
Notes
35. Test conditions used are Load 2.
36. Timing shown is for x18 bus matching; x9 bus matching is similar with 4 cycles between address inputs.
37. See table “Right Port Operation“ for data output on first and subsequent cycles.
38. CNTEN = V . In x9 and x18 Bus Matching Burst Mode operations (Write or Read), ADS can toggle on the rising edge of every clock cycle or it can be at V level all
IL
IH
the time except when loading the initial external address (i.e. ADS = V only required when reading or writing the first Byte or Word).
IL
39. CE = ADS = CNTEN = V ; CNTRST = V
.
IL
IH
40. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
41. BM, SIZE, and BE must be reconfigured 1 cycle before operation is guaranteed. BM, SIZE, and BE should remain static for any particular port configuration.
Document Number: 38-06054 Rev. *H
Page 16 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 13. Flow-Through Read-to-Write-to-Read (OE = VIL) [42, 43, 44, 45, 46, 47]
tCYC1
tCL1
tCH1
CLK
CE
tSW
tHW
R/W
tSW
tHW
An
An+1
An+2
An+2
An+3
An+4
Address
DataIN
tSD
tHD
tSA
tHA
Dn+2
tCD1
tCD1
tCD1
tCD1
DataOUT
Qn
tDC
Qn+1
tCKHZ
Qn+3
tCKLZ
tDC
No
Operation
Read
Write
Read
Figure 14. Flow-Through Read-to-Write-to-Read (OE Controlled) [42, 43,46, 47, 48]
tCYC1
tCH1
tCL1
CLK
CE
tSW
tHW
R/W
tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
Address
DataIN
tSD
tHD
tSA
tHA
Dn+2
Dn+3
tOE
tCD1
tDC
tCD1
tCD1
Qn
Qn+4
DataOUT
OE
tOHZ
tDC
tCKLZ
Read
Write
Read
Notes
42. ADS = V , CNTEN = V and CNTRST = V .
IH
IL
IL
43. Addresses do not have to be accessed sequentially since ADS = V constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
IL
44. Timing shown is for x18 bus matching; x9 bus matching is similar with 4 cycles between address inputs.
45. See table “Right Port Operation“ for data output on first and subsequent cycles.
46. CE = ADS = CNTEN = V ; CNTRST = V
.
IL
IH
47. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
48. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
Document Number: 38-06054 Rev. *H
Page 17 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 15. Bus Match Flow-Through Read-to-Write-to-Read (OE = VIL) [49, 50, 51, 52, 53, 54, 55]
tCYC1
tCH1 tCL1
CLK
CE
tSC tHC
tSW tHW
tSW tHW
R/W
tSA tHA
An+1
Address
ADS
An
An+1
An+1
An+2
An+1
An+1
An
tSD tHD
Dn+1
Dn+1
DataIN
tCD1
tDC
2nd Word
1st Word
tCKHZ
tCD1
tCD1
tCD1
Qn
1st Word
Qn+1
Qn+1
Qn
DataOUT
2nd Word
tDC
tCKLZ
Read
1st Cycle
Read
2nd Cycle
No
Operation
Write
1st Cycle
Write
2nd Cycle
Read
1st Cycle
Read
2nd Cycle
Notes
49. Test conditions used are Load 2.
50. Timing shown is for x 18 bus matching; x 9 bus matching is similar with 4 cycles between address inputs.
51. See table “Right Port Operation“ for data output on first and subsequent cycles.
52. CNTEN = V . In x9 and x18 Bus Matching Burst Mode operations (Write or Read), ADS can toggle on the rising edge of every clock cycle or it can be at V level
IL
IH
all the time except when loading the initial external address (i.e. ADS = V only required when reading or writing the first Byte or Word).
IL
53. CE = ADS = CNTEN = V ; CNTRST = V
.
IL
IH
54. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
55. BM, SIZE, and BE must be reconfigured 1 cycle before operation is guaranteed. BM, SIZE, and BE should remain static for any particular port configuration.
Document Number: 38-06054 Rev. *H
Page 18 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 16. Pipelined Read with Address Counter Advance [56]
tCYC2
tCL2
tCH2
CLK
tSA
tHA
Address
An
tSAD
tHAD
ADS
tSAD
tHAD
CNTEN
tSCN
tHCN
tSCN
tHCN
tCD2
DataOUT
Qx–1
Qx
tDC
Qn
Qn+1
Qn+2
Qn+3
Read
Counter Hold
Read with Counter
Read with Counter
External
Address
Figure 17. Flow-Through Read with Address Counter Advance [56]
tCYC1
tCL1
tCH1
CLK
tSA
tHA
An
Address
tSAD
tHAD
ADS
tSAD
tHAD
CNTEN
tSCN
tHCN
tCD1
tSCN
Qn+2
tHCN
Qx
tDC
Qn
Qn+1
DataOUT
Qn+3
Qn+4
Counter Hold
Read
tDC
tDC
Read
with
External
Address
Read with Counter
tCD1
tCD1
Counter
Note
56. CE = OE = V ; R/W = CNTRST = V
.
IH
IL
Document Number: 38-06054 Rev. *H
Page 19 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 18. Write with Address Counter Advance (Flow-Through or Pipelined Outputs) [57, 58]
tCYC2
tCL2
tCH2
CLK
tSA
tHA
An
Address
Internal
Address
An
An+1
An+2
An+3
An+4
tSAD
tHAD
ADS
CNTEN
DataIN
tSCN
tHCN
Dn
Dn+1
Dn+1
Dn+2
Dn+3
Dn+4
tSD
tHD
Write External Address
Write with Counter Write Counter Hold Write with Counter
Notes
57. CE= B0 = B1 = B2 = B3 = R/W = V ; CNTRST = V
.
IH
IL
58. The “Internal Address” is equal to the “External Address” when ADS = CNTEN = V and CNTRST = V
.
IL
IH
Document Number: 38-06054 Rev. *H
Page 20 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 19. Counter Reset (Pipelined Outputs) [59, 60, 61, 62, 63]
tCYC2
tCH2 tCL2
CLK
tHA
Am
tSA
Ap
An
Address
Internal
Address
Ap
Ax
An
1
0
Am
tHW
tSW
R/W
ADS
CNTEN
CNTRST
tHRST
tSRST
tHD
tSD
DataIN
D0
tCD2
tCD2
[63]
DataOUT
Q0
Qn
Q1
tCKLZ
Read Address 1 Read Address An
Write Address 0 Read Address 0
Counter Reset
Read Address Am
Notes
59. Test conditions used are Load 2.
60. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
61. CE = B0 = B1 = B2 = B3 = V .
IL
62. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
63. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. Ideally, DATA
a valid WRITE cycle.
should be in the High-Impedance state during
OUT
Document Number: 38-06054 Rev. *H
Page 21 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 20. Counter Reset (Flow-Through Outputs) [64, 65, 66, 67, 68]
tCYC2
tCL2
tCH2
CLK
tSA tHA
An
An+1
Address
Internal
Address
AX
0
An
An+1
1
tSW tHW
R/W
ADS
CNTEN
tHRST
tSRST
CNTRST
DataIN
tHD
tSD
D0
tCD1
DataOUT
Q0
Qn
Q1
Counter Reset
Write Address 0
Read Address 0
Read Address 1 Read Address n
Notes
64. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
65. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
66. CE = B0 = B1 = B2 = B3 = V .
IL
67. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
68. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. Ideally, DATA
should be in the High-Impedance state during
OUT
a valid WRITE cycle.
Document Number: 38-06054 Rev. *H
Page 22 of 33
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Figure 21. Pipelined Read of State of Address Counter [69, 70, 71]
tCYC2
tCH2 tCL2
CLK
tSA
tHA
An
Address
Internal
Address
An
An+2
An+1
tSAD
tHAD
ADS
CNTEN
DataOUT
tSAD
tHAD
tSCN
tHCN
tSCN
tHCN
tSCN
tHCN
tCA2
Qx-1
Qx-2
Qn
An
Qn+1
Qn+2
Read with
Counter
Load
External
Address
tDC
Read Counter Address
Counter
Hold
Read With Counter
Figure 22. Flow-Through Read of State of Address Counter [69, 70, 72]
tCYC1
tCH1 tCL1
CLK
tSA
tHA
An
Address
Internal
Address
An
An+1
An+3
An+2
tSAD
tHAD
ADS
CNTEN
tSAD
tHAD
tSCN
tHCN
tSCN
tHCN
tCA1
tHCN
tSCN
DataOUT
Qn
Qx
An
Qn+2
Qn+1
Read with
Qn+3
tDC
Read Counter Address
Load
External
Address
Counter
Counter
Hold
Read with Counter
Notes
69. CE = OE = V ; R/W = CNTRST = V
.
IL
IH
70. When reading ADDRESS
in x 9 Bus Match mode, readout of A is extended by 1 cycle.
OUT
N
71. For Pipelined address counter read, signals from address counter operation table from must be valid for 2 consecutive cycles for x 36 and x 18 mode and for 3
consecutive cycles for x 9 mode.
72. For flow-through address counter read, signals from address counter operation table must be valid for consecutive cycles for x 36.
Document Number: 38-06054 Rev. *H
Page 23 of 33
CY7C09569V
CY7C09579V
Read/Write and Enable Operation
The Read/Write and Enable Operation is described as follows. [73, 74, 75]
Inputs
Outputs
Operation
Deselected [76]
OE
CLK
CE
R/W
I/O0–I/O35
X
H
X
High Z
X
L
L
L
L
L
H
X
DIN
Write
DOUT
High Z
Read[76]
H
X
Outputs disabled
Address Counter Control Operation
The Address Counter Control Operation is described as follows. [73, 77]
Previous
Address
Address
CLK
OE
R/W ADS CNTEN CNTRST
Mode
Operation
X
X
X
X
X
H
X
L
L
X
L
L
H
H
Reset
Counter reset
An
An
X
X
L
Load
Address load into counter
An
H
Hold + Read External address blocked –
counter address readout
X
X
An
An
X
X
X
X
H
H
H
L
H
H
Hold
External address blocked –
counter disabled
Increment Counter increment
Notes
73. “X” = “Don’t Care,” “H” = V , “L” = V .
IH
IL
74. ADS, CNTEN, CNTRST = “Don’t Care.”
75. OE is an asynchronous input signal.
76. When CE changes state In the pipelined mode, deselection and read happen in the following clock cycle.
77. Counter operation is independent of CE.
Document Number: 38-06054 Rev. *H
Page 24 of 33
CY7C09569V
CY7C09579V
Right Port Configuration
The Right Port Configuration is described as follows. [78, 79]
BM
0
SIZE
Configuration
I/O Pins used
I/O0R–35R
I/O0R–17R
I/O0R–8R
0
0
1
× 36
× 18
× 9
1
1
Right Port Operation
The Right Port Operation is described as follows. [80]
Configuration
BE
0
Data on 1st Cycle
Q0R–17R
Data on 2nd Cycle Data on 3rd Cycle
Data on 4th Cycle
× 18
× 18
× 9
Q18R–35R
Q0R–17R
Q9R–17R
Q18R–26R
–
–
–
1
Q18R–35R
–
0
Q0R–8R
Q18R–26R
Q9R–17R
Q27R–35R
Q0R–8R
× 9
1
Q27R–35R
Readout of Internal Address Counter
The Readout of Internal Address Counter is described as follows. [81]
Configuration Address on 1st Cycle I/O Pins used on 1st Cycle Address on 2nd Cycle I/O Pins used on 2nd Cycle
Left Port × 36
Right Port × 36
Right Port × 18
Right Port × 9
A0L–14L
A0R–14R
I/O3L–17L
I/O3R–17R
I/O2R–17R
I/O0R–8R
–
–
–
–
–
WA, A0R–14R
A6R–14R
–
BA, WA, A0R–5R
I/O1R–8R
Left Port Operation
The Left Port Operation is described as follows.
Control Pin
Effect
B0
B1
B2
B3
I/O0–8 Byte Control
I/O9–17 Byte Control
I/O18–26 Byte Control
I/O27–35 Byte Control
Notes
78. BM, SIZE, and BE must be reconfigured 1 cycle before operation is guaranteed. BM, SIZE, and BE should remain static for any particular port configuration.
79. In x36 mode, BE input is a “Don’t Care.”
80. DQ represents data output of the chip.
81. x18 and x9 configuration apply to right port only.
Document Number: 38-06054 Rev. *H
Page 25 of 33
CY7C09569V
CY7C09579V
long-word, 18-bit word, or 9-bit byte format for data I/O. The data
lines are divided into four lanes, each consisting of 9 bits
(byte-size data lines).
Counter Operation
The CY7C09569V/CY7C09579V Dual-Port RAM (DPRAM)
contains on-chip address counters (one for each port) for the
synchronous members of the product family. Besides the main
× 36 format, the right port allows bus matching (× 18 or × 9,
user-selectable). An internal sub-counter provides the extra
addresses required to sequence out the 36-bit word in 18-bit or
9-bit increments. The sub-counter counts up in the “Little Endian”
mode, and counts down if the user has chosen the “Big Endian”
mode. The address counter is required to be in increment mode
in order for the sub-counter to sequence out the second word (in
× 18 mode) or the remaining three bytes (in × 9 mode).
Figure 24. Bus Match Operation Diagram
BE
9
/
CY7C09569V
CY7C09579V
16K/32Kx36
Dual Port
9
/
9
/
x36
/
x9, x18, x36
/
9
/
For a × 36 format (the only active format on the left port), each
address counter in the CY7C09579V uses addresses (A0–14).
For the right port (allowing for the bus-matching feature), a
maximum of two address bits (out of a 2-bit sub-counter) are
added.
BM SIZE
The Bus Match Select (BM) pin works with Bus Size Select
(SIZE) and Big Endian Select (BE) to select the bus width
(long-word, word, or byte) and data sequencing arrangement for
the right port of the dual-port device. A logic LOW applied to both
the Bus Match Select (BM) pin and to the Bus Size Select (SIZE)
pin will select long-word (36-bit) operation. A logic HIGH level
applied to the Bus Match Select (BM) pin will enable whether
byte or word bus width operation on the right port I/Os depending
on the logic level applied to the SIZE pin. The level of Bus Match
Select (BM) must be static throughout normal device operation.
1. ADSL/R (pin #23/86) is a port’s address strobe, allowing the
loading of that port's burst counters if the corresponding
CNTENL/R pin is active as well.
2. CNTENL/R (pin #25/84) is a port’s count enable, provided to
stall the operation of the address input and utilize the internal
address generated by the internal counter for fast interleaved
memory applications; when asserted, the address counter will
increment on each positive transition of that port's clock
signal.
3. CNTRSTL/R (pin #24/85) is a port's burst counter reset.
The Bus Size Select (SIZE) pin selects either a byte or word data
arrangement on the right port when the Bus Match Select (BM)
pin is HIGH. A logic HIGH on the SIZE pin when the BM pin is
HIGH selects a byte bus (9-bit) data arrangement. A logic LOW
on the SIZE pin when the BM pin is HIGH selects a word bus
(18-bit) data arrangement. The level of the Bus Size Select
(SIZE) must also be static throughout normal device operation.
A new read-back (Hold+Read Mode) feature has been added,
which is different between the left and right port due to the bus
matching feature provided only for the right port. In read-back
mode the internal address of the counter will be read from the
data I/Os as shown in Figure 23.
Figure 23. Counter Operation Diagram
The Big Endian Select (BE) pin is a multiple-function pin during
word or byte bus selection (BM = 1). BE is used in Big Endian
Select mode to determine the order by which bytes (or words) of
data are transferred through the right data port. A logic LOW on
the BE pin will select Little Endian data sequencing arrangement
and a logic HIGH on the BE pin will select a Big Endian data
sequencing arrangement. Under these circumstances, the level
on the BE pin should be static throughout dual-port operation.
Address
CY7C09569V
CY7C09579V
RAM
ARRAY
Long-Word (36-bit) Operation
_______
Bus Match Select (BM) and Bus Size Select (SIZE) set to a logic
LOW will enable standard cycle long-word (36-bit) operation. In
this mode, the right port’s I/O operates essentially in an identical
fashion to the left port of the dual-port SRAM. However no Byte
Select control is available. All 36 bits of the long-word are shifted
into and out of the right port’s I/O buffer stages. All read and write
timing parameters may be identical with respect to the two data
ports. When the right port is configured for a long-word size, Big-
Endian Select (BE) pin has no application and their inputs are
“Don’t Care”[82] for the external user.
ADS
______________
CNTRST
____________
CNTEN
Bus Match Operation
The
right
port
of
the
CY7C09569V/CY7C09579V
16 K / 32 K × 36 dual-port SRAM can be configured in a 36-bit
Note
82. Even though a logic level applied to a “Don’t Care” input will not change the logical operation of the dual-port, inputs that are temporarily a “Don’t Care” (along with
unused inputs) must not be allowed to float. They must be forced either HIGH or LOW.
Document Number: 38-06054 Rev. *H
Page 26 of 33
CY7C09569V
CY7C09579V
Word (18-bit) Operation
Byte (9-bit) Operation
Word (18-bit) bus sizing operation is enabled when Bus Match
Select (BM) is set to a logic HIGH and the Bus Size Select (SIZE)
pin is set to a logic LOW. In this mode, 18 bits of data are ported
through I/O0R–17R. The level applied to the Big Endian (BE) pin
determines the right port data I/O sequencing order (Big Endian
or Little Endian).
Byte (9-bit) bus sizing operation is enabled when Bus Match
Select (BM) is set to a logic HIGH and the Bus Size Select (SIZE)
pin is set to a logic HIGH. In this mode, 9 bits of data are ported
through I/O0R–8R
.
Big Endian and Little Endian data sequencing is available for
dual-port operation. The level applied to the Big Endian pin (BE)
under these circumstances will determine the right port data I/O
sequencing order (Big or Little Endian). A logic LOW applied to
the BE pin during byte (9-bit) bus size operation will select Little
Endian operation. In this case, the least significant data byte is
read from the right port first or written to the right port first. A logic
HIGH on the BE pin during byte (9-bit) bus size operation will
select Big Endian operation resulting in the most significant data
word to be transferred through the right port first. Internally, the
data will be stored in the appropriate 36-bit LSB or MSB I/O
memory location. Device operation requires a minimum of four
clock cycles to read or write during byte (9-bit) bus size
operation. An internal sub-counter automatically increments the
right port multiplexer control when Little or Big Endian operation
is in effect. When transferring data in byte (9-bit) bus match
format, the unused I/O pins (I/O9R–35R) are three-stated.
During word (18-bit) bus size operation, a logic LOW applied to
the BE pin will select Little Endian operation. In this case, the
least significant data word is read from the right port first or
written to the right port first. A logic HIGH on the BE pin during
word (18-bit) bus size operation will select Big Endian operation
resulting in the most significant data word being transferred
through the right port first. Internally, the data will be stored in the
appropriate 36-bit LSB or MSB I/O memory location. Device
operation requires a minimum of two clock cycles to read or write
during word (18-bit) bus size operation. An internal sub-counter
automatically increments the right port multiplexer control when
Little or Big Endian operation is in effect.
Document Number: 38-06054 Rev. *H
Page 27 of 33
CY7C09569V
CY7C09579V
Ordering Information
16 K × 36 3.3 V Synchronous Dual-Port SRAM
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
144-pin TQFP (Pb-free)
100
CY7C09569V-100AXC
A144
Commercial
32K × 36 3.3 V Synchronous Dual-Port SRAM
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
144-pin TQFP (Pb-free)
100
CY7C09579V-100AXC
CY7C09579V-100BBC
CY7C09579V-83AXC
CY7C09579V-83BBC
A144
BB172
A144
Commercial
172-ball BGA
83
144-pin TQFP (Pb-free)
172-ball BGA
Commercial
BB172
Ordering Code Definitions
CY 09 X9 V - XXX X
7
C
5
X
X
Temperature Range:
C = Commercial
X = Pb-free (RoHS Compliant)
Package Type: X = A or BB
A = 144-pin TQFP
BB = 172-ball BGA
Speed Grade: XXX = 83 MHz or 100 MHz
V = 3.3 V
Depth: X9, where X = 6 or 7
6 = 16K; 7 = 32K
5 = Width: × 36
09 = Sync
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress Device
Document Number: 38-06054 Rev. *H
Page 28 of 33
CY7C09569V
CY7C09579V
Package Diagrams
Figure 25. 144-pin TQFP (20 × 20 × 1.4 mm) A144SA Package Outline, 51-85047
51-85047 *D
Document Number: 38-06054 Rev. *H
Page 29 of 33
CY7C09569V
CY7C09579V
Package Diagrams (continued)
Figure 26. 172-ball FBGA (15 × 15 × 1.25 mm) BB172 Package Outline, 51-85114
51-85114 *E
Document Number: 38-06054 Rev. *H
Page 30 of 33
CY7C09569V
CY7C09579V
Acronyms
Document Conventions
Units of Measure
Acronym
Description
ADS
address strobe
Symbol
°C
Unit of Measure
BGA
ball grid array
chip enable
degree Celsius
megahertz
microampere
milliampere
millimeter
nanosecond
picofarad
volt
CE
MHz
µA
mA
mm
ns
CMOS
CNTEN
CNTRST
I/O
complementary metal oxide semiconductor
count enable
counter reset
input/output
LSB
least significant bit
pF
MSB
OE
most significant bit
V
output enable
W
watt
SRAM
TQFP
TTL
static random access memory
thin quad flat pack
transistor-transistor logic
Document Number: 38-06054 Rev. *H
Page 31 of 33
CY7C09569V
CY7C09579V
Document History Page
Document Title: CY7C09569V/CY7C09579V, 3.3 V 16 K / 32 K × 36 FLEx36® Synchronous Dual-Port Static RAM
Document Number: 38-06054
Orig. of
Change
Submission
Date
Rev.
ECN
Description of Change
**
110213
122304
SZV
RBI
12/16/01
12/27/02
Change from Spec number: 38-00743 to 38-06054
*A
Updated Maximum Ratings (Added Power up requirements to Maximum
Ratings Information).
*B
*C
349775
RUY
See ECN Updated Ordering Information (Added Pb-free Information).
2897215
RAME
03/22/10
12/14/10
02/04/11
Updated Ordering Information (Removed inactive parts).
Updated Package Diagrams.
*D
*E
3110406
3162642
ADMU
ADMU
Added Ordering Code Definitions.
Minor edits and updated in new template.
Updated Selection Guide (Removed speed bin -67 related information).
Updated Operating Range (Removed Industrial Temperature Range
information).
Updated Electrical Characteristics (Removed speed bin -67 related
information).
Updated Switching Characteristics (Removed speed bin -67 related
information).
Added Acronyms and Units of Measure.
*F
3352391
3702863
ADMU
SMCH
08/23/11
Updated Package Diagrams (Spec 51-85047 (Changed revision from *C to
*D)).
*G
08/20/2012 Updated Logic Block Diagram (Aligned all the objects correctly).
Updated Switching Waveforms (Updated Figure 18 (Aligned the naming of
objects correctly), updated Figure 19 (Aligned the naming of objects correctly),
updated Figure 20 (Aligned the naming of objects correctly)).
Updated Right Port Operation (Updated the columns Data on 1st Cycle, Data
on 2nd Cycle, Data on 3rd Cycle and Data on 4th Cycle).
Updated Bus Match Operation (Updated Byte (9-bit) Operation (description)).
Updated Package Diagrams (Spec 51-85114 (Changed revision from *C to
*D)).
Replaced Logic ‘0’ with Logic LOW and replaced Logic ‘1’ with Logic HIGH
across the document.
*H
3859909
SMCH
01/07/2013 Updated Ordering Information (Updated part numbers).
Updated Package Diagrams:
spec 51-85114 – Changed revision from *D to *E.
Document Number: 38-06054 Rev. *H
Page 32 of 33
CY7C09569V
CY7C09579V
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2001-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-06054 Rev. *H
Revised January 7, 2013
Page 33 of 33
FLEx36 is a registered trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
相关型号：
CY7C09579V-67AI
Dual-Port SRAM, 128KX9, 8ns, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-144
CYPRESS
CY7C09579V-67BAC
Dual-Port SRAM, 32KX36, 8ns, CMOS, PBGA172, 15 X 15 MM, 0.51 MM HEIGHT, 1 MM PITCH, BGA-172
CYPRESS
CY7C09579V-67BAI
Dual-Port SRAM, 128KX9, 8ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, MINI, BGA-144
CYPRESS
CY7C09579V-83BAI
Dual-Port SRAM, 32KX36, 6ns, CMOS, PBGA172, 15 X 15 MM, 0.51 MM HEIGHT, 1 MM PITCH, BGA-172
CYPRESS
©2020 ICPDF网 联系我们和版权申明