CY7C1012AV33-10BGCT [CYPRESS]
Standard SRAM, 512KX24, 10ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119;
| 型号： | CY7C1012AV33-10BGCT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 512KX24, 10ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119 静态存储器 内存集成电路 |
| 文件： | 总9页 (文件大小：303K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1012AV33
512K x 24 Static RAM
power-down feature that significantly reduces power
consumption when deselected.
Features
• High speed
Writing the data bytes into the SRAM is accomplished when
the chip select controlling that byte is LOW and the write
enable input (WE) input is LOW. Data on the respective
input/output (I/O) pins is then written into the location specified
on the address pins (A0–A18). Asserting all of the chip selects
LOW and write enable LOW will write all 24 bits of data into
the SRAM. Output enable (OE) is ignored while in WRITE
mode.
— tAA = 8 ns
• Low active power
— 1080 mW (max.)
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
Data bytes can also be individually read from the device.
Reading a byte is accomplished when the chip select
controlling that byte is LOW and write enable (WE) HIGH while
output enable (OE) remains LOW. Under these conditions, the
contents of the memory location specified on the address pins
will appear on the specified data input/output (I/O) pins.
Asserting all the chip selects LOW will read all 24 bits of data
from the SRAM.
• Easy memory expansion with CE0, CE1 and CE2
features
• Available in non Pb-free 119 ball PBGA.
Functional Description
The 24 I/O pins (I/O0–I/O23) are placed in a high-impedance
state when all the chip selects are HIGH or when the output
enable (OE) is HIGH during a READ mode. For further details,
refer to the truth table of this data sheet.
The CY7C1012AV33 is a high-performance CMOS static RAM
organized as 512K words by 24 bits. Each data byte is
separately controlled by the individual chip selects (CE0, CE1,
CE2). CE0 controls the data on the I/O0–I/O7, while CE1
controls the data on I/O8–I/O15, and CE2 controls the data on
the data pins I/O16–I/O23. This device has an automatic
TheCY7C1012AV33isavailableinastandard119-ballPBGA.
Functional Block Diagram
INPUT BUFFER
A
0
A
1
A
2
I/O –I/O
0
7
A
3
512K x 24
ARRAY
A
4
I/O –I/O
8
15
A
5
A
6
I/O –I/O
16
23
A
7
A
8
A
9
CE , CE , CE
2
0
1
COLUMN
DECODER
WE
OE
CONTROL LOGIC
Selection Guide
–8
8
–10
10
Unit
ns
Maximum Access Time
Maximum Operating Current
Commercial
300
300
50
275
275
50
mA
Industrial
Maximum CMOS Standby Current
Commercial/Industrial
mA
Cypress Semiconductor Corporation
Document #: 38-05254 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 3, 2006
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CY7C1012AV33
Pin Configurations[1, 2]
119 PBGA
Top View
1
2
3
4
5
6
7
A
B
C
D
E
F
NC
A
A
A
A
A
NC
NC
A
A
CE0
NC
A
A
NC
I/O12
I/O13
I/O14
I/O15
I/O16
I/O17
NC
NC
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
A
CE1
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
NC
A
CE2
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
NC
A
NC
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
A
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
DNU
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
G
H
J
K
L
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
NC
M
N
P
R
T
A
WE
OE
A
U
NC
A
A
A
A
NC
Notes:
1. NC pins are not connected on the die.
2. DNU pins have to be left floating or tied to VSS to ensure proper application.
Document #: 38-05254 Rev. *E
Page 2 of 9
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CY7C1012AV33
DC Input Voltage[3] ................................ –0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Operating Range
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[3] .... –0.5V to +4.6V
Ambient
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VCC
3.3V ± 0.3V
DC Voltage Applied to Outputs
in High-Z State[3] ....................................–0.5V to VCC + 0.5V
DC Electrical Characteristics Over the Operating Range
–8
–10
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Test Conditions[4]
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
Min.
Max.
Min.
Max.
Unit
2.4
2.4
V
V
VOL
0.4
0.4
VIH
2.0
–0.3
–1
VCC + 0.3
2.0
–0.3
–1
VCC + 0.3
V
[3]
VIL
0.8
+1
+1
0.8
+1
+1
V
IIX
Input Leakage Current GND < VI < VCC
µA
µA
IOZ
Output Leakage Current GND < VOUT < VCC, Output
Disabled
–1
–1
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
Commercial
Industrial
300
300
100
275
275
100
mA
mA
mA
ISB1
Automatic CE
Power-down Current
Max. VCC, CE > VIH
VIN > VIH or
—TTL Inputs
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-down Current
—CMOS Inputs
Max. VCC
CE > VCC – 0.3V,
IN > VCC – 0.3V,
or VIN < 0.3V, f = 0
,
Commercial
/Industrial
50
50
mA
V
Capacitance[5]
Parameter
CIN
Description
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 3.3V
Max.
Unit
Input Capacitance
I/O Capacitance
8
pF
pF
COUT
10
AC Test Loads and Waveforms[6]
R1 317
Ω
50Ω
3.3V
OUTPUT
OUTPUT
= 1.5V
VTH
Z = 50Ω
30 pF*
0
R2
351Ω
* Capacitive Load consists of all
5 pF
components of the test environment.
(a)
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
(b)
3.3V
90%
10%
90%
10%
GND
Rise time > 1 V/ns
Fall time: > 1 V/ns
(c)
Notes:
3. V (min.) = –2.0V for pulse durations of less than 20 ns.
IL
4. CE refers to a combination of CE , CE , and CE . CE is active LOW when all three of these signals are active LOW at the same time.
0
1
2
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05254 Rev. *E
Page 3 of 9
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CY7C1012AV33
AC Switching Characteristics Over the Operating Range[7]
–8
–10
Parameter
Description
Min.
Max.
Min.
Max.
Unit
Read Cycle
[8]
tpower
VCC(typical) to the first access
Read Cycle Time
1
8
1
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
10
tAA
Address to Data Valid
8
10
tOHA
tACE
Data Hold from Address Change
CE1, CE2, and CE3 LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[9]
OE HIGH to High-Z[9]
CE1, CE2, and CE3 LOW to Low-Z[9]
CE1, CE2, or CE3 HIGH to High-Z[9]
CE1, CE2, and CE3 LOW to Power-up[10]
CE1, CE2, or CE3 HIGH to Power-down[10]
Byte Enable to Data Valid
3
3
8
5
10
5
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
1
3
0
1
3
0
5
5
5
5
tPD
8
5
10
5
tDBE
tLZBE
tHZBE
Write Cycle[11, 12]
tWC
Byte Enable to Low-Z[9]
Byte Disable to High-Z[9]
1
1
5
5
Write Cycle Time
8
6
6
0
0
6
5
0
3
10
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE1, CE2, and CE3 LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tAW
7
tHA
0
tSA
0
tPWE
tSD
7
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z[9]
5.5
0
tHD
tLZWE
tHZWE
3
WE LOW to High-Z[9]
5
5
tBW
Byte Enable to End of Write
6
7
Notes:
6. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V (3.0V). As soon as 1 ms (T
) after reaching the
DD
power
minimum operating V , normal SRAM operation can begin including reduction in V to the data retention (V , 2.0V) voltage.
DD
DD
CCDR
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I and transmission line loads. Test conditions for the read cycle use output loading as shown in part a) of the AC test loads, unless specified otherwise.
OL OH
8. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. t
started.
time has to be provided initially before a read/write operation is
power
9. t
, t
, t
, t
, and t
, t
, t
, t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
HZOE HZCE HZWE HZBE
LZOE LZCE LZWE LZBE
±200 mV from steady-state voltage.
10. These parameters are guaranteed by design and are not tested.
Document #: 38-05254 Rev. *E
Page 4 of 9
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CY7C1012AV33
Switching Waveforms
Read Cycle No. 1[13, 14]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[4, 14, 15]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
ISB
t
PU
V
CC
50%
50%
SUPPLY
CURRENT
Write Cycle No. 1 (CE Controlled)[4, 16, 17]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Notes:
11. The internal write time of the memory is defined by the overlap of CE , CE , and CE LOW and WE LOW. The chip enables must be active and WE must be LOW
1
2
3
to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge
of the signal that terminates the write.
12. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
13. Device is continuously selected. OE, CE = V .
IL
14. WE is HIGH for read cycle.
15. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05254 Rev. *E
Page 5 of 9
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CY7C1012AV33
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[16, 17]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 18
t
HZOE
Write Cycle No. 3 (WE Controlled, OE LOW)[4, 17]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 18
DATA I/O
DATA VALID
t
t
LZWE
HZWE
Notes:
16. Data I/O is high impedance if OE = V
.
IH
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
18. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05254 Rev. *E
Page 6 of 9
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CY7C1012AV33
Truth Table
CE0
H
L
CE1
H
H
L
CE2
H
H
H
L
OE
X
L
WE
X
I/O0–I/O23
Mode
Power
High-Z
Power-down
Read
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
H
H
H
H
L
I/O0–I/O7 Data Out
I/O8–I/O15 Data Out
I/O16–I/O23 Data Out
Full Data Out
)
H
H
L
L
Read
)
H
L
L
Read
)
L
L
Read
)
L
H
L
H
H
L
X
X
X
X
H
I/O0–I/O7 Data In
I/O8–I/O15 Data In
I/O16–I/O23 Data In
Full Data In
Write
)
H
H
L
L
Write
)
H
L
L
Write
)
L
L
Write
)
L
L
L
H
High-Z
Selected, Outputs Disabled
)
Ordering Information
Speed
Package
Diagram
Operating
Range
(ns)
Ordering Code
CY7C1012AV33-8BGC
CY7C1012AV33-8BGI
CY7C1012AV33-10BGC
CY7C1012AV33-10BGI
Package Type
8
51-85115 119-ball (14 x 22 x 2.4 mm) PBGA
Commercial
Industrial
10
Commercial
Industrial
Document #: 38-05254 Rev. *E
Page 7 of 9
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CY7C1012AV33
Package Diagram
119-ball PBGA (14 x 22 x 2.4 mm) (51-85115)
51-85115-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05254 Rev. *E
Page 8 of 9
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1012AV33
Document History Page
Document Title: CY7C1012AV33 512K x 24 Static RAM
Document Number: 38-05254
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
113711
117057
117988
118992
Description of Change
03/11/02
07/31/02
09/03/02
09/19/02
NSL
DFP
DFP
DFP
New Data Sheet
Removed 15-ns bin
Added 8-ns bin
*A
*B
*C
Change Cin - input capacitance -from 6 pF to 8 pF
Change Cout -output capacitance from 8 pF to 10 pF
*D
*E
120382
492137
11/15/02
See ECN
DFP
NXR
Final data sheet. Added note 4 to “AC Test Loads and Waveforms”
Removed 12 ns speed bin from product offering
Included note #1 and 2 on page #2
Changed the description of IIX from Input Load Current to Input Leakage
Current in DC Electrical Characteristics table
Updated Ordering Information Table
Document #: 38-05254 Rev. *E
Page 9 of 9
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