CY7C1021D-10VXI [CYPRESS]
1-Mbit (64K x 16) Static RAM; 1兆位（ 64K ×16 ）静态RAM
| 型号： | CY7C1021D-10VXI |
| 厂家： | 
CYPRESS |
| 描述： | 1-Mbit (64K x 16) Static RAM |
| 文件： | 总11页 (文件大小：557K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1021D
1-Mbit (64K x 16) Static RAM
Features
Functional Description [1]
• Pin-and function-compatible with CY7C1021B
• High speed
The CY7C1021D is a high-performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
automatic power-down feature that significantly reduces
power consumption when deselected. The input/output pins
(IO0 through IO15) are placed in a high-impedance state when:
— tAA = 10 ns
• Low active power
— ICC = 80 mA @ 10 ns
• Deselected (CE HIGH)
• Outputs are disabled (OE HIGH)
• Low CMOS Standby Power
— ISB2 = 3 mA
• BHE and BLE are disabled (BHE, BLE HIGH)
• When the write operation is active (CE LOW, and WE LOW)
• 2.0V Data Retention
Write to the device by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW,
then data from IO pins (IO0 through IO7), is written into the
location specified on the address pins (A0 through A15). If Byte
High Enable (BHE) is LOW, then data from IO pins (IO8
through IO15) is written into the location specified on the
address pins (A0 through A15).
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Independent control of upper and lower bits
• Available in Pb-free 44-pin 400-Mil wide Molded SOJ and
44-pin TSOP II packages
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
If Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO0 to IO7.
If Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. See the “Truth Table” on page 8 for a
complete description of read and write modes.
Logic Block Diagram
DATA IN DRIVERS
A7
A6
A5
64K x 16
A4
IO0–IO7
RAM Array
A3
A2
A1
A0
IO8–IO15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05462 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 22, 2007
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CY7C1021D
Pin Configuration [2]
SOJ/TSOP II
Top View
A
A
A
A
A
OE
BHE
BLE
IO
15
IO
IO
13
IO
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
4
3
5
6
7
A
A
A
2
1
0
CE
IO
0
1
2
3
IO
IO
IO
V
14
9
10
11
12
13
14
15
16
12
V
CC
SS
V
SS
V
CC
IO
IO
IO
4
5
6
7
11
10
IO
IO
IO
IO
IO
9
8
NC
WE 17
A
A
A
A
18
19
20
21
22
A
15
14
13
12
8
A
9
A
A
10
11
NC
NC
Selection Guide
–10 (Industrial)
–12 (Automotive) [3]
Unit
ns
10
80
3
Maximum Access Time
12
120
15
mA
mA
Maximum Operating Current
Maximum CMOS Standby Current
Notes
2. NC pins are not connected on the die.
3. Automotive Product Information is Preliminary.
Document #: 38-05462 Rev. *E
Page 2 of 11
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CY7C1021D
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.
Latch-up Current .................................................... > 200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND [4] ... –0.5V to +6.0V
Ambient
Temperature
Range
VCC
Speed
Industrial
–40°C to +85°C
5V ± 10%
10 ns
12 ns
DC Voltage Applied to Outputs
in High-Z State [4].....................................–0.5V to VCC+0.5V
Automotive –40°C to +125°C
DC Input Voltage [4]..................................–0.5V to VCC+0.5V
Electrical Characteristics (Over the Operating Range)
–10 (Industrial)
–12 (Automotive)
Parameter
Description
Test Conditions
Unit
Min
Max
Min
Max
VOH
VOL
VIH
VIL
IIX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
IOH = –4.0 mA
2.4
2.4
V
V
IOL = 8.0 mA
0.4
0.4
2.2
−0.5
−1
VCC + 0.5V
2.0
–0.5
–5
VCC + 0.5V
V
Input LOW Voltage [4]
Input Leakage Current
Output Leakage Current
0.8
+1
+1
80
72
58
37
10
0.8
+5
+5
-
V
GND < VI < VCC
µA
µA
mA
mA
mA
mA
mA
IOZ
ICC
GND < VI < VCC, Output Disabled
−1
–5
VCC Operating
Supply Current
VCC = Max,
IOUT = 0 mA,
f = fmax = 1/tRC
100 MHz
83 MHz
66 MHz
40 MHz
120
100
63
50
ISB1
ISB2
Automatic CE Power-down Max VCC, CE > VIH
Current —TTL Inputs VIN > VIH or VIN < VIL, f = fmax
Automatic CE Power-down Max VCC, CE > VCC – 0.3V,
Current —CMOS Inputs IN > VCC – 0.3V,
or VIN < 0.3V, f = 0
3
15
mA
V
Note
4.
V (min) = –2.0V and V (max) = V + 1V for pulse durations of less than 5 ns.
IL IH CC
Document #: 38-05462 Rev. *E
Page 3 of 11
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CY7C1021D
Capacitance [5]
Parameter
CIN
Description
Input Capacitance
Output Capacitance
Test Conditions
Max
8
Unit
pF
TA = 25°C, f = 1 MHz, VCC = 5.0V
COUT
8
pF
Thermal Resistance [5]
Parameter
ΘJA
Description
Test Conditions
SOJ
TSOP II
Unit
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
59.52
53.91
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
36.75
21.24
°C/W
AC Test Loads and Waveforms [6]
ALL INPUT PULSES
3.0V
Z = 50Ω
90%
10%
90%
10%
OUTPUT
50Ω
GND
30 pF*
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
Fall Time: ≤ 3 ns
Rise Time: ≤ 3 ns
(b)
(a)
High-Z characteristics:
R1 480Ω
5V
OUTPUT
R2
255Ω
5 pF
INCLUDING
JIG AND
SCOPE
(c)
Notes
5. Tested initially and after any design or process changes that may affect these parameters.
6. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
Document #: 38-05462 Rev. *E
Page 4 of 11
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CY7C1021D
Switching Characteristics (Over the Operating Range) [7]
–10 (Industrial)
–12 (Automotive)
Parameter
Description
Unit
Min
Max
Min
Max
Read Cycle
[8]
tpower
VCC(typical) to the first access
Read Cycle Time
100
10
100
12
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z [9]
OE HIGH to High Z [9, 10]
CE LOW to Low Z [9]
CE HIGH to High Z [9, 10]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
10
12
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
3
3
10
5
12
6
0
3
0
0
3
0
5
5
6
6
tPD
10
5
12
6
tDBE
tLZBE
tHZBE
Write Cycle [12]
tWC
0
0
Byte Disable to High Z
5
6
Write Cycle Time
10
7
12
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
7
tHA
0
tSA
0
0
tPWE
tSD
7
10
7
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z [9]
6
tHD
0
0
tLZWE
tHZWE
tBW
3
3
WE LOW to High Z [9, 10]
5
6
Byte Enable to End of Write
7
10
Notes
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified
I
/I and 30-pF load capacitance.
OL OH
8.
t
gives the minimum amount of time that the power supply should be at typical V values until the first memory access can be performed.
CC
POWER
9. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
10. t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in (c) of “AC Test Loads and Waveforms [6]” on page 4. Transition is measured when
HZOE HZBE HZCE
HZWE
the outputs enter a high impedance state.
11. This parameter is guaranteed by design and is not tested.
12. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that
terminates the write.
Document #: 38-05462 Rev. *E
Page 5 of 11
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CY7C1021D
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
Description
VCC for Data Retention
Conditions
Min
Max Unit
2.0
V
ICCDR
Data Retention Current
VCC = VDR = 2.0 V, CE > VCC – 0.3 V, Industrial
3
mA
mA
ns
VIN > VCC – 0.3 V or VIN < 0.3 V
Automotive
15
[4]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
[13]
tR
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
DR > 2V
4.5V
4.5V
V
V
CC
t
t
R
CDR
CE
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled) [14, 15]
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled) [15, 16]
ADDRESS
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
BHE, BLE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
ISB
t
PU
VCC
SUPPLY
CURRENT
50%
50%
Notes
13. Full device operation requires linear V ramp from V to V
> 50 µs or stable at V > 50 µs.
CC(min)
CC
DR
CC(min)
14. Device is continuously selected. OE, CE, BHE and/or BLE = V .
IL
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05462 Rev. *E
Page 6 of 11
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CY7C1021D
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled) [17, 18]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATA IO
Write Cycle No. 2 (BLE or BHE Controlled)
t
WC
ADDRESS
t
t
BW
SA
BHE, BLE
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
SD
HD
DATA IO
Notes
17. Data IO is high impedance if OE or BHE and/or BLE = V
.
IH
18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05462 Rev. *E
Page 7 of 11
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CY7C1021D
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA IO
t
LZWE
Truth Table
CE OE WE BLE BHE
IO0–IO7
High Z
IO8–IO15
Mode
Power
H
L
X
L
X
H
X
L
X
L
High Z
Data Out
High Z
Data Out
Data In
High Z
Data In
High Z
High Z
Power-Down
Read – All bits
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
Data Out
Data Out
High Z
)
L
H
L
Read – Lower bits only
Read – Upper bits only
Write – All bits
)
H
L
)
L
X
L
L
Data In
Data In
High Z
)
L
H
L
Write – Lower bits only
Write – Upper bits only
)
H
X
H
)
L
L
H
X
H
X
X
H
High Z
Selected, Outputs Disabled
Selected, Outputs Disabled
)
High Z
)
Ordering Information
Speed
Package
Diagram
Operating
Range
Package Type
(ns)
Ordering Code
CY7C1021D-10VXI
10
51-85082
51-85087
51-85087
44-pin (400-Mil) Molded SOJ (Pb-free)
44-pin TSOP Type II (Pb-free)
44-pin TSOP Type II (Pb-free)
Industrial
CY7C1021D-10ZSXI
CY7C1021D-10ZSXE
12
Automotive
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05462 Rev. *E
Page 8 of 11
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CY7C1021D
Package Diagrams
Figure 1. 44-pin (400-Mil) Molded SOJ, 51-85082
51-85082-*B
Document #: 38-05462 Rev. *E
Page 9 of 11
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CY7C1021D
Package Diagrams (continued)
Figure 2. 44-Pin Thin Small Outline Package Type II, 51-85087
51-85087-*A
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05462 Rev. *E
Page 10 of 11
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1021D
Document History Page
Document Title: CY7C1021D, 1-Mbit (64K x 16) Static RAM
Document Number: 38-05462
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
**
201560
233695
See ECN
See ECN
SWI
Advance Information data sheet for C9 IPP
*A
RKF
DC parameters modified as per EROS (Spec # 01-02165)
Pb-free Offering in the Ordering Information
*B
263769
See ECN
RKF
Added Data Retention Characteristics Table
Added Tpower Spec in Switching Characteristics Table
Shaded Ordering Information
*C
*D
307601
520647
See ECN
See ECN
RKF
VKN
Reduced Speed bins to –10 and –12 ns
Converted from Preliminary to Final
Removed Commercial Operating range
Added ICC values for the frequencies 83MHz, 66MHz and 40MHz
Updated Thermal Resistance table
Added Automotive Product Information
Updated Ordering Information Table
Changed Overshoot spec from VCC+2V to VCC+1V in footnote #4
*E
802877
See ECN
VKN
Changed Commercial operating range ICC spec from 60 mA to 80 mA for
100MHz, 55 mA to 72 mA for 83MHz, 45 mA to 58 mA for 66MHz, 30 mA to
37 mA for 40MHz
Changed Automotive operating range ICC spec from 100 mA to 120 mA for
83MHz, 90 mA to 100 mA for 66MHz, 60 mA to 63 mA for 40MHz
Document #: 38-05462 Rev. *E
Page 11 of 11
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