CY7C1034DV33-8BGXC [CYPRESS]
6-Mbit (256K X 24) Static RAM; 6兆位（ 256K ×24 ）静态RAM
| 型号： | CY7C1034DV33-8BGXC |
| 厂家： | 
CYPRESS |
| 描述： | 6-Mbit (256K X 24) Static RAM |
| 文件： | 总8页 (文件大小：299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1034DV33
PRELIMINARY
6-Mbit (256K X 24) Static RAM
Features
Functional Description
• High speed
The CY7C1034DV33 is a high-performance CMOS static
RAM organized as 256K words by 24 bits. This device has an
automatic power-down feature that significantly reduces
power consumption when deselected.
— tAA = 8 ns
• Low active power
— ICC = 185 mA @ 8 ns
• Low CMOS standby power
— ISB2 = 25 mA
To write to the device, enable the chip (CE1 LOW, CE2 HIGH
and CE3 LOW) while forcing the Write Enable (WE) input
LOW.
To read from the device, enable the chip by taking CE1 LOW
CE2 HIGH and CE3 LOW while forcing the Output Enable (OE)
LOW and the Write Enable (WE) HIGH. See the truth table at
the back of this data sheet for a complete description of Read
and Write modes.
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
The 24 I/O pins (I/O0–I/O23) are placed in a high-impedance
state when the device is deselected (CE1 HIGH/CE2
LOW/CE3 HIGH) or when the output enable (OE) is HIGH
during a Write operation. (CE1 LOW, CE2 HIGH, CE3 LOW
and WE LOW).
• Easy memory expansion with CE1, CE2 and CE3
features
• Available in Pb-Free Standard 119-ball PBGA
Functional Block Diagram
INPUT BUFFER
A
0
A
1
A
2
I/O0–I/O23
A
3
4
256K x 24
ARRAY
A
A
5
6
A
A
7
A
8
A
9
CE1, CE2, CE3
COLUMN
DECODER
WE
CONTROL LOGIC
OE
Selection Guide
–8
8
Unit
ns
Maximum Access Time
Maximum Operating Current
185
25
mA
mA
Maximum CMOS Standby Current
Cypress Semiconductor Corporation
Document #: 001-08351 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 4, 2006
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PRELIMINARY
CY7C1034DV33
Pin Configurations[1]
119 PBGA
Top View
1
2
3
4
5
6
7
A
B
C
D
E
F
NC
A
A
A
A
A
NC
NC
A
A
CE1
A
A
A
NC
I/O12
I/O13
I/O14
I/O15
I/O16
I/O17
NC
NC
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
A
CE2
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
NC
A
CE3
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
NC
A
NC
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
A
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
WE
OE
G
H
J
K
L
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
NC
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
NC
M
N
P
R
T
U
NC
A
A
A
A
NC
Note:
1. NC pins are not connected on the die
Document #: 001-08351 Rev. *A
Page 2 of 8
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PRELIMINARY
CY7C1034DV33
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage ............ ...............................>2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Latch-up Current ..................................................... >200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VCC Relative to GND[2] .... –0.5V to +4.6V
Operating Range
Ambient
Temperature
Range
VCC
DC Voltage Applied to Outputs
in High-Z State[2]....................................–0.5V to VCC + 0.5V
DC Input Voltage[2] ................................–0.5V to VCC + 0.5V
Commercial
0°C to +70°C
3.3V ± 0.3V
DC Electrical Characteristics Over the Operating Range
–8
Min.
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions[7]
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
Max.
Unit
V
2.4
VOL
0.4
V
VIH
2.0
–0.3
–1
VCC + 0.3
0.8
V
V
[2]
VIL
Input LOW Voltage
IIX
Input Leakage Current
Output Leakage Current
VCC Operating Supply Current
GND < VI < VCC
+1
µA
µA
mA
IOZ
ICC
GND < VOUT < VCC, Output Disabled
–1
+1
VCC = Max., f = fMAX = 1/tRC
IOUT = 0 mA CMOS levels
,
185
ISB1
ISB2
Automatic CE Power-down
Current —TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or VIN < VIL, f = fMAX
30
25
mA
mA
Automatic CE Power-down
Current —CMOS Inputs
Max. VCC, CE > VCC – 0.3V,
VIN > VCC – 0.3V, or VIN < 0.3V, f = 0
Capacitance[3]
Parameter
Description
Input Capacitance
I/O Capacitance
Test Conditions
Max.
8
Unit
CIN
TA = 25°C, f = 1 MHz, VCC = 3.3V
pF
pF
COUT
10
Thermal Resistance[3]
Parameter
Description
Test Conditions
PBGA
TBD
Unit
°C/W
°C/W
ΘJA
ΘJC
Thermal Resistance (Junction to Ambient) Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
Thermal Resistance (Junction to Case)
TBD
AC Test Loads and Waveforms[4]
50Ω
R1 317Ω
= 1.5V
OUTPUT
3.3V
VTH
* Capacitive Load consists of all compo-
nents of the test environment.
OUTPUT
Z = 50Ω
30 pF*
0
R2
351Ω
5 pF
(a)
ALL INPUT PULSES
INCLUDING
JIG AND
SCOPE
3.0V
GND
90%
10%
90%
10%
(b)
Fall time: > 1 V/ns
Rise time > 1 V/ns
(c)
Notes:
2. V (min.) = –2.0V and V (max) = V + 2V for pulse durations of less than 20 ns.
IL
IH
CC
3. Tested initially and after any design or process changes that may affect these parameters.
4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V (3.0V). 100 µs (t
) after reaching the minimum
power
DD
operating V , normal SRAM operation can begin including reduction in V to the data retention (V , 2.0V) voltage.
CCDR
DD
DD
Document #: 001-08351 Rev. *A
Page 3 of 8
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PRELIMINARY
CY7C1034DV33
[5]
AC Switching Characteristics Over the Operating Range
–8
Parameter
Read Cycle
Description
Min.
Max.
Unit
[6]
tpower
tRC
VCC(typical) to the first access
100
8
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
tAA
Address to Data Valid
8
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data Hold from Address Change
CE active LOW to Data Valid[7]
OE LOW to Data Valid
OE LOW to Low-Z[8]
OE HIGH to High-Z[8]
CE active LOW to Low-Z[7, 8]
CE deselect HIGH to High-Z[7, 8]
CE active LOW to Power-up[7, 9]
CE deselect HIGH to Power-down[7, 9]
3
8
5
1
3
0
5
5
8
tPD
Write Cycle[10, 11]
tWC
tSCE
tAW
tHA
Write Cycle Time
8
6
6
0
0
6
5
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE active LOW to Write End[7]
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tSA
tPWE
tSD
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z[8]
tHD
tLZWE
tHZWE
WE LOW to High-Z[8]
5
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. Test conditions for the read cycle use
output loading as shown in part a) of the AC test loads, unless specified otherwise.
6. t
gives the minimum amount of time that the power supply should be at typical V values until the first memory access is performed.
CC
POWER
7. CE refers to a combination of CE , CE , and CE . CE is active LOW when CE is LOW and CE is HIGH and CE is LOW. CE is deselect HIGH when CE is
1
2
3
1
2
3
1
HIGH or CE is LOW or CE is HIGH
2
3
8. t
, t
, t
, and t
, t
, t
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from
HZOE HZCE HZWE
LZOE LZCE LZWE
steady-state voltage.
9. These parameters are guaranteed by design and are not tested.
10. The internal write time of the memory is defined by the overlap of CE LOW and CE HIGH and CE LOW and WE LOW. The chip enables must be active and
1
2
3
WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced
to the leading edge of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
and t
.
SD
HZWE
Document #: 001-08351 Rev. *A
Page 4 of 8
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PRELIMINARY
CY7C1034DV33
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
Description
VCC for Data Retention
Conditions
Min.
Typ.
Max.
Unit
V
2
ICCDR
Data Retention Current
VCC = 2V , CE1 > VCC – 0.2V,
CE2 < 0.2V, VIN > VCC – 0.2V or
VIN < 0.2V
25
mA
[3]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
ns
[12]
tR
tRC
Data Retention Waveform
DATA RETENTION MODE
3V
3V
V
DR
> 2V
VCC
CE
t
t
R
CDR
Switching Waveforms
Read Cycle No. 1[13, 14]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[7, 14, 15]
ADDRESS
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
t
PU
V
CC
50%
50%
SUPPLY
CURRENT
ISB
Notes:
12. Full device operation requires linear V ramp from V to V
> 50 µs or stable at V > 50 µs
CC(min.)
CC
DR
CC(min.)
13. Device is continuously selected. OE, CE = V
.
IL
14. WE is HIGH for read cycle.
15. Address valid prior to or coincident with CE transition LOW.
Document #: 001-08351 Rev. *A
Page 5 of 8
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PRELIMINARY
CY7C1034DV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[7, 16, 17]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[16, 17]
t
WC
ADDRESS
CE
t
SCE
t
t
AW
HA
t
t
PWE
SA
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 18
t
HZOE
Write Cycle No. 3 (WE Controlled, OE LOW)[7, 17]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 18
DATA I/O
DATA VALID
t
t
LZWE
HZWE
Notes:
16. Data I/O is high impedance if OE = V
.
IH
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
18. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 001-08351 Rev. *A
Page 6 of 8
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PRELIMINARY
CY7C1034DV33
Truth Table
CE1
H
X
CE2
X
CE3
X
OE
X
WE
X
I/O0–I/O23
Mode
Power
High-Z
Power-down
Standby (ISB
Standby (ISB
Standby (ISB
)
)
)
L
X
X
X
High-Z
Power-down
Power-down
Read
X
X
H
L
X
X
High-Z
L
H
L
H
Full Data Out
Full Data In
High-Z
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
H
L
X
L
Write
L
H
L
H
H
Selected, Outputs Disabled
Ordering Information
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
8
CY7C1034DV33-8BGXC 51-85115 119-ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-free) Commercial
Package Diagram
119-ball PBGA (14 x 22 x 2.4 mm) (51-85115)
51-85115-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-08351 Rev. *A
Page 7 of 8
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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PRELIMINARY
CY7C1034DV33
Document History Page
Document Title: CY7C1034DV33 6-Mbit (256K X 24) Static RAM
Document Number: 001-08351
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
469517
499604
See ECN
See ECN
NXR
NXR
New Data Sheet
*A
Added note# 1 for NC pins
Changed ICC spec from 150 mA to 185 mA
Updated Test Condition for ICC in DC Electrical Characteristics table
Added note for tACE, tLZCE, tHZCE, tPU, tPD, tSCE in AC Switching Characteristics
Table on page# 4
Document #: 001-08351 Rev. *A
Page 8 of 8
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