CY7C1041V33L-25VC [CYPRESS]
256K x 16 Static RAM; 256K ×16静态RAM
| 型号： | CY7C1041V33L-25VC |
| 厂家： | 
CYPRESS |
| 描述： | 256K x 16 Static RAM |
| 文件： | 总10页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
V33
CY7C1041V33
256K x 16 Static RAM
written into the location specified on the address pins (A
Features
0
through A ). If Byte High Enable (BHE) is LOW, then data
17
• High speed
from I/O pins (I/O through I/O ) is written into the location
8
15
specified on the address pins (A through A ).
0
17
— t = 15 ns
AA
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O to I/O . If Byte High Enable (BHE) is
• Low active power
— 612 mW (max.)
• Low CMOS standby power (Commercial L version)
— 1.8 mW (max.)
0
7
LOW, then data from memory will appear on I/O to I/O . See
8
15
• 2.0V Data Retention (600 W at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
µ
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O through I/O ) are placed in a
0
15
• Easy memory expansion with CE and OE features
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Functional Description
The CY7C1041V33 is a high-performance CMOS Static RAM
organized as 262,144 words by 16 bits.
The CY7C1041V33 is available in
a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O through I/O ), is
0
7
Logic Block Diagram
Pin Configuration
SOJ
TSOP II
Top View
INPUT BUFFER
A
44
1
0
A
A
A
A
OE
BHE
BLE
I/O
I/O
I/O
0
17
16
15
A
43
42
41
40
39
38
1
A
2
3
4
5
6
1
A
2
A
2
I/O0 – I/O7
I/O8 – I/O15
256K x 16
ARRAY
A
3
4
A
3
A
A
4
1024 x 4096
A
5
6
CE
A
I/O
7
0
15
A
7
8
37
36
35
34
33
I/O
I/O
8
1
2
14
13
12
A
9
10
11
12
13
I/O
V
SS
I/O
3
CC
V
SS
COLUMN
DECODER
V
V
CC
I/O
32
I/O
I/O
4
5
6
7
11
10
I/O
I/O
I/O
31
30
29
28
14
15
16
I/O
I/O
NC
9
8
WE 17
BHE
18
27
26
25
A
14
A
WE
CE
OE
5
19
A
6
A
13
A
20
21
22
A
7
12
A
BLE
A
24
23
11
8
9
A
A
10
1041V33–1
1041V33–2
Selection Guide
1041V33-12 1041V33-15 1041V33-17 1041V33-20 1041V33-25
Maximum Access Time (ns)
12
190
8
15
170
8
17
160
8
20
150
8
25
130
8
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA) Com’l/Ind’l
Com’l
L
0.5
0.5
0.5
0.5
0.5
Shaded areas contain preliminary information.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
June 2, 1999
CY7C1041V33
[1]
DC Input Voltage ................................ –0.5V to V + 0.5V
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
CC
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Ambient
[2]
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
V
CC
[1]
Supply Voltage on V to Relative GND .... –0.5V to +4.6V
CC
3.3V ± 0.3V
DC Voltage Applied to Outputs
[1]
in High Z State ....................................–0.5V to V + 0.5V
CC
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
7C1041-12V33
7C1041V33-15
Min.
Max.
Min.
Max.
Unit
V
V
V
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
V
= Min.,
CC
= –4.0 mA
2.4
2.4
V
V
V
OH
OL
IH
I
OH
V
= Min.,
0.4
0.4
CC
I
= 8.0 mA
OL
2.2
V
2.2
V
CC
CC
+ 0.5
0.8
+1
+ 0.5
0.8
+1
[1]
Input LOW Voltage
–0.5
–1
–0.5
–1
V
IL
I
I
I
Input Load Current
GND < V < V
CC
µA
µA
mA
IX
I
Output Leakage Current GND < V
< V , Output Disabled
–1
+1
–1
+1
OZ
CC
OUT
CC
V
Operating
V
= Max., f = f
= 1/t
RC
190
170
CC
CC
MAX
Supply Current
I
Automatic CE
Power-Down Current
—TTL Inputs
Max. V , CE > V
IH
40
40
mA
SB1
SB2
CC
V
V
> V or
IN
IN
IH
< V , f = f
IL
MAX
I
Automatic CE
Power-Down Current
—CMOS Inputs
Max. V
,
Com’l/Ind’l
Com’l
8
8
mA
mA
CC
CE > V – 0.3V,
CC
L
0.5
0.5
V
> V – 0.3V,
CC
IN
or V < 0.3V, f=0
IN
Shaded areas contain preliminary information.
Notes:
1.
VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “Instant On” case temperature.
2
CY7C1041V33
Electrical Characteristics Over the Operating Range (continued)
Test Conditions
1041V33-17 1041V33-20 1041V33-25
Min. Max. Min. Max. Min. Max. Unit
Parameter
Description
V
V
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
V
V
= Min., I = –4.0 mA
OH
2.4
2.4
2.4
V
V
V
OH
OL
IH
CC
CC
= Min., I = 8.0 mA
0.4
0.4
0.4
OL
2.2
V
+
2.2
V
+
2.2
V
+
CC
0.5
CC
0.5
CC
0.5
[1]
V
Input LOW Voltage
–0.5 0.8 –0.5
0.8
+1
+1
–0.5
–1
0.8
+1
+1
V
IL
I
I
Input Load Current
GND < V < V
CC
–1
–1
+1
+1
–1
–1
µA
µA
IX
I
Output Leakage
Current
GND < V
< V
,
–1
OZ
OUT
CC
Output Disabled
I
I
V
Operating
V
CC
= Max.,
160
40
150
40
130
40
mA
mA
CC
SB1
CC
Supply Current
f = f
= 1/t
MAX RC
Automatic CE
Max. V , CE > V
CC
IH
Power-Down Current
—TTL Inputs
V
V
> V or
IN
IN
IH
< V , f = f
IL
MAX
I
Automatic CE
Power-Down Current
—CMOS Inputs
Max. V
CE > V – 0.3V,
,
Com’l/Ind’l
Com’l
8
8
8
mA
mA
SB2
CC
CC
L
0.5
0.5
0.5
V
> V – 0.3V,
CC
IN
or V < 0.3V, f=0
IN
Capacitance[3]
Parameter
Description
Input Capacitance
I/O Capacitance
Test Conditions
Max.
Unit
C
C
T = 25°C, f = 1 MHz, V = 3.3V
8
8
pF
pF
IN
A
CC
OUT
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
ALL INPUT PULSES
90%
R1 317
Ω
THÉ
VENIN EQUIVALENT
3.3V
3.3V
GND
167
Ω
90%
10%
1.73V
OUTPUT
OUTPUT
10%
R2
351
(b)
30 pF
Ω
3 ns
3 ns
≤
≤
INCLUDING
JIG AND
SCOPE
(a)
1041V33–4
1041V33–3
3
CY7C1041V33
Switching Characteristics[4] Over the Operating Range
1041V33-12
1041V33-15
1041V33-17
Parameter
Description
Min. Max. Min. Max. Min. Max.
Unit
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
12
3
15
3
17
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
12
15
17
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
12
6
15
7
17
8
0
3
0
0
3
0
0
3
0
[5, 6]
OE HIGH to High Z
6
6
7
7
7
7
[6]
CE LOW to Low Z
[5, 6]
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
12
6
15
7
17
7
PD
DBE
LZBE
HZBE
0
0
0
Byte Disable to High Z
6
7
8
[7, 8]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
12
10
10
0
15
12
12
0
17
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
HA
0
0
0
SA
10
7
12
8
12
9
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
0
0
0
HD
[6]
WE HIGH to Low Z
3
3
3
LZWE
HZWE
BW
[5, 6]
WE LOW to High Z
6
7
8
Byte Enable to End of Write
10
12
12
Shaded areas contain preliminary information.
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5.
tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CELOW, and WE LOW. CE and WEmust be LOW to initiate a write, and the transition of either of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
4
CY7C1041V33
Switching Characteristics[4] Over the Operating Range (continued)
1041V33-20
1041V33-25
Parameter
Description
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
20
3
25
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
20
25
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
20
8
25
10
0
3
0
0
5
0
[5, 6]
OE HIGH to High Z
8
8
10
10
[6]
CE LOW to Low Z
[5, 6]
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
20
8
25
10
PD
DBE
LZBE
HZBE
0
0
Byte Disable to High Z
8
10
[7,8]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
20
13
13
0
25
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
HA
0
0
SA
13
9
15
10
0
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
0
HD
[6]
WE HIGH to Low Z
3
5
LZWE
HZWE
BW
[5, 6]
WE LOW to High Z
8
10
Byte Enable to End of Write
13
15
Data Retention Characteristics Over the Operating Range (For L version only)
[10]
Parameter
Description
Conditions
Min.
Max.
Unit
V
V
V
for Data Retention
CC
2.0
DR
I
Data Retention Current
V
= V = 2.0V,
330
µA
ns
CCDR
CC
DR
CE > V – 0.3V,
CC
[3]
t
Chip Deselect to Data
Retention Time
0
CDR
V
> V – 0.3V or V < 0.3V
IN
CC IN
[9]
R
t
Operation Recovery Time
t
ns
RC
Notes:
9. tr < 3 ns for the –12 and –15 speeds. tr < 5 ns for the –20 and slower speeds.
10. No input may exceed VCC + 0.5V.
5
CY7C1041V33
Data Retention Waveform
DATA RETENTION MODE
VDR > 2V
3.0V
3.0V
VCC
CE
t
t
R
CDR
1041V33–5
Switching Waveforms
[11, 12]
Read Cycle No. 1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
1041V33-6
[12, 13]
Read Cycle No. 2(OE Controlled)
ADDRESS
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
BHE, BLE
t
LZOE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
t
LZCE
t
PD
I
t
CC
PU
50%
50%
I
SB
1041V33-7
Notes:
11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
6
CY7C1041V33
Switching Waveforms (continued)
[14, 15]
Write Cycle No. 1 (CE Controlled)
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATAI/O
1041V33-8
Write Cycle No. 2 (BLEor BHE Controlled)
t
WC
ADDRESS
t
SA
t
BW
BHE, BLE
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
HD
SD
DATAI/O
1041V33-9
Notes:
14. Data I/O is high impedance if OE or BHE and/or BLE= VIH
.
15. If CEgoes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
7
CY7C1041V33
Switching Waveforms (continued)
Write Cycle No.3 (WE Controlled, LOW)
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
SD
t
HD
DATA I/O
t
LZWE
1041V33-10
Truth Table
CE
H
L
OE WE BLE
BHE
X
I/O –I/O
I/O –I/O
15
Mode
Power
0
7
8
X
L
X
H
H
H
L
X
L
High Z
High Z
Power Down
Read All Bits
Standby (I
)
SB
L
Data Out
Data Out
High Z
Data Out
High Z
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
)
)
)
)
)
)
)
CC
CC
CC
CC
CC
CC
CC
L
L
L
H
L
Read Lower Bits Only
Read Upper Bits Only
Write All Bits
L
L
H
L
Data Out
Data In
High Z
L
X
X
X
H
L
Data In
Data In
High Z
L
L
L
H
L
Write Lower Bits Only
Write Upper Bits Only
Selected, Outputs Disabled
L
L
H
X
Data In
High Z
L
H
X
High Z
8
CY7C1041V33
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Pin TSOP II Z44
12
CY7C1041V33 -12VC
CY7C1041V33L-12VC
CY7C1041V33 - 12ZC
CY7C1041V33L-12ZC
CY7C1041V33 -15VC
CY7C1041V33L-15VC
CY7C1041V33 - 15ZC
CY7C1041V33L-15ZC
CY7C1041V33 - 17VC
CY7C1041V33L-17VC
CY7C1041V33 - 17ZC
CY7C1041V33L-17ZC
CY7C1041V33 - 20VC
CY7C1041V33L-20VC
CY7C1041V33 - 20ZC
CY7C1041V33L-20ZC
CY7C1041V33 - 25VC
CY7C1041V33L-25VC
CY7C1041V33 - 25ZC
CY7C1041V33L-25ZC
V34
V34
Z44
Z44
V34
V34
Z44
Z44
V34
V34
Z44
Z44
V34
V34
Z44
Z44
V34
V34
Z44
Z44
Commercial
44-Pin TSOP II Z44
15
17
20
25
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Pin TSOP II Z44
44-Pin TSOP II Z44
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Pin TSOP II Z44
44-Pin TSOP II Z44
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Pin TSOP II Z44
44-Pin TSOP II Z44
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Pin TSOP II Z44
44-Pin TSOP II Z44
Document #: 38–00645–B
9
CY7C1041V33
Package Diagrams
44-Lead (400-Mil) Molded SOJ V34
51-85082-B
44-Pin TSOP II Z44
51-85087-A
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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