CY7C1046B [CYPRESS]
1M x 4 Static RAM; 1M ×4静态RAM
| 型号： | CY7C1046B |
| 厂家： | 
CYPRESS |
| 描述： | 1M x 4 Static RAM |
| 文件： | 总8页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
046B
CY7C1046B
1M x 4 Static RAM
sion is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and three-state drivers. Writing to
the device is accomplished by taking Chip Enable (CE) and
Write Enable (WE) inputs LOW. Data on the four I/O pins (I/O0
through I/O3) is then written into the location specified on the
address pins (A0 through A19).
Features
• High speed
— tAA = 12 ns
• Low active power
— 935 mW (max.)
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
• Low CMOS standby power (L version)
— 2.75 mW (max.)
• 2.0V Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
The four input/output pins (I/O0 through I/O3) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
Functional Description
The CY7C1046B is available in a standard 400-mil-wide
32-pin SOJ package with center power and ground (revolu-
tionary) pinout.
The CY7C1046B is a high-performance CMOS static RAM or-
ganized as 1,048,576 words by 4 bits. Easy memory expan-
Logic Block Diagram
Pin Configuration
SOJ
Top View
A0
A1
32
31
30
29
28
1
2
3
4
5
A19
A18
A17
A16
A15
A2
A3
A4
CE
I/O0
VCC
27
26
25
6
7
8
9
10
11
OE
I/O3
GND
VCC
I/O2
A14
A13
A12
A11
A10
NC
INPUT BUFFER
A
0
24
23
GND
I/O1
WE
A
1
A
2
22
21
20
19
18
17
I/O
0
A
A5
A6
A7
A8
A9
3
4
12
13
14
15
16
A
A
I/O
I/O
I/O
5
6
1
2
3
1M x 4
A
ARRAY
A
7
A
8
A
9
A
10
1046B–2
POWER
DOWN
COLUMN
DECODER
CE
WE
1046B–1
OE
Selection Guide
7C1046B-12
7C1046B-15
7C1046B-20
Maximum Access Time (ns)
12
170
8
15
150
8
20
130
8
Maximum Operating Current (mA)
Maximum CMOS Standby
Current (mA)
Com’l
L version
0.5
0.5
0.5
Shaded areas contain advance information.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05144 Rev. **
Revised September 6, 2001
CY7C1046B
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V
Range
Temperature[2]
VCC
DC Voltage Applied to Outputs
Commercial
0°C to +70°C
4.5V–5.5V
in High Z State[1]....................................–0.5V to VCC + 0.5V
DC Input Voltage[1] ................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
7C1046B-12 7C1046B-15 7C1046B-20
Min. Max. Min. Max. Min. Max. Unit
VOH
VOL
VIH
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
VCC = Min., IOH = –4.0 mA
2.4
2.2
2.4
2.4
V
V
V
VCC = Min., IOL = 8.0 mA
0.4
0.4
0.4
VCC
+ 0.3
2.2
VCC
+ 0.3
2.2
VCC
+ 0.3
VIL
IIX
Input LOW Voltage[1]
Input Load Current
–0.3
–1
0.8
+1
+1
–0.3
–1
0.8
+1
+1
–0.3
–1
0.8
+1
+1
V
GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VOUT < VCC
Output Disabled
,
–1
–1
–1
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
170
20
150
20
130
20
mA
mA
ISB1
Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC
,
Com’l
8
8
8
mA
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
L version
0.5
0.5
0.5
Shaded areas contain advance information.
Capacitance[3]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
pF
CIN
Input Capacitance
I/O Capacitance
6
6
COUT
pF
Note:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. A is the “Instant On” case temperature.
T
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05144 Rev. **
Page 2 of 8
CY7C1046B
AC Test Loads and Waveforms
ALL INPUT PULSES
90%
10%
Ω
R1 481Ω
R1 481
Vcc
5V
5V
OUTPUT
90%V
CC
10%V
OUTPUT
CC
GND
R2
R2
255 Ω
30 pF
5 pF
255 Ω
Rise Time:1 V/ns
Fall Time:1 V/ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
1046B–4
(b)
1046B–3
(a)
THÉ
Equivalent to:
VENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Switching Characteristics[4] Over the Operating Range
7C1046B-12
7C1046B-15
7C1046B-20
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tpower
tRC
VCC(typical) to the first access[5]
1
1
1
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
12
15
20
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[7]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[7]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
12
15
20
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
3
3
3
12
6
15
7
20
8
0
3
0
0
3
0
0
3
0
6
6
7
7
8
8
tPD
12
15
20
WRITE CYCLE[8, 9]
tWC
tSCE
tAW
tHA
Write Cycle Time
12
8
15
10
10
0
20
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
8
0
tSA
0
0
0
tPWE
tSD
8
10
8
12
10
0
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[7]
6
tHD
0
0
tLZWE
3
3
3
tHZWE
WE LOW to High Z[6, 7]
6
7
8
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. tpower time has to be provided initially before a read/write operation
is started.
6.
tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
Document #: 38-05144 Rev. **
Page 3 of 8
CY7C1046B
Data Retention Characteristics Over the Operating Range
Parameter
VDR
Description
VCC for Data Retention
Conditions[10]
Min.
Max Unit
2.0
V
ICCDR
Data Retention Current
Com’l
VCC = VDR = 2.0V,
CE > VCC – 0.3V
VIN > VCC – 0.3V or VIN < 0.3V
200
µA
ns
µs
[3]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
tR
200
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
V
DR
CC
t
t
R
CDR
CE
1046B–5
Switching Waveforms
Read Cycle No. 1[11, 12]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
1046B–6
Read Cycle No. 2 (OE Controlled)[12, 13]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
I
t
PU
CC
V
CC
50%
50%
SUPPLY
CURRENT
I
SB
1046B–7
Notes:
10. No input may exceed VCC + 0.5V.
11. Device is continuously selected. OE, CE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05144 Rev. **
Page 4 of 8
CY7C1046B
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[14, 15]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
1046B–8
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 16
t
HZOE
1046B–9
Notes:
14. Data I/O is high impedance if OE = VIH
.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
16. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05144 Rev. **
Page 5 of 8
CY7C1046B
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[15]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 16
DATA I/O
DATA VALID
t
t
LZWE
HZWE
1046B–10
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
12
15
20
12
15
20
Ordering Code
CY7C1046B-12VC
CY7C1046B-15VC
CY7C1046B-20VC
CY7C1046BL-12VC
CY7C1046BL-15VC
CY7C1046BL-20VC
Package Type
V33
V33
V33
V33
V33
V33
32-Lead (400-Mil) Molded SOJ
32-Lead (400-Mil) Molded SOJ
32-Lead (400-Mil) Molded SOJ
32-Lead (400-Mil) Molded SOJ
32-Lead (400-Mil) Molded SOJ
32-Lead (400-Mil) Molded SOJ
Commercial
Shaded areas contain advance information.
Document #: 38-05144 Rev. **
Page 6 of 8
CY7C1046B
Package Diagram
32-Lead (400-Mil) Molded SOJ V33
51-85033-A
Document #: 38-05144 Rev. **
Page 7 of 8
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1046B
Document Title: CY7C1046B 1M x 4 Static RAM
Document Number: 38-05144
Issue
ECN NO. Date
Orig. of
Change
REV.
Description of Change
**
109888
09/22/01
SZV
Change from Spec number: 38-00948 to 38-05144
Document #: 38-05144 Rev. **
Page 8 of 8
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