概述
规格参数
数据手册CY7C1046BN-15VC 概述
1M x 4 Static RAM 1M ×4静态RAM SRAM
CY7C1046BN-15VC 规格参数
| 生命周期： | Obsolete | 零件包装代码： | SOJ |
| 包装说明： | SOJ, | 针数： | 32 |
| Reach Compliance Code： | unknown | ECCN代码： | 3A991.B.2.A |
| HTS代码： | 8542.32.00.41 | 风险等级： | 5.62 |
| 最长访问时间： | 15 ns | JESD-30 代码： | R-PDSO-J32 |
| 长度： | 20.955 mm | 内存密度： | 4194304 bit |
| 内存集成电路类型： | STANDARD SRAM | 内存宽度： | 4 |
| 功能数量： | 1 | 端子数量： | 32 |
| 字数： | 1048576 words | 字数代码： | 1000000 |
| 工作模式： | ASYNCHRONOUS | 最高工作温度： | 70 °C |
| 最低工作温度： | 组织： | 1MX4 | |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | SOJ |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE |
| 并行/串行： | PARALLEL | 认证状态： | Not Qualified |
| 座面最大高度： | 3.7592 mm | 最大供电电压 (Vsup)： | 5.5 V |
| 最小供电电压 (Vsup)： | 4.5 V | 标称供电电压 (Vsup)： | 5 V |
| 表面贴装： | YES | 技术： | CMOS |
| 温度等级： | COMMERCIAL | 端子形式： | J BEND |
| 端子节距： | 1.27 mm | 端子位置： | DUAL |
| 宽度： | 10.16 mm | Base Number Matches： | 1 |
CY7C1046BN-15VC 数据手册
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PDF下载CY7C1046BN
1M x 4 Static RAM
You write to the device by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. Data on the four IO pins (IO0
Features
• Low active power
through IO3) is then written into the location specified on the
address pins (A0 through A19).
— 825 mW (max)
• Low CMOS standby power
You read from the device by taking Chip Enable (CE) and
Output Enable (OE) LOW while forcing Write Enable (WE)
HIGH. Under these conditions, the contents of the memory
location specified by the address pins appears on the IO pins.
— 44 mW (max)
• 2.0V data retention (400 μW at 2.0V retention)
• Automatic power down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in non Pb-free 400 mil wide 32-pin SOJ package
The four input and output pins (IO0 through IO3) are placed in
a high impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or when the write
operation is active (CE LOW, and WE LOW).
Functional Description
The CY7C1046BN is available in a standard 400-mil-wide
32-pin SOJ package with center power and ground (revolu-
tionary) pinout.
The CY7C1046BN is a high performance CMOS static RAM
organized as 1,048,576 words by 4 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers.
Logic Block Diagram
Pin Configuration
SOJ
TOP VIEW
A
A
32
31
30
29
1
2
3
4
5
6
A
0
1
19
A
A
A
A
18
17
16
15
A
2
A
A
3
4
INPUT BUFFER
A
1
0
28
27
A
CE
OE
A
2
IO
26
25
IO
GND
7
8
IO
0
3
0
A
3
V
CC
A
4
24
23
GND
IO
1
WE
9
10
11
V
A
CC
IO
IO
IO
5
1
2
3
1M x 4
IO
A
2
6
ARRAY
22
21
20
A
A
7
14
A
A
8
A
5
12
13
14
15
16
13
A
9
A
A
12
6
A
10
19
18
17
A
7
A
11
A
A
8
10
A
9
NC
POWER
DOWN
COLUMN
DECODER
CE
WE
1046B–1
1046B–2
OE
Selection Guide
7C1046BN-15
Maximum Access Time (ns)
15
150
8
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Cypress Semiconductor Corporation
Document #: 001-11924 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 30, 2006
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CY7C1046BN
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage............................................>2001V
(in accordance with MIL-STD-883, Method 3015)
Exceeding maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Latch-Up Current.....................................................>200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on VCC Relative to GND[1] .... –0.5V to +7.0V
Ambient
Range
VCC
Temperature[2]
DC Voltage Applied to Outputs
in High-Z State[1] ....................................–0.5V to VCC + 0.5V
Commercial
0°C to +70°C
4.5V–5.5V
DC Input Voltage[1].................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
7C1046BN-15
Min
Max
Unit
VOH
VOL
VIH
VIL
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
VCC = Min, IOH = –4.0 mA
VCC = Min, IOL = 8.0 mA
2.4
V
V
0.4
VCC + 0.3
0.8
2.2
–0.3
–1
V
Input LOW Voltage[1]
V
IIX
Input Load Current
GND < VI < VCC
+1
mA
mA
mA
mA
IOZ
ICC
ISB1
Output Leakage Current
VCC Operating Supply Current
GND < VOUT < VCC, Output Disabled
VCC = Max, f = fMAX = 1/tRC
–1
+1
150
Automatic CE Power Down
Current – TTL Inputs
Max VCC, CE > VIH, VIN > VIH or
VIN < VIL, f = fMAX
20
ISB2
Automatic CE Power Down
Current – CMOS Inputs
Max VCC, CE > VCC – 0.3V,
VIN > VCC – 0.3V, or VIN < 0.3V, f = 0
8
mA
Capacitance[3]
Parameter
Description
Input Capacitance
IO Capacitance
Test Conditions
Max
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
VCC = 5.0V
6
6
COUT
pF
Notes
1.
V (min) = –2.0V for pulse durations of less than 20 ns.
IL
2. T is the “Instant On” case temperature.
A
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-11924 Rev. **
Page 2 of 9
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CY7C1046BN
AC Test Loads and Waveforms
ALL INPUT PULSES
90%
10%
Ω
R1 481Ω
R1 481
Vcc
5V
5V
OUTPUT
90%VCC
10%VCC
OUTPUT
GND
R2
R2
255Ω
30 pF
5 pF
255 Ω
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
Rise Time:1 V/ns
Fall Time:1 V/ns
1046B–4
(b)
1046B–3
(a)
THÉ
VENIN EQUIVALENT
Equivalent to:
167Ω
1.73V
OUTPUT
Switching Characteristics (over the operating range)[4]
7C1046BN-15
Parameter
READ CYCLE
tpower
tRC
Description
Min
Max
Unit
VCC(typ) to the First Access[5]
1
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
15
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[7]
15
tOHA
3
tACE
15
7
tDOE
tLZOE
0
3
0
tHZOE
tLZCE
tHZCE
tPU
OE HIGH to High-Z[6, 7]
CE LOW to Low-Z[7]
7
7
CE HIGH to High-Z[6, 7]
CE LOW to Power Up
CE HIGH to Power Down
tPD
15
Notes
4. Test conditions are based on signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the
specified I /I and 30-pF load capacitance.
OL OH
5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. t
initially before a Read or Write operation can be initiated.
is the time that the power needs to be supplied above V (typ)
CC
POWER
6.
t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
HZOE HZCE
HZWE
7. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
Document #: 001-11924 Rev. **
Page 3 of 9
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CY7C1046BN
Switching Characteristics (over the operating range)[4] (continued)
7C1046BN-15
Parameter
Description
Min
Max
Unit
WRITE CYCLE[8, 9]
tWC
tSCE
tAW
Write Cycle Time
CE LOW to Write End
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
tHA
tSA
0
tPWE
tSD
10
8
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low-Z[7]
tHD
0
tLZWE
tHZWE
3
WE LOW to High-Z[6, 7]
7
Data Retention Characteristics (over the operating range)
Parameter
VDR
Description
VCC for Data Retention
Conditions[10]
Min
Max
Unit
2.0
V
ICCDR
Data Retention Current
Com’l
VCC = VDR = 2.0V,
CE > VCC – 0.3V
VIN > VCC – 0.3V or VIN < 0.3V
200
μA
ns
μs
[3]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
tR
200
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
VCC
CE
DR
t
t
R
CDR
1046B–5
Notes
8. The internal memory write time is defined by the overlap of CELOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals
can terminate the write. The input data setup and hold timing must be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle 3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
10. No input may exceed V + 0.5V.
CC
Document #: 001-11924 Rev. **
Page 4 of 9
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CY7C1046BN
Switching Waveforms
Read Cycle 1[11, 12]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
1046B–6
Read Cycle 2 (OE controlled)[12, 13]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
V
t
PU
CC
50%
50%
SUPPLY
CURRENT
ISB
1046B–7
Notes
11. Device is continuously selected. OE, CE = V .
IL
12. WE is HIGH for read cycle.
13. Address valid before or similar to CE transition LOW.
Document #: 001-11924 Rev. **
Page 5 of 9
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CY7C1046BN
Switching Waveforms (continued)
Write Cycle 1 (CE controlled)[14, 15]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA VALID
DATA IO
1046B–8
Write Cycle 2 (WE controlled, OE HIGH during write)[14, 15]
t
WC
ADDRESS
t
SCE
CE
t
t
HA
AW
t
t
PWE
SA
WE
OE
t
t
SD
HD
DATA VALID
DATA IO
IN
NOTE 16
t
HZOE
1046B–9
Notes
14. Data IO is high impedance if OE = V
.
IH
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
16. During this period the IOs are in the output state and input signals must not be applied.
Document #: 001-11924 Rev. **
Page 6 of 9
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CY7C1046BN
Switching Waveforms (continued)
Write Cycle 3 (WE controlled, OE LOW)[15]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 16
DATA VALID
DATA IO
t
t
LZWE
HZWE
1046B–10
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Package Type
Ordering Code
15
CY7C1046BN-15VC
51-85033
32-Pin (400-Mil) Molded SOJ
Commercial
Document #: 001-11924 Rev. **
Page 7 of 9
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CY7C1046BN
Package Diagram
Figure 1. 32-pin (400-Mil) Molded SOJ, 51-85033
51-85033-*B
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-11924 Rev. **
Page 8 of 9
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1046BN
Document History Page
Document Title: CY7C1046BN 1M x 4 Static RAM
Document Number: 001-11924
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
**
610496
See ECN NXR
New data sheet
Document #: 001-11924 Rev. **
Page 9 of 9
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CY7C1046BN-15VC 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| CY7C1046BN-15VCT | CYPRESS | Standard SRAM, 1MX4, 15ns, CMOS, PDSO32, 0.400 INCH, SOJ-32 | 获取价格 |
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| CY7C1046BV33-12VCT | CYPRESS | Standard SRAM, 1MX4, 12ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32 | 获取价格 |
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