CY7C1049GN [CYPRESS]
4-Mbit (512K words à 8 bit) Static RAM;
| 型号： | CY7C1049GN |
| 厂家： | 
CYPRESS |
| 描述： | 4-Mbit (512K words à 8 bit) Static RAM |
| 文件： | 总18页 (文件大小：554K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1049GN
4-Mbit (512K words × 8 bit) Static RAM
4-Mbit (512K words
× 8 bit) Static RAM
Features
Functional Description
■ High speed
❐ tAA = 10 ns
CY7C1049GN is a high-performance CMOS fast static RAM
device organized as 512K words by 8-bits.
Data writes are performed by asserting the Chip Enable (CE) and
Write Enable (WE) inputs LOW, while providing the data on I/O0
through I/O7 and address on A0 through A18 pins.
■ Low active and standby currents
❐ Active current: ICC = 38 mA typical
❐ Standby current: ISB2 = 6 mA typical
Data reads are performed by asserting the Chip Enable (CE) and
■ Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and
4.5 V to 5.5 V
Output Enable (OE) inputs LOW and providing the required
address on the address lines. Read data is accessible on the I/O
lines (I/O0 through I/O7).
■ 1.0-V data retention
All I/Os (I/O0 through I/O7) are placed in a high-impedance state
during the following events:
■ TTL-compatible inputs and outputs
■ Pb-free 36-pin SOJ and 44-pin TSOP II packages
■ The device is deselected (CE HIGH)
■ The control signal OE is de-asserted
The logic block diagram is on page 2.
Product Portfolio
Power Dissipation
Speed
Operating ICC, (mA)
(ns)
Product
Range
VCC Range (V)
Standby, ISB2 (mA)
f = fmax
10/15
Typ[1]
–
Max
40
Typ[1]
Max
CY7C1049GN18
1.65 V–2.2 V
2.2 V–3.6 V
4.5 V–5.5 V
15
10
10
CY7C1049GN30
CY7C1049GN
Industrial
38
45
6
8
38
45
Notes
1. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for a V range of 1.65 V–2.2 V),
CC
CC
V
= 3 V (for a V range of 2.2 V–3.6 V), and V = 5 V (for a V range of 4.5 V–5.5 V), T = 25 °C.
CC
CC CC CC A
Cypress Semiconductor Corporation
Document Number: 002-10613 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 12, 2016
CY7C1049GN
Logic Block Diagram – CY7C1049GN
INPUT BUFFER
A0
A1
A2
A3
I/O0‐I/O7
512K x 8
RAM ARRAY
A4
A5
A6
A7
A8
A9
COLUMN
DECODER
WE
OE
CE
Document Number: 002-10613 Rev. *A
Page 2 of 18
CY7C1049GN
Contents
Pin Configurations ...........................................................4
Maximum Ratings .............................................................6
Operating Range ...............................................................6
DC Electrical Characteristics ..........................................6
Capacitance ......................................................................7
Thermal Resistance ..........................................................7
AC Test Loads and Waveforms .......................................7
Data Retention Characteristics .......................................8
Data Retention Waveform ................................................8
AC Switching Characteristics .........................................9
Switching Waveforms ....................................................10
Truth Table ......................................................................13
Ordering Information ......................................................14
Ordering Code Definitions .........................................14
Package Diagrams ..........................................................15
Acronyms ........................................................................16
Document Conventions .................................................16
Units of Measure .......................................................16
Document History Page .................................................17
Sales, Solutions, and Legal Information ......................18
Worldwide Sales and Design Support .......................18
Products ....................................................................18
PSoC® Solutions ......................................................18
Cypress Developer Community .................................18
Technical Support .....................................................18
Document Number: 002-10613 Rev. *A
Page 3 of 18
CY7C1049GN
Pin Configurations
Figure 1. 36-pin SOJ pinout [2]
A0
A1
1
2
3
4
5
6
7
8
9
36 NC
A18
A17
A16
A15
35
34
33
32
A2
A3
A4
CE
I/O0
I/O1
VCC
31 OE
30 I/O7
29 I/O6
28 GND
27 VCC
26 I/O5
GND 10
I/O2 11
SOJ
I/O3
WE
A5
I/O4
A14
A13
A12
A11
A10
NC
12
13
14
15
16
17
18
25
24
23
22
21
20
19
A6
A7
A8
A9
Note
2. NC pins are not connected internally to the die.
Document Number: 002-10613 Rev. *A
Page 4 of 18
CY7C1049GN
Pin Configurations (continued)
Figure 2. 44-pin TSOP II pinout, Single Chip Enable [3]
NC
NC
A0
1
2
3
4
5
6
7
8
9
44 NC
NC
43
42
41
40
NC
A1
A18
A17
A2
A3
39 A16
38 A15
37 /OE
36 I/O7
35 I/O6
34 VSS
A4
/CE
I/O0
44-pin TSOP II
I/O1 10
VCC 11
VSS
I/O2
I/O3
/WE
VCC
I/O5
I/O4
A14
12
13
14
15
33
32
31
30
A5 16
29 A13
A6
A7
A8
A9
NC
NC
A12
A11
A10
NC
17
18
19
20
21
22
28
27
26
25
24
23
NC
NC
Notes
3. NC pins are not connected internally to the die.
Document Number: 002-10613 Rev. *A
Page 5 of 18
CY7C1049GN
DC input voltage [4].............................. –0.5 V to VCC + 0.5 V
Current into outputs (in LOW state) ............................ 20 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static discharge voltage
(MIL-STD-883, Method 3015) .................................> 2001 V
Storage temperature ................................ –65 C to +150 C
Latch-up current ....................................................> 140 mA
Ambient temperature
with power applied ................................... –55 C to +125 C
Operating Range
Supply voltage
Grade
Ambient Temperature
VCC
on VCC relative to GND [4] ..................... –0.5 to VCC + 0.5 V
Industrial
–40 C to +85 C
1.65 V to 2.2 V,
2.2 V to 3.6 V,
4.5 V to 5.5 V
DC voltage applied to outputs
in HI-Z State [4] ...................................–0.5 V to VCC + 0.5 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
10 ns / 15 ns
Parameter
Description
Test Conditions
Unit
Max
Min
Typ [5]
VOH
Output HIGH
voltage
1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA
2.2 V to 2.7 V VCC = Min, IOH = –1.0 mA
1.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
38
–
–
–
V
2
–
2.7 V to 3.6 V
4.5 V to 5.5 V
V
CC = Min, IOH = –4.0 mA
CC = Min, IOH = –4.0 mA
2.2
–
V
2.4
VCC – 0.5[6]
–
4.5 V to 5.5 V VCC = Min, IOH = –0.1mA
1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA
–
VOL
VIH
VIL
Output LOW
voltage
–
0.2
V
V
V
2.2 V to 2.7 V
2.7 V to 3.6 V VCC = Min, IOL = 8 mA
4.5 V to 5.5 V CC = Min, IOL = 8 mA
1.65 V to 2.2 V –
VCC = Min, IOL = 2 mA
–
0.4
–
–
0.4
V
0.4
VCC + 0.2[4]
VCC + 0.3[4]
VCC + 0.3[4]
Input HIGH
voltage
1.4
2
2.2 V to 2.7 V
2.7 V to 3.6 V
4.5 V to 5.5 V
–
–
–
2
2.2
–0.2[4]
–0.3[4]
–0.3[4]
–0.5[4]
–1
VCC + 0.5[4]
Input LOW
voltage
1.65 V to 2.2 V –
0.4
0.6
0.8
0.8
+1
+1
45
2.2 V to 2.7 V
2.7 V to 3.6 V
4.5 V to 5.5 V
–
–
–
IIX
Input leakage current
Output leakage current
Operating supply current
GND < VIN < VCC
A
A
IOZ
ICC
GND < VOUT < VCC, Output disabled
Max VCC, IOUT = 0 mA, f = 100 MHz
–1
–
mA
CMOS levels
f = 66.7 MHz
–
40
ISB1
ISB2
Automatic CE power-down
current – TTL inputs
Max VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fMAX
–
15
mA
mA
Automatic CE power-down
current – CMOS inputs
Max VCC, CE > VCC – 0.2 V,
–
6
8
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0
Notes
4. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 2 ns.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V – 2.2 V),
VCC = 3 V (for VCC range of 2.2V – 3.6 V), and VCC = 5 V (for VCC range of 4.5 V – 5.5 V), TA = 25 °C.
6. This parameter is guaranteed by design and not tested.
Document Number: 002-10613 Rev. *A
Page 6 of 18
CY7C1049GN
Capacitance
Parameter [7]
Description
Input capacitance
I/O capacitance
Test Conditions
TA = 25 C, f = 1 MHz,
VCC = VCC(typ)
36-pin SOJ 44-pin TSOP II Unit
CIN
10
10
10
10
pF
pF
COUT
Thermal Resistance
Parameter [7]
Description
Test Conditions
36-pin SOJ 44-pin TSOP II Unit
JA
Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
59.52
68.85
C/W
JC
Thermal resistance
(junction to case)
31.48
15.97
C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [8]
High-Z Characteristics:
R1
50
VCC
Output
VTH
Output
R2
Z = 50
30 pF*
0
5 pF*
* Including
jig and
scope
(a)
(b)
* Capacitive load consists
of all components of the
test environment
All Input Pulses
V
HIGH
90%
10%
90%
10%
GND
Fall Time:
> 1 V/ns
Rise Time:
> 1 V/ns
(c)
Parameters
R1
1.8 V
1667
1538
0.9
3.0 V
317
351
1.5
3
5.0 V
Unit
317
351
1.5
3
R2
VTH
V
VHIGH
1.8
V
Notes
7. Tested initially and after any design or process changes that may affect these parameters.
8. Full-device AC operation assumes a 100-µs ramp time from 0 to VCC(min) and a 100-µs wait time after VCC stabilization.
Document Number: 002-10613 Rev. *A
Page 7 of 18
CY7C1049GN
Data Retention Characteristics
Over the operating range of –40 C to 85 C
Parameter
VDR
ICCDR
Description
VCC for data retention
Data retention current
Conditions
Min
1
Max
–
Unit
V
VCC = 1.2 V, CE > VCC – 0.2 V[9]
IN > VCC – 0.2 V, or VIN < 0.2 V
,
–
8
mA
V
[10]
tCDR
Chip deselect to data retention
time
0
–
ns
[9, 10]
tR
Operation recovery time
VCC > 2.2 V
VCC < 2.2 V
10
15
–
–
ns
ns
Data Retention Waveform
Figure 4. Data Retention Waveform [9]
DATA RETENTION MODE
VDR = 1.0 V
VCC
VCC(min)
tCDR
VCC(min)
tR
CE
Notes
9. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC (min) > 100 s.
10. These parameters are guaranteed by design.
Document Number: 002-10613 Rev. *A
Page 8 of 18
CY7C1049GN
AC Switching Characteristics
Over the operating range of –40 C to 85 C
10 ns
15 ns
Unit
Parameter [11]
Description
Min
Max
Min
Max
Read Cycle
tRC
Read cycle time
10
–
3
–
–
0
–
3
–
0
–
–
10
–
15
–
3
–
–
0
–
3
–
0
–
–
15
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data
tOHA
Data / ERR hold from address change
CE LOW to data
tACE
10
4.5
–
15
8
tDOE
OE LOW to data
tLZOE
tHZOE
tLZCE
tHZCE
tPU
OE LOW to low impedance[12]
OE HIGH to HI-Z[12]
CE LOW to low impedance[12]
CE HIGH to HI-Z[12]
CE LOW to power-up[13, 14]
CE HIGH to power-down[13, 14]
–
5
8
–
–
5
8
–
–
tPD
10
15
Write Cycle [14, 15]
tWC Write cycle time
tSCE
tAW
10
7
7
0
0
7
5
0
3
–
–
–
–
–
–
–
–
–
–
5
15
12
12
0
–
–
–
–
–
–
–
–
–
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
tHA
tSA
0
tPWE
tSD
12
8
Data setup to write end
Data hold from write end
WE HIGH to low impedance[12]
WE LOW to HI-Z[12]
tHD
0
tLZWE
tHZWE
3
–
Notes
11. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V).Testconditionsforthereadcycleuseoutputloading, asshowninpart(a)ofFigure3onpage7, unlessspecifiedotherwise.
12. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 3 on page 7. Transition is measured 200 mV from steady state
voltage.
13. These parameters are guaranteed by design and are not tested.
14. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any
of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
15. The minimum write cycle pulse width in Write Cycle No. 2 (WE Controlled, OE LOW) should be equal to sum of tDS and tHZWE
.
Document Number: 002-10613 Rev. *A
Page 9 of 18
CY7C1049GN
Switching Waveforms
Figure 5. Read Cycle No. 1 (Address Transition Controlled) [16, 17]
tRC
ADDRESS
tAA
tOHA
PREVIOUS DATAOUT
VALID
DATA I/O
DATAOUT VALID
Figure 6. Read Cycle No. 2 (OE Controlled) [16, 17]
ADDRESS
tRC
CE
OE
tPD
tHZCE
tACE
tHZOE
tDOE
tLZOE
BHE/
BLE
tDBE
tLZBE
tHZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
tLZCE
tPU
DATA I/O
DATAOUT VALID
VCC
SUPPLY
CURRENT
ISB
Notes
16. WE is HIGH for the read cycle.
17. Address valid prior to or coincident with CE LOW transition.
Document Number: 002-10613 Rev. *A
Page 10 of 18
CY7C1049GN
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (CE Controlled) [18, 19]
tW
C
A D D R E S S
tS A
t S C
E
C E
tA
W
tH
A
t P W
E
W E
tB W
B H E/
B L E
O E
t H
tH
D
Z O
E
tS
D
D A T A I / O
D A T AIN V A L ID
Figure 8. Write Cycle No. 2 (WE Controlled, OE LOW) [18, 19, 20]
tW C
AD DRESS
tSCE
CE
tBW
BH E
BLE
/
tAW
tHA
tSA
tPW E
W E
tLZW E
t
tSD
HZW E
tHD
VALID
DATA I /O
DATA
IN
Notes
18. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any
of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
19. Data I/O is in HI-Z state if CE = VIH, or OE = VIH
.
20. The minimum write cycle pulse width should be equal to sum of tSD and tHZWE
.
Document Number: 002-10613 Rev. *A
Page 11 of 18
CY7C1049GN
Switching Waveforms (continued)
Figure 9. Write Cycle No. 3 (WE Controlled) [21, 22, 23]
tWC
ADDRESS
CE1
tSCE
CE2
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tHD
tSD
NOTE 24
DATA I/O
DATA IN VALID
tHZOE
Notes
21. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any
of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
22. Data I/O is in HI-Z state if CE = VIH, or OE = VIH
.
23. Data I/O is high impedance if OE = VIH
.
24. During this period the I/Os are in output state. Do not apply input signals.
Document Number: 002-10613 Rev. *A
Page 12 of 18
CY7C1049GN
Truth Table
CE
H
L
OE
X[25]
L
WE
X[25]
H
I/O0–I/O7
HI-Z
Mode
Power
Power down
Read all bits
Write all bits
Standby (ISB)
Data out
Data in
HI-Z
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
X
L
L
H
H
Selected, outputs disabled
Note
25. The input voltage levels on these pins should be either at VIH or VIL
.
Document Number: 002-10613 Rev. *A
Page 13 of 18
CY7C1049GN
Ordering Information
Speed
(ns)
Voltage
Range
Package
Diagram
Operating
Range
Ordering Code
Package Type (all Pb-free)
10
2.2 V–3.6 V CY7C1049GN30-10ZSXI
CY7C1049GN30-10VXI
51-85087 44-pin TSOP II
Industrial
51-85090 36-pin Molded SOJ
51-85090 36-pin Molded SOJ
4.5 V–5.5 V CY7C1049GN-10VXI
Ordering Code Definitions
CY 7 1 04 9 GN XX
-
XX
C
XX
I
X
Temperature Range: I = Industrial
Pb-free
Package Type: XX = V or ZS
V= 36-pin Molded SOJ; ZS = 44-pin TSOP II
Speed: XX = 10 ns
Voltage Range: XX = 30 or blank
30 = 2.2 V–3.6 V; no character = 4.5 V–5.5 V
Process Technology: GN = 65 nm
Data width: 9 = × 8-bits
Density: 04 = 4-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 002-10613 Rev. *A
Page 14 of 18
CY7C1049GN
Package Diagrams
Figure 10. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85087 *E
Figure 11. 36L SOJ V36.4 (Molded) Package Outline, 51-85090
51-85090 *G
Document Number: 002-10613 Rev. *A
Page 15 of 18
CY7C1049GN
Acronyms
Document Conventions
Units of Measure
Acronym
Description
BHE
BLE
byte high enable
Symbol
°C
Unit of Measure
byte low enable
chip enable
Degrees Celsius
megahertz
microamperes
microseconds
milliamperes
millimeter
nanoseconds
ohms
MHz
A
s
CE
CMOS
I/O
complementary metal oxide semiconductor
input/output
mA
mm
ns
OE
output enable
SRAM
TSOP
TTL
static random access memory
thin small outline package
transistor-transistor logic
very fine-pitch ball grid array
write enable
%
percent
VFBGA
WE
pF
V
picofarads
volts
W
watts
Document Number: 002-10613 Rev. *A
Page 16 of 18
CY7C1049GN
Document History Page
Document Title: CY7C1049GN, 4-Mbit (512K words × 8 bit) Static RAM
Document Number: 002-10613
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
5074703
5082587
NILE
NILE
01/06/2016 New data sheet.
*A
01/12/2016 Updated Logic Block Diagram – CY7C1049GN.
Updated Ordering Information:
Updated part numbers.
Document Number: 002-10613 Rev. *A
Page 17 of 18
CY7C1049GN
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2016. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 002-10613 Rev. *A
Revised January 12, 2016
Page 18 of 18
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