CY7C1061BV33-12ZIT [CYPRESS]
Standard SRAM, 1MX16, 12ns, CMOS, PDSO54, TSOP2-54;
| 型号： | CY7C1061BV33-12ZIT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 1MX16, 12ns, CMOS, PDSO54, TSOP2-54 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总9页 (文件大小：295K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1061BV33
16-Mbit (1M x 16) Static RAM
Low Enable (BLE) is LOW, then data from I/O pins (I/O0
through I/O7), is written into the location specified on the
address pins (A0 through A19). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O8 through I/O15) is written into
the location specified on the address pins (A0 through A19).
Features
• High speed
— tAA = 10 ns
• Low active power
Reading from the device is accomplished by enabling the chip
by taking CE LOW while forcing the Output Enable (OE) LOW
and the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is
LOW, then data from the memory location specified by the
address pins will appear on I/O0 to I/O7. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O8 to
I/O15. See the truth table at the back of this data sheet for a
complete description of Read and Write modes.
— 990 mW (max.)
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Available in Pb-free and non Pb-free 54-pin TSOP II
package
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW and WE LOW).
Functional Description
The CY7C1061BV33 is a high-performance CMOS Static
RAM organized as 1,048,576 words by 16 bits.
The CY7C1061BV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout.
Writing to the device is accomplished by enabling the chip (CE
LOW) while forcing the Write Enable (WE) input LOW. If Byte
Logic Block Diagram
Pin Configurations[1, 2]
54-pin TSOP II (Top View)
I/O
V
I/O
I/O
1
54
53
I/O
V
11
12
CC
INPUT BUFFER
2
3
4
5
6
SS
I/O
52
51
50
13
14
10
A
0
I/O
V
9
A
1
V
SS
A
CC
2
I/O
49 I/O
A
15
8
3
I/O –I/O
1M x 16
ARRAY
0
7
A
48
47
A
5
A
A
A
A
A
BHE
4
7
4
3
A
5
A
8
6
I/O –I/O
8
15
A
6
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A
7
9
2
A
7
A
10
11
12
8
A
9
1
0
A
8
A
9
NC
CE 13
OE
V
V
COLUMN
DECODER
CC
SS
14
15
16
17
18
19
20
21
22
DNU/V
BLE
WE
CC
SS
DNU/V
A
19
A
10
A
18
A
11
BHE
WE
A
A
A
A
13
17
16
15
12
A
A
14
CE
I/O
V
I/O
V
OE
BLE
0
7
23
24
25
26
27
CC
SS
I/O
I/O
6
5
1
2
I/O
I/O
V
V
CC
SS
I/O
28 I/O
3
4
Notes:
1. DNU/V Pin (#16) has to be left floating or connected to V and DNU/V Pin (#40) has to be left floating or connected to V to ensure proper application.
CC
CC
SS
SS
2. NC – No Connect Pins are not connected to the die
Cypress Semiconductor Corporation
Document #: 38-05693 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 3, 2006
CY7C1061BV33
Selection Guide
–10
10
–12
12
Unit
ns
Maximum Access Time
Maximum Operating Current
Commercial
275
275
50
260
260
50
mA
Industrial
Maximum CMOS Standby Current
Commercial/Industrial
mA
DC Input Voltage[3] ................................ –0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Operating Range
Storage Temperature .................................–65°C to +150°C
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
3.3V ± 0.3V
–40°C to +85°C
Supply Voltage on VCC to Relative GND[3]–0.5V to +4.6VDC
Voltage Applied to Outputs
in High-Z State[3] ....................................–0.5V to VCC + 0.5V
DC Electrical Characteristics Over the Operating Range
–10
–12
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[3]
Input Leakage Current
Test Conditions
Min.
Max.
Min.
Max.
Unit
V
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
2.4
2.4
0.4
0.4
VCC + 0.3
0.8
V
VIH
2.0
–0.3
–1
VCC + 0.3
0.8
2.0
–0.3
–1
V
VIL
V
IIX
GND < VI < VCC
+1
+1
µA
µA
mA
mA
mA
IOZ
Output Leakage Current GND < VOUT < VCC, Output Disabled
–1
+1
–1
+1
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
Commercial
Industrial
275
275
70
260
260
ISB1
Automatic CE
Max. VCC, CE > VIH
70
Power-down Current
—TTL Inputs
VIN > VIH or VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-down Current
—CMOS Inputs
Max. VCC
CE > VCC – 0.3V,
IN > VCC – 0.3V,
or VIN < 0.3V, f = 0
,
Commercial/
Industrial
50
50
mA
V
Capacitance[4]
Parameter
Description
Input Capacitance
I/O Capacitance
Test Conditions
Max.
Unit
CIN
TA = 25°C, f = 1 MHz, VCC = 3.3V
6
8
pF
pF
COUT
Thermal Resistance[4]
Parameter
Description
Test Conditions
54-pin TSOP-II
49.95
Unit
°C/W
°C/W
ΘJA
ΘJC
Thermal Resistance (Junction to Ambient) Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA/JESD51.
Thermal Resistance (Junction to Case)
3.34
Notes:
3. V (min.) = –2.0V and V (max) = V + 0.5V for pulse durations of less than 20 ns.
IL
IH
CC
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05693 Rev. *B
Page 2 of 9
CY7C1061BV33
AC Test Loads and Waveforms[5]
50Ω
R1 317
Ω
3.3V
= 1.5V
OUTPUT
VTH
OUTPUT
Z = 50Ω
30 pF*
0
* Capacitive Load consists of all com-
ponents of the test environment.
R2
351Ω
5 pF*
INCLUDING
JIG AND
SCOPE
(a)
(b)
ALL INPUT PULSES
3.3V
GND
90%
10%
90%
10%
Fall time: > 1V/ns
Rise time > 1V/ns
(c)
AC Switching Characteristics Over the Operating Range[6]
–10
–12
Parameter
Read Cycle
tpower
tRC
Description
Min.
Max.
Min.
Max.
Unit
VCC(typical) to the first access[7]
Read Cycle Time
1
1
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
12
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z[8]
CE LOW to Low-Z[8]
CE HIGH to High-Z[8]
CE LOW to Power-Up[9]
CE HIGH to Power-Down[9]
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
10
12
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
3
3
10
5
12
6
1
3
0
1
3
0
5
5
6
6
tPD
10
5
12
6
tDBE
tLZBE
1
1
tHZBE
5
6
Notes:
5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V (3.0V). As soon as 1ms (T
) after reaching the
power
DD
minimum operating V , normal SRAM operation can begin including reduction in V to the data retention (V , 2.0V) voltage.
DD
DD
CCDR
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I and specified transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.
OL OH
7. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. t
started.
time has to be provided initially before a Read/Write operation is
power
8. t
, t
,t
, t
andt
, t
, t
, t
arespecifiedwithaloadcapacitanceof5pFasin(b)ofACTestLoads. Transitionismeasured ±200mVfromsteady-state
HZOE HZCE HZWE HZBE
LZOE LZCE \LZWE LZBE
voltage.
9. These parameters are guaranteed by design and are not tested.
10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Chip enables must be active and WE and byte enables must be LOW to
initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge
of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document #: 38-05693 Rev. *B
Page 3 of 9
CY7C1061BV33
AC Switching Characteristics Over the Operating Range[6] (continued)
–10
–12
Parameter
Description
Min.
Max.
Min.
Max.
Unit
Write Cycle[10, 11]
tWC
tSCE
tAW
Write Cycle Time
10
7
12
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-up to Write End
Address Set-up to Write Start
WE Pulse Width
7
7
tSA
0
0
tPWE
tSD
7
8
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z[8]
5.5
0
6
tHD
0
tLZWE
tHZWE
tBW
3
3
WE LOW to High-Z[8]
5
6
Byte Enable to End of Write
Address Hold from Write End
7
0
8
0
tHA
Data Retention Waveform
DATA RETENTION MODE
3.0V
3.0V
V
DR
> 2V
V
CC
t
t
R
CDR
CE
Switching Waveforms
Read Cycle No. 1[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
12. Device is continuously selected. OE, CE, BHE and/or BHE = V .
IL
13. WE is HIGH for Read cycle.
Document #: 38-05693 Rev. *B
Page 4 of 9
CY7C1061BV33
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
BHE, BLE
t
LZOE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
t
LZCE
t
PD
I
CC
t
PU
50%
50%
ISB
Write Cycle No. 1 (CE Controlled)[15, 16]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATAI/O
Notes:
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high-impedance if OE or BHE and/or BLE = V
.
IH
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05693 Rev. *B
Page 5 of 9
CY7C1061BV33
Switching Waveforms (continued)
Write Cycle No. 2 (BLE or BHE Controlled)
t
WC
ADDRESS
t
SA
t
BW
BHE, BLE
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
HD
SD
DATAI/O
Write Cycle No. 3 (WE Controlled, OE LOW)[15, 16]
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA I/O
t
LZWE
Document #: 38-05693 Rev. *B
Page 6 of 9
CY7C1061BV33
Truth Table
CE
H
L
OE
X
L
WE
X
BLE
X
BHE
X
I/O0–I/O7
High-Z
I/O8–I/O15
High-Z
Mode
Power
Power-down
Read All Bits
Standby (ISB)
H
H
H
L
L
L
Data Out
Data Out
High-Z
Data Out
High-Z
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
)
)
L
L
L
H
L
Read Lower Bits Only
Read Upper Bits Only
Write All Bits
L
L
H
L
Data Out
Data In
High-Z
L
X
X
X
H
L
Data In
Data In
High-Z
L
L
L
H
L
Write Lower Bits Only
Write Upper Bits Only
Selected, Outputs Disabled
L
L
H
X
Data In
High-Z
L
H
X
High-Z
Ordering Information
Speed
Package
(ns)
Ordering Code
CY7C1061BV33-10ZC
Name
Package Type
Operating Range
Commercial
Industrial
10
51-85160
54-pin TSOP II
CY7C1061BV33-10ZI
CY7C1061BV33-10ZXC
CY7C1061BV33-10ZXI
CY7C1061BV33-12ZC
CY7C1061BV33-12ZI
CY7C1061BV33-12ZXC
CY7C1061BV33-12ZXI
54-pin TSOP II (Pb-free)
54-pin TSOP II
Commercial
Industrial
12
Commercial
Industrial
54-pin TSOP II (Pb-free)
Commercial
Industrial
Document #: 38-05693 Rev. *B
Page 7 of 9
CY7C1061BV33
Package Diagram
54-pin TSOP II (51-85160)
51-85160-**
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05693 Rev. *B
Page 8 of 9
CY7C1061BV33
Document History Page
Document Title: CY7C1061BV33 16-Mbit (1M x 16) Static RAM
Document Number: 38-05693
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
283950
309453
492137
See ECN
See ECN
See ECN
RKF
RKF
NXR
New data sheet
*A
Final data sheet
*B
Removed 8 ns speed bin
Changed the description of IIX from Input Load Current to Input Leakage
Current in DC Electrical Characteristics table
Updated the Ordering Information Table
Document #: 38-05693 Rev. *B
Page 9 of 9
相关型号：
CY7C1061DV33-10BAXI
Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, FBGA-48
CYPRESS
CY7C1061DV33-10BV1XI
Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CYPRESS
CY7C1061DV33-10BV1XIT
Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CYPRESS
CY7C1061DV33-10BVJXI
Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CYPRESS
CY7C1061DV33-10BVJXIT
Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CYPRESS
©2020 ICPDF网 联系我们和版权申明