CY7C1061DV33-10BV1XI [CYPRESS]
Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48;
| 型号： | CY7C1061DV33-10BV1XI |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48 静态存储器 内存集成电路 |
| 文件： | 总19页 (文件大小：1632K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1061DV33
16-Mbit (1M × 16) Static RAM
16-Mbit (1M
× 16) Static RAM
Features
Functional Description
■ High speed
❐ tAA = 10 ns
The CY7C1061DV33 is a high performance CMOS Static RAM
organized as 1,048,576 words by 16 bits.
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
■ Low active power
❐ ICC = 175 mA at 100 MHz
■ Low CMOS standby power
❐ ISB2 = 25 mA
A
19). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written into the location specified on the
address pins (A0 through A19).
■ Operating voltages of 3.3 ± 0.3 V
■ 2.0 V data retention
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See Truth Table on page 12
for a complete description of Read and Write modes.
■ Automatic power down when deselected
■ TTL compatible inputs and outputs
■ Easy memory expansion with CE1 and CE2 features
■ Available in Pb-free 54-pin TSOP II and 48-ball VFBGA
packages
The input or output pins (I/O0 through I/O15) are placed in a high
impedance state when the device is deselected (CE1 HIGH/CE2
LOW), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE1
LOW, CE2 HIGH, and WE LOW).
■ Offered in single CE and dual CE options
The CY7C1061DV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and 48-ball
VFBGA packages.
For a complete list of related documentation, click here.
Logic Block Diagram
INPUT BUFFER
A
0
A
1
A
2
A
4
3
I/O0 – I/O7
I/O8 – I/O15
1M x 16
ARRAY
A
A
5
A
6
A
7
A
8
A
9
COLUMN
DECODER
BHE
WE
CE2
CE1
OE
BLE
Cypress Semiconductor Corporation
Document Number: 38-05476 Rev. *K
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 22, 2016
CY7C1061DV33
Contents
Selection Guide ................................................................3
Pin Configurations ...........................................................3
Maximum Ratings .............................................................5
Operating Range ...............................................................5
DC Electrical Characteristics ..........................................5
Capacitance ......................................................................6
Thermal Resistance ..........................................................6
AC Test Loads and Waveforms .......................................6
Data Retention Characteristics .......................................7
Over the Operating Range ...............................................7
Data Retention Waveform ................................................7
AC Switching Characteristics .........................................8
Switching Waveforms ......................................................9
Truth Table ......................................................................12
Truth Table ......................................................................12
Ordering Information ......................................................13
Ordering Code Definitions .........................................13
Package Diagrams ..........................................................14
Acronyms ........................................................................16
Document Conventions .................................................16
Units of Measure .......................................................16
Document History Page .................................................17
Sales, Solutions, and Legal Information ......................19
Worldwide Sales and Design Support .......................19
Products ....................................................................19
PSoC®Solutions .......................................................19
Cypress Developer Community .................................19
Technical Support .....................................................19
Document Number: 38-05476 Rev. *K
Page 2 of 19
CY7C1061DV33
Selection Guide
Description
-10
10
Unit
ns
Maximum access time
Maximum operating current
Maximum CMOS standby current
175
25
mA
mA
Pin Configurations
Figure 1. 48-ball VFBGA (8 × 9.5 × 1 mm) Dual Chip Enable (-BVXI) pinout (Top View) [1, 2]
1
2
3
4
5
6
A0
A1
A2
CE2
A
B
C
OE
BLE
A4
A6
A3
A5
CE1
I/O8 BHE
I/O0
I/O10
I/O11
I/O1 I/O2
VCC
I/O9
VSS
VCC
A7 I/O3
D
E
F
A17
A16
A15
A13
A10
I/O4 VSS
I/O5 I/O6
I/O12 NC
A14
I/O14 I/O13
I/O15 NC
A12
A9
I/O7
A19
WE
A11
G
H
A8
A18
Figure 2. 48-ball VFBGA (8 × 9.5 × 1 mm) Dual Chip Enable (-BVJXI) pinout (Top View) [1, 2]
1
2
3
4
6
5
A0
A1
A2
CE2
A
B
C
OE
BLE
A4
A6
A3
A5
CE1
I/O8 BHE
I/O9 I/O10
I/O0
I/O1 I/O2
I/O11
VSS
VCC
A7 I/O3
D
E
F
A17
VCC
A16 I/O4 VSS
I/O12 NC
A14
A15
I/O5 I/O6
I/O14 I/O13
I/O15 A19
A12 A13
I/O7
NC
WE
G
H
A9 A10 A11
A8
A18
Notes
1. NC pins are not connected on the die.
2. In BVXI package, ball H6 is MSB address A19 and ball G2 is NC; in BVJXI package, ball H6 is NC and ball G2 is MSB address A19.
Document Number: 38-05476 Rev. *K
Page 3 of 19
CY7C1061DV33
Pin Configurations (continued)
Figure 3. 48-ball VFBGA (8 × 9.5 × 1 mm) Single Chip Enable (-BV1XI) pinout (Top View) [3, 4]
1
2
3
4
5
6
A
A
A
NC
A
B
C
OE
BLE
0
1
2
A
A
CE
I/O
I/O
I/O BHE
8
I/O
4
3
5
0
A
A
A
I/O I/O
I/O
2
6
7
9
10
1
I/O
V
V
V
D
E
F
A
11
CC
SS
3
17
V
SS
A
A
I/O
I/O
NC
CC
16
4
12
A
I/O
I/O
6
I/O
I/O
A
14
15
13
5
14
A
A
I/O
I/O
WE
G
H
12
13
10
15
19
7
A
9
A
A
A
NC
A
11
8
18
Figure 4. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) pinout (Top View) [3]
I/O
V
I/O
V
12
54
53
52
51
50
49
48
47
46
1
2
3
4
5
6
11
CC
SS
I/O
I/O
I/O
V
13
14
10
9
I/O
V
SS
CC
I/O
I/O
A
5
15
8
A
7
4
3
2
1
0
A
A
A
A
A
6
8
9
A
7
A
8
A
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
45
44
NC
BHE
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
OE
V
CE
V
1
CC
SS
WE
CE
A
A
A
A
A
NC
BLE
2
A
19
10
A
18
11
A
17
12
A
16
13
A
15
14
I/O
7
I/O
0
V
V
CC
SS
I/O
6
I/O
5
I/O
1
I/O
2
V
V
SS
CC
I/O
3
I/O
4
Notes
3. NC pins are not connected on the die.
4. In BV1XI package, ball A6 is NC, ball H6 is NC and ball G2 is MSB address A19. BV1XI package has only single Chip Enable (CE).
Document Number: 38-05476 Rev. *K
Page 4 of 19
CY7C1061DV33
DC Input Voltage [5] ............................ –0.5 V to VCC + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage
(MIL-STD-883, Method 3015) ..................................>2001V
Storage Temperature ............................... –65 C to +150 C
Latch Up Current ....................................................>200 mA
Ambient Temperature
with Power Applied .................................. –55 C to +125 C
Operating Range
Supply Voltage
on VCC relative to GND [5] ...........................–0.5 V to +4.6 V
Range
Ambient Temperature
VCC
DC Voltage Applied to Outputs
Industrial
–40 C to +85 C
3.3 V 0.3 V
in High Z State [5] ................................–0.5 V to VCC + 0.5 V
DC Electrical Characteristics
Over the Operating Range
-10
Parameter
VOH
Description
Test Conditions
Unit
Min
2.4
–
Max
–
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage [5]
Input leakage current
Output leakage current
VCC operating supply current
VCC = Min, IOH = –4.0 mA
V
V
VOL
VIH
VIL
IIX
VCC = Min, IOL = 8.0 mA
0.4
–
2.0
–0.3
–1
VCC + 0.3
0.8
V
–
V
GND < VI < VCC
+1
A
A
mA
IOZ
ICC
GND < VOUT < VCC, Output disabled
–1
+1
VCC = Max, f = fMAX = 1/tRC, OUT
I
= 0 mA,
–
175
CMOS levels
ISB1
ISB2
Automatic CE power down
current – TTL inputs
Max VCC, CE1 > VIH, CE2 < VIL,
–
–
30
25
mA
mA
V
IN > VIH or VIN < VIL, f = fMAX
Max VCC, CE1 > VCC – 0.3 V, CE2 < 0.3 V,
IN > VCC – 0.3 V, or VIN < 0.3 V, f = 0
Automatic CE power down
current – CMOS inputs
V
Note
5.
V
= –2.0 V and V
= V + 2 V for pulse durations of less than 20 ns.
IH(max) CC
IL(min)
Document Number: 38-05476 Rev. *K
Page 5 of 19
CY7C1061DV33
Capacitance
Parameter [6]
Description
Input capacitance
I/O capacitance
Test Conditions
54-pin TSOP II 48-ball VFBGA Unit
CIN
TA = 25 C, f = 1 MHz, VCC = 3.3 V
6
8
8
pF
pF
COUT
10
Thermal Resistance
Parameter [6]
Description
Test Conditions
54-pin TSOP II 48-ball VFBGA Unit
JA
Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
76.15
28.37
C/W
JC
Thermal resistance
(junction to case)
14.15
5.79
C/W
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms [7]
High-Z Characteristics:
R1 317
50
3.3 V
= 1.5 V
Output
VTH
Output
Z = 50
R2
351
30 pF*
0
5 pF*
Including
JIG and
Scope
(a)
(b)
* Capacitive Load Consists
of all Components of the
Test Environment
All Input Pulses
3.0 V
90%
10%
90%
10%
GND
Fall Time:
> 1 V/ns
Rise Time:
> 1 V/ns
(c)
Notes
6. Tested initially and after any design or process changes that may affect these parameters.
7. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V (3.0 V). 100 s (t
) after reaching the minimum operating
power
DD
V
, normal SRAM operation begins including reduction in V to the data retention (V
, 2.0 V) voltage.
DD
DD
CCDR
Document Number: 38-05476 Rev. *K
Page 6 of 19
CY7C1061DV33
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
ICCDR
Description
VCC for data retention
Data retention current
Conditions
Min
2
Max
–
Unit
V
–
VCC = 2 V, CE1 > VCC – 0.2 V, CE2 < 0.2 V,
IN > VCC – 0.2 V or VIN < 0.2 V
–
25
mA
V
[8]
tCDR
Chip deselect to data retention
time
–
0
–
–
ns
ns
[9]
tR
Operation recovery time
–
tRC
Data Retention Waveform
Figure 6. Data Retention Waveform [10]
Data Retention Mode
3.0 V
3.0 V
VCC
CE
VDR > 2 V
t
t
R
CDR
Notes
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full device operation requires linear V ramp from V to V > 50 s or stable at V > 50 s.
CC(min.)
CC
DR
CC(min.)
10. For all packages except -BV1XI, CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW,
1
2
1
2
1
2
CE is HIGH. For -BV1XI package, CE refers to CE.
Document Number: 38-05476 Rev. *K
Page 7 of 19
CY7C1061DV33
AC Switching Characteristics
Over the Operating Range
-10
Parameter [11]
Description
Unit
Min
Max
Read Cycle
tpower
tRC
VCC(typical) to the first access [12]
100
10
–
–
–
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read cycle time
tAA
Address to data valid
10
–
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data hold from address change
CE1 LOW/CE2 HIGH to data valid
OE LOW to data valid
OE LOW to low Z [13]
OE HIGH to high Z [13]
CE1 LOW/CE2 HIGH to low Z [13]
CE1 HIGH/CE2 LOW to high Z [13]
CE1 LOW/CE2 HIGH to power-up [14]
CE1 HIGH/CE2 LOW to power-down [14]
Byte enable to data valid
3
–
10
5
–
1
–
–
5
3
–
–
5
0
–
tPD
–
10
5
tDBE
tLZBE
tHZBE
–
Byte enable to low Z
1
–
Byte disable to high Z
–
5
Write Cycle [15, 16]
tWC
tSCE
tAW
Write cycle time
10
7
–
–
–
–
–
–
–
–
–
5
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE1 LOW/CE2 HIGH to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
7
tHA
0
tSA
0
tPWE
tSD
7
Data setup to write end
Data hold from write end
WE HIGH to low Z [13]
5.5
0
tHD
tLZWE
tHZWE
tBW
3
WE LOW to high Z [13]
–
Byte Enable to End of Write
7
Notes
11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use
output loading shown in part (a) of Figure 5 on page 6, unless specified otherwise.
12. t
13. t
gives the minimum amount of time that the power supply is at typical V values until the first memory access is performed.
CC
POWER
, t
, t
, t
, t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 6. Transition is measured 200 mV from steady
HZOE HZCE HZWE HZBE LZOE LZCE LZWE
LZBE
state voltage.
14. These parameters are guaranteed by design and are not tested.
15. The internal write time of the memory is defined by the overlap of WE, CE = V , and CE = V . Chip enables must be active and WE and byte enables must be
1
IL
2
IH
LOW to initiate a write, and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal
that terminates the write.
16. The minimum write cycle time for Write Cycle No. 2 (WE Controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document Number: 38-05476 Rev. *K
Page 8 of 19
CY7C1061DV33
Switching Waveforms
Figure 7. Read Cycle No. 1 (Address Transition Controlled) [17, 18]
tRC
Address
t
AA
t
OHA
Data Out
Previous Data Valid
Data Valid
Figure 8. Read Cycle No. 2 (OE Controlled) [18, 19, 20]
Address
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
BHE, BLE
t
LZOE
t
HZCE
t
DBE
t
LZBE
t
HZBE
High
Impedance
High Impedance
Data Out
VCC
Supply
Current
Data Valid
t
LZCE
t
PD
I
CC
t
PU
50%
50%
I
SB
Notes
17. The device is continuously selected. OE, CE = V , BHE, BLE or both = V .
IL
IL
18. WE is HIGH for read cycle.
19. For all packages except -BV1XI, CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW,
1
2
1
2
1
2
CE is HIGH. For -BV1XI package, CE refers to CE.
20. Address valid before or similar to CE transition LOW.
Document Number: 38-05476 Rev. *K
Page 9 of 19
CY7C1061DV33
Switching Waveforms (continued)
Figure 9. Write Cycle No. 1 (CE Controlled) [21, 22, 23]
t
WC
Address
CE
t
SA
t
SCE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
Data I/O
Figure 10. Write Cycle No. 2 (WE Controlled, OE LOW) [21, 22, 23, 24]
t
WC
Address
t
SCE
CE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
Data I/O
t
LZWE
Notes
21. For all packages except -BV1XI, CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW,
1
2
1
2
1
2
CE is HIGH. For -BV1XI package, CE refers to CE.
22. Data I/O is high impedance if OE, BHE, and/or BLE = V
.
IH
23. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
24. The minimum write cycle time is the sum of t
and t
.
HZWE
SD
Document Number: 38-05476 Rev. *K
Page 10 of 19
CY7C1061DV33
Switching Waveforms (continued)
Figure 11. Write Cycle No. 3 (BLE or BHE Controlled) [25]
t
WC
Address
t
t
BW
SA
BHE, BLE
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
SD
HD
Data I/O
Note
25. For all packages except -BV1XI, CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW,
1
2
1
2
1
2
CE is HIGH. For -BV1XI package, CE refers to CE.
Document Number: 38-05476 Rev. *K
Page 11 of 19
CY7C1061DV33
Truth Table
For all packages except -BV1XI
CE1 CE2 OE WE BLE BHE I/O0–I/O7 I/O8–I/O15
Mode
Power
H
X
L
L
L
L
L
L
L
X
L
X
X
L
X
X
H
H
H
L
X
X
L
X
X
L
High Z
High Z
Data out
Data out
High Z
Data in
Data in
High Z
High Z
High Z
High Z
Data out
High Z
Data out
Data in
High Z
Data in
High Z
Power down
Power down
Read all bits
Standby (ISB
)
)
Standby (ISB
H
H
H
H
H
H
H
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
)
)
L
L
H
L
Read lower bits only
Read upper bits only
Write all bits
L
H
L
X
X
X
H
L
L
L
H
L
Write lower bits only
Write upper bits only
Selected, outputs disabled
L
H
X
H
X
Truth Table
For -BV1XI package only
CE OE WE BLE BHE I/O0–I/O7 I/O8–I/O15
Mode
Power
Standby (ISB
H
L
L
L
L
L
L
L
X
L
X
H
H
H
L
X
L
X
L
High Z
Data out
Data out
High Z
Data in
Data in
High Z
High Z
High Z
Data out
High Z
Data out
Data in
High Z
Data in
High Z
Power down
)
Read all bits
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
)
)
L
L
H
L
Read lower bits only
Read upper bits only
Write all bits
L
H
L
X
X
X
H
L
L
L
H
L
Write lower bits only
Write upper bits only
Selected, outputs disabled
L
H
X
H
X
Document Number: 38-05476 Rev. *K
Page 12 of 19
CY7C1061DV33
Ordering Information
Speed
Package
Diagram
Operating
Range
Ordering Code
(ns)
Package Type
10
CY7C1061DV33-10BVJXI
51-85178 48-ball VFBGA (8 × 9.5 × 1 mm) (Pb-free) (Dual Chip Enable - Industrial
JEDEC compatible)
Ordering Code Definitions
CY 7 1 06 1 D V33 - 10 XXX X
C
I
Temperature Range:
I = Industrial
Pb-free
Package Type: XXX = BVJ
BVJ = 48-ball VFBGA (Dual Chip Enable - JEDEC compatible)
Speed: 10 ns
Voltage Range: V33 = 3 V to 3.6 V
D = C9, 90 nm Technology
Data Width: 1 = × 16-bits
Density: 06 = 16-Mbit density
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05476 Rev. *K
Page 13 of 19
CY7C1061DV33
Package Diagrams
Figure 12. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Z54-II Package Outline, 51-85160
51-85160 *E
Document Number: 38-05476 Rev. *K
Page 14 of 19
CY7C1061DV33
Package Diagrams (continued)
Figure 13. 48-ball VFBGA (8 × 9.5 × 1.0 mm) VCG048/BZ48B Package Outline, 51-85178
2X
0.10 C
B
E1
A1 CORNER
(datum B)
E
6
5
4
3
2
1
7
A1 CORNER
A
6
B
C
D
E
F
SD
D
D1
(datum A)
G
H
eD
2X
0.10 C
eE
6
A
TOP VIEW
SE
BOTTOM VIEW
0.25 C
DETAIL A
A1
0.10 C
C
A
48XØb
5
Ø0.05 M C A B
Ø0.25 M C
DETAIL A
SIDE VIEW
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
NOM.
SYMBOL
2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
MIN.
MAX.
1.00
0.26
A
A1
D
-
-
0.21
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
0.16
9.50 BSC
E
8.00 BSC
5.25 BSC
3.75 BSC
8
D1
E1
MD
ME
N
5.
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
6.
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
6
48
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" = 0.
0.30
b
0.25
0.35
eD
eE
SD
SE
0.75 BSC
0.75 BSC
0.38
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK
METALIZED MARK, INDENTATION OR OTHER MEANS.
7.
0.38
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
51-85178 *D
Document Number: 38-05476 Rev. *K
Page 15 of 19
CY7C1061DV33
Acronyms
Document Conventions
Units of Measure
Acronym
Description
BHE
BLE
Byte High Enable
Symbol
°C
Unit of Measure
Byte Low Enable
Chip Enable
degree Celsius
megahertz
microampere
microsecond
milliampere
millimeter
nanosecond
ohm
MHz
A
s
CE
CMOS
I/O
Complementary Metal Oxide Semiconductor
Input/Output
mA
mm
ns
OE
Output Enable
SRAM
TSOP
TTL
Static Random Access Memory
Thin Small Outline Package
Transistor-Transistor Logic
Very Fine-Pitch Ball Grid Array
Write Enable
%
percent
VFBGA
WE
pF
V
picofarad
volt
W
watt
Document Number: 38-05476 Rev. *K
Page 16 of 19
CY7C1061DV33
Document History Page
Document Title: CY7C1061DV33, 16-Mbit (1M × 16) Static RAM
Document Number: 38-05476
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
201560
233748
SWI
RKF
See ECN Advance data sheet for C9 IPP
*A
See ECN Updated AC and DC parameters as per EROS (Specification Number
01-02165).
Updated Ordering Information (Added Pb-free devices).
*B
469420
NXR
See ECN Changed status from Advance Information to Preliminary.
Updated Document Title (Corrected typo).
Removed 8 ns and 12 ns speed bins related information in all instances across
the document.
Removed Commercial Temperature Range related information in all instances
across the document.
Updated Selection Guide:
Changed value of “Maximum Operating Current” corresponding to 10 ns speed
bin from 176 mA to 125 mA.
Changed value of “Maximum CMOS Standby Current” corresponding to 10 ns
speed bin from 40 mA to 25 mA.
Updated Pin Configurations:
Changed ball 2G of FBGA and pin 40 of TSOP II from DNU to NC.
Updated Maximum Ratings:
Included details corresponding to “Static Discharge Voltage” and “Latch-Up
Current”.
Updated DC Electrical Characteristics:
Updated Note 5 (Specified the Overshoot specification).
Changed maximum value of ICC parameter corresponding to 10 ns speed bin
from 176 mA to 125 mA
Changed maximum value of ISB1 parameter corresponding to 10 ns speed bin
from 70 mA to 30 mA.
Changed maximum value of ISB2 parameter corresponding to 10 ns speed bin
from 40 mA to 25 mA.
Updated Ordering Information.
*C
*D
499604
NXR
See ECN Updated Pin Configurations:
Added Note 1 and referred the same note in Pin Configurations.
Updated DC Electrical Characteristics:
Updated details in “Test Condition” column corresponding to ICC parameter.
Updated Package Diagrams:
Updated figure corresponding to 48-ball FBGA Package (Removed spec
51-85150 *D and added spec 51-85178 **).
1462583
VKN /
AESA
See ECN Changed status from Preliminary to Final.
Updated Selection Guide:
Changed value of “Maximum Operating Current” from 125 mA to 175 mA
corresponding to 10 ns speed bin.
Updated DC Electrical Characteristics:
Changed maximum value of ICC parameter from 125 mA to 175 mA
corresponding to 10 ns speed bin.
Updated Thermal Resistance:
Replaced TBD with values for all packages.
*E
*F
2704415
3109102
VKN /
PYRS
05/11/09
Included 48-ball FBGA Dual Chip Enable - JEDEC compatible package related
information in all instances across the document.
Updated Pin Configurations:
Added Note 2 and referred the same note in Figure 1 and Figure 2.
AJU
12/13/2010 Added Ordering Code Definitions under Ordering Information.
Updated Package Diagrams.
Document Number: 38-05476 Rev. *K
Page 17 of 19
CY7C1061DV33
Document History Page (continued)
Document Title: CY7C1061DV33, 16-Mbit (1M × 16) Static RAM
Document Number: 38-05476
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*G
3126531
PRAS
01/03/2011 Added 48-ball VFBGA Single Chip Enable package related information in all
instances across the document.
Updated Ordering Information.
Added Acronyms.
*H
3414708
TAVA
10/19/2011 Updated Features.
Updated DC Electrical Characteristics.
Updated Switching Waveforms.
Updated Package Diagrams.
Added Units of Measure.
Updated to new template.
*I
4574311
4990813
TAVA
NILE
11/19/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagrams:
spec 51-85160 – Changed revision from *C to *E.
spec 51-85178 – Changed revision from *A to *C.
*J
10/27/2015 Updated Thermal Resistance:
Changed value of JA parameter corresponding to 54-pin TSOP II package
from 24.18 C/W to 76.15 C/W.
Changed value of JC parameter corresponding to 54-pin TSOP II package
from 5.40 C/W to 14.15 C/W.
Updated Switching Waveforms:
Added Note 24 and referred the same note in Figure 10.
Updated to new template.
Completing Sunset Review.
*K
5529600
VINI
11/22/2016 Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
spec 51-85178 – Changed revision from *C to *D.
Updated to new template.
Completing Sunset Review.
Document Number: 38-05476 Rev. *K
Page 18 of 19
CY7C1061DV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
ARM® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Forums | Projects | Video | Blogs | Training | Components
Technical Support
Internet of Things
Lighting & Power Control
Memory
cypress.com/support
cypress.com/powerpsoc
cypress.com/memory
cypress.com/psoc
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2004-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-05476 Rev. *K
Revised November 22, 2016
Page 19 of 19
相关型号：
CY7C1061DV33-10BV1XIT
Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CYPRESS
CY7C1061DV33-10BVJXI
Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CYPRESS
CY7C1061DV33-10BVJXIT
Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CYPRESS
©2020 ICPDF网 联系我们和版权申明