CY7C1301A-133AC [CYPRESS]
Dual-Port SRAM, 256KX36, 4ns, CMOS, PQFP176, 24 X 24 MM, 1.40 MM HEIGHT, TQFP-176;
| 型号： | CY7C1301A-133AC |
| 厂家： | 
CYPRESS |
| 描述： | Dual-Port SRAM, 256KX36, 4ns, CMOS, PQFP176, 24 X 24 MM, 1.40 MM HEIGHT, TQFP-176 时钟 静态存储器 内存集成电路 |
| 文件： | 总15页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
301A
PRELIMINARY
CY7C1301A
256K X 36 Dual I/O Dual Address Synchronous SRAM
The CY7C1301A allows the user to concurrently perform
reads, writes, or pass-through cycles in combination on the
Features
• Fast clock speed: 133, 100, and 83 MHz
• Fast Access Times: 4.0/5.0/6.0 ns Max.
• Single Clock Operation
two data ports. The two address ports (AX, AY) determine the
read or write locations for their respective data ports (DQX,
DQY).
All input pins except output enable pins (OEX, OEY) are gated
by registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, depth-expansion chip enables (CE1X, CE2X, CE1Y
and CE2Y), pass-through controls (PTX and PTY), and
read-write control (WEX and WEY).
• Single 3.3V –5% and +5% power supply VCC
• Separate VCCQ for output buffer
• Two chip enables for simple depth expansion
• Address, DataInput, CE1X, CE2X, CE1Y, CE2Y, PTX, PTY,
WEX, WEY, and Data Output Registers On-Chip
• Concurrent Reads and Writes
• Two bidirectional Data Buses
• Can be configured as separate I/O
• Pass-Through feature
• Asynchronous Output Enables (OEX, OEY)
• LVTTL-Compatible I/O
The pass-through feature allows data to be passed from one
port to the other, in either direction. The PTX# input must be
asserted to pass data from port X to port Y. The PTY# will
likewise pass data from port Y to port X. A pass-through oper-
ation takes precedence over a read operation.
For the case when AX and AY are the same, certain protocols
are followed. If both ports are read, the reads occur normally.
If one port is written and the other is read, the read from the
array will occur before the data is written. If both ports are
written, only the data on DQY will be written to the array.
• Self-Timed write
• Automatic power-down
• 176-Pin TQFP Package
The CY7C1301A operate from a +3.3V power supply. All in-
puts and outputs are LVTTL compatible. These dual I/O, dual
address synchronous SRAMs are well suited for ATM, Ether-
net switches, routers, cell/frame buffers, SNA switches and
shared memory applications.
Functional Description
The CY7C1301A SRAM integrates 262,144 x 36 SRAM cells
with advanced synchronous peripheral circuitry. It employs
high-speed, low power CMOS designs using advanced tri-
ple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high valued
resistors.
The CY7C1301A device needs one extra cycle after power for
proper power on reset. The extra cycle is needed after Vcc is
stable on the device.
This device is available in a 176-pin TQFP package.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05076 Rev. **
Revised June 6, 2001
PRELIMINARY
CY7C1301A
.
[1]
Logic Block Diagram
18/17
18/17
*AX
AY*
Address
Register
Address
Register
256K/128K x 9 x 4
SRAM Array
WEX#
PTX#
WEY#
PTY#
Write X
Register
Write
Driver
Sensing
Amplifiers
Sensing
Amplifiers
Write
Driver
Write Y
Register
PTX
Register
PTX
Register
Pass-Through
Data In
Register
Output
Register
Output
Register
Data In
Register
CLK
CLK
CE1X#
CE1Y#
CE2Y
DQX
DQY
Chip Enable
Register
Chip Enable
Register
Chip Enable
Register
Chip Enable
Register
CE2X
OEX#
OEY#
bus.
.
Selection Guide
-133
4.0
-100
5.0
-83
6.0
Maximum Access Time (ns)
Maximum Operating Current (mA)
400
100
350
100
300
100
Maximum CMOS Standby Current (mA)
Shaded areas contain advanced information.
Note:
1. For 256 x 36 device, AX and AY are 18-bit wide busses.
Document #: 38-05076 Rev. **
Page 2 of 15
PRELIMINARY
CY7C1301A
Pin Configuration
176-Pin TQFP
VSS
DQX20
DQY20
VCCQ
VSS
DQX21
DQY21
DQX22
DQY22
VCCQ
VSS
DQX23
DQY23
DQX24
DQY24
VCCQ
VSS
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
DQX15
DQY15
VSS
VCCQ
DQX14
DQY14
DQX13
DQY13
VSS
VCCQ
DQX12
DQY12
DQX11
DQY11
VSS
VCCQ
DQX10
DQY10
DQX9
DQY9
VSS
DQX25
DQY25 19
DQX26
DQY26
VCC
20
21
22
23
24
25
26
27
28
29
VSS
VCC
DQY27
DQX27
DQY28
DQX28
VCCQ
VSS
DQY8
DQX8
DQY7
DQX7
VSS
VCCQ
DQY6
DQX6
DQY5
DQX5
VSS
VCCQ
DQY4
DQX4
DQY3
DQX3
VSS
DQY29 30
DQX29
DQY30
DQX30
VCCQ
VSS
DQY31
DQX31
DQY32
DQX32
VCCQ
31
32
33
34
35
36
37
38
39
40
98
97
96
95
94
93
VSS 41
92
91
90
89
VCCQ
DQY2
DQX2
VSS
DQY33
42
43
44
DQX33
VSS
454647 4849505152535455 565758596061626364 656667686970717273 7475767778798081 82838485868788
Document #: 38-05076 Rev. **
Page 3 of 15
PRELIMINARY
CY7C1301A
Pin Definitions(176-pin TQFP)
Name
I/O
Description
AX0–AX17
Input-
Synchronous Address Inputs of Port X: Do not allow address pins to float.
Synchronous
AY0–AY17
WEX
WEY
PTX
Input-
Synchronous
Synchronous Address Inputs of Port Y: Do not allow address pins to float.
Input-
Synchronous
Read Write of Port X: WEX signal is a synchronous input that identifies whether the current
loaded cycle is a Read or Write operation.
Input-
Synchronous
Read Write of Port Y: WEY signal is a synchronous input that identifies whether the current
loaded cycle is a Read or Write operation.
Input-
Synchronous
Pass-Through of Port X: PTX signal is a synchronous input that enables passing Port X input
to Port Y output.
PTY
Input-
Synchronous
Pass-Through of Port Y: PTY signal is a synchronous input that enables passing Port Y input
to Port X output.
OEX
Input
Input
Asynchronous Output Enable of Port X: OEX must be LOW to read data. When OEX is HIGH,
the DQXx pins are in high-impedance state.
OEY
Asynchronous Output Enable of Port Y: OEY must be LOW to read data. When OEY is HIGH,
the DQYx pins are in high-impedance state.
DQX0 -
DQX35
Input/
Output
Data Inputs/Outputs of Port X: Both the data input path and data output path are registered
and triggered by the rising edge of CLK.
DQY0 -
DQY35
Input/
Output
Data Inputs/Outputs of Port Y: Both the data input path and data output path are registered
and triggered by the rising edge of CLK.
CLK
Input-
Synchronous
Clock: This is the clock input to this device. Except for OEX and OEY, all timing references of
the address, data in, and all control signals for the device are made with respect to the rising
edge of CLK.
CE1X
CE2X
CE1Y
CE2Y
Input-
Synchronous
Synchronous Active LOW Chip Enable Port X: CE1X is used with CE2X to enable Port X of
this device. CE1X sampled HIGH at the rising edge of clock initiates a deselect cycle for
Port X.
input-
Synchronous
Synchronous Active HIGH Chip Enable Port X: CE2X is used with CE1X to enable Port X of
this device. CE2X sampled LOW at the rising edge of clock initiates a deselect cycle for
Port X.
Input-
Synchronous
Synchronous Active LOW Chip Enable Port Y: CE1Y is used with CE2Y to enable Port Y of
this device. CE1Y sampled HIGH at the rising edge of clock initiates a deselect cycle for
Port Y.
input-
Synchronous
Synchronous Active HIGH Chip Enable Port Y: CE2Y is used with CE1Y to enable Port Y of
this device. CE2Y sampled LOW at the rising edge of clock initiates a deselect cycle for
Port Y.
VCC
VSS
VSS
Supply
Ground
Ground
Power Supply: +3.3V –5% and +5%.
Ground: GND.
Ground: GND. No chip current flows through these pins. However, user needs to connect
GND to these pins. Pins 140 and 141 are VSS for 128K x 36 device.
VCCQ
NC
I/O Supply
-
Output Buffer Supply: +3.3V –5% and +5%.
No Connect: These signals are not internally connected. User can connect them to VCC, VSS
or any signal lines or simply leave them floating.
,
Document #: 38-05076 Rev. **
Page 4 of 15
PRELIMINARY
CY7C1301A
Cycle Description Truth Table[2, 3, 4, 5, 6, 7, 8, 9]
Operation
DESELECT CYCLE
DESELECT CYCLE
WRITE PORT X
CE1X
CE2X
CE1Y
CE2Y
WEX
WEY
PTX
X
PTY
X
H
X
L
X
L
H
X
X
L
X
L
X
X
0
X
X
X
0
X
X
H
X
H
X
H
H
X
X
WRITE PORT Y
X
L
X
X
X
X
PASS-THROUGH from
X to Y
L
X
0
X
PASS-THROUGH from
Y to X
L
H
L
H
X
X
X
0
READ PORT X
READ PORT Y
L
H
X
X
L
X
H
1
X
1
1
1
1
1
X
X
DC Input Voltage[10]................................−0.5V to VCCQ + 0.5V
Maximum Ratings
Current into Outputs (LOW) ........................................ 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................... −55°C to +125°C
Latch-Up Current................................................... >200 mA.
Ambient Temperature with
Power Applied.................................................... −10°C to +85°C
Operating Range
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V
Ambient
Range
Com’l
Temperature[11]
VDD/VDDQ
DC Voltage Applied to Outputs
in High Z State[10]....................................−0.5V to VCCQ + 0.5V
0°C to +70°C
3.3V ± 5%
Notes:
2. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
3. All inputs except OEX and OEY must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
4. OEX and OEY must be asserted to avoid bus contention during Write and Pass-Through cycles. For a Write and Pass-Through operation following a READ
operation, OEX/OEY must be HIGH before the input data required setup time plus High-Z time for OEX/OEY and staying HIGH throughout the input data hold time.
5. Operation number 3 – 6 can be used in any combination.
6. Operation number 4 and 7, 3 and 8, 7 and 8 can be combined.
7. Operation number 5 can not be combined with operation number 7 or 8 because Pass-Through operation has higher priority over a READ operation.
8. Operation number 6 can not be combined with operation number 7 or 8 because Pass-Through operation has higher priority over a READ operation.
9. This device contains circuitry that will ensure the outputs will be in High-Z during power-up
10. Minimum voltage equals –2.0V for pulse duration less than 20 ns.
11. TA is the case temperature.
Document #: 38-05076 Rev. **
Page 5 of 15
PRELIMINARY
CY7C1301A
Electrical Characteristics Over the Operating Range
Parameter
VDD
Description
Test Conditions
Min.
3.135
3.135
2.4
Max.
3.465
3.465
Unit
V
Power Supply Voltage
I/O Supply Voltage
VDDQ
VOH
V
Output HIGH Voltage VDD = Min., IOH = –4.0 mA
V
VOL
Output LOW Voltage VDD = Min., IOL = 8.0 mA
0.4
V
VIH
Input HIGH Volt-
age[12]
2.0
VCC + 0.5V
V
VIL
IX
Input LOW Voltage[13]
−0.5
−5
0.8
5
V
Input Load Current
GND ≤ VIN ≤ VDDQ
µA
µA
IOZ
Output Leakage
Current
GND ≤ VIN ≤ VDDQ, Output Disabled
−5
5
ICC
VDD Operating
Supply
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
7.0-ns cycle, 133 MHz
7.5-ns cycle, 100 MHz
10.0-ns cycle, 83MHz
All speed grades
400
350
300
100
mA
mA
mA
mA
ISB
Automatic CE
Power-Down
Current—CMOS
Inputs
Max. VDD, DeviceDeselected[14]
IN ≤ 0.3V or VIN > VDDQ – 0.3V,
f = 0
,
V
Note:
12. Overshoot: VIH ≤ +6.0V for t ≤ tKC /2
13. Undershoot:VIL ≤ –2.0V for t ≤ tKC /2
.
14. “Device Deselected” means the device is in Power -Down mode as defined in the truth table.
Document #: 38-05076 Rev. **
Page 6 of 15
PRELIMINARY
CY7C1301A
Capacitance[15]
Parameter
Description
Test Conditions
Max.
Unit
pF
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
VCC = 3.3V,
VCCQ = 3.3V
6
6
8
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
pF
pF
AC Test Loads and Waveforms[16]
R=317Ω
3.3V
OUTPUT
OUTPUT
[16]
ALL INPUT PULSES
Z =50Ω
0
3.0V
R =50Ω
L
5 pF
R=351Ω
GND
V = 1.5V
1V/ns
L
1V/ns
INCLUDING
JIG AND
SCOPE
1350B-2
(a)
(b)
Thermal Resistance
Description
Test Conditions
Symbol
TQFP Typ.
Units
Notes
Thermal Resistance
(Junction to Ambient)
(@200lfm) Single-layer printed circuit board
ΘJA
40
°C/W
15
Thermal Resistance
(Junction to Ambient)
(@200lfm) Four-layer printed circuit board
ΘJC
ΘJA
ΘJC
35
23
9
°C/W
°C/W
°C/W
15
15
15
Thermal Resistance
(Junction to Board)
Bottom
Top
Thermal Resistance
(Junction to Case)
Notes:
15. Tested initially and after any design or process change that may affect these parameters.
16. AC test conditions assume signal transition time of 1 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading shown in
part (a) of AC Test Loads.
Document #: 38-05076 Rev. **
Page 7 of 15
PRELIMINARY
CY7C1301A
Switching Characteristics Over the Operating Range[16, 17, 18]
-133
Max.
-100
Max.
-80
Parameter
Clock
Description
Min.
Min.
Min.
Max.
Unit
tKC
tKH
Clock cycle time
7.5
3.0
3.0
10
3.5
3.5
12
4.0
4.0
ns
ns
ns
Clock HIGH time
Clock LOW time
tKL
Output times
tKQ
Clock to output valid
4.0
5.0
6.0
ns
ns
ns
ns
ns
ns
ns
tKQX
Clock to output invalid
1.5
0
1.5
0
1.5
0
tKQLZ
Clock to output in Low-Z[19]
Clock to output in High-Z[19]
OEX#/OEY# to output valid
OEX#/OEY# to output in Low-Z[19]
OEX#/OEY# to output in High-Z[19]
tKQHZ
tOEQ
3.0
4.0
3.0
5.0
3.0
6.0
tOELZ
0
0
0
tOEHZ
Setup times
tS
3.0
3.0
3.0
Addresses, Controls and Data In
Addresses, Controls and Data In
1.5
0.5
1.5
0.5
2.0
0.5
ns
ns
Hold times
tH
Shaded areas contain advance information.
Notes:
17. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with A/C test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
18. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
19. This parameter is sampled and not 100% tested.
20. CE LOW means (CE1X and CE1Y) equals LOW and (CE2X and CE2Y) equals HIGH. CE HIGH means (CE1X and CE1Y) equals HIGH or (CE2X and CE2Y)
equals LOW.
Document #: 38-05076 Rev. **
Page 8 of 15
PRELIMINARY
CY7C1301A
Switching Waveforms [20]
READ CYCLE TIMING FROM BOTH PORTS (WEX, WEY, PTX, PTY HIGH)[19]
t
KC
t
KL
CLK
t
t
S
KH
AX
1
2
3
4
5
6
7
8
Q(6)
19
9
t
t
OEQ
H
PORT X
OEX#
t
KQ
t
OEHZ
Q(1)
14
Q(2)
Q(3)
16
Q(5)
Q(7)
DQX
CE#
t
OELZ
t
S
(See Note)
t
H
AY
12
13
15
6
7
20
t
PORT Y
OEY#
DQY
KQLZ
t
KQHZ
Q(12)
Q(13)
Q(14)
Q(16)
Q(6)
Q(7)
t
KQ
Document #: 38-05076 Rev. **
Page 9 of 15
PRELIMINARY
CY7C1301A
Switching Waveforms (continued)[20]
WRITE CYCLE TIMING TO BOTH PORTS (PTX, PTY HIGH)[19]
t
KC
t
KL
CLK
t
KH
AX
WEX#
OEX#
1
2
3
4
5
6
7
8
9
t
H
t
S
PORT X
t
H
t
S
D(2)
D(3)
D(4)
D(8)
D(9)
DQX
CE#
t
S
(See Note)
t
H
AY
12
13
14
15
5
6
18
19
20
WEY#
PORT Y
OEY#
DQY
D(14)
D(15)
D(5)
D(6)
D(18)
D(19)
PORT Y TAKES
PRIORITY OVER PORT X
WHEN AX=AY AND
WRITING TO BOTH
Document #: 38-05076 Rev. **
Page 10 of 15
PRELIMINARY
CY7C1301A
Switching Waveforms (continued)[20]
WRITE TO PORT X AND PASS-THROUGH TO PORT Y[19]
t
KC
t
KL
CLK
t
KH
AX
WEX#
OEX#
PTY#
1
2
3
4
5
6
7
8
9
PORT X
t
H
t
t
S
H
t
S
D(2)
D(3)
D(X)
D(Y)
D(6)
DQX
CE#
(See Note)
AY
12
13
14
15
16
17
18
19
20
WEY#
PORT Y
OEY#
PTY#
DQY
t
KQ
t
KQHZ
Q(3)
D(X)
D(Y)
Q(17)
t
KQX
Document #: 38-05076 Rev. **
Page 11 of 15
PRELIMINARY
CY7C1301A
Switching Waveforms (continued)[20]
COMBINATION READ/WRITE WITH SAME ADDRESS ON EACH PORT
t
KC
t
t
KL
KH
CLK
AX
TRY TO
WRITE
TRY TO
WRITE
READ
READ
READ
READ
READ
READ
1
2
1
2
3
t
H
WEX#
OEX#
DQX
t
S
PORT X
D(ABC) D(DEF)
Q(PQR)
Q(XYZ) Q(JKL)
READ
READ
READ
READ
READ
READ
WRITE
WRITE
AY
WEY#
OEY#
DQY
1
2
1
2
3
PORT Y
D(PQR) D(XYZ)
Q(PQR) D(JKL)
Q(JKL)
PORT Y TAKES
PRIORITY OVER PORT X
WHEN AX=AY AND
WRITING TO BOTH
PORTS.
PTX# = PTY# = HIGH
D(Value) = Value is the input of the data port.
Q(Value) = Value is the output of the data port.
Document #: 38-05076 Rev. **
Page 12 of 15
PRELIMINARY
CY7C1301A
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
133
100
83
Ordering Code
Package Type
CY7C1301A-133AC
CY7C1301A-100AC
CY7C1301A-83BGC
ACx
176 Pin TQFP
Commercial
Shaded areas contain advance information.
Document #: 38-05076 Rev. **
Page 13 of 15
PRELIMINARY
CY7C1301A
Package Diagram
176-Lead Thin Quad Flat Pack (24x24x1.4 mm) A176
Document #: 38-05076 Rev. **
Page 14 of 15
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
CY7C1301A
Document Title: CY7C1301A - 256K x 36 Dual I/O Dual Address Synchronous SRAM
Document: 38-05076
Issue
Date
Orig. of
REV.
ECN NO.
Change Description of Change
**
107305
06/08/01
NSL
New Data Sheet
Document #: 38-05076 Rev. **
Page 15 of 15
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