CY7C1344-90AC [CYPRESS]
Cache SRAM, 64KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100;
| 型号： | CY7C1344-90AC |
| 厂家： | 
CYPRESS |
| 描述： | Cache SRAM, 64KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总14页 (文件大小：386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
fax id: 1110
PRELIMINARY
CY7C1344
64K x 36 Synchronous Flow-Through 3.3V Cache RAM
Features
Functional Description
• Supports117-MHzmicroprocessorcachesystems with
zero wait states
• 64K by 36 common I/O
• Low Standby Power (1.65 mW, L version)
• Fast clock-to-output times
— 7.5 ns (117-MHz version)
The CY7C1344 is a 3.3V 64K by 36 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
7.5 ns (117-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access.
The CY7C1344 allows both interleaved and linear burst se-
quences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs. Address advancement is controlled by the ad-
dress advancement (ADV) input.
• Two-bit wrap-around counter supporting either inter-
leaved or linear burst sequence
• Separate processorand controller address strobes pro-
vide direct interface with the processor and external
cache controller
• Synchronous self-timed write
• Asynchronous output enable
• 3.3V I/Os
• JEDEC-standard pinout
• 100-pin TQFP packaging
• ZZ “sleep” mode
A synchronous self-timed write mechanism is provided to sim-
plify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.
Logic Block Diagram
MODE
2
(A ,A )
0
1
Q
Q
CLK
ADV
ADSC
0
BURST
COUNTER
CE
CLR
1
ADSP
Q
14
16
ADDRESS
REGISTER
CE
D
64K X 36
MEMORY
ARRAY
A
[15:0]
GW
16
14
DQ[31:24],DP3
Q
Q
Q
D
BYTEWRITE
BWE
BWS
REGISTERS
3
DQ[23:16],DP2
D
BYTEWRITE
REGISTERS
BWS
BWS
2
DQ[15:8],DP1
D
BYTEWRITE
1
REGISTERS
D
DQ[7:0],DP0 Q
BWS
BYTEWRITE
0
REGISTERS
36
36
CE
CE
CE
1
2
D
CE
ENABLE
Q
REGISTER
3
CLK
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ
[31:0]
DP
[3:0]
Selection Guide
7C1344–117
7C1344–100
7C1344–90
7C1344–50
11.0
Maximum Access Time (ns)
7.5
350
2.0
8.0
325
2.0
8.5
300
2.0
Maximum Operating Current (mA)
250
Maximum Standby Current (mA)
2.0
Pentium is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
August 24, 1998
PRELIMINARY
CY7C1344
Pin Configuration
100-Lead TQFP
DP2
1
DP1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ16
DQ17
VDDQ
VSSQ
DQ18
DQ19
DQ20
DQ21
VSSQ
VDDQ
DQ22
DQ23
VSSQ
VDD
2
DQ15
DQ14
3
4
VDDQ
VSSQ
DQ13
DQ12
DQ11
DQ10
VSSQ
VDDQ
DQ9
5
6
7
8
BYTE2
9
BYTE1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DQ8
VSS
NC
NC
VDD
ZZ
VSS
DQ24
DQ25
VDDQ
VSSQ
DQ26
DQ27
DQ28
DQ29
VSSQ
VDDQ
DQ30
DQ31
DP3
DQ7
DQ6
VDDQ
VSSQ
DQ5
DQ4
DQ3
DQ2
VSSQ
VDDQ
DQ1
DQ0
DP0
BYTE3
BYTE0
2
PRELIMINARY
CY7C1344
Pin Descriptions
TQFP Pin
Number
Name
I/O
Description
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted
LOW, A is captured in the address registers. A are also loaded into the burst
85
ADSC
Input-
Synchronous
[15:0]
[1:0]
counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
84
ADSP
Input-
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted
Synchronous
LOW, A
is captured in the address registers. A
are also loaded into the burst
[15:0]
[1:0]
counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP
is ignored when CE is deasserted HIGH.
1
36, 37
A
A
Input-
Synchronous
A , A Address Inputs, These inputs feed the on-chip burst counter as the LSBs as
1 0
well as being used to access a particular memory location in the memory array.
[1:0]
49 −44,
81–82,
99–100,
32–35
Input-
Synchronous
Address Inputs used in conjunction with A to select one of the 64K address loca-
[15:2]
[1:0]
tions. Sampled at the rising edge of the CLK, if CE , CE , and CE are sampled active,
1 2 3
and ADSP or ADSC is active LOW.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes.
96–93
BW
Input-
[3:0]
Synchronous
Sampled on the rising edge. BW controls DQ
and DP , BW controls DQ
and
0
[7:0]
0
1
[15:8]
DP , BW controls DQ
and DP , and BW controls DQ
and DP . See Write
1
2
[23:16]
2
3
[31:24] 3
Cycle Descriptions table for further details.
83
ADV
Input-
Synchronous
Advance input used to advance the on-chip address counter. When LOW, the internal
burst counter is advanced in a burst sequence. The burst sequence is selected using
the MODE input.
87
88
BWE
GW
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Input-
Synchronous
Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is
used to conduct a global write, independent of the state of BWE and BW
. Global
[3:0]
writes override byte writes.
89
98
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device.
CE
CE
CE
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in con-
junction with CE and CE , to select/deselect the device. CE gates ADSP.
1
2
3
2
3
1
97
92
86
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in con-
junction with CE and CE to select/deselect the device.
1
3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in con-
junction with CE and CE to select/deselect the device.
1
2
OE
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
Asynchronous When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins.
64
31
ZZ
Input-
Snooze input. Active HIGH asynchronous. When HIGH, the device enters a low-power
Asynchronous standby mode in which all other inputs are ignored, but the data in the memory array
is maintained. Leaving ZZ floating or NC will default the device into an active state.
MODE
-
Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. When left floating or NC, de-
faults to interleaved burst order.
30–28,
25–22,
19–18,
13–12,
9–6, 3-1,
80–78,
75–72,
69–68,
63–62,
59–56,
53–51
DQ
,
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
[31:0]
DP
[3:0]
memory location specified by A
during the previous clock rise of the read cycle.
[16:0]
The direction of the pins is controlled by OE in conjunction with the internal control
logic. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ
[31:0]
and DP
are placed in a three-state condition. The outputs are automatically
[3:0]
three-stated when a Write cycle is detected.
15, 41, 65,
91
V
Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
DD
3
PRELIMINARY
CY7C1344
Pin Descriptions (continued)
TQFP Pin
Number
Name
I/O
Ground
Description
17, 40, 67,
90
V
V
Ground for the I/O circuitry of the device. Should be connected to ground of the sys-
tem.
SS
5, 10, 14,
21, 26, 55,
60, 71, 76
Ground
Ground for the device. Should be connected to ground of the system.
Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
No connects.
SSQ
DDQ
4, 11, 20,
27, 54, 61,
70, 77
V
I/O Power
Supply
1,16, 30,
50–51, 66,
80
NC
-
-
38, 39, 42, DNU
43
Do not use pins. Should be left unconnected or tied LOW.
to the presentation of data to DQ
precaution, the data lines are three-stated once a write cycle
is detected, regardless of the state of OE.
and DP
. As a safety
[3:0]
Functional Description
[31:0]
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are sat-
Single Read Accesses
isfied at clock rise: (1) CE , CE , and CE are all asserted
1
2
3
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE , CE , and CE are all as-
active, and (2) ADSP is asserted LOW. The addresses pre-
sented are loaded into the address register and the burst
counter/control logic and delivered to the RAM core. The write
1
2
3
serted active, and (2) ADSP or ADSC is asserted LOW (if the
access is initiated by ADSC, the write inputs must be deassert-
ed during this first cycle). The address presented to the ad-
dress inputs is latched into the address register and the burst
counter/control logic and presented to the memory core. If the
OE input is asserted LOW, the requested data will be available
inputs (GW, BWE, and BWS
) are ignored during this first
[3:0]
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
at the data outputs a maximum to t after clock rise. ADSP
During byte writes, BWS controls DQ
and DP , BWS
CDV
0
[7:0]
0
1
is ignored if CE is HIGH.
controls DQ
and DP , BWS controls DQ
and DP ,
1
[15:8]
1
2
[23:16]
2
and BWS controls DQ
and DP . All I/Os are three-stat-
3
[31:24]
3
Burst Sequences
ed during a byte write. Since these are common I/O device, the
asynchronous OE input signal must be deasserted and the
I/Os must be three-stated prior to the presentation of data to
The CY7C1344 provides an on-chip 2-bit wraparound burst
counter inside the SRAM. The burst counter is fed by A
,
[1:0]
DQ
and DP
. As a safety precaution, the data lines are
[31:0]
[3:0]
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LOW on MODE will select a linear burst sequence. A HIGH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default to an interleaved
burst sequence.
three-stated once a write cycle is detected, regardless of the
state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE , CE , and CE are all asserted
1
2
3
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
Table 1. Counter Implementation for the Intel
Pentium®/80486 Processor’s Sequence
HIGH, and (4) the write input signals (GW, BWE, and BWS
)
[3:0]
indicate a write access. ADSC is ignored if ADSP is active LOW.
First
Address
Second
Address
Third
Address
Fourth
Address
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the RAM
core. The information presented to DQ
written into the specified address location. Byte writes are al-
and DP
will be
A
,A
A
, A
A
, A
A
, A
X + 1 x
[31:0]
[3:0]
X + 1
x
X + 1
x
X + 1
x
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
lowed. During byte writes, BWS controls DQ
and DP ,
0
[7:0]
0
BWS controls DQ
and DP , BWS controls DQ
and
1
[15:8]
1
2
[23:16]
DP , and BWS controls DQ
and DP . All I/Os are
2
3
[31:24]
3
three-stated when a write is detected, even a byte write. Since
these are common I/O device, the asynchronous OE input sig-
nal must be deasserted and the I/Os must be three-stated prior
4
PRELIMINARY
CY7C1344
Sleep Mode
Table 2. Counter Implementation for a Linear Sequence
The ZZ input pin is an asynchronous input. Asserting ZZ HIGH
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed. Ac-
cesses pending when entering the “sleep” mode are not con-
sidered valid nor is the completion of the operation guaran-
teed. The device must be deselected prior to entering the
First
Second
Third
Fourth
Address
Address
Address
Address
A
, A
A
, A
A
, A
A
, A
X + 1
X + 1
x
X + 1
x
X + 1
x
x
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
“sleep” mode. CE , CE , CE ADSP, and ADSC must remain
1
2
3,
inactive for the duration of t
after the ZZ input returns
ZZREC
LOW. Leaving ZZ unconnected defaults the device into an ac-
tive state.
Cycle Description Table[1, 2, 3]
ADD
Cycle Description
Used
CE CE
CE
X
L
ZZ ADSP ADSP ADV WE
OE CLK
DQ
1
3
2
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Snooze Mode, Power-down
Read Cycle, Begin Burst
None
None
H
L
X
X
H
X
X
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
None
L
X
L
L
None
L
H
H
X
L
None
X
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
X
X
L
X
High-Z
Q
External
External
External
External
External
Next
L-H
Read Cycle, Begin Burst
L
L
L
H
X
L
L-H High-Z
Write Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H
L-H
D
Q
Read Cycle, Begin Burst
L
L
L
H
H
H
H
H
H
L
Read Cycle, Begin Burst
L
L
L
H
L
L-H High-Z
L-H
L-H High-Z
L-H
L-H High-Z
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L-H
L-H
L-H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H High-Z
L-H
L-H High-Z
Q
H
X
X
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Notes:
L-H
L-H
D
D
L
1. X=Don't Care, 1=Logic HIGH, 0=Logic LOW.
2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWS[3:0]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE
is a don't care for the remainder of the write cycle.
3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inactive, and DQ=data when OE is active.
5
PRELIMINARY
CY7C1344
Write Cycle Descriptions[1, 2, 3, 4]
Function
GW
1
BWE
1
BW
X
1
BW
X
1
BW
X
1
BW
X
1
3
2
1
0
Read
Read
1
0
Write Byte 0, DP
Write Byte 1, DP
1
0
1
1
1
0
0
1
1
0
1
1
0
1
Write Bytes 1, 0, DP , DP
1
0
1
1
0
0
0
1
Write Byte 2, DP
1
0
1
0
1
1
2
Write Bytes 2, 0, DP , DP
1
0
1
0
1
0
2
0
1
Write Bytes 2, 1, DP , DP
1
0
1
0
0
1
2
Write Bytes 2, 1, 0, DP , DP , DP
1
0
1
0
0
0
2
1
0
0
Write Byte 3, DP
1
0
0
1
1
1
3
Write Bytes 3, 0, DP , DP
1
0
0
1
1
0
3
0
0
Write Bytes 3, 1, DP , DP
1
0
0
1
0
1
3
Write Bytes 3, 1, 0, DP , DP , DP
1
0
0
1
0
0
3
1
Write Bytes 3, 2, DP , DP
1
0
0
0
1
1
3
2
Write Bytes 3, 2, 0, DP , DP , DP
1
0
0
0
1
0
3
2
0
1
Write Bytes 3, 2, 1, DP , DP , DP
1
0
0
0
0
1
3
2
Write All Bytes
Write All Bytes
1
0
0
0
0
0
0
X
X
X
X
X
[5]
DC Input Voltage ........................................... –0.5V to V + 0.5V
Maximum Ratings
DD
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ...................................–65°C to +150°C
Latch-Up Current.................................................... >200 mA
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Operating Range
Supply Voltage on V Relative to GND................ –0.5V to +4.6V
Ambient
DD
[6]
Range Temperature
V
V
DDQ
DD
DC Voltage Applied to Outputs
[5]
in High Z State ...............................................–0.5V to V + 0.5V
DD
Com’l
0°C to +70°C
3.135V to 3.6V 2.375V to V
DD
Notes:
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
6. TA is the “instant on” case temperature.
6
PRELIMINARY
CY7C1344
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min. Max. Unit
V
V
Output HIGH Voltage
V
V
V
V
= 3.3V, V = Min., I =–4.0 mA
2.4
1.7
V
V
V
V
V
OH
DDQ
DDQ
DDQ
DDQ
DD
OH
= 2.5V, V = Min., I =–2.0 mA
DD
OH
Output LOW Voltage
Input HIGH Voltage
= 3.3V, V = Min., I =8.0 mA
0.4
0.7
OL
DD
OL
= 2.5V, V = Min., I =2.0 mA
DD
OL
V
V
1.7
V
+
DD
IH
IL
0.3V
0.8
1
[5]
Input LOW Voltage
–0.3
V
I
Input Load Current
GND ≤ V ≤ V
−1
µA
X
I
DDQ
(except ZZ and MODE)
Input Current of MODE
Input = V
Input = V
Input = V
Input = V
–30
–5
µA
µA
µA
µA
µA
SS
5
DDQ
SS
Input Current of ZZ
30
5
DDQ
I
I
I
Output Leakage Current
GND ≤ V ≤ V Output Disabled
–5
OZ
OS
DD
I
DD,
[7]
Output Short Circuit Current
V
V
f=f
=Max., V =GND
–300 mA
DD
OUT
V
Operating Supply Current
=Max., Iout=0mA,
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
11-ns cycle, 90 MHz
20-ns cycle, 50 MHz
350
325
300
250
125
110
100
75
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
DD
DD
=1/t
.
MAX
CYC
I
Automatic CE Power-Down
Max. V , Device Deselected, 8.5-ns cycle, 117 MHz
DD
V
f = f
SB1
Current—TTL Inputs switching
≥ V or V ≤ V
IN
IH
IN
IL
10-ns cycle, 100 MHz
11-ns cycle, 90 MHz
20-ns cycle, 50 MHz
= 1/t
MAX
CYC
I
I
Automatic CE Power-Down
Max. V , Device Deselected, Std version - All speeds
V
f = 0
10
SB2
SB3
DD
Current — CMOS Inputs static
≤ 0.3V or V > V
– 0.3V,
IN
IN
DDQ
L version - All speeds
2
Automatic CE Power-Down
Max. V , Device Deselected, 8.5-ns cycle, 117 MHz
95
85
70
60
60
50
40
35
mA
mA
mA
mA
mA
mA
mA
mA
DD
DDQ
Current—CMOS Inputs switching, V ≥ V
– 0.3V or V ≤ 0.3V,
IN
IN
10-ns cycle, 100 MHz
11-ns cycle, 90 MHz
20-ns cycle, 50 MHz
F=Max
f=f
, inputs switching
MAX
I
AutomaticCEPower-DownCurrent Max. V , Device Deselected, 8.5-ns cycle, 117 MHz
DD
— CMOS Inputs static, F=Max
SB4
V
f=f
≥ V – 0.3V or V ≤ 0.3V,
IN DD IN
10-ns cycle, 100 MHz
11-ns cycle, 90 MHz
20-ns cycle, 50 MHz
, inputs static
MAX
Note:
7. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
7
PRELIMINARY
CY7C1344
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
ZZ > V − 0.2V
Min
Max
Unit
I
Snooze mode
3
mA
CCZZ
DD
standby current
I
(L Version)
Snooze mode
standby current
ZZ > V − 0.2V
800
µA
ns
ns
CCZZ
DD
t
Deviceoperationto
ZZ
ZZ > V − 0.2V
2t
CYC
ZZS
DD
t
ZZ recovery time
ZZ < 0.2V
2t
CYC
ZZREC
Capacitance[8]
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
pF
C
C
C
Input Capacitance
6
8
8
IN
A
V
V
= 3.3V,
DD
Clock Input Capacitance
Input/Output Capacitance
pF
CLK
= 3.3V
DDQ
pF
I/O
Note:
8. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1=317
Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
OUTPUT
Z =50
Ω
0
3.0V
GND
90%
10%
R =50
Ω
L
10%
3.0 ns
R2=351
Ω
5 pF
V =1.5V
L
INCLUDING
JIG AND
SCOPE
3.0 ns
≤
≤
(a)
(b)
8
PRELIMINARY
CY7C1344
[9]
Switching Characteristics Over the Operating Range
-117
-100
-90
-50
Parameter
Description
Clock Cycle Time
Min. Max. Min. Max. Min. Max. Min. Max. Unit
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
8.5
3.0
3.0
2.0
0.5
10
4.0
4.0
2.0
0.5
11
4.5
4.5
2.0
0.5
20
4.5
4.5
2.0
0.5
ns
CYC
CH
Clock HIGH
ns
Clock LOW
ns
CL
Address Set-Up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-Up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
ns
AS
ns
AH
7.5
8.0
8.5
11.0 ns
CDV
DOH
ADS
ADH
WES
WEH
ADVS
ADVH
DS
2.0
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BWS , GW,BWE Set-Up Before CLK Rise
[1:0]
BWS , GW,BWE Hold After CLK Rise
[1:0]
ADV Set-Up Before CLK Rise
ADV Hold After CLK Rise
Data Input Set-Up Before CLK Rise
Data Input Hold After CLK Rise
Chip Enable Set-Up
DH
CES
CEH
CHZ
CLZ
EOHZ
EOLZ
EOV
Chip Enable Hold After CLK Rise
[10,11]
Clock to High-Z
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
ns
ns
ns
ns
ns
[10,11]
Clock to Low-Z
0
0
0
0
0
0
0
0
[10,12]
OE HIGH to Output High-Z
[10,12]
OE LOW to Output Low-Z
OE LOW to Output Valid
Note:
9. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC test loads.
10.
tCHZ, tCLZ, tEOHZ, and tEOLZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
11. At any given voltage and temperature, tCHZ (max) is less than tCLZ (min).
12. This parameter is sampled and not 100% tested.
9
PRELIMINARY
CY7C1344
Timing Diagrams
Read/Write Timing
t
t
t
CYC
CL
CH
CLK
t
AH
t
t
AS
A
D
B
C
ADD
t
ADH
ADS
ADSP
t
t
ADH
ADS
ADSC
ADV
t
t
ADVH
ADVS
t
CEH
t
CES
CE
CE
1
t
t
CEH
CES
t
t
WES
WEH
WE
OE
ADSP ignored
with CE HIGH
1
t
EOHZ
D(C)
t
t
CLZ
Data
D
(C+3)
Q
(B+3)
D
(C+1)
D
(C+2)
Q
(B+2)
Q
(B+1)
Q(B)
Q(B)
Q(A)
Q(D)
In/Out
CDV
t
DOH
t
CHZ
Device originally
deselected
WE is the combination of BWE, BWS
and GW to define a write cycle (see Write Cycle Descriptions table).
[1:0]
CE is the combination of CE and CE . All chip selects need to be active in order to select
2
3
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
Qx stands for Data-out X.
= UNDEFINED
= DON’T CARE
10
PRELIMINARY
CY7C1344
Timing Diagrams (continued)
Pipeline Timing
t
t
t
CYC
CL
CH
CLK
t
t
AS
C
E
F
G
H
B
D
A
ADD
t
ADH
ADS
ADSP
ADSC
ADV
t
t
CEH
CES
CE
CE
1
t
t
WES
WEH
WE
OE
ADSP ignored
with CE HIGH
1
t
t
CLZ
Data
D (E)
D (F)
D (H)
Q(A)
D (G)
Q(B)
Q(C)
Q(D)
In/Out
CDV
t
DOH
t
CHZ
Device originally
deselected
WE is the combination of BWE, BWS
, and GW to define a write cycle (see Write Cycle Descriptions table).
[1:0]
CE is the combination of CE and CE . All chip selects need to be active in order to select
2
3
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
Qx stands for Data-out X.
= UNDEFINED
= DON’T CARE
11
PRELIMINARY
CY7C1344
Timing Diagrams (continued)
OE Switching Waveforms
OE
t
EOV
t
EOHZ
three-state
I/Os
t
EOLZ
12
Timing Diagrams (continued)
[13,14]
ZZ Mode Timing
CLK
ADSP
HIGH
ADSC
CE
1
2
LOW
HIGH
CE
CE
3
ZZ
t
ZZS
I
CC
I
(active)
CC
t
ZZREC
I
CCZZ
I/Os
Three-state
Note:
13. Device must be deselected when entering ZZ mode. See Cycle Description for all possible signal conditions to deselect the device.
14. I/Os are in three-state when exiting ZZ sleep mode.
PRELIMINARY
CY7C1344
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
117
100
90
Ordering Code
Package Type
CY7C1344–117AC
CY7C1344–100AC
CY7C1344–90AC
CY7C1344–50AC
A101
A101
A101
A101
100-Lead Thin Quad Flat Pack
100-Lead Thin Quad Flat Pack
100-Lead Thin Quad Flat Pack
100-Lead Thin Quad Flat Pack
Commercial
Commercial
Commercial
Commercial
50
Document #: 38-00724
Package Diagram
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
相关型号：
CY7C1344F-100ACT
Cache SRAM, 64KX36, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
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