CY7C13451G-100BZXE [CYPRESS]
Cache SRAM, 128KX36, CMOS, PBGA165, FBGA-165;
| 型号： | CY7C13451G-100BZXE |
| 厂家： | 
CYPRESS |
| 描述： | Cache SRAM, 128KX36, CMOS, PBGA165, FBGA-165 静态存储器 内存集成电路 |
| 文件： | 总23页 (文件大小：601K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C13451G
4-Mbit (128K × 36) Flow-Through
Sync SRAM
4-Mbit (128K
× 36) Flow-Through Sync SRAM
Features
Functional Description
■ 128K × 36 common I/O
The CY7C13451G is a 128K × 36 synchronous cache RAM
designed to interface with high speed microprocessors with
minimum glue logic. The maximum access delay from clock rise
is 8.0 ns (100 MHz version). A 2 bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive edge triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address pipelining Chip Enable (CE1), depth expansion
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,
■ 3.3 V core Power Supply (VDD
)
■ 2.5 V or 3.3 V I/O Supply (VDDQ
)
■ Fast Clock-to-output times
❐ 8.0 ns (100 MHz version)
■ Provide high performance 2-1-1-1 access rate
■ User selectable burst counter supporting Intel Pentium
interleaved or Linear Burst Sequences
ADSP,
ADV), Write Enables BW and BWE), and Global
( ,
x
and
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
■ Separate Processor and Controller Address Strobes
■ Synchronous Self Timed Write
The CY7C13451G enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses are initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address Strobe
(ADSC) inputs.
■ Asynchronous output enable
■ Available in Pb-free 165-ball FBGA Package
■ ZZ Sleep Mode option
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (
are internally generated as controlled by the Advance pin (ADV).
) is active. Subsequent burst addresses
ADSC
The CY7C13451G operates from a +3.3 V core power supply
while all outputs operate with either a +2.5 or +3.3 V supply. All
inputs and outputs are JEDEC standard JESD8-5 compatible.
For a complete list of related documentation, click here.
Selection Guide
Description
100 MHz Unit
Maximum Access Time
8.0
180
60
ns
Maximum Operating Current
Maximum CMOS Standby Current
mA
mA
Cypress Semiconductor Corporation
Document Number: 001-88572 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 22, 2017
CY7C13451G
Logic Block Diagram
ADDRESS
REGISTER
A0, A1,
A
A
[1:0]
MODE
ADV
CLK
Q1
Q0
BURST
COUNTER
AND LOGIC
CLR
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D, DQP D
DQ
BYTE
WRITE REGISTER
D, DQP D
BW
D
DQ
BYTE
WRITE REGISTER
C, DQP C
DQ
BYTE
WRITE REGISTER
C, DQP C
BW
C
OUTPUT
BUFFERS
DQ s
MEMORY
ARRAY
SENSE
AMPS
DQP
DQP
DQP
DQP
A
DQ
BYTE
WRITE REGISTER
B, DQP B
B
C
D
DQ
BYTE
WRITE REGISTER
B, DQP B
BW
B
DQ
BYTE
WRITE REGISTER
A, DQP A
DQ
A, DQPA
BW
A
BYTE
BWE
WRITE REGISTER
INPUT
GW
REGISTERS
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
CONTROL
ZZ
Document Number: 001-88572 Rev. *G
Page 2 of 23
CY7C13451G
Contents
Pin Configurations ...........................................................4
Pin Definitions ..................................................................5
Functional Overview ........................................................6
Single Read Accesses ................................................6
Single Write Accesses Initiated by ADSP ...................6
Single Write Accesses Initiated by ADSC ...................6
Burst Sequences .........................................................7
Sleep Mode .................................................................7
Interleaved Burst Address Table .................................7
Linear Burst Address Table .........................................7
ZZ Mode Electrical Characteristics ..............................7
Truth Table ........................................................................8
Truth Table for Read or Write ..........................................9
Maximum Ratings ...........................................................10
Operating Range .............................................................10
Neutron Soft Error Immunity .........................................10
Electrical Characteristics ...............................................10
Capacitance ....................................................................11
Thermal Resistance ........................................................11
AC Test Loads and Waveforms .....................................12
Switching Characteristics ..............................................13
Timing Diagrams ............................................................14
Ordering Information ......................................................18
Ordering Code Definitions .........................................18
Package Diagrams ..........................................................19
Acronyms ........................................................................20
Document Conventions .................................................20
Units of Measure .......................................................20
Errata ...............................................................................21
Part Numbers Affected ..............................................21
Product Status ...........................................................21
Ram9 Sync ZZ Pin Issues Errata Summary ..............21
Document History Page .................................................22
Sales, Solutions, and Legal Information ......................23
Worldwide Sales and Design Support .......................23
Products ....................................................................23
PSoC®Solutions .......................................................23
Cypress Developer Community .................................23
Technical Support .....................................................23
Document Number: 001-88572 Rev. *G
Page 3 of 23
CY7C13451G
Pin Configurations
Figure 1. 165-ball FBGA pinout [1]
CY7C13451G (128K × 36)
1
2
A
3
CE1
4
BWC
5
BWB
6
CE3
7
8
9
ADV
10
A
11
NC
NC/288M
NC/144M
DQPC
BWE
GW
VSS
VSS
ADSC
A
B
C
D
A
CE2
VDDQ
VDDQ
BWD
VSS
BWA
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
ADSP
VDDQ
VDDQ
A
NC/576M
DQPB
DQB
NC
DQC
NC/1G
DQB
DQC
VDD
DQC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
E
F
DQC
DQC
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQB
DQB
ZZ
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
NC
DQD
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
NC
VSS
VSS
NC
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
NC/9M
M
N
P
NC/18M
A1
NC/72M
A0
MODE
NC/36M
A
A
NC
NC
A
A
A
A
R
Note
1. Errata: The ZZ pin (Ball H11) needs to be externally connected to ground. For more information, see “Errata” on page 21.
Document Number: 001-88572 Rev. *G
Page 4 of 23
CY7C13451G
Pin Definitions
Name
I/O
Description
Address Inputs Used to Select One of the 128K Address Locations. Sampled at the rising edge
A0, A1, A
Input-
Synchronous of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed
the two bit counter.
BWA, BWB,
BWC, BWD
Input-
Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
GW
BWE
CLK
Input-
Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global
Synchronous write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE).
Input-
Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal is asserted
Synchronous LOW to conduct a byte write.
Input Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Input-
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
CE1
CE2
Synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when
a new external address is loaded.
Input-
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE3 to select or deselect the device. CE2 is sampled only when a new external address is
loaded.
Input-
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
CE3
OE
Synchronous and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.
Input- Output Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When
Asynchronou LOW, the I/O pins act as outputs. When deasserted HIGH, I/O pins are tristated and act as input data
s
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input-
Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically incre-
Synchronous ments the address in a burst cycle.
ADSP
Input-
Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are
also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
Input-
Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are
also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-
nized.
ZZ [2]
Input-
ZZ sleep Input, Active HIGH. When asserted HIGH places the device in a non-time critical sleep
Asynchronou condition with data integrity preserved. During normal operation, this pin is low or left floating. ZZ pin
s
has an internal pull down.
DQs, DQPA,
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
DQPB, DQPC, Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by
DQPD
the addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by
. When OE is asserted LOW, the pins act as outputs. When HIGH, DQs and DQP
OE
[A:D]
are placed in a tristate condition.
VDD
VSS
Power Supply Power Supply Inputs to the Core of the Device.
Ground
Ground for the Core of the Device.
VDDQ
I/O Power Power Supply for the I/O Circuitry.
Supply
Note
2. Errata: The ZZ pin (Ball H11) needs to be externally connected to ground. For more information, see “Errata” on page 21.
Document Number: 001-88572 Rev. *G
Page 5 of 23
CY7C13451G
Pin Definitions (continued)
Name
I/O
Description
MODE
Input Static Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and must remain static during device operation.
Mode Pin has an internal pull up.
NC
–
–
No Connects. Not Internally connected to the die.
NC/9M,
NC/18M,
NC/36M,
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M,
NC/288M, NC/576M, and NC/1G are address expansion pins and are not internally connected to the
die.
Single Write Accesses Initiated by ADSP
Functional Overview
Single write access is initiated when the following conditions are
satisfied at clock rise:
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (tCO) is 8.0 ns (100 MHz device).
1. CE1, CE2, and CE3 are all asserted active
2. ADSP is asserted LOW.
The CY7C13451G supports secondary cache in systems using
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486™ processors. The linear
burst sequence is suited for processors that use a linear burst
sequence. The burst order is user selectable and is determined
by sampling the MODE input. Accesses are initiated with either
the Processor Address Strobe (ADSP) or the Controller Address
Strobe (ADSC). Address advancement through the burst
sequence is controlled by the ADV input. A two bit on-chip wrap
around burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
The addresses presented are loaded into the address register
and the burst inputs (GW, BWE, and BWx) are ignored during this
first clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data is latched and
written into the device. Byte writes are allowed. During byte
writes, BWA controls DQA and BWB controls DQB, BWC controls
DQC, and BWD controls DQD. All I/Os are tristated during a byte
write. Since this is a common I/O device, the asynchronous OE
input signal is deasserted and the I/Os are tristated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tristated after a write cycle is detected, regardless of the
state of OE.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous self
timed write circuitry.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise:
Three synchronous Chip Selects (CE1, CE2, and CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tristate control. ADSP is ignored if CE1 is
HIGH.
1. CE1, CE2, and CE3 are all asserted active.
2. ADSC is asserted LOW.
3. ADSP is deasserted HIGH
4. The write input signals (GW, BWE, and BWx) indicate a write
access. ADSC is ignored if ADSP is active LOW.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise:
The addresses presented are loaded into the address register
and the burst counter or control logic and delivered to the
memory core. The information presented to DQ[D:A] is written
into the specified address location. Byte writes are allowed.
During byte writes, BWA controls DQA, BWB controls DQB, BWC
controls DQC, and BWD controls DQD. All I/Os and even a byte
write are tristated when a write is detected. Since this is a
common I/O device, the asynchronous OE input signal is
deasserted and the I/Os are tristated prior to the presentation of
data to DQs. As a safety precaution, the data lines are tristated
1. CE1, CE2, and CE3 are all asserted active.
2. ADSP or ADSC is asserted LOW (if the access is initiated by
ADSC, the write inputs are deasserted during this first cycle).
The address presented to the address inputs is latched into the
address register and the burst counter or control logic and
presented to the memory core. If the OE input is asserted LOW,
the requested data is available at the data outputs a maximum
to tCDV after clock rise. ADSP is ignored if CE1 is HIGH.
after a write cycle is detected, regardless
of the state of OE.
Document Number: 001-88572 Rev. *G
Page 6 of 23
CY7C13451G
Burst Sequences
The CY7C13451G provides an on-chip two bit wrap around burst
counter inside the SRAM. The burst counter is fed by A[1:0] and
follows either a linear or interleaved burst order. The burst order
is determined by the state of the MODE input. A LOW on MODE
selects a linear burst sequence. A HIGH on MODE selects an
interleaved burst order. Leaving MODE unconnected causes the
device to default to a interleaved burst sequence.
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. In this
mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device is
deselected prior to entering the sleep mode. CEs, ADSP, and
ADSC must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Linear Burst Address Table
(MODE = GND)
First
Address
A1,A0
Second
Address
A1,A0
Third
Address
A1,A0
Fourth
Address
A1,A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
Min
Max
Unit
mA
ns
ZZ > VDD– 0.2 V
–
40
2tCYC
–
tZZS
ZZ > VDD – 0.2 V
ZZ < 0.2 V
–
2tCYC
–
tZZREC
tZZI
ns
ZZ Active to sleep current
This parameter is sampled
2tCYC
–
ns
tRZZI
ZZ Inactive to exit sleep current This parameter is sampled
0
ns
Document Number: 001-88572 Rev. *G
Page 7 of 23
CY7C13451G
Truth Table
The Truth Table for part CY7C13451G is as follows. [3, 4, 5, 6, 7]
Address
Cycle Description
Deselected Cycle,
CE1 CE2 CE3 ZZ
ADSP ADSC ADV WRITE OE CLK
DQ
Used
None
H
L
L
L
X
X
L
X
X
H
X
H
L
L
L
L
L
X
L
L
X
X
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L–H
L–H
L–H
L–H
L–H
Tristate
Power down
Deselected Cycle,
Power down
None
None
None
None
Tristate
Tristate
Tristate
Tristate
Deselected Cycle,
Power down
X
L
L
Deselected Cycle,
Power down
H
H
Deselected Cycle,
Power down
X
Sleep Mode, Power down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
None
External
External
External
External
External
Next
X
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
X
X
X
L
X
X
X
X
X
X
L
X
X
X
L
X
L
X
Tristate
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
Q
L
L
L
H
X
L
Tristate
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
D
L
L
L
H
H
H
H
H
H
L
Q
L
L
L
H
L
Tristate
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Tristate
Next
L
Q
Next
L
H
X
X
L
Tristate
Next
L
D
Next
L
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
Tristate
Q
H
L
H
X
X
Tristate
D
L
D
Notes
3. X = “Don’t Care,” H = Logic HIGH, and L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals (BW , BW , BW , BW ) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BW ,
A
B
C
D
A
BW , BW , BW ), BWE, GW = H.
B
C
D
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks after
[A: D]
the ADSP or with the assertion of ADSC. As a result, OE is driven HIGH prior to the start of the write cycle to enable the outputs to tristate. OE is a “Do Not Care” for
the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is
inactive
OE
or when the device is deselected, and all data bits behave as output when
is active (LOW).
Document Number: 001-88572 Rev. *G
Page 8 of 23
CY7C13451G
Truth Table for Read or Write
The Truth Table for read or write for part CY7C13451G is as follows. [8, 9]
Function
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
BWD
X
H
H
H
H
H
H
H
H
L
BWC
X
H
H
H
H
L
BWB
X
H
H
L
BWA
X
H
L
Read
Read
Write Byte (A, DQPA)
L
Write Byte (B, DQPB)
L
H
L
Write Bytes (B, A, DQPA, DQPB)
Write Byte (C, DQPC)
L
L
L
H
H
L
H
L
Write Bytes (C, A, DQPC, DQPA)
Write Bytes (C, B, DQPC, DQPB)
Write Bytes (C, B, A, DQPC, DQPB, DQPA)
Write Byte (D, DQPD)
L
L
L
L
H
L
L
L
L
L
H
H
H
H
L
H
H
L
H
L
Write Bytes (D, A, DQPD, DQPA)
Write Bytes (D, B, DQPD, DQPA)
Write Bytes (D, B, A, DQPD, DQPB, DQPA)
Write Bytes (D, B, DQPD, DQPB)
Write Bytes (D, B, A, DQPD, DQPC, DQPA)
Write Bytes (D, C, A, DQPD, DQPB, DQPA)
Write All Bytes
L
L
L
L
H
L
L
L
L
L
L
H
H
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
Write All Bytes
X
X
X
X
X
Notes
8. X = “Don’t Care,” H = Logic HIGH, and L = Logic LOW.
9. This table is only a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write is done based on the active byte write.
x
Document Number: 001-88572 Rev. *G
Page 9 of 23
CY7C13451G
Maximum Ratings
Operating Range
Exceeding the maximum ratings may shorten the battery life of
the device. These user guidelines are not tested.
Ambient
Temperature
Range
VDD
VDDQ
Storage Temperature ............................... –65 °C to +150 °C
Automotive
–40 °C to +125 °C 3.3 V5% / 2.5 V – 5%
+ 10% to VDD
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Supply Voltage on
Neutron Soft Error Immunity
V
DD Relative to GND ...................................–0.5 V to +4.6 V
Supply Voltage on
DDQ Relative to GND .................................. –0.5 V to +VDD
Test
Parameter Description
Conditions
Typ Max* Unit
V
DC Voltage Applied to Outputs
in tristate ...........................................–0.5 V to VDDQ + 0.5 V
LSBU
LMBU
SEL
Logical
Single-Bit
Upsets
25 °C
25 °C
85 °C
361 394 FIT/
Mb
DC Input Voltage ................................–0.5 V to VDD + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Logical
Multi-Bit
Upsets
0
0
0.01 FIT/
Mb
Static Discharge Voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
SingleEvent
Latch up
0.1 FIT/
Dev
Latch up Current .................................................... >200 mA
* No LMBU or SEL events occurred during testing; this column represents a
2
statistical , 95% confidence limit calculation. For more details refer to
Application Note AN54908 “Accelerated Neutron SER Testing and Calculation
of Terrestrial Failure Rates”
Electrical Characteristics
Over the Operating Range
Parameter [10, 11]
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min
3.135
2.375
2.4
Max
Unit
V
VDD
3.6
VDDQ
VOH
VDD
V
Output HIGH Voltage
for 3.3 V I/O, IOH = –4.0 mA
for 2.5 V I/O, IOH = –1.0 mA
for 3.3 V, I/O, IOL= 8.0 mA
for 2.5 V I/O, IOL = 1.0 mA
for 3.3 V I/O
–
V
2.0
–
0.4
V
VOL
VIH
VIL
IX
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[10]
–
V
–
0.4
V
2.0
VDD + 0.3
VDD + 0.3
0.8
V
for 2.5 V I/O
1.7
V
for 3.3 V I/O
–0.3
–0.3
5
V
for 2.5 V I/O
0.7
V
Input Leakage Current except ZZ GND VI VDDQ
and MODE
5
A
Input Current of MODE
Input = VSS
–30
–
–
5
A
A
A
A
A
Input = VDD
Input Current of ZZ
Input = VSS
–5
–
–
Input = VDD
30
5
IOZ
Output Leakage Current
GND VI VDDQ, Output Disabled
–5
Notes
10. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > –2V (Pulse width less than t
/2).
CYC
IH
DD
CYC
IL
11. T
: Assumes a linear ramp from 0 V to V (min) within 200 ms. During this time V < V and V
< V
Power up
DD
IH
DD
DDQ DD.
Document Number: 001-88572 Rev. *G
Page 10 of 23
CY7C13451G
Electrical Characteristics (continued)
Over the Operating Range
Parameter [10, 11]
Description
Test Conditions
VDD = Max., IOUT = 0 mA,
Min
Max
Unit
IDD
VDD Operating Supply Current
100 MHz
–
180
mA
f = fMAX = 1/tCYC
ISB1
ISB2
ISB3
ISB4
Automatic CE Power-down
Current – TTL Inputs
Max. VDD, Device Deselected,
VIN> VIH or VIN < VIL, f = fMAX,
inputs switching
100 MHz
(Automotive)
–
–
–
–
150
40
mA
mA
mA
mA
Automatic CE Power-down
Current – CMOS Inputs
Max. VDD, Device Deselected,
VIN > VDD – 0.3 V or VIN < 0.3 V, (Automotive)
f = 0, inputs static
100 MHz
Automatic CE Power-down
Current – CMOS Inputs
Max. VDD, Device Deselected,
100 MHz
120
60
VIN > VDDQ – 0.3 V or VIN < 0.3 V, (Automotive)
f = fMAX, inputs switching
Automatic CE Power-down
Current – TTL Inputs
Max. VDD, Device Deselected,
100 MHz
(Automotive)
VIN > VIH or VIN < VIL,
f = 0, inputs static
Capacitance
165-ballFBGA
Max.
Parameter [12]
Description
Test Conditions
Unit
CIN
Input capacitance
TA = 25 C, f = 1 MHz,
DD = 3.3 V, VDDQ = 2.5 V
5
5
7
pF
pF
pF
V
CCLK
CI/O
Clock input capacitance
Input/Output capacitance
Thermal Resistance
165-ballFBGA
Package
Parameter [12]
Description
Test Conditions
Unit
JA
Thermal resistance
(junction to ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
16.8
°C/W
JC
Thermal resistance
(junction to case)
3.0
°C/W
Note
12. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-88572 Rev. *G
Page 11 of 23
CY7C13451G
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
OUTPUT
90%
10%
Z = 50
0
R = 50
10%
L
GND
5 pF
R = 351
1ns
1ns
V = 1.5V
T
INCLUDING
JIG AND
SCOPE
(a)
2.5V I/O Test Load
OUTPUT
(b)
(c)
R = 1667
2.5V
OUTPUT
R = 50
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50
0
10%
L
5 pF
R = 1538
1 ns
INCLUDING
1 ns
V = 1.25V
T
JIG AND
SCOPE
(a)
(b)
(c)
Document Number: 001-88572 Rev. *G
Page 12 of 23
CY7C13451G
Switching Characteristics
Over the Operating Range
-100
Unit
Max
Parameter [13, 14]
Description
VDD(Typical) to the first Access [15]
Min
tPOWER
Clock
tCYC
1
–
ms
Clock Cycle Time
Clock HIGH
10
4.0
4.0
–
–
–
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCDV
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low Z [16, 17, 18]
–
2.0
0
8.0
–
ns
ns
ns
ns
ns
ns
ns
tDOH
tCLZ
–
tCHZ
Clock to High Z [16, 17, 18]
–
3.5
3.5
–
tOEV
OE LOW to Output Valid
–
tOELZ
tOEHZ
Setup Times
tAS
OE LOW to Output Low Z [16, 17, 18]
OE HIGH to Output High Z [16, 17, 18]
0
–
3.5
Address Setup Before CLK Rise
ADSP, ADSC Setup Before CLK Rise
ADV Setup Before CLK Rise
2.0
2.0
2.0
2.0
2.0
2.0
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADS
tADVS
tWES
GW, BWE, BWx Setup Before CLK Rise
Data Input Setup Before CLK Rise
Chip Enable Setup
tDS
tCES
Hold Times
tAH
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
GW, BWE, BWx Hold After CLK Rise
ADV Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADH
tWEH
tADVH
tDH
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
tCEH
Notes
13. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
14. Test conditions shown in (a) of unless otherwise noted.
15. This part has a voltage regulator internally; t
initiated.
is the time that the power needs to be supplied above V (minimum) initially before a read or write operation is
POWER
DD
16. t
, t
,t
, and t
are specified with AC test conditions shown in (b) of Figure 2 on page 12. Transition is measured ± 200 mV from steady state voltage.
CHLZ CLZ OELZ
OEHZ
17. At any voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data bus.
OEHZ
OELZ
CHZ
CLZ
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High Z
prior to Low Z under the same system conditions.
18. This parameter is sampled and not 100% tested.
Document Number: 001-88572 Rev. *G
Page 13 of 23
CY7C13451G
Timing Diagrams
Figure 3. Read Cycle Timing [19]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
ADDRESS
t
t
WES
WEH
GW, BWE,BW
[A:B]
Deselect Cycle
t
t
CES
CEH
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
t
CDV
OEV
OELZ
t
t
OEHZ
CHZ
t
DOH
t
CLZ
Q(A2)
Q(A2 + 1)
Q(A2
+
2)
Q(A2
+
3)
Q(A2)
Q(A2
+
1)
Q(A2
+
2)
Q(A1)
Data Out (Q)
High-Z
t
CDV
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note
19. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document Number: 001-88572 Rev. *G
Page 14 of 23
CY7C13451G
Timing Diagrams (continued)
Figure 4. Write Cycle Timing [20, 21]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BW[A:B]
t
t
WEH
WES
GW
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
ADV suspends burst
OE
t
t
DH
DS
Data in (D)
High-Z
D(A2)
D(A2
+
1)
D(A2
+
1)
D(A2
+
2)
D(A2
+
3)
D(A3)
D(A3
+
1)
D(A3 + 2)
D(A1)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
Extended BURST WRITE
Single WRITE
DON’T CARE
UNDEFINED
Notes
20. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
21.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
x
Document Number: 001-88572 Rev. *G
Page 15 of 23
CY7C13451G
Timing Diagrams (continued)
Figure 5. Read/Write Timing [22, 23, 24]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
BWE, BW [A:B]
CE
t
t
WEH
WES
t
t
CEH
CES
ADV
OE
t
t
DH
DS
t
OELZ
t
High-Z
D(A3)
D(A5)
D(A6)
Data In (D)
t
OEHZ
CDV
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
Back-to-Back READs
Single WRITE
BURST READ
DON’T CARE
UNDEFINED
Notes
22.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
x
23. The data bus (Q) remains in High Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
24. GW is HIGH.
Document Number: 001-88572 Rev. *G
Page 16 of 23
CY7C13451G
Timing Diagrams (continued)
Figure 6. ZZ Mode Timing [25, 26]
CLK
ZZ
t
t
ZZ
ZZREC
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
25. Device must be deselected when entering ZZ mode. See Truth Table on page 8 for all possible signal conditions to deselect the device.
26. DQs are in High Z when exiting ZZ sleep mode.
Document Number: 001-88572 Rev. *G
Page 17 of 23
CY7C13451G
Ordering Information
The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices
Table 1. Ordering Information
Speed
(MHz)
Package
Diagram
Operating
Range
Part and Package Type
Ordering Code
100 CY7C13451G-100BZXE
51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
Automotive
Ordering Code Definitions
CY
7
C
13451 G - 100 BZ
X
E
Temperature Range:
E = Automotive-E
Pb-free
Package Type:
BZ = 165-ball FBGA
Speed Grade: 100 MHz
Process Technology: G 90 nm
Part Identifier: 13451 = FT, 128Kb × 36 (4Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-88572 Rev. *G
Page 18 of 23
CY7C13451G
Package Diagrams
Figure 7. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
51-85180 *G
Document Number: 001-88572 Rev. *G
Page 19 of 23
CY7C13451G
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CMOS
CE
Complementary Metal Oxide Semiconductor
Chip Enable
Symbol
°C
Unit of Measure
degree Celsius
megahertz
microampere
milliampere
millimeter
millisecond
megahertz
nanosecond
picofarad
volt
MHz
µA
CEN
GW
Clock Enable
Global Write
mA
mm
ms
MHz
ns
I/O
Input/Output
OE
Output Enable
SRAM
TQFP
WE
Static Random Access Memory
Thin Quad Flat Pack
Write Enable
pF
V
W
watt
Document Number: 001-88572 Rev. *G
Page 20 of 23
CY7C13451G
Errata
This section describes the Ram9 Sync SRAM ZZ pin issues. Details include trigger conditions, the devices affected, proposed
workaround and silicon revision applicability. Please contact your local Cypress sales representative if you have further questions.
Part Numbers Affected
Density & Revision
Package Type Operating Range
165-ball FBGA Automotive
4Mb-Ram9 Synchronous SRAMs: CY7C134**G
Product Status
All of the devices in the Ram9 4Mb Sync family are qualified and available in production quantities.
Ram9 Sync ZZ Pin Issues Errata Summary
The following table defines the errata applicable to available Ram9 4Mb Sync family devices.
Item
Issues
Description
Device
Fix Status
1. ZZ Pin
When asserted HIGH, the ZZ pin places
deviceina“sleep”conditionwithdataintegrity
preserved.The ZZ pin currently does not have
an internal pull-down resistor and hence
cannot be left floating externally by the user
during normal mode of operation.
4M-Ram9 (90nm)
For the 4M Ram9 (90 nm)
devices, there is no plan to fix
this issue.
1. ZZ Pin Issue
■ PROBLEM DEFINITION
The problem occurs only when the device is operated in the normal mode with ZZ pin left floating. The ZZ pin on the SRAM
device does not have an internal pull-down resistor. Switching noise in the system may cause the SRAM to recognize a HIGH
on the ZZ input, which may cause the SRAM to enter sleep mode. This could result in incorrect or undesirable operation of the
SRAM.
■ TRIGGER CONDITIONS
Device operated with ZZ pin left floating.
■ SCOPE OF IMPACT
When the ZZ pin is left floating, the device delivers incorrect data.
■ WORKAROUND
Tie the ZZ pin externally to ground.
■ FIX STATUS
For the 4M Ram9 (90 nm) devices, there is no plan to fix this issue
Document Number: 001-88572 Rev. *G
Page 21 of 23
CY7C13451G
Document History Page
Document Title: CY7C13451G, 4-Mbit (128K × 36) Flow-Through Sync SRAM
Document Number: 001-88572
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
4077242
4287129
PRIT
PRIT
09/12/2013 New data sheet.
*A
02/20/2014 Updated Electrical Characteristics:
Changed maximum value of IDD parameter from 205 mA to 180 mA.
Changed maximum value of ISB1 parameter from 80 mA to 150 mA.
Changed maximum value of ISB3 parameter from 65 mA to 120 mA.
Changed maximum value of ISB4 parameter from 45 mA to 60 mA.
*B
*C
4419347
4430376
PRIT
PRIT
06/25/2014 Included 100-pin TQFP package related information in all instances across
the document.
Updated Pin Configurations:
Updated Figure 1.
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams:
Added spec 51-85050 *E.
07/04/2014 Changed status from Preliminary to Final.
Removed 100-pin TQFP package related information across the document.
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams:
Removed spec 51-85050 *E.
*D
*E
4598640
5099908
5329574
PRIT
PRIT
PRIT
12/16/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated to new template.
01/22/2016 Updated Package Diagrams:
spec 51-85180 – Changed revision from *F to *G.
Completing Sunset Review.
*F
06/29/2016 Updated Truth Table.
Updated to new template.
*G
5974265 AESATMP9 11/22/2017 Updated logo and copyright.
Document Number: 001-88572 Rev. *G
Page 22 of 23
CY7C13451G
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
ARM® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
cypress.com/mcu
cypress.com/support
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PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
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Wireless Connectivity
cypress.com/pmic
cypress.com/touch
cypress.com/usb
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© Cypress Semiconductor Corporation, 2013-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-88572 Rev. *G
Revised November 22, 2017
Page 23 of 23
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