CY7C1345-50AC [ETC]
x36 Fast Synchronous SRAM ; X36高速同步SRAM
| 型号： | CY7C1345-50AC |
| 厂家： | 
ETC |
| 描述： | x36 Fast Synchronous SRAM
|
| 文件： | 总16页 (文件大小：319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1345
128K x 36 Synchronous Flow-Through 3.3V Cache RAM
Features
Functional Description
• Supports117-MHzmicroprocessorcachesystems with
zero wait states
• 128K by 36 common I/O
• Fast clock-to-output times
— 7.5 ns (117-MHz version)
The CY7C1345 is a 3.3V, 128K by 36 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap-
tures the first address in a burst and increments the address
automatically for the rest of the burst access.
• Two-bit wrap-around counter supporting either
interleaved or linear burst sequence
• Separate processorand controller address strobes pro-
vide direct interface with the processor and external
cache controller
• Synchronous self-timed write
• Asynchronous output enable
• Supports 3.3V & 2.5V I/O levels
• JEDEC-standard pinout
• 100-pin TQFP packaging
• ZZ “sleep” mode
The CY7C1345 allows either interleaved or linear burst se-
quences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address
Strobe (ADSC) inputs. Address advancement is controlled by
the address advancement (ADV) input.
A synchronous self-timed write mechanism is provided to sim-
plify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.
Logic Block Diagram
MODE
2
(A ,A )
0
1
Q
Q
0
CLK
ADV
ADSC
BURST
COUNTER
CE
CLR
1
ADSP
Q
15
17
ADDRESS
REGISTER
CE
D
128K X 36
MEMORY
ARRAY
A
[16:0]
GW
17
15
DQ[31:24],DP3
Q
Q
Q
D
BYTEWRITE
BWE
BWS
REGISTERS
3
DQ[23:16],DP2
D
BYTEWRITE
REGISTERS
BWS
BWS
2
DQ[15:8],DP1
D
D
BYTEWRITE
1
REGISTERS
DQ[7:0],DP0 Q
BWS
BYTEWRITE
0
REGISTERS
36
36
CE
CE
CE
1
2
D
ENABLE
Q
CE
REGISTER
3
CLK
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ
[31:0]
DP
[3:0]
Selection Guide
7C1345-117
7.5
7C1345-100
8.0
7C1345-90
8.5
7C1345-50
11.0
Maximum Access Time (ns)
Maximum Operating Current (mA)
350
325
300
250
Maximum Standby Current (mA)
10.0
10.0
10.0
10.0
Pentium is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
May 8, 2000
CY7C1345
Pin Configuration
100-Lead TQFP
DP2
1
DP1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ16
DQ17
VDDQ
VSSQ
DQ18
DQ19
DQ20
DQ21
VSSQ
VDDQ
DQ22
DQ23
VSSQ
VDD
2
DQ15
DQ14
3
4
VDDQ
VSSQ
DQ13
DQ12
DQ11
DQ10
VSSQ
VDDQ
DQ9
5
6
7
8
BYTE2
9
BYTE1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DQ8
100-Pin TQFP
CY7C1345
VSS
NC
NC
VDD
ZZ
VSS
DQ24
DQ25
VDDQ
VSSQ
DQ26
DQ27
DQ28
DQ29
VSSQ
VDDQ
DQ30
DQ31
DP3
DQ7
DQ6
VDDQ
VSSQ
DQ5
DQ4
DQ3
DQ2
VSSQ
VDDQ
DQ1
DQ0
DP0
BYTE3
BYTE0
2
CY7C1345
Pin Descriptions
Pin Number
Name
I/O
Description
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted
LOW, A is captured in the address registers. A are also loaded into the burst
85
ADSC
Input-
Synchronous
[15:0]
[1:0]
counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
84
ADSP
Input-
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted
Synchronous
LOW, A
is captured in the address registers. A
are also loaded into the burst
[1:0]
[15:0]
counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP
is ignored when CE is deasserted HIGH.
1
36, 37
A
A
Input-
Synchronous
A , A Address Inputs. These inputs feed the on-chip burst counter as the LSBs as
1 0
well as being used to access a particular memory location in the memory array.
[1:0]
49 −44,
81–82,
99–100,
32–35
Input-
Synchronous
Address Inputs used in conjunction with A to select one of the 64K address
[16:2]
[1:0]
locations. Sampled at the rising edge of the CLK, if CE , CE , and CE are sampled
1 2 3
active, and ADSP or ADSC is active LOW.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes.
96–93
BW
Input-
[3:0]
Synchronous
Sampled on the rising edge. BW controls DQ
and DP , BW controls DQ
0
[7:0]
0
1
[15:8]
and DP , BW controls DQ
and DP , and BW controls DQ
and DP . See
1
2
[23:16]
2
3
[31:24] 3
Write Cycle Description table for further details.
83
ADV
Input-
Synchronous
Advance Input, used to advance the on-chip address counter. When LOW the inter-
nal burst counter is advanced in a burst sequence. The burst sequence is selected
using the MODE input.
87
88
BWE
GW
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Input-
Synchronous
Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is
used to conduct a global write, independent of the state of BWE and BW
writes override byte writes.
. Global
[3:0]
89
98
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device.
CE
CE
CE
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE and CE to select/deselect the device. CE gates ADSP.
1
2
3
2
3
1
97
92
86
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE and CE to select/deselect the device.
1
3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE and CE to select/deselect the device.
1
2
OE
ZZ
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O
Asynchronous pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins
are three-stated, and act as input data pins.
64
31
Input-
Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a
Asynchronous low-power standby mode in which all other inputs are ignored, but the data in the
memory array is maintained.Leaving ZZ floating or NC will default the device into an
active state. ZZ pin has an internal pull-down.
MODE
-
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. When left floating or NC,
defaults to interleaved burst order. Mode pin has an internal pull-up.
30–28,
25–22,
DQ
DP
,
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in
[31:0]
[3:0]
19–18,
the memory location specified by A
cycle. The direction of the pins is controlled by OE in conjunction with the internal
control logic. When OE is asserted LOW, the pins behave as outputs. When HIGH,
during the previous clock rise of the read
[16:0]
13–12, 9–6,
3–1, 80–78,
75–72,
DQ
and DP
are placed in a three-state condition. The outputs are automat-
[31:0]
[3:0]
69–68,
ically three-stated when a Write cycle is detected.
63–62,
59–56,
53–51
15, 41, 65,
91
V
Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
DD
3
CY7C1345
Pin Descriptions (continued)
Pin Number
Name
I/O
Ground
Description
17, 40, 67,
90
V
Ground for the I/O circuitry of the device. Should be connected to ground of the
system.
SS
5, 10, 14, 21,
26, 55, 60,
71, 76
V
V
Ground
Ground for the device. Should be connected to ground of the system.
Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
No connects.
SSQ
4, 11, 20, 27,
54, 61, 70,
77
I/O Power
Supply
DDQ
1, 16, 30,
50–51, 66,
80
NC
-
-
38, 39, 42,
43
DNU
Do not use pins. Should be left unconnected or tied LOW.
counter/control logic and delivered to the RAM core. The write
Functional Overview
inputs (GW, BWE, and BW
) are ignored during this first
[3:0]
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
the clock rise (t
) is 7.5 ns (117-MHz device).
CDV
The CY7C1345 supports secondary cache in systems utilizing
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486 processors. The linear
burst sequence is suited for processors that utilize a linear
burst sequence. The burst order is user selectable, and is de-
termined by sampling the MODE input. Accesses can be initi-
ated with either the Processor Address Strobe (ADSP) or the
Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first ad-
dress in a burst sequence and automatically increments the
address for the rest of the burst access.
During byte writes, BW controls DQ
, BW controls
0
[7:0]
1
DQ
, BW controls DQ
, and BW controls DQ
.
[31:24]
[15:8]
2
[23:16]
3
All I/Os are three-stated during a byte write. Since this is a
common I/O device, the asynchronous OE input signal must
be deasserted and the I/Os must be three-stated prior to the
presentation of data to DQ
. As a safety precaution, the
[31:0]
data lines are three-stated once a write cycle is detected, re-
gardless of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE , CE , and CE are all asserted
1
2
3
Byte write operations are qualified with the Byte Write Enable
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
(BWE) and Byte Write Select (BW
) inputs. A Global Write
[3:0]
HIGH, and (4) the write input signals (GW, BWE, and BW
)
[3:0]
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip synchro-
nous self-timed write circuitry.
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the RAM
Three synchronous Chip Selects (CE , CE , CE ) and an
1
2
3
core. The information presented to DQ
will be written into
[31:0]
asynchronous Output Enable (OE) provide for easy bank se-
the specified address location. Byte writes are allowed. During
byte writes, BW controls DQ , BW controls DQ , BW
2
lection and output three-state control. ADSP is ignored if CE
is HIGH.
1
0
[7:0]
1
[15:8]
. All I/Os are
controls DQ
, and BWS controls DQ
[23:16]
3
[31:24]
three-stated when a write is detected, even a byte write. Since
this is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be three-stated prior to
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE , CE , and CE are all as-
1
2
3
the presentation of data to DQ
. As a safety precaution, the
[31:0]
serted active, and (2) ADSP or ADSC is asserted LOW (if the
access is initiated by ADSC, the write inputs must be deassert-
ed during this first cycle). The address presented to the ad-
dress inputs is latched into the address register and the burst
counter/control logic and presented to the memory core. If the
OE input is asserted LOW, the requested data will be available
data lines are three-stated once a write cycle is detected, re-
gardless of the state of OE.
Burst Sequences
The CY7C1345 provides an on-chip 2-bit wraparound burst
at the data outputs a maximum to t
after clock rise. ADSP
counter inside the SRAM. The burst counter is fed by A
,
CDV
[1:0]
is ignored if CE is HIGH.
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LOW on MODE will select a linear burst sequence. A HIGH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default to a interleaved
burst sequence.
1
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) CE , CE , and CE are all asserted
1
2
3
active, and (2) ADSP is asserted LOW. The addresses pre-
sented are loaded into the address register and the burst
4
CY7C1345
Sleep Mode
Table 1. Counter Implementation for the Intel
Pentium®/80486 Processor’s Sequence
The ZZ input pin is an asynchronous input. Asserting ZZ HIGH
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed. Access-
es pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep” mode.
First
Address
Second
Address
Third
Address
Fourth
Address
A
, A
A
,A
A
, A
A
, A
X + 1 x
X + 1
x
X + 1
x
X + 1
x
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
CE , CE , CE , ADSP, and ADSC must remain inactive for the
1
2
3
duration of t
after the ZZ input returns LOW. Leaving ZZ
ZZREC
unconnected defaults the device into an active state.
Table 2. Counter Implementation for a Linear Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A
, A
A
, A
A
, A
A
, A
X + 1 x
X + 1
x
X + 1
x
X + 1
x
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
I
t
t
Snooze mode stand- ZZ > V − 0.2V
3
ns
CCZZ
DD
by current
Device operation to
ZZ
ZZ > V − 0.2V
2t
CYC
ns
ZZS
DD
ZZ recovery time
ZZ < 0.2V
2t
mA
ZZREC
CYC
5
CY7C1345
Cycle Description Table[1, 2, 3]
ADD
Cycle Description
Used
CE CE
CE
X
L
ZZ ADSP ADSC ADV WE
OE CLK
DQ
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
1
3
2
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Snooze Mode, Power-down
Read Cycle, Begin Burst
None
H
L
X
X
H
X
X
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
None
None
L
X
L
L
None
L
H
H
X
L
None
X
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
X
X
L
X
High-Z
Q
External
External
External
External
External
Next
L-H
Read Cycle, Begin Burst
L
L
L
H
X
L
L-H High-Z
Write Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H
L-H
D
Q
Read Cycle, Begin Burst
L
L
L
H
H
H
H
H
H
L
Read Cycle, Begin Burst
L
L
L
H
L
L-H High-Z
L-H
L-H High-Z
L-H
L-H High-Z
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L-H
L-H
L-H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H High-Z
L-H
L-H High-Z
Q
H
X
X
L-H
L-H
D
D
Write Cycle, Suspend Burst
L
Notes:
1. X=”Don't Care,” 1=Logic HIGH, 0=Logic LOW.
2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWS[3:0]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE
is a don't care for the remainder of the write cycle.
3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inactive, and DQ=data when OE is active.
6
CY7C1345
Write Cycle Descriptions[1, 2, 3, 4]
Function
GW
1
BWE
1
BW
X
1
BW
X
1
BW
X
1
BW
X
1
3
2
1
0
Read
Read
1
0
Write Byte 0, DP
Write Byte 1, DP
1
0
1
1
1
0
0
1
1
0
1
1
0
1
Write Bytes 1, 0, DP , DP
1
0
1
1
0
0
0
1
Write Byte 2, DP
1
0
1
0
1
1
2
Write Bytes 2, 0, DP , DP
1
0
1
0
1
0
2
0
1
Write Bytes 2, 1, DP , DP
1
0
1
0
0
1
2
Write Bytes 2, 1, 0, DP , DP , DP
1
0
1
0
0
0
2
1
0
0
Write Byte 3, DP
1
0
0
1
1
1
3
Write Bytes 3, 0, DP , DP
1
0
0
1
1
0
3
0
0
Write Bytes 3, 1, DP , DP
1
0
0
1
0
1
3
Write Bytes 3, 1, 0, DP , DP , DP
1
0
0
1
0
0
3
1
Write Bytes 3, 2, DP , DP
1
0
0
0
1
1
3
2
Write Bytes 3, 2, 0, DP , DP , DP
1
0
0
0
1
0
3
2
0
1
Write Bytes 3, 2, 1, DP , DP , DP
1
0
0
0
0
1
3
2
Write All Bytes
Write All Bytes
1
0
0
0
0
0
0
X
X
X
X
X
[5]
DC Input Voltage ................................ –0.5V to V + 0.5V
Maximum Ratings
DD
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-Up Current.................................................... >200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on V Relative to GND........ –0.5V to +4.6V
Ambient
DD
[6]
Range Temperature
V
V
DDQ
DD
DC Voltage Applied to Outputs
[5]
in High Z State ....................................–0.5V to V + 0.5V
DD
Com’l
0°C to +70°C
3.135V to 3.6V 2.375V to V
DD
Notes:
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
6. TA is the case temperature.
7
CY7C1345
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min. Max. Unit
V
V
Output HIGH Voltage
V
V
V
V
V
= 3.3V, V = Min., I = –4.0 mA
2.4
2.0
V
V
V
V
V
OH
DDQ
DDQ
DDQ
DDQ
DDQ
DD
OH
= 2.5V, V = Min., I = –2.0 mA
DD
OH
Output LOW Voltage
= 3.3V, V = Min., I = 8.0 mA
0.4
0.7
OL
DD
OL
= 2.5V, V = Min., I = 2.0 mA
DD
OL
V
V
Input HIGH Voltage
Input HIGH Voltage
= 3.3V
2.0
1.7
V
+
DD
IH
IH
0.3V
V
= 2.5V
V
+
V
DDQ
DD
0.3V
[5]
V
V
Input LOW Voltage
V
V
= 3.3V
= 2.5V
–0.3
–0.3
−1
0.8
0.7
1
V
V
IL
IL
DDQ
DDQ
[5]
Input LOW Voltage
I
Input Load Current
GND ≤ V ≤ V
µA
X
I
DDQ
(except ZZ and MODE)
Input Current of MODE
Input Current of ZZ
Input = V
Input = V
Input = V
Input = V
–30
–5
µA
µA
µA
µA
µA
SS
5
DDQ
SS
30
5
DDQ
I
I
I
Output Leakage Current
GND ≤ V ≤ V Output Disabled
–5
OZ
OS
DD
I
DD,
[7]
Output Short Circuit Current
V
= Max., V
= GND
–300 mA
DD
OUT
V
Operating Supply Current
V
f = f
= Max., I
= 0 mA,
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
11-ns cycle, 90 MHz
20-ns cycle, 50 MHz
350
325
300
250
125
110
100
90
mA
mA
mA
mA
mA
mA
mA
mA
mA
DD
DD
OUT
= 1/t
CYC
MAX
I
Automatic CE Power-Down
Current—TTL Inputs
Max. V , Device Deselected, 8.5-ns cycle, 117 MHz
DD
V
f = f
SB1
≥ V or V ≤ V
IN IH IN IL
10-ns cycle, 100 MHz
11-ns cycle, 90 MHz
20-ns cycle, 50 MHz
All speeds
= 1/t
,
MAX
CYC
inputs switching
I
I
Automatic CE Power-Down
Current—CMOS Inputs
Max. V , Device Deselected,
V
f = 0, inputs static
10
SB2
SB3
DD
≤ 0.3V or V > V
– 0.3V,
IN
IN
DDQ
Automatic CE Power-Down
Current—CMOS Inputs
Max. V , Device Deselected,
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
11-ns cycle, 90 MHz
20-ns cycle, 50 MHz
95
85
75
65
30
mA
mA
mA
mA
mA
DD
V
≥ V
– 0.3V or V ≤ 0.3V,
IN
DDQ IN
f = f
, inputs switching
MAX
I
Automatic CE Power-Down
Max. V , Device Deselected,
DD
SB4
Current—TTL Inputs
V ≥V –0.3V or V ≤ 0.3V, f=0,
inputs static
IN DD IN
Notes:
7. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
8
CY7C1345
Capacitance[8]
Parameter
Description
Input Capacitance
I/O Capacitance
Test Conditions
T = 25°C, f = 1 MHz,
Max.
4.0
Unit
pF
C
C
IN
A
V
= 5.0V
DD
4.0
pF
I/O
AC Test Loads and Waveforms
R1=317
Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
OUTPUT
Z =50
Ω
0
3.0V
GND
90%
10%
R =50
Ω
L
10%
3.0 ns
R2=351
Ω
5 pF
V =1.5V
L
INCLUDING
JIG AND
SCOPE
3.0 ns
≤
≤
(a)
(b)
[9]
Switching Characteristics Over the Operating Range
-117
-100
-90
-50
Parameter
Description
Clock Cycle Time
Min. Max. Min. Max. Min. Max. Min. Max. Unit
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
8.5
3.0
3.0
2.0
0.5
10
4.0
4.0
2.0
0.5
11
20
4.5
4.5
2.0
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CYC
CH
Clock HIGH
4.5
4.5
2.0
0.5
Clock LOW
CL
Address Set-Up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-Up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
AS
AH
7.5
8.0
8.5
11.0
CDV
DOH
ADS
ADH
WES
WEH
ADVS
ADVH
DS
2.0
2.0
0.5
2.0
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
BWS
BWS
, GW,BWE Set-Up Before CLK Rise 2.0
[1:0]
[1:0]
, GW,BWE Hold After CLK Rise
0.5
2.0
0.5
2.0
0.5
2.0
0.5
ADV Set-Up Before CLK Rise
ADV Hold After CLK Rise
Data Input Set-Up Before CLK Rise
Data Input Hold After CLK Rise
Chip Enable Set-Up
DH
CES
CEH
CHZ
CLZ
EOHZ
EOLZ
EOV
Chip Enable Hold After CLK Rise
[10, 11]
Clock to High-Z
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
[10, 11]
Clock to Low-Z
0
0
0
0
0
0
0
0
[10, 12]
OE HIGH to Output High-Z
[10, 12]
OE LOW to Output Low-Z
OE LOW to Output Valid
Notes:
8. Tested initially and after any design or process changes that may affect these parameters.
9. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC test loads.
10.
tCHZ, tCLZ, tEOHZ, and tEOLZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
11. At any given voltage and temperature, tCHZ (max) is less than tCLZ (min).
12. This parameter is sampled and not 100% tested.
9
CY7C1345
Timing Diagrams
[13, 14]
Write Cycle Timing
Single W rite
Burst W rite
Pipelined Write
t
Unselected
CH
t
CYC
CLK
t
ADH
t
ADS
t
ADSP ignored with CE inactive
CL
1
ADSP
t
ADH
t
ADSC initiated write
ADS
ADSC
ADV
t
t
ADVH
ADVS
t
ADV Must Be Inactive for ADSP Write
WD2
AS
WD3
WD1
ADD
GW
WE
t
AH
t
WH
t
WH
t
WS
t
WS
t
t
CES
CEH
CE masks ADSP
1
CE
1
t
t
CEH
CES
Unselected with CE
2
CE
CE
2
3
t
CES
t
CEH
OE
t
DH
t
DS
High-Z
High-Z
Data In
3a
2a
= UNDEFINED
2c
2d
1a
2b
= DON’T CARE
Notes:
13. WE is the combination of BWE, BW[3:0] and GW to define a write cycle (see Write Cycle Descriptions table).
14. WDx stands for Write Data to Address X.
10
CY7C1345
Timing Diagrams (continued)
[13, 15]
Read Cycle Timing
Burst Read
Single Read
Unselected
t
t
CYC
CH
Pipelined Read
CLK
t
t
ADH
ADS
t
ADSP ignored with CE inactive
CL
1
ADSP
t
ADS
ADSC initiated read
ADSC
ADV
t
ADVS
t
ADH
Suspend Burst
t
t
ADVH
AS
ADD
GW
WE
RD3
RD1
RD2
t
AH
t
WS
t
WS
t
WH
t
t
CES
CEH
t
WH
CE masks ADSP
1
CE
1
2
Unselected with CE
2
CE
t
t
CES
t
CEH
CE
3
t
CEH
CES
OE
t
EOV
t
OEHZ
t
DOH
t
CDV
3a
Data Out
2d
2a
2b
2c
1a
t
CLZ
t
CHZ
= DON’T CARE
= UNDEFINED
Note:
15. RDx stands for Read Data from Address X.
11
CY7C1345
Timing Diagrams (continued)
Read/Write Timing
t
t
t
CYC
CL
CH
CLK
t
AH
t
t
AS
A
D
B
C
ADD
t
ADH
ADS
ADSP
t
t
ADH
ADS
ADSC
ADV
t
t
ADVH
ADVS
t
CEH
t
CES
CE
CE
1
t
t
CEH
CES
t
t
WES
WEH
WE
OE
ADSP ignored
with CE HIGH
1
t
EOHZ
D(C)
t
t
CLZ
Data
D
(C+3)
Q
(B+3)
D
(C+1)
D
(C+2)
Q
(B+2)
Q
(B+1)
Q(B)
Q(B)
Q(A)
Q(D)
In/Out
CDV
t
DOH
t
CHZ
Device originally
deselected
WE is the combination of BWE, BWS
, and GW to define a write cycle (see Write Cycle Descriptions table).
[1:0]
CE is the combination of CE and CE . All chip selects need to be active in order to select
2
3
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
Qx stands for Data-out X.
= UNDEFINED
= DON’T CARE
12
CY7C1345
Timing Diagrams (continued)
Pipeline Timing
t
t
t
CYC
CL
CH
CLK
t
AS
WD1
WD2
WD3
WD4
RD1
RD2
RD3
RD4
ADD
t
t
ADS
ADH
ADSC initiated Reads
ADSC
ADSP initiated Reads
ADSP
ADV
t
t
CEH
CES
CE
1
CE
t
t
WEH
WES
WE
ADSP ignored
with CE HIGH
1
OE
t
CLZ
Data In/Out
1a
In
1a
2a
3a
4a
2a
In
3a
In
4a
Out Out Out Out
In
t
CDV
t
DOH
Back to Back Reads
t
CHZ
Back to Back Writes
= UNDEFINED
= DON’T CARE
13
CY7C1345
Timing Diagrams (continued)
OE Switching Waveforms
OE
t
EOV
t
EOHZ
three-state
I/Os
t
EOLZ
14
CY7C1345
Timing Diagrams (continued)
[16, 17]
ZZ Mode Timing
CLK
ADSP
HIGH
ADSC
CE
1
2
LOW
HIGH
CE
CE
3
ZZ
t
ZZS
I
CC
I
(active)
CC
t
ZZREC
I
CCZZ
I/Os
Three-state
Note:
16. Device must be deselected when entering ZZ mode. See Cycle Description Table for all possible signal conditions to deselect the device.
17. I/Os are in three-state when exiting ZZ sleep mode.
15
CY7C1345
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
117
100
90
Ordering Code
Package Type
100-Lead Thin Quad Flat Pack
100-Lead Thin Quad Flat Pack
100-Lead Thin Quad Flat Pack
100-Lead Thin Quad Flat Pack
CY7C1345–117AC
CY7C1345–100AC
CY7C1345–90AC
CY7C1345–50AC
A101
A101
A101
A101
Commercial
50
Document #: 38-00725-B
Package Diagram
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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