CY7C1381CV25-133BZC [CYPRESS]
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; 18兆位（ 512K ×36 / 1M ×18 ）流通型SRAM
| 型号： | CY7C1381CV25-133BZC |
| 厂家： | 
CYPRESS |
| 描述： | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
| 文件： | 总35页 (文件大小：501K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1381CV25
CY7C1383CV25
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
Features
Functional Description[1]
• Supports 133-MHz bus operations
• 512K X 36/1M X 18 common I/O
• 2.5V +/–5% core power supply (VDD
The CY7C1381CV25/CY7C1383CV25 is a 2.5V, 512K x 36
and 1M x 18 Synchronous Flow through SRAMs, respectively
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
)
• 2.5V I/O supply (VDDQ
)
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
— 7.5 ns (117-MHz version)
— 8.5 ns (100-MHz version)
addresses, all data inputs, address-pipelining Chip Enable
[2]
(
), depth-expansion Chip Enables (CE and
), Burst
CE3
CE1
2
Control inputs (
,
,
), Write Enables
(
ADV
BWx
and
,
• Provide high-performance 2-1-1-1 access rate
ADSC ADSP
), and Global Write (
BWE
). Asynchronous
GW
and
inputs
• User-selectable burst counter supporting Intel
(
)
and the ZZ pin
OE
.
include the Output Enable
Pentium interleaved or linear burst sequences
The CY7C1381CV25/CY7C1383CV25 allows either inter-
leaved or linear burst sequences, selected by the MODE input
pin. A HIGH selects an interleaved burst sequence, while a
LOW selects a linear burst sequence. Burst accesses can be
initiated with the Processor Address Strobe (ADSP) or the
cache Controller Address Strobe (ADSC) inputs. Address
advancement is controlled by the Address Advancement
(ADV) input.
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in JEDEC-standard 100-pin TQFP,119-ball BGA
and 165-ball fBGA packages
• JTAG boundary scan for BGA and fBGA packages
• “ZZ” Sleep Mode option
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (
) or
ADSP
Address Strobe Controller (
) are active. Subsequent
ADSC
burst addresses can be internally generated as controlled by
the Advance pin ( ).
ADV
The CY7C1381CV25/CY7C1383CV25 operates from a +2.5V
core power supply. All outputs also operate with a +2.5 supply.
All
inputs
and
outputs
are
JEDEC-standard
JESD8-5-compatible.
Selection Guide
133 MHz
117 MHz
7.5
100 MHz
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
6.5
210
70
8.5
175
70
190
70
Notes:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. CE CE are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.
3,
2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05241 Rev. *B
Revised April 19, 2004
CY7C1381CV25
CY7C1383CV25
1
Logic Block Diagram – CY7C1381CV25 (512K
ADDRESS
REGISTER
A0, A1, A
A[1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
AND LOGIC
Q0
CLR
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D, DQPD
DQ
BYTE
WRITE REGISTER
D, DQPD
BW
D
DQ
BYTE
WRITE REGISTER
C, DQPC
DQ
C, DQPC
BW
C
BYTE
OUTPUT
BUFFERS
DQs
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
DQP
DQP
DQP
A
DQ
B,
DQPB
B
C
DQB, DQPB
BYTE
BW
B
BYTE
WRITE REGISTER
DQPD
WRITE REGISTER
DQ
A, DQPA
BYTE
DQ
A, DQPA
BW
A
WRITE REGISTER
BYTE
BWE
WRITE REGISTER
INPUT
REGISTERS
GW
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
CONTROL
ZZ
2
Logic Block Diagram – CY7C1383CV25 (1M x 18)
ADDRESS
A0,A1,A
REGISTER
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
B,DQPB
DQ
B,DQPB
WRITE DRIVER
WRITE REGISTER
BW
B
A
MEMORY
ARRAY
OUTPUT
BUFFERS
DQs
DQP
DQP
SENSE
AMPS
A
B
DQ
A,DQPA
DQA,DQPA
WRITE REGISTER
WRITE DRIVER
BW
BWE
GW
INPUT
REGISTERS
ENABLE
REGISTER
CE
CE
CE
1
2
3
OE
SLEEP
CONTROL
ZZ
Document #: 38-05241 Rev. *B
Page 2 of 35
CY7C1381CV25
CY7C1383CV25
Pin Configurations
100-pin TQFP Pinout
DQPC
1
DQPB
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
DQB
NC
2
NC
DQC
3
DQB
NC
NC
3
VDDQ
VDDQ
VDDQ
4
4
5
VDDQ
VSSQ
NC
VSSQ
VSSQ
VSSQ
5
DQC
6
DQB
NC
6
DQC
7
DQB
NC
7
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
DQC
8
DQB
DQB
8
DQC
9
DQB
DQB
9
VSSQ
10
VSSQ
VSSQ
10
VDDQ
11
VDDQ
VDDQ
11
DQC
12
DQB
DQB
12
DQC
13
DQB
DQB
13
NC
14
VSS
NC
14
VDD
15
NC
VDD
CY7C1383CV25
(1M x 18)
15
CY7C1381CV25
(512K x 36)
NC
16
VDD
NC
16
VDD
ZZ
VSS
17
ZZ
VSS
17
DQD
18
DQA
DQB
18
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
DQD
19
DQA
DQB
19
VDDQ
20
VDDQ
VDDQ
20
VSSQ
21
VSSQ
VSSQ
21
DQD
22
DQA
DQB
22
DQD
23
DQA
DQB
23
DQD
24
DQA
DQPB
24
DQD
25
DQA
NC
25
NC
VSSQ
26
VSSQ
VSSQ
26
VSSQ
VDDQ
NC
VDDQ
27
VDDQ
VDDQ
27
DQD
28
DQA
NC
28
DQD
29
DQA
NC
29
NC
DQPD
30
DQPA
NC
NC
30
Document #: 38-05241 Rev. *B
Page 3 of 35
CY7C1381CV25
CY7C1383CV25
Pin Configurations (continued)
119-ball BGA (1 Chip Enable with JTAG)
CY7C1381CV25 (512K x 36)
1
2
3
4
5
6
7
VDDQ
A
A
A
A
VDDQ
A
ADSP
B
C
NC
NC
A
A
A
A
A
A
A
A
NC
NC
ADSC
VDD
DQC
DQC
VDDQ
DQPC
DQC
DQC
VSS
VSS
VSS
NC
CE1
OE
VSS
VSS
VSS
DQPB
DQB
DQB
DQB
DQB
VDDQ
D
E
F
DQC
DQC
VDDQ
DQD
DQD
VDDQ
DQD
DQC
DQC
VDD
DQB
DQB
VDD
DQA
DQA
DQA
DQA
DQB
DQB
VDDQ
DQA
DQA
VDDQ
DQA
G
H
J
BWC
VSS
NC
ADV
GW
VDD
CLK
NC
BWE
A1
BWB
VSS
NC
DQD
VSS
VSS
K
L
M
N
DQD
DQD
DQD
BWD
VSS
VSS
BWA
VSS
VSS
P
R
DQD
NC
DQPD
A
VSS
MODE
A0
VDD
VSS
NC
DQPA
A
DQA
NC
T
U
NC
VDDQ
NC
TMS
A
TDI
A
TCK
A
TDO
NC
NC
ZZ
VDDQ
CY7C1383CV25 (1M x 18)
2
A
A
1
3
A
A
4
5
A
A
A
VSS
VSS
VSS
VSS
VSS
6
A
7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
VDDQ
NC
NC
DQB
NC
VDDQ
NC
DQB
VDDQ
VDDQ
NC
NC
NC
DQA
VDDQ
DQA
NC
VDDQ
ADSP
ADSC
VDD
A
A
DQPA
NC
A
A
NC
DQB
NC
DQB
NC
VDD
VSS
VSS
VSS
BWB
VSS
NC
NC
CE1
OE
ADV
DQA
NC
DQA
VDD
NC
DQA
NC
GW
VDD
NC
VSS
NC
DQB
VSS
CLK
NC
BWE
A1
DQA
DQB
VDDQ
DQB
NC
NC
DQB
NC
VSS
VSS
VSS
VSS
NC
VDDQ
NC
BWA
VSS
VSS
VSS
DQA
NC
DQPB
A0
DQA
R
T
NC
NC
A
A
MODE
A
VDD
NC
NC
A
A
A
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Document #: 38-05241 Rev. *B
Page 4 of 35
CY7C1381CV25
CY7C1383CV25
Pin Configurations (continued)
165-ball fBGA (3 Chip Enable)
CY7C1381CV25 (512K x 36)
1
NC / 288M
NC
DQPC
DQC
2
A
A
NC
DQC
DQC
DQC
DQC
VSS
3
4
5
6
7
8
9
10
11
NC
NC / 144M
DQPB
DQB
CE1
BWC
BWB
CE3
BWE
GW
VSS
VSS
VSS
ADSC
ADV
A
A
B
C
D
E
F
G
H
J
K
L
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
BWD
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
BWA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
A
NC
DQB
DQB
DQB
DQB
NC
DQA
DQA
DQA
DQC
DQB
DQC
DQC
NC
DQD
DQD
DQD
VSS
VSS
VSS
VSS
VSS
VSS
DQB
DQB
ZZ
DQA
DQA
DQA
DQD
DQD
DQD
DQD
DQPD
NC
DQD
NC
NC / 72M
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
TDI
VSS
A
A1
VSS
NC
TDO
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
A0
MODE NC / 36M
A
A
TMS
TCK
A
A
A
A
R
CY7C1383CV25 (1M x 18)
1
NC / 288M
NC
2
3
4
5
6
7
8
9
10
11
A
A
CE1
BWB
NC
CE
BWE
GW
VSS
VSS
ADSC
ADV
A
A
3
A
NC
DQB
DQB
DQB
DQB
VSS
NC
NC
NC
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
BWA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
A
NC
NC
NC
NC
NC
NC / 144M
DQPA
DQA
B
C
D
E
F
G
H
J
K
L
NC
NC
NC
NC
NC
VSS
DQB
DQB
DQB
VSS
DQA
VSS
VSS
VSS
VSS
VSS
VSS
DQA
DQA
ZZ
NC
NC
NC
DQA
DQA
DQA
NC
DQB
DQPB
NC
NC
NC
NC / 72M
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
TDI
VSS
A
A1
VSS
NC
TDO
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
A
M
N
P
MODE NC / 36M
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05241 Rev. *B
Page 5 of 35
CY7C1381CV25
CY7C1383CV25
CY7C1381CV25–Pin Definitions
TQFP
(3-Chip
Enable)
BGA
fBGA
(3-Chip
Enable)
(1-Chip
Enable)
Name
I/O
Description
A0, A1, A
37,36,32,33,34, P4,N4,A2,B2,C2 R6,P6,A2,A10,
Input-
Address Inputs used to select one of the
35,42,43,44,45, ,R2,A3,B3,C3,T B2,B10,N6,P3, Synchronous 512K address locations. Sampled at the
46,47,48,49,50, 3,T4,A5,B5,C5, P4,P8,P9,P10,
81,82,99,100 T5,A6,B6,C6,R6 P11,R3,R4,R8,
R9,R10,R11
rising edge of the CLK if ADSP or ADSC is
active LOW, and CE1, CE2, and CE3[2] are
sampled active. A[1:0] feed the 2-bit counter.
93,94,95,96
88
L5,G5,G3,L3
H4
B5,A5,A4,B4
B7
Input-
Byte Write Select Inputs, active LOW.
BWA,BWB
BWC,BWD
Synchronous Qualified with BWE to conduct byte writes to
the SRAM. Sampled on the rising edge of
CLK.
Input-
Global Write Enable Input, active LOW.
GW
Synchronous When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes
are written, regardless of the values on
BW[A:D]and BWE).
CLK
CE1
CE2
89
98
K4
E4
B6
A3
Input-
Clock
Clock Input. Used to capture all
synchronous inputs to the device. Also used
to increment the burst counter when ADV is
asserted LOW, during a burst operation.
Input-
Chip Enable 1 Input, active LOW. Sampled
Synchronous on the rising edge of CLK. Used in
conjunction with CE2 and CE3[2] to
select/deselect the device. ADSP is ignored
if CE1 is HIGH.
97
92
86
-
-
B3
A6
B8
Input-
Chip Enable 2 Input, active HIGH.
Synchronous Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3[2] to
select/deselect the device.
[2]
Input-
Chip Enable 3 Input, active LOW. Sampled
CE3
Synchronous on the rising edge of CLK. Used
in
conjunction with CE1 and CE2 to
select/deselect the device.
F4
Input-
Output Enable, asynchronous input,
OE
Asynchronous active LOW. Controls the direction of the I/O
pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins
are tri-stated, and act as input data pins. OE
is masked during the first clock of a read
cycle when emerging from a deselected
state.
83
84
G4
A4
A9
B9
Input-
Advance Input signal, sampled on the
ADV
Synchronous rising edge of CLK. When asserted, it
automatically increments the address in a
burst cycle.
Input-
Address Strobe from Processor, sampled
ADSP
Synchronous on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented
to the device are captured in the address
registers. A[1:0] are also loaded into the burst
counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is
ignored when
CE1 is deasserted HIGH
Document #: 38-05241 Rev. *B
Page 6 of 35
CY7C1381CV25
CY7C1383CV25
CY7C1381CV25–Pin Definitions (continued)
TQFP
(3-Chip
Enable)
BGA
fBGA
(3-Chip
Enable)
(1-Chip
Enable)
Name
ADSC
I/O
Description
85
B4
A8
Input-
Address Strobe from Controller, sampled
Synchronous on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented
to the device are captured in the address
registers. A[1:0] are also loaded into the burst
counter. When ADSP and ADSC are both
.
asserted, only ADSP is recognized
87
64
M4
T7
A7
Input-
Byte Write Enable Input, active LOW.
BWE
ZZ
Synchronous Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a
byte write.
H11
Input-
ZZ “sleep” Input, active HIGH. When
Asynchronous asserted HIGH places the device in a
non-time-critical “sleep” condition with data
integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin
has an internal pull-down.
52,53,56,57,58, K6,L6,M6,N6,K7 M11,L11,K11,
I/O-
Bidirectional Data I/O lines. As inputs, they
DQs
59,62,63,68,69, ,L7,N7,P7,E6,F
J11,J10,K10,
Synchronous feed into an on-chip data register that is
triggered by the rising edge of CLK. As
outputs, they deliver the data contained in
the memory location specified by the
72,73,74,75,78, 6,G6,H6,D7,E7, L10,M10,D10,
79,2,3,6,7,8,9, G7,H7,D1,E1,G E10,F10,G10,
12,13,18,19,22, 1,H1,E2,F2,G2, D11,E11,F11,
23,24,25,28,29 H2,K1,L1,N1,P1
,K2,L2,M2,N2
G11,D1,E1,
F1,G1,D2,E2,
F2,G2,J1,K1,
L1,M1,J2,
addresses presented during the previous
clock rise of the read cycle. The direction of
the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP[A:D] are placed
K2,L2,M2,
The outputs are
in a tri-state condition.
automatically tri-stated during the data
portion of a write sequence, during the first
clock when emerging from a deselected
state, and when the device is deselected,
regardless of the state of OE.
51,80,1,30
31
P6,D6,D2,P2 N11,C11,C1,N1
I/O-
Bidirectional Data Parity I/O Lines.
DQP[A:D]
MODE
Synchronous Functionally, these signals are identical to
DQs. During write sequences, DQP[A:D] is
controlled by BW[A:D] correspondingly.
R3
R1
Input-Static Selects Burst Order. When tied to GND
selects linear burst sequence. When tied to
VDD or left floating selects interleaved burst
sequence. This is a strap pin and should
remain static during device operation. Mode
Pin has an internal pull-up.
VDD
15,41,65,91
J2,C4,J4,R4,J6
D4,D8,E4,
E8,F4,F8,
G4,G8,H4,
H8,J4,J8,
K4,K8,L4,
L8,M4,M8
Power Supply Power supply inputs to the core of the
device.
Document #: 38-05241 Rev. *B
Page 7 of 35
CY7C1381CV25
CY7C1383CV25
CY7C1381CV25–Pin Definitions (continued)
TQFP
(3-Chip
Enable)
BGA
fBGA
(3-Chip
Enable)
(1-Chip
Enable)
Name
VDDQ
I/O
Description
4,11,20,27,
54,61,70,77
A1,F1,J1,M1,U1
C3,C9,D3,
D9,E3,E9,
F3,F9,G3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,
N3,N9
I/O Power
Supply
Power supply for the I/O circuitry.
,
A7,F7,J7,M7,U7
VSS
17,40,67,90 H2,D3,E3,F3,H3
C4,C5,C6,
C7,C8,D5,
Ground
Ground for the core of the device.
,K3,
M3,N3,
D6,D7,E5,
P3,D5,E5,F5,H5
,K5,
E6,E7,F5,
F6,F7,G5,
M5,N5,P5
G6,G7,H5,
H6,H7,J5,
J6,J7,K5,K6,K7,
L5,L6,L7,M5,M6
,M7,N4,N8
VSSQ
TDO
5,10,21,26,
55,60,71,76
-
-
I/O Ground Ground for the I/O circuitry.
-
U5
P7
JTAG serial Serial data-out to the JTAG circuit.
output
Delivers data on the negative edge of TCK.
Synchronous If the JTAG feature is not being utilized, this
pin should be left unconnected. This pin is
not available on TQFP packages.
TDI
-
U3
U2
P5
R5
JTAG serial Serial data-In to the JTAG circuit. Sampled
input
ontherisingedgeofTCK. IftheJTAGfeature
Synchronous is not being utilized, this pin can be left
floating or connected to VDD through a pull
up resistor. This pin is not available on TQFP
packages.
TMS
-
JTAG serial Serial data-In to the JTAG circuit. Sampled
input
ontherisingedgeofTCK. IftheJTAGfeature
Synchronous is not being utilized, this pin can be discon-
nected or connected to VDD. This pin is not
available on TQFP packages.
TCK
NC
-
U4
R7
JTAG-Clock Clock input to the JTAG circuitry. If the
JTAG feature is not being utilized, this pin
must be connected to VSS. This pin is not
available on TQFP packages.
16,38,39,66
B1,C1,R1,T1,T2
A1,A11,B1,
-
No Connects. Not internally connected to
the die. 18M, 36M, 72M, 144M and 288M are
address expansion pins are not internally
connected to the die.
,J3,D4,L4,J5,R5 B11,C2,C10,H1,
,T6,U6,B7,C7,R
7
H3,H9,
H10,N2,N5,N7,
N10,P1,P2,R2
VSS/DNU
14
-
-
Ground/DNU This pin can be connected to Ground or
should be left floating.
Document #: 38-05241 Rev. *B
Page 8 of 35
CY7C1381CV25
CY7C1383CV25
CY7C1383CV25:Pin Definitions
TQFP
(3-Chip
Enable)
BGA
fBGA
(3-Chip
Enable)
(1-Chip
Enable)
Name
I/O
Description
A0, A1, A
37,36,32,33,34, P4,N4,A2,B2,
35,42,43,44,45, C2,R2,T2,A3,
46,47,48,49,50, B3,C3,T3,A5,
80,81,82,99,100 B5,C5,T5,A6,
B6,C6,R6,T6
R6,P6,A2,
A10,A11,B2,
B10,N6,P3,P4,
P8,P9,P10,
Input-
Address Inputs used to select one of the
Synchronous 1M address locations. Sampled at the ris-
ing edge of the CLK if ADSP or ADSC is
active LOW, and CE1, CE2, and CE3[2] are
sampled active. A[1:0] feed the 2-bit counter.
P11,R3,R4,
R8,R9,R10,R11
93,94
L5,G3
B5,A4
Input-
Byte Write Select Inputs, active LOW.
BWA,BWB
GW
Synchronous Qualified with BWE to conduct byte writes
to the SRAM. Sampled on the rising edge of
CLK.
88
H4
B7
Input-
Global Write Enable Input, active LOW.
Synchronous When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes
are written, regardless of the values on
BW[A:B] and BWE).
87
89
98
M4
K4
E4
A7
B6
A3
Input-
Byte Write Enable Input, active LOW.
BWE
CLK
Synchronous Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a
byte write.
Input-
Clock
Clock Input. Used to capture all
synchronous inputs to the device. Also used
to increment the burst counter when ADV is
asserted LOW, during a burst operation.
Input-
Chip Enable 1 Input, active LOW.
CE1
CE2
Synchronous Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3[2] to
select/deselect the device. ADSP is ignored
if CE1 is HIGH.
97
92
86
-
-
B3
A6
B8
Input-
Chip Enable 2 Input, active HIGH.
Synchronous Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3[2] to
select/deselect the device.
[2]
Input-
Chip Enable 3 Input, active LOW.
CE3
Synchronous Sampled on the rising edge of CLK.
Used in
conjunction with CE1 and CE2 to
select/deselect the device.
F4
Input-
Output Enable, asynchronous input,
OE
Asynchronous active LOW. Controls the direction of the
I/O pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins
are tri-stated, and act as input data pins. OE
is masked during the first clock of a read
cycle when emerging from a deselected
state.
83
G4
A9
Input-
Advance Input signal, sampled on the
ADV
Synchronous rising edge of CLK. When asserted, it
automatically increments the address in a
burst cycle.
Document #: 38-05241 Rev. *B
Page 9 of 35
CY7C1381CV25
CY7C1383CV25
CY7C1383CV25:Pin Definitions (continued)
TQFP
(3-Chip
Enable)
BGA
fBGA
(3-Chip
Enable)
(1-Chip
Enable)
Name
ADSP
I/O
Description
84
A4
B9
Input-
Address Strobe from Processor,
Synchronous sampled on the rising edge of CLK,
active LOW. When asserted LOW,
addresses presented to the device are
captured in the address registers. A[1:0] are
also loaded into the burst counter. When
ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when
CE1 is deasserted HIGH
85
64
B4
T7
A8
Input-
Address Strobe from Controller,
ADSC
Synchronous sampled on the rising edge of CLK,
active LOW. When asserted LOW,
addresses presented to the device are
captured in the address registers. A[1:0] are
also loaded into the burst counter. When
and ADSC are both asserted, only
ADSP
.
ADSP is recognized
ZZ
H11
Input-
ZZ “sleep” Input, active HIGH. When
Asynchronous asserted HIGH places the device in a
non-time-critical “sleep” condition with data
integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin
has an internal pull-down.
58,59,62,63,68, P7,K7,G7,E7,F6
69,72,73,8,9,12, ,H6,L6,N6,D1,H
J10,K10,
L10,M10,
D11,E11,
F11,G11,J1,K1,
L1,M1,
I/O-
Bidirectional Data I/O lines. As inputs,
DQs
Synchronous they feed into an on-chip data register that
is triggered by the rising edge of CLK. As
outputs, they deliver the data contained in
the memory location specified by the
13,
1,L1,N1,E2,G2,
K2,M2
18,19,22,23
D2,E2,F2,
G2
addresses presented during the previous
clock rise of the read cycle. The direction of
the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP[A:B] are placed
The outputs are
in a tri-state condition.
automatically tri-stated during the data
portion of a write sequence, during the first
clock when emerging from a deselected
state, and when the device is deselected,
regardless of the state of OE.
74,24
31
D6,P2
R3
C11,N1
R1
I/O-
Bidirectional Data Parity I/O Lines.
DQP[A:B]
MODE
Synchronous Functionally, these signals are identical to
DQs. During write sequences, DQP[A:B] is
controlled by BW[A:B] correspondingly.
Input-Static
Selects Burst Order. When tied to GND
selects linear burst sequence. When tied to
VDD or left floating selects interleaved burst
sequence. This is a strap pin and should
remain static during device operation. Mode
Pin has an internal pull-up.
Document #: 38-05241 Rev. *B
Page 10 of 35
CY7C1381CV25
CY7C1383CV25
CY7C1383CV25:Pin Definitions (continued)
TQFP
(3-Chip
Enable)
BGA
fBGA
(3-Chip
Enable)
(1-Chip
Enable)
Name
VDD
I/O
Description
15,41,65,91
C4,J2,J4,J6,R4
D4,D8,E4,
E8,F4,F8,
G4,G8,
Power Supply Power supply inputs to the core of the
device.
H4,H8,J4,
J8,K4,K8,
L4,L8,M4,
M8
VDDQ
4,11,20,27,
54,61,70,77
A1,A7,F1,F7,J1,
J7,M1,M7,U1,U
7
C3,C9,D3,
D9,E3,E9,
F3,F9,G3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,
N3,N9
I/O Power
Supply
Power supply for the I/O circuitry.
Ground for the core of the device.
VSS
17,40,67,90
D3,D5,E3,E5,F3
,F5,G5,H3,
H5,K3,K5,L3,M3
,
C4,C5,C6,
C7,C8,D5,
D6,D7,E5,
E6,E7,F5,
F6,F7,G5,
G6,G7,H1,
H2,H5,H6,
H7,J5,J6,J7,K5,
K6,K7,L5,L6,L7,
M5,
Ground
M5,N3,
N5,P3,P5
M6,M7,N4,
N8
VSSQ
TDO
5,10,21,26,
-
-
I/O Ground
Ground for the I/O circuitry.
55,60,71,76,
-
U5
P7
JTAG serial Serial data-out to the JTAG circuit.
output
Delivers data on the negative edge of TCK.
Synchronous If the JTAG feature is not being utilized, this
pin should be left unconnected. This pin is
not available on TQFP packages.
TDI
-
U3
P5
JTAG serial Serial data-In to the JTAG circuit.
input
Sampled on the rising edge of TCK. If the
Synchronous JTAG feature is not being utilized, this pin
can be left floating or connected to VDD
through a pull up resistor. This pin is not
available on TQFP packages.
TMS
TCK
-
-
U2
U4
R5
R7
JTAG serial Serial data-In to the JTAG circuit.
input
Sampled on the rising edge of TCK. If the
Synchronous JTAG feature is not being utilized, this pin
can be disconnected or connected to VDD
.
This pin is not available on TQFP packages.
JTAG-Clock Clock input to the JTAG circuitry. If the
JTAG feature is not being utilized, this pin
must be connected to VSS. This pin is not
available on TQFP packages.
Document #: 38-05241 Rev. *B
Page 11 of 35
CY7C1381CV25
CY7C1383CV25
CY7C1383CV25:Pin Definitions (continued)
TQFP
(3-Chip
Enable)
BGA
fBGA
(3-Chip
Enable)
(1-Chip
Enable)
Name
NC
I/O
Description
1,2,3,6,7,16,25, B1,B7,C1,C7,D
A1,A5,B1,
-
No Connects. Not internally connected to
the die. 36M, 72M, 144M and 288M are
address expansion pins are not internally
connected to the die.
28,29,30,38,39, 2,D4,D7,E1,E6, B4,B11,C1,C2,C
51,52,53,56,57, H2,F2,G1,G6,H 10,D1,D10,E1,E
66,75,78,79,95, 7,J3,J5,K1,K6,L 10,F1,F10,G1,G
96
14
4,L2,L7,M6,N2, 10,H3,H9,H10,J
N7,L7,P1,P6,R1 2,J11,K2,K11,
,R5,R7,T1,T4,U L2,L11,M2,M11,
6
N2,N5,N7,N10,
N11,P1,P2,R2
VSS/DNU
-
-
Ground/DNU This pin can be connected to Ground or
should be left floating.
Document #: 38-05241 Rev. *B
Page 12 of 35
CY7C1381CV25
CY7C1383CV25
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active LOW.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (tCDV) is 6.5 ns (133-MHz device).
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ[A:D] will be
written into the specified address location. Byte writes are
allowed. All I/Os are tri-stated when a write is detected, even
a byte write. Since this is a common I/O device, the
asynchronous OE input signal must be deasserted and the
I/Os must be tri-stated prior to the presentation of data to DQs.
As a safety precaution, the data lines are tri-stated once a write
The CY7C1381CV25 supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium® and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
cycle is detected, regardless
of the state of OE.
Burst Sequences
The CY7C1381CV25 provides an on-chip two-bit wraparound
burst counter inside the SRAM. The burst counter is fed by
A
[1:0], and can follow either a linear or interleaved burst order.
The burst order is determined by the state of the MODE input.
A LOW on MODE will select a linear burst sequence. A HIGH
on MODE will select an interleaved burst order. Leaving
MODE unconnected will cause the device to default to a inter-
leaved burst sequence.
Byte write operations are qualified with the Byte Write Enable
X
(BWE) and Byte Write Select (BW ) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Interleaved Burst Address Table
Three synchronous Chip Selects (CE1, CE2, CE3[2]) and an
(MODE = Floating or VDD
)
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if
is HIGH.
CE1
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Address
A1: A0
Single Read Accesses
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
A single read access is initiated when the following conditions
[2]
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to tCDV after clock
Linear Burst Address Table
(MODE = GND)
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
rise. ADSP is ignored if CE1 is HIGH.
Address
A1: A0
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
CE1, CE2, CE3[2] are all asserted
satisfied at clock rise: (1)
ADSP is asserted LOW. The addresses
active, and (2)
presented are loaded into the address register and the burst
inputs (
GW, BWE, and BWX)are ignored during this first clock
cycle. If the write inputs are asserted active ( see Write Cycle
Descriptions table for appropriate states that indicate a write)
on the next clock rise,the appropriate data will be latched and
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
All I/Os are
written into the device.Byte writes are allowed.
tri-stated during a byte write.Since this is a common I/O
device, the asynchronous
OE input signal must be deasserted
and the I/Os must be tri-stated prior to the presentation of data
to DQs. As a safety precaution, the data lines are tri-stated
once a write cycle is detected, regardless of the state of OE.
“sleep” mode. CE , CE , CE [2], ADSP, and ADSC must
the
1
2
3
Single Write Accesses Initiated by ADSC
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3[2] are all asserted
Document #: 38-05241 Rev. *B
Page 13 of 35
CY7C1381CV25
CY7C1383CV25
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
Description
Snooze mode standby current
Device operation to ZZ
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
Min.
Max.
60
2tCYC
Unit
mA
ns
tZZREC
tZZI
tRZZI
ZZ recovery time
ZZ active to snooze current
ZZ Inactive to exit snooze current
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
2tCYC
0
ns
ns
ns
2tCYC
Truth Table[ 3, 4, 5, 6, 7]
ADDRESS
Used
Cycle Description
CE1 CE2 CE3 ZZ
ADSP
ADSC ADV WRITE OE CLK
DQ
Deselected Cycle,
None
None
None
None
None
None
H
X
X
X
H
X
X
X
L
L
L
L
L
H
X
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
L
L
L
L
L
X
L
L
H
H
X
X
X
X
X
L
Snooze Mode, Pow-
er-down
X
X
Tri-State
Q
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
External
External
External
External
External
Next
Next
Next
Next
Next
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
L-H
L-H Tri-State
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H
L-H
D
Q
L-H Tri-State
L-H
L-H Tri-State
L-H
L-H Tri-State
Q
Q
L-H
L-H
L-H
D
D
Q
Next
Current
Current
Current
Current
Current
Current
L-H Tri-State
L-H
L-H Tri-State
Q
L-H
L-H
D
D
Write Cycle, Suspend Burst
L
Notes:
3. X=”Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the signal. is asynchronous and is not sampled with the clock.
OE
OE
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks
X
after the
or with the assertion of
. As a result,
must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state.
OE
is a
ADSC
OE
ADSP
don't care for the remainder of the write cycle.
7.
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when
OE
is
OE
inactive or when the device is deselected, and all data bits behave as output when
is active (LOW).
OE
3
Document #: 38-05241 Rev. *B
Page 14 of 35
CY7C1381CV25
CY7C1383CV25
Partial Truth Table for Read/Write[3, 8]
Function (CY7C1381CV25)
BWD
X
BWC
X
BWB
X
BWA
X
GW
H
BWE
H
Read
Read
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
L
H
L
H
L
H
L
H
L
Write Byte A (DQA, DQPA)
Write Byte B(DQB, DQPB)
Write Bytes A, B (DQA, DQB, DQPA, DQPB)
Write Byte C (DQC, DQPC)
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
Write Bytes C, B (DQC, DQB, DQPC, DQPB)
L
H
H
L
Write Bytes C, B, A (DQC, DQB, DQA, DQPC,
L
DQPB, DQPA)
Write Byte D (DQD, DQPD)
Write Bytes D, A (DQD, DQA, DQPD, DQPA)
Write Bytes D, B (DQD, DQA, DQPD, DQPA)
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
H
L
H
L
Write Bytes D, B, A (DQD, DQB, DQA, DQPD,
L
DQPB, DQPA)
Write Bytes D, B (DQD, DQB, DQPD, DQPB)
H
H
L
L
L
L
L
L
H
H
H
L
Write Bytes D, B, A (DQD, DQC, DQA, DQPD,
DQPC, DQPA)
Write Bytes D, C, A (DQD, DQB, DQA, DQPD,
DQPB, DQPA)
H
L
L
L
L
H
Write All Bytes
Write All Bytes
H
L
L
X
L
X
L
X
L
X
L
X
Note:
8. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid Appropriate write will be done based on which byte write is active.
X
Truth Table for Read/Write[3]
Function (CY7C1383CV25)
BWB
X
BWA
X
BWE
H
GW
Read
Read
H
H
H
H
H
L
L
L
L
L
X
H
H
L
L
X
H
L
H
L
Write Byte A - (DQA and DQPA)
Write Byte B - (DQB and DQPB)
Write All Bytes
Write All Bytes
X
Document #: 38-05241 Rev. *B
Page 15 of 35
CY7C1381CV25
CY7C1383CV25
Test MODE SELECT (TMS)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
The CY7C1381CV25 incorporates a serial boundary scan test
access port (TAP). This port operates in accordance with IEEE
Standard 1149.1-1990 but does not have the set of functions
required for full 1149.1 compliance. These functions from the
IEEE specification are excluded because their inclusion
places an added delay in the critical speed path of the SRAM.
Note that the TAP controller functions in a manner that does
not conflict with the operation of other devices using 1149.1
fully compliant TAPs. The TAP operates using
JEDEC-standard 2.5V I/O logic levels.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see Figure . TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most signif-
icant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
The CY7C1381CV25 contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID
register.
Disabling the JTAG Feature
Test Data-Out (TDO)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alter-
nately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
TAP Controller State Diagram
0
Bypass Register
TEST-LOGIC
1
RESET
0
2
1
0
0
0
1
1
1
Selection
Circuitry
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
Instruction Register
31 30 29
Identification Register
0
Selection
TDI
TDO
Circuitr
y
0
0
.
.
. 2 1
1
1
CAPTURE-DR
CAPTURE-IR
0
0
x
.
.
.
.
. 2 1
SHIFT-DR
0
SHIFT-IR
0
Boundary Scan Register
1
1
1
1
EXIT1-DR
EXIT1-IR
TCK
TMS
0
0
TAP CONTROLLER
PAUSE-DR
0
PAUSE-IR
0
1
1
0
0
EXIT2-DR
1
EXIT2-IR
1
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
UPDATE-DR
UPDATE-IR
1
0
1
0
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
TAP Registers
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Document #: 38-05241 Rev. *B
Page 16 of 35
CY7C1381CV25
CY7C1383CV25
Instruction Register
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
IDCODE
Boundary Scan Register
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The x36 configuration has a
70-bit-long register and the x18 configuration has a 51-bit long
register.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the device TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls
is captured in the boundary scan register.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus
hold time (tCS plus tCH).
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
Document #: 38-05241 Rev. *B
Page 17 of 35
CY7C1381CV25
CY7C1383CV25
possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the
same effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the operating Range[9, 10]
Parameter
Symbol
Min.
Max
Units
Clock
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
Output Times
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
Setup Times
tTCYC
tTF
tTH
100
ns
MHz
ns
10
20
40
40
tTL
ns
tTDOV
tTDOX
ns
ns
0
TMS Set-Up to TCK Clock Rise
TDI Set-Up to TCK Clock Rise
Capture Set-Up to TCK Rise
Hold Times
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
tTMSS
tTDIS
tCS
10
10
10
ns
ns
tTMSH
tTDIH
tCH
10
10
10
ns
ns
ns
Capture Hold after Clock Rise
Notes:
t
t
9. CS and CH refer to the setup and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC test Conditions. T. /t = 1ns
R
F
Document #: 38-05241 Rev. *B
Page 18 of 35
CY7C1381CV25
CY7C1383CV25
2.5V TAP AC Test Conditions
2.5V TAP AC Output Load Equivalent
1.25V
Input pulse levels ...... ........................................VSS to 2.5V
Input rise and fall time...................................................... 1ns
Input timing reference levels.........................................1.25V
Output reference levels.................................................1.25V
Test load termination supply voltage.............................1.25V
50Ω
TDO
ZO= 50Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; Vdd = 2.5V ±0.125V unless otherwise noted)[11]
PARAMETER
VOH1
DESCRIPTION
TEST CONDITIONS
MIN
2.0
MAX
UNITS
V
V
Output HIGH Voltage IOH = -1.0 mA, VDDQ = 2.5V
Output HIGH Voltage IOH = -100 µA,VDDQ = 2.5V
Output LOW Voltage IOL = 8.0 mA, VDDQ = 2.5V
2.1
VOH2
0.4
0.2
V
VOL1
VDDQ = 2.5V
V
VOL2
Output LOW Voltage IOL = 100 µA
Input HIGH Voltage
V
DDQ = 2.5V
DDQ = 2.5V
1.7
-0.3
-5
VDD + 0.3
V
VIH
V
0.7
5
V
VIL
Input LOW Voltage
µA
IX
Input Load Current
GND < VIN < VDDQ
Note:
11. All voltages referenced to VSS (GND).
Identification Register Definitions
CY7C1381CV25
CY7C1383CV25
(1MX18)
DESCRIPTION
INSTRUCTION FIELD
(512KX36)
010
010
01011
Revision Number (31:29)
Device Depth (28:24)
Describes the version number.
Reserved for Internal Use
01011
000001
100101
00000110100
000001
010101
00000110100
Device Width (23:18)
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
Defines memory type and architecture
Defines width and density
Allows unique identification of SRAM
vendor.
1
1
ID Register Presence Indicator (0)
Indicates the presence of an ID register.
Scan Register Sizes
BIT SIZE(X36)
REGISTER NAME
BIT SIZE(X18)
Instruction
Bypass
3
3
Bypass
1
1
ID
32
72
32
72
Boundary Scan Order
Document #: 38-05241 Rev. *B
Page 19 of 35
CY7C1381CV25
CY7C1383CV25
Identification Codes
INSTRUCTION
CODE
DESCRIPTION
000
EXTEST
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
001
010
IDCODE
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
SAMPLE Z
011
100
RESERVED
SAMPLE/PRELOAD
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
101
110
111
RESERVED
RESERVED
BYPASS
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
119-Ball BGA Boundary Scan Order
CY7C1381CV25 (512K x 36)
BIT#
1
BALL ID
BIT#
BALL ID
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
B2
K4
H4
M4
F4
B4
A4
G4
C6
A6
D6
D7
E6
G6
H7
E7
F6
G7
H6
T7
K7
L6
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
P4
N4
R6
T5
T3
R2
R3
P2
P1
N2
L2
K1
N1
M2
L1
K2
Not Bonded (Preset to 0)
H1
G2
E2
D1
H2
G1
F2
E1
D2
A5
N6
P7
K6
L7
M6
N7
P6
Document #: 38-05241 Rev. *B
Page 20 of 35
CY7C1381CV25
CY7C1383CV25
119-Ball BGA Boundary Scan Order (continued)
29
30
31
32
33
34
35
36
B5
B3
C5
C3
C2
A2
T4
B6
65
66
67
68
69
70
71
72
A3
E4
Internal
L3
G3
G5
L5
Internal
CY7C1383CV25 (1M x 18)
BIT#
1
2
3
4
5
6
7
8
BALL ID
BIT#
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
BALL ID
B2
P4
N4
R6
T5
T3
R2
R3
K4
H4
M4
F4
B4
A4
G4
C6
9
A6
T6
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
P2
N1
M2
L1
K2
Internal
H1
G2
D6
E7
F6
G7
H6
T7
K7
L6
E2
D1
N6
P7
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
A5
A3
E4
Internal
B5
B3
C5
C3
C2
A2
T2
B6
Not Bonded (Preset to 0)
Internal
G3
L5
Internal
Document #: 38-05241 Rev. *B
Page 21 of 35
CY7C1381CV25
CY7C1383CV25
165-Ball fBGA Boundary Scan Order
CY7C1381CV25 (512K x 36)
BIT#
1
BALL ID
B6
BIT#
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
BALL ID
N6
R6
P6
R4
R3
P4
P3
R1
N1
L2
K2
J2
M2
M1
L1
K1
2
3
4
5
6
7
8
9
B7
A7
B8
A8
B9
A9
B10
A10
C11
E10
F10
G10
D10
D11
E11
F11
G11
H11
J10
K10
L10
M10
J11
K11
L11
M11
N11
R11
R10
R9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
J1
Not Bonded (Preset to 0)
G2
F2
E2
D2
G1
F1
E1
D1
C1
A2
B2
A3
B3
B4
A4
A5
B5
A6
R8
P10
P9
P8
P11
Document #: 38-05241 Rev. *B
Page 22 of 35
CY7C1381CV25
CY7C1383CV25
165-Ball fBGA Boundary Scan Order (continued)
CY7C1383CV25 (1M x 18)
BIT#
1
2
3
4
5
6
7
8
BALL ID
BIT#
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
BALL ID
B6
B7
A7
B8
A8
B9
A9
B10
N6
R6
P6
R4
R3
P4
P3
R1
9
A10
A11
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
10
11
12
13
14
15
16
17
18
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
N1
M1
L1
K1
C11
D11
E11
F11
G11
J1
Not Bonded (Preset to 0)
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
H11
J10
K10
L10
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
G2
F2
E2
D2
M10
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
A2
B2
A3
B3
R11
R10
R9
R8
P10
P9
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
A4
B5
A6
P8
P11
Document #: 38-05241 Rev. *B
Page 23 of 35
CY7C1381CV25
CY7C1383CV25
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(Above which the useful life may be impaired. For user guide-
(per MIL-STD-883, Method 3015)
lines, not tested.)
Latch-up Current..................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND........ –0.3V to +4.6V
Ambient
Range
Temperature
VDD
2.5V +/– 5%
VDDQ
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
Commercial 0°C to +70°C
2.5V – 5%
to VDD
DC Input Voltage....................................–0.5V to VDD + 0.5V
Industrial
-40°C to +85°C
Electrical Characteristics Over the Operating Range[12, 13]
Parameter
VDD
VDDQ
VOH
VOL
VIH
VIL
IX
Description
Test Conditions
Min.
2.375
2.375
2.0
Max.
2.625
VDD
Unit
V
V
V
V
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
VDDQ = 2.5V
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA
0.4
VDD + 0.3V
Input HIGH Voltage[12] VDDQ = 2.5V
1.7
–0.3
–5
V
V
Input LOW Voltage[12]
Input Load
VDDQ = 2.5V
GND ≤ VI ≤ VDDQ
0.7
5
µA
µA
µA
µA
µA
µA
µA
Input Current of MODE Input = VSS
Input = VDD
Input Current of ZZ
–30
30
Input = VSS
Input = VDD
–30
–5
30
5
-300
IOZ
IOS
Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled
Output Short Circuit
VDD = Max., VOUT = GND
Current
IDD
VDD Operating Supply VDD = Max., IOUT = 0 mA,
7.5-ns cycle, 133 MHz
8.8-ns cycle, 117 MHz
10-ns cycle, 100 MHz
7.5-ns cycle, 133 MHz
8.8-ns cycle, 117 MHz
10-ns cycle, 100 MHz
All speeds
210
190
175
120
110
100
70
mA
mA
mA
mA
mA
Current
f = fMAX = 1/tCYC
ISB1
Automatic CE
Max. VDD, Device Deselected,
Power-down
VIN ≥ VIH or VIN ≤ VIL, f = fMAX,
Current—TTL Inputs
inputs switching
ISB2
Automatic CE
Power-down
Max. VDD, Device Deselected,
mA
V
IN ≥ VDD – 0.3V or VIN ≤ 0.3V,
Current—CMOS Inputs f = 0, inputs static
ISB3
Automatic CE
Max. VDD, Device Deselected,
7.5-ns cycle, 133 MHz
8.8-ns cycle, 117 MHz
10-ns cycle, 100 MHz
All Speeds
105
100
95
mA
mA
mA
mA
Power-down
V
IN ≥ VDDQ – 0.3V or VIN ≤ 0.3V,
Current—CMOS Inputs f = fMAX, inputs switching
ISB4
Automatic CE
Max. VDD, Device Deselected,
IN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
80
Power-down
V
Current—TTL Inputs
Notes:
12. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > -2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
13. T
: Assumes a linear ramp from 0v to V (min.) within 200ms. During this time V < V and V
< V
DDQ DD
Power-up
DD
IH
DD
Document #: 38-05241 Rev. *B
Page 24 of 35
CY7C1381CV25
CY7C1383CV25
Thermal Resistance[14]
TQFP
BGA
fBGA
Parameter
Description
Test Conditions
Package
Package
Package
Unit
ΘJA
Thermal Resistance
Test conditions follow standard
test methods and procedures
for measuring thermal
31
45
46
°C/W
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
6
7
3
°C/W
impedance, per EIA / JESD51.
Capacitance[14]
TQFP
BGA
fBGA
Parameter
CIN
Description
Input Capacitance
Test Conditions
Package
Package
Package
Unit
pF
TA = 25°C, f = 1 MHz,
5
5
5
8
8
8
9
9
9
VDD = 2.5V.
CCLK
Clock Input Capacitance
Input/Output Capacitance
pF
CI/O
pF
Notes:
14. Tested initially and after any design or process change that may affect these parameters
AC Test Loads and Waveforms
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
ALL INPUT PULSES
90%
VDD
OUTPUT
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
GND
5 pF
R =1538Ω
≤ 1ns
≤ 1ns
V = 1.25V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Document #: 38-05241 Rev. *B
Page 25 of 35
CY7C1381CV25
CY7C1383CV25
Switching Characteristics Over the Operating Range[19, 20]
133 MHz
117 MHz
100 MHz
Parameter
tPOWER
Clock
tCYC
tCH
tCL
Description
Min.
1
Max.
Min.
1
Max.
Min.
1
Max.
Unit
ms
VDD(Typical) to the first Access[15]
Clock Cycle Time
Clock HIGH
7.5
2.1
2.1
8.5
2.3
2.3
10
2.5
2.5
ns
ns
ns
Clock LOW
Output Times
tCDV
tDOH
tCLZ
tCHZ
tOEV
tOELZ
tOEHZ
Setup Times
tAS
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[16, 17, 18]
6.5
7.5
8.5
ns
ns
ns
ns
ns
ns
ns
2.0
2.0
0
2.0
2.0
0
2.0
2.0
0
Clock to High-Z[16, 17, 18]
4.0
3.2
4.0
3.4
5.0
3.8
OE LOW to Output Valid
OE LOW to Output Low-Z[16, 17, 18]
OE HIGH to Output High-Z[16, 17, 18]
0
0
0
4.0
4.0
5.0
Address Set-up Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
tADS
tADVS
tWES
ADSP, ADSC Set-up Before CLK Rise
ADV Set-up Before CLK Rise
Set-up Before CLK
GW, BWE, BW[A:D]
Rise
tDS
tCES
Data Input Set-up Before CLK Rise
Chip Enable Set-up
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
Hold Times
tAH
tADH
tWEH
tADVH
tDH
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ADSP, ADSC Hold After CLK Rise
,
,
GW BWE BW[A:D] Hold After CLK Rise
ADV Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
tCEH
Notes:
15. This part has a voltage regulator internally; t
can be initiated.
is the time that the power needs to be supplied above V (minimum) initially, before a read or write operation
DD
POWER
16. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
17. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
18. This parameter is sampled and not 100% tested.
19. Timing reference level is 1.25V.
20. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05241 Rev. *B
Page 26 of 35
CY7C1381CV25
CY7C1383CV25
Timing Diagrams
Read Cycle Timing[21]
t
CYC
t
CLK
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
ADDRESS
t
t
WES
WEH
GW, BWE,BW
X
Deselect Cycle
t
t
CES
CEH
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
t
CDV
OEV
OELZ
t
t
OEHZ
CHZ
t
DOH
t
CLZ
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Data Out (Q)
High-Z
t
CDV
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Notes:
21. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05241 Rev. *B
Page 27 of 35
CY7C1381CV25
CY7C1383CV25
Timing Diagrams (continued)
Write Cycle Timing[21, 22]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BW
X
t
t
WEH
WES
GW
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
ADV suspends burst
OE
t
t
DH
DS
Data in (D)
High-Z
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
Extended BURST WRITE
Single WRITE
DON’T CARE
UNDEFINED
Notes:
22.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
X
4
Document #: 38-05241 Rev. *B
Page 28 of 35
CY7C1381CV25
CY7C1383CV25
Timing Diagrams (continued)
Read/Write Cycle Timing[21, 23, 24]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
DS
t
OELZ
t
High-Z
D(A3)
D(A5)
D(A6)
Data In (D)
t
OEHZ
CDV
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
Back-to-Back READs
Single WRITE
BURST READ
WRITEs
DON’T CARE
UNDEFINED
Note:
23.
24.
.
The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by
GW is HIGH.
ADSP or ADSC
Document #: 38-05241 Rev. *B
Page 29 of 35
CY7C1381CV25
CY7C1383CV25
Timing Diagrams (continued)
ZZ Mode Timing [25, 26]
CLK
ZZ
t
t
ZZ
ZZREC
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
25. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
26. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05241 Rev. *B
Page 30 of 35
CY7C1381CV25
CY7C1383CV25
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
Part and Package Type
133
CY7C1381CV25-133AC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
Commercial
CY7C1383CV25-133AC
3 Chip Enables
CY7C1381CV25-133BGC
CY7C1383CV25-133BGC
BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
CY7C1381CV25-133BZC
BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
CY7C1383CV25-133BZC
3 Chip Enables and JTAG
117
CY7C1381CV25-117AC
CY7C1383CV25-117AC
CY7C1381CV25-117BGC
CY7C1383CV25-117BGC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Commercial
BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
CY7C1381CV25-117BZC
BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
3 Chip Enables and JTAG
CY7C1383CV25-117BZC
CY7C1381CV25-117AI
CY7C1383CV25-117AI
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
Industrial
3 Chip Enables
CY7C1381CV25-117BGI
BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
CY7C1383CV25-117BGI
CY7C1381CV25-117BZI
CY7C1383CV25-117BZI
BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
3 Chip Enables and JTAG
100
CY7C1381CV25-100AC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Commercial
CY7C1383CV25-100AC
CY7C1381CV25-100BGC
CY7C1383CV25-100BGC
CY7C1381CV25-100BZC
CY7C1383CV25-100BZC
CY7C1381CV25-100AI
CY7C1383CV25-100AI
CY7C1381CV25-100BGI
CY7C1383CV25-100BGI
CY7C1381CV25-100BZI
CY7C1383CV25-100BZI
BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
3 Chip Enables and JTAG
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Industrial
BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
3 Chip Enables and JTAG
Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.
Document #: 38-05241 Rev. *B
Page 31 of 35
CY7C1381CV25
CY7C1383CV25
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
DIMENSIONS ARE IN MILLIMETERS.
ꢁ6.00 0.20
ꢁ4.00 0.ꢁ0
ꢁ.40 0.05
ꢁ00
ꢀꢁ
ꢀ0
ꢁ
0.30 0.0ꢀ
0.65
TYP.
ꢁ2° ꢁ°
(ꢀX)
SEE DETAIL
A
30
5ꢁ
3ꢁ
50
0.20 MAX.
ꢁ.60 MAX.
R 0.0ꢀ MIN.
0.20 MAX.
0° MIN.
STAND-OFF
0.05 MIN.
0.ꢁ5 MAX.
SEATING PLANE
0.25
GAUGE PLANE
R 0.0ꢀ MIN.
0.20 MAX.
0°-7°
0.60 0.ꢁ5
0.20 MIN.
ꢁ.00 REF.
51-85050-*A
DETAIL
A
Document #: 38-05241 Rev. *B
Page 32 of 35
CY7C1381CV25
CY7C1383CV25
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05241 Rev. *B
Page 33 of 35
CY7C1381CV25
CY7C1383CV25
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*C
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05241 Rev. *B
Page 34 of 35
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Cypressproductsarenotwarrantednorintendedtobeusedformedical, life-support, life-saving, criticalcontrolorsafetyapplications, unlesspursuanttoanexpresswrittenagreementwithCypress.
CY7C1381CV25
CY7C1383CV25
Document History Page
Document Title: CY7C1381CV25/ CY7C1383CV2518-Mbit (512K x 36/1M x 18) Flow-Through SRAM
Document #: 38-05241 Rev. *B
Orig. of
REV.
**
*A
ECN NO. Issue Date Change
Description of Change
116281
206081
225181
08/28/02
See ECN
See ECN
SKX
RKF
VBL
New Data Sheet
Final Data Sheet
*B
Update Ordering Info section: shade all part numbers
Correct in feature page, core power supply tolerance to +/–5%
Document #: 38-05241 Rev. *B
Page 35 of 35
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