CY7C1381D-100AXC [CYPRESS]
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; 18兆位（ 512K ×36 / 1M ×18 ）流通型SRAM
| 型号： | CY7C1381D-100AXC |
| 厂家： | 
CYPRESS |
| 描述： | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
| 文件： | 总29页 (文件大小：466K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1381D
CY7C1383D
PRELIMINARY
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
Features
Functional Description[1]
• Supports 133-MHz bus operations
• 512K × 36/1M × 18 common I/O
• 3.3V –5% and +10% core power supply (VDD
The CY7C1381D/CY7C1383D is a 3.3V, 512K x 36 and 1 Mbit
18 Synchronous Flow-through SRAMs, respectively
x
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
)
• 2.5V or 3.3V I/O supply (VDDQ
• Fast clock-to-output time
— 6.5 ns (133-MHz version)
— 8.5 ns (100-MHz version)
)
addresses, all data inputs, address-pipelining Chip Enable
[2]
• Provide high-performance 2-1-1-1 access rate
(
), depth-expansion Chip Enables (CE and
), Burst
CE3
CE1
2
• User-selectable burst counter supporting Intel
Control inputs (
,
,
), Write Enables
(
ADV
BWx
and
,
ADSC ADSP
Pentium interleaved or linear burst sequences
), and Global Write (
BWE
). Asynchronous
GW
and
inputs
(
)
and the ZZ pin
OE
.
include the Output Enable
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
The CY7C1381D/CY7C1383D allows either interleaved or
linear burst sequences, selected by the MODE input pin. A
HIGH selects an interleaved burst sequence, while a LOW
selects a linear burst sequence. Burst accesses can be
initiated with the Processor Address Strobe (ADSP) or the
cache Controller Address Strobe (ADSC) inputs. Address
advancement is controlled by the Address Advancement
(ADV) input.
• Offered in JEDEC-standard lead-free 100-pin TQFP
,119-ball BGA and 165-ball fBGA packages
• JTAG boundary scan for BGA and fBGA packages
• “ZZ” Sleep Mode option
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (
) or
ADSP
Address Strobe Controller (
) are active. Subsequent
ADSC
burst addresses can be internally generated as controlled by
the Advance pin ( ).
ADV
The CY7C1381D/CY7C1383D operates from a +3.3V core
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
133 MHz
6.5
100 MHz
8.5
Unit
ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
210
70
175
70
mA
mA
Notes:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. CE CE are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.
3,
2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05544 Rev. *A
Revised November 2, 2004
PRELIMINARY
CY7C1381D
CY7C1383D
1
Logic Block Diagram – CY7C1381D (512K x 36)
ADDRESS
REGISTER
A0, A1, A
A[1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
AND LOGIC
Q0
CLR
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D, DQPD
DQ
BYTE
WRITE REGISTER
D, DQPD
BW
D
DQ
BYTE
WRITE REGISTER
C, DQPC
DQ
BYTE
WRITE REGISTER
C, DQPC
BW
C
OUTPUT
BUFFERS
DQs
MEMORY
ARRAY
SENSE
AMPS
DQP
DQP
DQP
A
DQ
BYTE
WRITE REGISTER
B, DQPB
B
C
DQ
BYTE
WRITE REGISTER
B, DQPB
BW
B
DQPD
DQ
BYTE
WRITE REGISTER
A, DQPA
DQ
A, DQPA
BW
A
BYTE
BWE
WRITE REGISTER
INPUT
GW
REGISTERS
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
CONTROL
ZZ
2
Logic Block Diagram – CY7C1383D (1 Mbit x 18)
ADDRESS
REGISTER
A0,A1,A
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
B,DQPB
DQ
B,DQPB
WRITE DRIVER
WRITE REGISTER
BW
B
A
MEMORY
ARRAY
OUTPUT
BUFFERS
DQs
DQP
DQP
SENSE
AMPS
A
B
DQ
A,DQPA
DQA,DQPA
WRITE REGISTER
WRITE DRIVER
BW
BWE
GW
INPUT
REGISTERS
ENABLE
REGISTER
CE
CE
CE
1
2
3
OE
SLEEP
CONTROL
ZZ
Document #: 38-05544 Rev. *A
Page 2 of 29
PRELIMINARY
CY7C1381D
CY7C1383D
Pin Configurations
100-pin TQFP Pinout
DQPC
1
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
A
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
NC
2
DQC
3
NC
NC
3
VDDQ
4
5
VDDQ
VSSQ
NC
VDDQ
VSSQ
NC
4
VSSQ
5
DQC
6
6
DQC
7
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
7
DQC
8
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS/DNU
VDD
8
DQC
9
9
VSSQ
10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
11
DQC
12
DQC
13
VSS/DNU
14
VDD
15
NC
CY7C1383D
(1M x 18)
CY7C1381D
(512K x 36)
NC
16
VDD
ZZ
NC
VDD
ZZ
VSS
17
VSS
DQD
18
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
DQD
19
VDDQ
20
VSSQ
21
DQD
22
DQD
23
DQD
24
DQD
25
NC
VSSQ
26
VSSQ
VDDQ
NC
VSSQ
VDDQ
NC
VDDQ
27
DQD
28
DQD
29
NC
NC
DQPD
30
NC
NC
Document #: 38-05544 Rev. *A
Page 3 of 29
PRELIMINARY
CY7C1381D
CY7C1383D
Pin Configurations (continued)
119-ball BGA (1 Chip Enable with JTAG)
CY7C1381D (512K x 36)
1
2
3
4
5
6
7
VDDQ
A
A
A
A
VDDQ
A
ADSP
B
C
NC
NC
A
A
A
A
A
A
A
A
NC
NC
ADSC
VDD
DQC
DQC
VDDQ
DQPC
DQC
DQC
VSS
VSS
VSS
NC
CE1
OE
VSS
VSS
VSS
DQPB
DQB
DQB
DQB
DQB
VDDQ
D
E
F
DQC
DQC
VDDQ
DQD
DQD
VDDQ
DQD
DQC
DQC
VDD
DQB
DQB
VDD
DQA
DQA
DQA
DQA
DQB
DQB
VDDQ
DQA
DQA
VDDQ
DQA
G
H
J
BWC
VSS
NC
ADV
GW
VDD
CLK
NC
BWE
A1
BWB
VSS
NC
DQD
VSS
VSS
K
L
M
N
DQD
DQD
DQD
BWD
VSS
VSS
BWA
VSS
VSS
P
R
DQD
NC
DQPD
A
VSS
MODE
A0
VDD
VSS
NC
DQPA
A
DQA
NC
T
U
NC
VDDQ
NC
TMS
A
TDI
A
TCK
A
TDO
NC
NC
ZZ
VDDQ
CY7C1383D (1M x 18)
2
A
A
1
3
A
A
4
5
A
A
A
VSS
VSS
VSS
NC
VSS
6
A
7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
VDDQ
NC
NC
DQB
NC
VDDQ
NC
DQB
VDDQ
VDDQ
NC
NC
NC
DQA
VDDQ
DQA
NC
VDDQ
ADSP
ADSC
VDD
A
A
DQPA
NC
A
A
NC
DQB
NC
DQB
NC
VDD
VSS
VSS
VSS
BWB
VSS
NC
NC
CE1
OE
ADV
DQA
NC
DQA
VDD
NC
DQA
NC
GW
VDD
NC
VSS
NC
DQB
VSS
CLK
NC
BWE
A1
DQA
DQB
VDDQ
DQB
NC
NC
DQB
NC
NC
VSS
VSS
VSS
NC
VDDQ
NC
BWA
VSS
VSS
VSS
DQA
NC
DQPB
A0
DQA
R
T
NC
NC
A
A
MODE
A
VDD
NC
NC
A
A
A
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Document #: 38-05544 Rev. *A
Page 4 of 29
PRELIMINARY
CY7C1381D
CY7C1383D
Pin Configurations (continued)
165-ball fBGA (3 Chip Enable)
CY7C1381D (512K x 36)
1
NC / 288M
NC
DQPC
DQC
2
A
A
NC
DQC
DQC
DQC
DQC
NC
3
4
5
6
7
8
9
10
11
NC
NC / 144M
DQPB
DQB
CE1
BWC
BWB
CE3
BWE
GW
VSS
VSS
VSS
ADSC
ADV
A
A
B
C
D
E
F
G
H
J
K
L
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
BWD
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
BWA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
A
NC
DQB
DQB
DQB
DQB
NC
DQA
DQA
DQA
DQC
DQB
DQC
DQC
NC
DQD
DQD
DQD
VSS
VSS
VSS
VSS
VSS
VSS
DQB
DQB
ZZ
DQA
DQA
DQA
DQD
DQD
DQD
DQD
DQPD
NC
DQD
NC
NC / 72M
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
TDI
VSS
A
A1
VSS
NC
TDO
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
A0
MODE NC / 36M
A
A
TMS
TCK
A
A
A
A
R
CY7C1383D (1M x 18)
1
NC / 288M
NC
2
3
4
5
6
7
8
9
10
11
A
A
CE1
BWB
NC
CE
BWE
GW
VSS
VSS
ADSC
ADV
A
A
3
A
NC
DQB
DQB
DQB
DQB
NC
NC
NC
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
BWA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
A
NC
NC
NC
NC
NC
NC / 144M
DQPA
DQA
B
C
D
E
F
G
H
J
K
L
NC
NC
NC
NC
NC
VSS
DQB
DQB
DQB
VSS
DQA
VSS
VSS
VSS
VSS
VSS
VSS
DQA
DQA
ZZ
NC
NC
NC
DQA
DQA
DQA
NC
NC
DQB
DQPB
NC
NC
NC
NC / 72M
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
TDI
VSS
A
A1
VSS
NC
TDO
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
A
M
N
P
MODE NC / 36M
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05544 Rev. *A
Page 5 of 29
PRELIMINARY
CY7C1381D
CY7C1383D
Pin Definitions
Name
I/O
Description
A0, A1 , A
Input-
Address Inputs used to select one of the address locations. Sampled at the rising edge
Synchronous
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2] are sampled active.
A[1:0] feed the 2-bit counter.
BWA, BWB
BWC, BWD
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the
Synchronous
SRAM. Sampled on the rising edge of CLK.
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
GW
Synchronous
global write is conducted (ALL bytes are written, regardless of the values on BW[A:D]and BWE).
CLK
Input-
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment
Clock
the burst counter when ADV is asserted LOW, during a burst operation.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
CE1
CE2
Synchronous
with CE2 and CE3[2] to select/deselect the device. ADSP is ignored
sampled only when a new external address is loaded.
CE is
if CE1 is HIGH.
1
Input-
Chip Enable 2 Input, active HIGH. Sampled onthe rising edge of CLK. Usedin conjunction
with CE1 and CE3[2] to select/deselect the device. CE2 is sampled only when a new external
address is loaded.
Synchronous
[2]
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used
CE3
in conjunction
CE3 is sampled only when a new external
Synchronous
with CE1 and CE2 to select/deselect the device.
address is loaded.
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
OE
Asynchronous When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when
emerging from a deselected state.
Input-
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automat-
ADV
Synchronous
ically increments the address in a burst cycle.
Input-
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both
ADSP
Synchronous
asserted, only ADSP is recognized. ASDP is ignored when
CE1 is deasserted HIGH
Input-
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both
ADSC
Synchronous
.
asserted, only ADSP is recognized
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
BWE
ZZ
Synchronous
must be asserted LOW to conduct a byte write.
Input-
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull-down.
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
DQs
Synchronous
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous
clock rise of the
read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the
The
pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.
outputs are automatically tri-stated during the data portion of a write sequence, during the
first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
I/O-
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs.
DQPX
Synchronous
During write sequences, DQPX is controlled by BWX correspondingly.
MODE
Input-Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD
or left floating selects interleaved burst sequence. This is a strap pin and should remain
static during device operation. Mode Pin has an internal pull-up.
VDD
VDDQ
VSS
Power Supply Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Ground Ground for the core of the device.
Document #: 38-05544 Rev. *A
Page 6 of 29
PRELIMINARY
CY7C1381D
CY7C1383D
Pin Definitions (continued)
Name
I/O
Description
VSSQ
I/O Ground
Ground for the I/O circuitry.
TDO
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
Synchronous
JTAG feature is not being utilized, this pin should be left unconnected. This pin is not
available on TQFP packages.
TDI
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
is not being utilized, this pin can be left floating or connected to VDD through a pull up
resistor. This pin is not available on TQFP packages.
TMS
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
is not being utilized, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
TCK
NC
JTAG-
Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to VSS. This pin is not available on TQFP packages.
–
No Connects. Not internally connected to the die. 36M, 72M, 144M and 288M are address
expansion pins are not internally connected to the die.
VSS/DNU
Ground/DNU
This pin can be connected to Ground or should be left floating.
Single Write Accesses Initiated by ADSP
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (tCDV) is 6.5 ns (133-MHz device).
This access is initiated when the follow[i2n]g conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BWE, and BWX)are ignored during this first clock
cycle. If the write inputs are asserted active ( see Write Cycle
Descriptions table for appropriate states that indicate a write)
on the next clock rise,the appropriate data will be latched and
written into the device.Byte writes are allowed. All I/Os are
tri-stated during a byte write.Since this is a common I/O
device, the asynchronous OE input signal must be deasserted
and the I/Os must be tri-stated prior to the presentation of data
to DQs. As a safety precaution, the data lines are tri-stated
once a write cycle is detected, regardless of the state of OE.
The CY7C1381D/CY7C1383D supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium® and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3[2] are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active LOW.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ[A:D] will be
written into the specified address location. Byte writes are
allowed. All I/Os are tri-stated when a write is detected, even
a byte write. Since this is a common I/O device, the
asynchronous OE input signal must be deasserted and the
I/Os must be tri-stated prior to the presentation of data to DQs.
As a safety precaution, the data lines are tri-stated once a write
Three synchronous Chip Selects (CE1, CE2, CE3[2]) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
[2]
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all
cycle is detected, regardless
of the state of OE.
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to tCDV after clock
rise. ADSP is ignored if CE1 is HIGH.
Burst Sequences
The CY7C1381D/CY7C1383D provides an on-chip two-bit
wraparound burst counter inside the SRAM. The burst counter
is fed by A[1:0], and can follow either a linear or interleaved
burst order. The burst order is determined by the state of the
MODE input. A LOW on MODE will select a linear burst
sequence. A HIGH on MODE will select an interleaved burst
Document #: 38-05544 Rev. *A
Page 7 of 29
PRELIMINARY
CY7C1381D
CY7C1383D
order. Leaving MODE unconnected will cause the device to
Sleep Mode
default to a interleaved burst sequence.
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Address
A1: A0
“sleep” mode. CE , CE , CE [2], ADSP, and ADSC must
the
1
2
3
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Linear Burst Address Table (MODE = GND)
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max.
80
2tCYC
Unit
mA
ns
ns
ns
2tCYC
0
2tCYC
tRZZI
ns
Truth Table [ 3, 4, 5, 6, 7]
ADDRESS
Used
Cycle Description
CE1 CE2 CE3 ZZ
ADSP
ADSC ADV WRITE OE CLK
DQ
Deselected Cycle,
None
None
None
None
None
None
H
X
X
X
H
X
X
X
L
L
L
L
L
H
X
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Sleep Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
L
L
L
L
L
X
L
L
H
H
X
L
L
X
X
L
X
X
X
X
L-H
Tri-State
Q
External
External
External
L
L
L
H
H
H
L
L
L
L
L
L
X
X
L
X
X
X
X
X
L
L
H
X
L-H Tri-State
L-H
Write Cycle, Begin Burst
H
D
Notes:
3. X=”Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals , BWE, GW = H..
5. The DQ pins are controlled by the current cycle and the signal. is asynchronous and is not sampled with the clock.
OE
OE
must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks
X
after the
or with the assertion of
. As a result,
ADSC
is a
OE
OE
ADSP
don't care for the remainder of the write cycle.
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when
7.
is
OE
inactive or when the device is deselected, and all data bits behave as output when
OE
is active (LOW).
OE
Document #: 38-05544 Rev. *A
Page 8 of 29
PRELIMINARY
CY7C1381D
CY7C1383D
Truth Table (continued)[ 3, 4, 5, 6, 7]
ADDRESS
Cycle Description
Used
CE1 CE2 CE3 ZZ
ADSP
ADSC ADV WRITE OE CLK
DQ
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
L
L
X
X
H
H
X
H
X
X
H
H
X
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
H
H
H
H
H
H
L
L
H
L
H
L
H
X
X
L
H
L
L-H
L-H Tri-State
L-H
L-H Tri-State
L-H
L-H Tri-State
Q
Q
Q
L-H
L-H
L-H
D
D
Q
L
L
H
H
H
H
H
H
H
H
H
H
L
L-H Tri-State
L-H
L-H Tri-State
Q
H
X
X
L-H
L-H
D
D
L
Partial Truth Table for Read/Write[3, 8]
Function (CY7C1381D)
BWD
BWC
BWB
BWA
GW
BWE
Read
Read
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
L
H
L
H
L
H
L
H
L
Write Byte A (DQA, DQPA)
Write Byte B(DQB, DQPB)
Write Bytes A, B (DQA, DQB, DQPA, DQPB)
Write Byte C (DQC, DQPC)
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
Write Bytes C, B (DQC, DQB, DQPC, DQPB)
L
H
H
L
Write Bytes C, B, A (DQC, DQB, DQA, DQPC,
L
DQPB, DQPA)
Write Byte D (DQD, DQPD)
Write Bytes D, A (DQD, DQA, DQPD, DQPA)
Write Bytes D, B (DQD, DQA, DQPD, DQPA)
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
H
L
H
L
Write Bytes D, B, A (DQD, DQB, DQA, DQPD,
L
DQPB, DQPA)
Write Bytes D, B (DQD, DQB, DQPD, DQPB)
H
H
L
L
L
L
L
L
H
H
H
L
Write Bytes D, B, A (DQD, DQC, DQA, DQPD,
DQPC, DQPA)
Write Bytes D, C, A ( DQD, DQB, DQA, DQPD,
DQPB, DQPA)
H
L
L
L
L
H
Write All Bytes
Write All Bytes
H
L
L
X
L
X
L
X
L
X
L
X
Note:
8. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid Appropriate write will be done based on which byte write is active.
X
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PRELIMINARY
CY7C1381D
CY7C1383D
Truth Table for Read/Write[3,8]
Function (CY7C1383D)
Read
BWB
X
BWA
X
BWE
H
GW
H
Read
H
H
H
H
L
L
L
L
L
X
H
H
L
L
X
H
L
H
L
Write Byte A – ( DQA and DQPA)
Write Byte B – ( DQB and DQPB)
Write All Bytes
Write All Bytes
X
IEEE 1149.1 Serial Boundary Scan (JTAG)
TAP Controller State Diagram
TEST-LOGIC
1
The CY7C1381D/CY7C1383D incorporates a serial boundary
scan test access port (TAP) in the BGA package only. The
TQFP package does not offer this functionality. This part
operates in accordance with IEEE Standard 1149.1-1900, but
doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.
RESET
0
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
0
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
1
1
EXIT1-DR
EXIT1-IR
The CY7C1381D/CY7C1383D contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
0
0
PAUSE-DR
0
PAUSE-IR
0
1
1
Disabling the JTAG Feature
0
0
EXIT2-DR
1
EXIT2-IR
1
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
UPDATE-DR
UPDATE-IR
1
0
1
0
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
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Page 10 of 29
PRELIMINARY
CY7C1381D
CY7C1383D
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
TAP Controller Block Diagram
0
Bypass Register
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.
2
1
0
0
0
Selection
Circuitry
Instruction Register
31 30 29
Identification Register
S
election
TDI
TDO
Circuitr
y
.
.
. 2 1
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
x
.
.
.
.
. 2 1
Boundary Scan Register
TCK
TMS
TAP CONTROLLER
TAP Instruction Set
Overview
Performing a TAP Reset
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
Document #: 38-05544 Rev. *A
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PRELIMINARY
CY7C1381D
CY7C1383D
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required - that is, while data
captured is shifted out, the preloaded data can be shifted in.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
Document #: 38-05544 Rev. *A
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PRELIMINARY
CY7C1381D
CY7C1383D
TAP AC Switching Characteristics Over the operating Range[9, 10]
Parameter
Description
Min.
Max.
Unit
Clock
tTCYC
tTF
tTH
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
20
5
25
25
tTL
ns
Output Times
tTDOV
tTDOX
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
ns
ns
0
Set-up Times
tTMSS
tTDIS
tCS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
5
5
5
ns
ns
Hold Times
tTMSH
tTDIH
tCH
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
5
5
5
ns
ns
ns
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ................................................ VSS to 3.3V
Input rise and fall times................................................... 1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
Input pulse levels ......................................... VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels......................................... 1.25V
Output reference levels ................................................ 1.25V
Test load termination supply voltage ............................ 1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
ZO= 50Ω
ZO= 50Ω
20pF
20pF
Notes:
t
t
9. CS and CH refer to the setup and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1ns
R
F
Document #: 38-05544 Rev. *A
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PRELIMINARY
CY7C1381D
CY7C1383D
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; Vdd = 3.3V ±0.165V unless otherwise noted)[11]
Parameter
VOH1
Description
IOH = –4.0 mA
Conditions
Min.
2.4
Max.
Unit
V
V
DDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
2.0
2.9
2.1
V
V
IOH = –1.0 mA
IOH = –100 µA
VOH2
VOL1
VOL2
VIH
V
DDQ = 2.5V
VDDQ = 3.3V
DDQ = 2.5V
VDDQ = 3.3V
DDQ = 2.5V
VDDQ = 3.3V
V
0.4
0.4
V
IOL = 8.0 mA
IOL = 8.0 mA
IOL = 100 µA
V
V
0.2
V
V
0.2
V
2.0
1.7
VDD + 0.3
VDD + 0.3
0.8
V
V
DDQ = 2.5V
DDQ = 3.3V
V
V
–0.3
–0.3
-5
V
VIL
VDDQ = 2.5V
0.7
V
5
µA
IX
GND < VIN < VDDQ
Identification Register Definitions
CY7C1381D
CY7C1383D
Instruction Field
Revision Number (31:29)
Device Depth (28:24)[12]
(512K × 36)
(1M × 18)
000
Description
Describes the version number.
Reserved for Internal Use
000
01011
01011
000001
100101
00000110100
1
000001
010101
00000110100
1
Device Width (23:18)
Defines memory type and architecture
Defines width and density
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Scan Register Sizes
Register Name
Bit Size (×36)
Bit Size (×18)
Instruction Bypass
3
3
Bypass
ID
1
1
32
85
89
32
85
89
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball fBGA package)
Notes:
11. All voltages referenced to VSS (GND).
12. Bit #24 is “1” in the Register Definitions for both 2.5v and 3.3v versions of this device.
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PRELIMINARY
CY7C1381D
CY7C1383D
Identification Codes
Instruction
Code
Description
000
EXTEST
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
001
010
IDCODE
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
SAMPLE Z
011
100
RESERVED
SAMPLE/PRELOAD
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
101
110
111
RESERVED
RESERVED
BYPASS
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
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PRELIMINARY
CY7C1381D
CY7C1383D
119-Ball BGA Boundary Scan Order [13, 14]
CY7C1381D (256K × 36)
CY7C1383D (512K × 18)
Bit#
1
2
3
4
5
6
7
8
Ball ID
Bit#
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
Ball ID
E4
G4
A4
G3
C3
B2
B3
A3
C2
A2
B1
C1
D2
E1
F2
G1
H2
D1
E2
G2
H1
J3
Bit#
1
2
3
4
5
6
7
8
Ball ID
Bit#
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
Ball ID
E4
G4
A4
G3
C3
B2
B3
A3
C2
A2
B1
C1
D2
E1
F2
G1
H2
D1
E2
G2
H1
J3
H4
T4
T5
T6
R5
L5
R6
U6
R7
T7
P6
N7
M6
L7
K6
P7
N6
L6
K7
J5
H6
G7
F6
E7
D7
H7
G6
E6
D6
C7
B7
C6
A6
C5
B5
G5
B6
D4
B4
F4
M4
A5
K4
H4
T4
T5
T6
R5
L5
R6
U6
R7
T7
P6
N7
M6
L7
K6
P7
N6
L6
K7
J5
H6
G7
F6
E7
D7
H7
G6
E6
D6
C7
B7
C6
A6
C5
B5
G5
B6
D4
B4
F4
M4
A5
K4
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
K2
L1
K2
L1
M2
N1
P1
K1
L2
N2
P2
R3
T1
R1
T2
L3
R2
T3
L4
M2
N1
P1
K1
L2
N2
P2
R3
T1
R1
T2
L3
R2
T3
L4
N4
P4
Internal
N4
P4
Internal
Notes:
13. Balls that are NC (No Connect) are Pre-Set LOW.
14. Bit# 85 is Pre-Set HIGH.
Document #: 38-05544 Rev. *A
Page 16 of 29
PRELIMINARY
CY7C1381D
CY7C1383D
165-Ball BGA Boundary Scan Order [13, 15]
CY7C1381D (256K x 36)
CY7C1381D (256Kx36)
Bit#
Ball ID
Bit#
Ball ID
Bit#
Ball ID
1
2
3
4
5
6
7
8
N6
N7
10N
P11
P8
R8
R9
P9
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
A9
B9
C10
A8
B8
A7
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
G1
D2
E2
F2
G2
H1
H3
J1
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
K2
L2
M2
N1
N2
P1
R1
R2
P3
R3
P2
R4
P4
N5
P6
R6
Internal
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
H10
G11
F11
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
K1
L1
M1
J2
Note:
15. Bit# 89 is Pre-Set HIGH.
Document #: 38-05544 Rev. *A
Page 17 of 29
PRELIMINARY
CY7C1381D
CY7C1383D
165-Ball BGA Boundary Scan Order [13, 15]
CY7C1383D (512K x 18)
CY7C1383D (512Kx18)
Bit#
1
2
3
4
5
6
7
8
Ball ID
N6
N7
10N
P11
P8
R8
R9
P9
Bit#
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Ball ID
A9
B9
C10
A8
B8
A7
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
G1
D2
E2
F2
G2
H1
H3
J1
K1
L1
M1
J2
Bit#
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
K2
L2
M2
N1
N2
P1
R1
R2
P3
R3
P2
R4
P4
N5
P6
R6
Internal
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
H10
G11
F11
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Document #: 38-05544 Rev. *A
Page 18 of 29
PRELIMINARY
CY7C1381D
CY7C1383D
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(Above which the useful life may be impaired. For user guide-
(per MIL-STD-883, Method 3015)
lines, not tested.)
Latch-up Current.................................................... > 200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Supply Voltage on VDD Relative to GND........ –0.3V to +4.6V
Range
Temperature
VDD
VDDQ
DC Voltage Applied to Outputs
Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%
in Tri-State........................................... –0.5V to VDDQ + 0.5V
to VDD
Industrial
–40°C to +85°C
DC Input Voltage....................................–0.5V to VDD + 0.5V
Electrical Characteristics Over the Operating Range [16, 17]
Parameter
VDD
VDDQ
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
2.4
Max.
3.6
VDD
Unit
V
V
V
V
V
V
V
V
VDDQ = 3.3V
VDDQ = 2.5V
2.625
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA
2.0
0.4
0.4
VDD + 0.3V
VDD + 0.3V
0.8
Input HIGH Voltage[16] VDDQ = 3.3V
VDDQ = 2.5V
2.0
1.7
–0.3
–0.3
–5
V
V
V
Input LOW Voltage[16]
VDDQ = 3.3V
VDDQ = 2.5V
GND ≤ VI ≤ VDDQ
0.7
5
Input Load
Input Current of MODE Input = VSS
Input = VDD
µA
µA
µA
µA
µA
µA
mA
mA
mA
–5
30
Input Current of ZZ
Input = VSS
Input = VDD
–30
–5
5
5
210
175
140
120
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled
VDD Operating Supply VDD = Max., IOUT = 0 mA,
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
Current
f = fMAX = 1/tCYC
ISB1
ISB2
ISB3
Automatic CE
Max. VDD, Device Deselected,
Power-down
VIN ≥ VIH or VIN ≤ VIL, f = fMAX,
Current—TTL Inputs
inputs switching
Automatic CE
Max. VDD, Device Deselected,
All speeds
70
mA
Power-down
V
IN ≥ VDD – 0.3V or VIN ≤ 0.3V,
Current—CMOS Inputs f = 0, inputs static
Automatic CE
Max. VDD, Device Deselected,
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
130
110
mA
mA
Power-down
V
IN ≥ VDDQ – 0.3V or VIN ≤ 0.3V,
Current—CMOS Inputs f = fMAX, inputs switching
ISB4
Automatic CE
Max. VDD, Device Deselected,
IN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
All Speeds
80
mA
Power-down
V
Current—TTL Inputs
Notes:
16. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > -2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
17. T
: Assumes a linear ramp from 0v to V (min.) within 200ms. During this time V < V and V
< V
DDQ DD
Power-up
DD
IH
DD
Document #: 38-05544 Rev. *A
Page 19 of 29
PRELIMINARY
CY7C1381D
CY7C1383D
Thermal Resistance[18]
Parameter
Description
Test Conditions
TQFP Package BGA Package fBGA Package Unit
ΘJA
Thermal Resistance
Test conditions follow standard
31
45
46
°C/W
(Junction to Ambient) test methods and procedures
for measuring thermal
Thermal Resistance
ΘJC
6
7
3
°C/W
impedence, per EIA / JESD51.
(Junction to Case)
Capacitance[18]
Parameter
Description
Test Conditions
TQFP Package BGA Package fBGA Package Unit
CIN
CCLK
CI/O
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
TA = 25°C, f = 1 MHz,
5
5
5
8
8
8
9
9
9
pF
pF
pF
V
DD = 3.3V.
DDQ = 2.5V
V
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
R = 317Ω
3.3V
ALL INPUT PULSES
90%
VDDQ
GND
OUTPUT
90%
10%
Z = 50Ω
0
R = 50Ω
10%
10%
L
5 pF
R = 351Ω
≤ 1ns
≤ 1ns
INCLUDING
JIG AND
SCOPE
V = 1.5V
T
(a)
(b)
(c)
2.5V I/O Test Load
OUTPUT
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
L
5 pF
R =1538Ω
≤ 1ns
≤ 1ns
INCLUDING
JIG AND
SCOPE
V = 1.25V
T
(a)
(b)
(c)
Switching Characteristics Over the Operating Range [20, 21]
133 MHz
100 MHz
Parameter
tPOWER
Clock
tCYC
tCH
tCL
Description
Min.
1
Max.
Min.
1
Max.
Unit
ms
VDD(Typical) to the first Access[19]
Clock Cycle Time
Clock HIGH
7.5
2.1
2.1
10
2.5
2.5
ns
ns
ns
Clock LOW
Output Times
tCDV
tDOH
tCLZ
tCHZ
tOEV
tOELZ
tOEHZ
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[20, 21, 22]
6.5
8.5
ns
ns
ns
ns
ns
ns
ns
2.0
2.0
0
2.0
2.0
0
Clock to High-Z[20, 21, 22]
4.0
3.2
5.0
3.8
OE LOW to Output Valid
OE LOW to Output Low-Z[20, 21, 22]
OE HIGH to Output High-Z[20, 21, 22]
0
0
4.0
5.0
Setup Times
tAS
Address Set-up Before CLK Rise
1.5
1.5
ns
Document #: 38-05544 Rev. *A
Page 20 of 29
PRELIMINARY
CY7C1381D
CY7C1383D
Switching Characteristics Over the Operating Range (continued)[20, 21]
133 MHz
Min. Max.
100 MHz
Min. Max.
Parameter
tADS
tADVS
tWES
tDS
tCES
Description
ADSP, ADSC Set-up Before CLK Rise
ADV Set-up Before CLK Rise
Unit
ns
ns
ns
ns
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Set-up Before CLK Rise
GW, BWE, BW[A:D]
Data Input Set-up Before CLK Rise
Chip Enable Set-up
ns
Hold Times
tAH
tADH
tWEH
tADVH
tDH
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ADSP, ADSC Hold After CLK Rise
,
,
GW BWE BW[A:D] Hold After CLK Rise
ADV Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
tCEH
Notes:
18. Tested initially and after any design or process change that may affect these parameters.
19. This part has a voltage regulator internally; t
can be initiated.
is the time that the power needs to be supplied above V ( minimum) initially, before a read or write operation
DD
POWER
20. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
OEHZ
CHZ CLZ OELZ
21. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
Document #: 38-05544 Rev. *A
Page 21 of 29
PRELIMINARY
CY7C1381D
CY7C1383D
Timing Diagrams
Read Cycle Timing[25]
t
CYC
t
CLK
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
ADDRESS
t
t
WES
WEH
GW, BWE,BW
X
Deselect Cycle
t
t
CES
CEH
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
t
CDV
OEV
OELZ
t
t
OEHZ
CHZ
t
DOH
t
CLZ
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Data Out (Q)
High-Z
t
CDV
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note:
22. This parameter is sampled and not 100% tested.
Document #: 38-05544 Rev. *A
Page 22 of 29
PRELIMINARY
CY7C1381D
CY7C1383D
Timing Diagrams (continued)
3
Write Cycle Timing[25, 26]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BW
X
t
t
WEH
WES
GW
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
ADV suspends burst
OE
t
t
DH
DS
Data in (D)
High-Z
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
Extended BURST WRITE
Single WRITE
DON’T CARE
UNDEFINED
Notes:
23. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
24. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05544 Rev. *A
Page 23 of 29
PRELIMINARY
CY7C1381D
CY7C1383D
Timing Diagrams (continued)
Read/Write Cycle Timing[25, 27, 28]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
DS
t
OELZ
t
High-Z
D(A3)
D(A5)
D(A6)
Data In (D)
t
OEHZ
CDV
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
Back-to-Back READs
Single WRITE
BURST READ
DON’T CARE
UNDEFINED
Notes:
25. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
26.
27.
28.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
X
The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by
GW is HIGH.
.
ADSP or ADSC
Document #: 38-05544 Rev. *A
Page 24 of 29
PRELIMINARY
CY7C1381D
CY7C1383D
Timing Diagrams (continued)
ZZ Mode Timing [29, 30]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
Part and Package Type
133
CY7C1381D-133AXC
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3
Commercial
CY7C1383D-133AXC
Chip Enables
CY7C1381D-133BGC
CY7C1383D-133BGC
BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG
CY7C1381D-133BZC
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
CY7C1383D-133BZC
CY7C1381D-133BGXC
CY7C1383D-133BGXC
BG119 Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables
and JTAG
CY7C1381D-133BZXC
BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x
1.4mm) 3 Chip Enables and JTAG
CY7C1383D-133BZXC
100
CY7C1381D-100AXC
CY7C1383D-100AXC
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3
Commercial
Chip Enables
CY7C1381D-100BGC
CY7C1383D-100BGC
CY7C1381D-100BZC
CY7C1383D-100BZC
CY7C1381D-100BGXC
CY7C1383D-100BGXC
CY7C1381D-100BZXC
CY7C1383D-100BZXC
BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
BG119 Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables
and JTAG
BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x
1.4mm) 3 Chip Enables and JTAG
Notes:
29. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
30. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05544 Rev. *A
Page 25 of 29
PRELIMINARY
CY7C1381D
CY7C1383D
Ordering Information (continued)
Speed
Package
Operating
Range
Industrial
(MHz)
Ordering Code
CY7C1381D-100AXI
CY7C1383D-100AXI
CY7C1381D-100BGI
CY7C1383D-100BGI
CY7C1381D-100BZI
CY7C1383D-100BZI
CY7C1381D-100BGXI
CY7C1383D-100BGXI
CY7C1381D-100BZXI
CY7C1383D-100BZXI
Name
Part and Package Type
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3
100
A101
Chip Enables
BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
BG119 Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables
and JTAG
BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x
1.4mm) 3 Chip Enables and JTAG
Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.
Lead-free BG packages (ordering Code:BGX) will be available in 2005.
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
DIMENSIONS ARE IN MILLIMETERS.
ꢁ6.00 0.20
ꢁ4.00 0.ꢁ0
ꢁ.40 0.05
ꢁ00
ꢀꢁ
ꢀ0
ꢁ
0.30 0.0ꢀ
0.65
TYP.
ꢁ2° ꢁ°
SEE DETAIL
A
(ꢀX)
30
5ꢁ
3ꢁ
50
0.20 MAX.
ꢁ.60 MAX.
R 0.0ꢀ MIN.
0.20 MAX.
0° MIN.
STAND-OFF
0.05 MIN.
0.ꢁ5 MAX.
SEATING PLANE
0.25
GAUGE PLANE
R 0.0ꢀ MIN.
0.20 MAX.
0°-7°
0.60 0.ꢁ5
ꢁ.00 REF.
0.20 MIN.
51-85050-*A
DETAIL
A
Document #: 38-05544 Rev. *A
Page 26 of 29
PRELIMINARY
CY7C1381D
CY7C1383D
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05544 Rev. *A
Page 27 of 29
PRELIMINARY
CY7C1381D
CY7C1383D
Package Diagrams (continued)
165 FBGA 13 x 15 x 1.40 MM BB165D
51-85180-**
i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05544 Rev. *A
Page 28 of 29
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
CY7C1381D
CY7C1383D
Document History Page
Document Title: CY7C1381D/CY7C1383D 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
Document Number: 38-05544
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
254518
See ECN
RKF
New data sheet
*A
288531
See ECN
SYT
Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for
non-compliance with 1149.1
Removed 117 Mhz Speed Bin
Added lead-free information for 100-Pin TQFP, 119 BGA and 165 FBGA
package
Added comment of ‘Lead-free BG packages availability’ below the Ordering
Information
Document #: 38-05544 Rev. *A
Page 29 of 29
相关型号：
CY7C1381D-100AXCT
Standard SRAM, 512KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100
CYPRESS
CY7C1381D-100BGCT
Cache SRAM, 512KX36, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
CYPRESS
CY7C1381D-100BGIT
Cache SRAM, 512KX36, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
CYPRESS
CY7C1381D-100BZIT
Standard SRAM, 512KX36, 8.5ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
CYPRESS
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