CY7C1480V33-250BZC [CYPRESS]
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; 72兆位（ 2M ×36 / 4M ×18 / 1M X 72 ），流水线同步SRAM
| 型号： | CY7C1480V33-250BZC |
| 厂家： | 
CYPRESS |
| 描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| 文件： | 总30页 (文件大小：399K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined
Sync SRAM
Features
Functional Description[1]
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200,167 MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply
The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM
integrates 2,097,152 x 36/4,194,304 x 18,1,048,576 × 72
SRAM cells with advanced synchronous peripheral circuitry
and a two-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
Chip Enable (CE1), depth-expansion Chip Enables (CE2 and
CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (BWX, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the
ZZ pin.
• 2.5V / 3.3V I/O operation
• Fast clock-to-output times
— 3.0 ns (for 250-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.4 ns (for 167-MHz device)
• Provide high-performance 3-1-1-1 access rate
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
• User-selectable burst counter supporting Intel®
Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active
• Asynchronous output enable
• Single Cycle Chip Deselect
• CY7C1480V33 and CY7C1482V33 offered in
JEDEC-standardlead-free100-pinTQFP, 165-BallfBGA
packages. CY7C1486V33 available in 209-Ball BGA
packages
causes all bytes to be written.
LOW
The CY7C1480V33/CY7C1482V33/CY7C1486V33 operates
from a +3.3V core power supply while all outputs may operate
with either a +2.5 or +3.3V supply. All inputs and outputs are
JEDEC-standard JESD8-5-compatible.
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option
Selection Guide
250 MHz
3.0
200 MHz
3.0
167 MHz
3.4
Unit
ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Shaded areas contain advance information.
500
500
450
mA
mA
120
120
120
Please contact your local Cypress sales representative for availability of these parts.
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05283 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised December 3, 2004
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
1
Logic Block Diagram – CY7C1480V33 (2M x 36)
A0, A1, A
ADDRESS
REGISTER
2
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER
AND
CLR
Q0
LOGIC
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D ,DQPD
DQ
BYTE
WRITE DRIVER
D ,DQPD
BW
D
DQC ,DQP
BYTE
WRITE DRIVER
C
DQC ,DQP
BYTE
WRITE REGISTER
C
BW
C
OUTPUT
BUFFERS
OUTPUT
REGISTERS
MEMORY
ARRAY
DQ s
SENSE
AMPS
DQPA
DQB ,DQP
BYTE
WRITE DRIVER
B
E
DQB ,DQP
BYTE
WRITE REGISTER
B
DQP
DQP
B
C
BW
BW
B
A
DQPD
DQ
BYTE
WRITE DRIVER
A ,DQPA
DQ
A ,DQPA
BYTE
WRITE REGISTER
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE
CE
CE
1
2
3
OE
SLEEP
CONTROL
ZZ
2
Logic Block Diagram – CY7C1482V33 (4M x 18)
ADDRESS
A0, A1, A
REGISTER
A[1:0]
2
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQB,DQP
B
DQB,DQP
WRITE REGISTER
B
WRITE DRIVER
OUTPUT
BUFFERS
BW
B
A
DQs
DQP
DQP
OUTPUT
REGISTERS
SENSE
AMPS
MEMORY
ARRAY
A
B
DQA,DQP
A
E
DQA,DQP
WRITE REGISTER
A
WRITE DRIVER
BW
BWE
GW
INPUT
REGISTERS
ENABLE
REGISTER
CE1
CE2
PIPELINED
ENABLE
CE3
OE
ZZ
SLEEP
CONTROL
Document #: 38-05283 Rev. *C
Page 2 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Logic Block Diagram – CY7C1486V33 (1M x 72)
ADDRESS
REGISTER
A0, A1,A
A[1:0]
MODE
Q1
ADV
CLK
BINARY
COUNTER
CLR
Q0
ADSC
ADSP
DQ
WRITE DRIVER
H
, DQP
H
DQ
WRITE DRIVER
H, DQPH
BW
BW
H
G
DQG, DQPG
WRITE DRIVER
DQF, DQPF
WRITE DRIVER
DQF, DQPF
WRITE DRIVER
DQF, DQPF
WRITE DRIVER
BW
BW
F
E
DQ E
E
, DQP
WRITE DRIVER
DQE, DQPE
WRITE DRIVER
MEMORY
ARRAY
DQD, DQPD
WRITE DRIVER
DQD, DQPD
WRITE DRIVER
BW
D
DQC, DQPC
WRITE DRIVER
DQC, DQPC
WRITE DRIVER
BW
C
OUTPUT
BUFFERS
OUTPUT
REGISTERS
SENSE
AMPS
DQs
DQP
DQP
DQP
DQP
DQP
DQP
DQP
DQP
A
B
C
D
E
E
DQB, DQPB
WRITE DRIVER
DQB, DQPB
WRITE DRIVER
BW
BW
B
A
DQA, DQPA
WRITE DRIVER
DQ
WRITE DRIVER
A
, DQP
A
F
G
H
BWE
INPUT
REGISTERS
GW
CE1
CE2
CE3
OE
ENABLE
REGISTER
PIPELINED
ENABLE
SLEEP
CONTROL
ZZ
Document #: 38-05283 Rev. *C
Page 3 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Pin Configurations
100-pin TQFP Pinout
DQPC
1
DQP
B
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
VDDQ
VSSQ
NC
A
NC
NC
VDDQ
VSSQ
NC
DQP
DQ
DQ
VSSQ
VDDQ
DQ
DQ
VSS
NC
VDD
ZZ
DQ
DQ
VDDQ
VSSQ
DQ
DQ
NC
NC
VSSQ
VDDQ
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
DQB
2
3
4
5
6
7
8
9
DQc
VDDQ
VSSQ
DQB
VDDQ
VSSQ
DQ
DQ
DQ
DQ
C
DQB
DQB
DQB
DQB
C
NC
A
C
DQB
A
C
DQB
A
9
VSSQ
VDDQ
VSSQ
VDDQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSSQ
VDDQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DQ
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
C
DQB
DQB
A
DQB
DQB
A
VSS
NC
VDD
ZZ
NC
VDD
NC
CY7C1482V33
(4M x 18)
CY7C1480V33
(2M x 36)
VSS
DQA
DQB
A
DQA
DQB
A
VDDQ
VSSQ
VDDQ
VSSQ
DQ
DQ
DQ
DQ
D
DQA
DQA
DQA
DQA
DQ
DQ
DQP
B
B
B
A
D
A
D
D
NC
VSSQ
VDDQ
NC
NC
NC
VSSQ
VDDQ
VSSQ
VDDQ
DQ
DQ
DQP
D
DQA
D
DQA
NC
NC
D
DQP
A
Document #: 38-05283 Rev. *C
Page 4 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Pin Configurations (continued)
165-ball fBGA
CY7C1480V33 (2M x 36)
1
NC / 288M
NC
2
3
4
5
6
7
8
9
10
A
11
NC
A
B
C
D
CE1
BWC
BWD
VSS
VDD
BWB
BWA
VSS
VSS
CE3
CLK
VSS
VSS
ADSC
A
BWE
GW
VSS
ADV
ADSP
VDDQ
VDDQ
A
CE2
VDDQ
VDDQ
A
NC / 144M
DQPB
DQB
OE
VSS
VDD
DQPC
DQC
NC
NC
DQC
VSS
DQB
DQC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
E
F
DQC
DQC
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQB
DQB
ZZ
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
NC
DQD
NC
A
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
TDI
A1
TDO
A0
MODE
A
A
A
TMS
TCK
A
A
A
A
R
CY7C1482V33 (4M x 18)
1
NC / 288M
NC
2
A
3
4
5
NC
6
7
8
9
10
A
11
A
A
BWB
NC
CE
CE1
CE2
BWE
GW
VSS
ADSC
OE
ADV
ADSP
VDDQ
VDDQ
3
A
BWA
VSS
VSS
CLK
VSS
VSS
A
NC / 144M
DQPA
DQA
B
C
D
NC
NC
VDDQ
VDDQ
VSS
VDD
VSS
NC
NC
NC
DQB
VSS
VDD
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQA
E
F
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQA
DQA
ZZ
NC
G
H
J
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
NC
NC
K
L
NC
NC
DQB
DQPB
NC
NC
NC
A
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
A
M
N
P
TDI
A1
TDO
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05283 Rev. *C
Page 5 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Pin Configurations (continued)
209-ball BGA
CY7C1486V33 (1M × 72)
1
2
3
4
5
6
7
8
9
10
11
DQG
DQG
DQG
A
B
C
D
E
F
DQG
DQG
CE3
DQB
DQB
CE2
ADSC
BWE
CE1
DQB
DQB
A
ADSP
NC
ADV
A
A
BWSB
BWSC
BWSH
VSS
BWSF
BWSG
BWSD
DQG
DQG
NC
NC
NC
BWSE
NC
BWSA DQB
DQB
DQB
DQG
GW
OE
VSS
NC
DQB
DQPG DQPC
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD
NC
NC
NC
NC
VSS
NC
NC
VDD
VSS
VDD
DQPF DQPB
DQC
DQC
VSS
DQF
DQF
VSS
VDDQ
VSS
VSS
G
H
J
DQC
DQC
DQC
VDDQ
VSS
VDDQ
VSSQ
DQF
DQF
DQF
DQ
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
A
DQC
DQC
NC
F
VDDQ
DQC
NC
VDDQ
VDDQ
CLK
VDDQ
VSS
VDDQ
NC
DQF
NC
DQF
NC
K
L
NC
NC
DQH
DQH
DQH
VDDQ
VDDQ
VSS
VDDQ
VSS
DQA
DQA
DQ
A
M
N
P
R
T
VSS
VDDQ
VSS
VDDQ
NC
DQH
DQH
DQH
VSS
VDD
VSS
DQA
DQA
DQA
VDDQ
DQH
DQH
DQPD
DQD
DQD
VDDQ
VSS
VDDQ
VSS
NC
ZZ
DQA
DQA
DQPA
DQE
DQE
VSS
VDDQ
VSS
A
VDDQ
VDD
NC
A
DQPH
DQD
DQD
DQD
DQD
VDDQ
VDD
DQPE
DQE
DQE
DQE
DQE
VSS
NC
A
MODE
A
U
V
W
A
A
A
A
A1
A
DQD
DQD
A
A
A
A
DQE
DQE
TDI
TDO
TCK
A0
A
TMS
Document #: 38-05283 Rev. *C
Page 6 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Pin Definitions
Pin Name
I/O
Description
Address Inputs used to select one of the address locations. Sampled at the rising
A0, A1, A
Input-
Synchronous edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled
active. A1: A0 are fed to the two-bit counter.
BWA,BWB,BWC,BWD,
BWE,BWF,BWG,BWH
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to
Synchronous the SRAM. Sampled on the rising edge of CLK.
GW
Input- Global Write Enable Input, active LOW. When asserted LOW on the rising edge of
Synchronous CLK, a global write is conducted (ALL bytes are written, regardless of the values on
BWX and BWE).
BWE
CLK
CE1
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
Synchronous must be asserted LOW to conduct a byte write.
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is
HIGH.
CE2
CE3
OE
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE3 to select/deselect the device.
Input- Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE2 to select/deselect the device.
Input- Output Enable, asynchronous input, active LOW. Controls the direction of the I/O
Asynchronous pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are
tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle
when emerging from a deselected state.
ADV
Input-
Advance Input signal, sampled on the rising edge of CLK, active LOW. When
Synchronous asserted, it automatically increments the address in a burst cycle.
ADSP
Input- Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.
Synchronous When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted
HIGH.
ADSC
Input-
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
Synchronous When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized.
ZZ
Input-
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
I/O-
Synchronous triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
DQs, DQPs
clock rise
of the read cycle. The direction of the pins is controlled by OE. When OE is asserted
LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state
condition.
VDD
Power Supply Power supply inputs to the core of the device.
VSS
Ground
Ground for the core of the device.
VSSQ
VDDQ
I/O Ground Ground for the I/O circuitry.
I/O Power
Supply
Power supply for the I/O circuitry.
MODE
Input Static Selects Burst Order. When tied to GND selects linear burst sequence. When tied to
DD or left floating selects interleaved burst sequence. This is a strap pin and should
remain static during device operation. Mode Pin has an internal pull-up.
V
Document #: 38-05283 Rev. *C
Page 7 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Pin Definitions (continued)
Pin Name
I/O
JTAG Serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
Output JTAG feature is not being utilized, this pin should be disconnected. This pin is not
Description
TDO
Synchronous available on TQFP packages.
TDI
JTAG Serial Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
Input
feature is not being utilized, this pin can be disconnected or connected to VDD. This pin
Synchronous is not available on TQFP packages.
TMS
TCK
JTAG Serial Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
Input
feature is not being utilized, this pin can be disconnected or connected to VDD. This pin
Synchronous is not available on TQFP packages.
JTAG Clock Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin
must be connected to VSS. This pin is not available on TQFP packages.
NC
-
No Connects. Not internally connected to the die
access. After the first cycle of the access, the outputs are
Functional Overview
controlled by the OE signal. Consecutive single Read cycles
are supported. Once the SRAM is deselected at clock rise by
the chip select and either ADSP or ADSC signals, its output
will tri-state immediately.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 3.0 ns
(250-MHz device).
Single Write Accesses Initiated by ADSP
The CY7C1480V33/CY7C1482V33/CY7C1486V33 supports
secondary cache in systems utilizing either a linear or inter-
leaved burst sequence. The interleaved burst order supports
Pentium and i486™ processors. The linear burst sequence is
suited for processors that utilize a linear burst sequence. The
burst order is user selectable, and is determined by sampling
the MODE input. Accesses can be initiated with either the
Processor Address Strobe (ADSP) or the Controller Address
Strobe (ADSC). Address advancement through the burst
sequence is controlled by the ADV input. A two-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the
rest of the burst access.
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE1, CE2, CE3 are all asserted active. The address
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The Write signals (GW, BWE, and BWX) and
ADV inputs are ignored during this first cycle.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corre-
sponding address location in the memory array. If GW is HIGH,
then the Write operation is controlled by BWE and BWX
signals.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
The CY7C1480V33/CY7C1482V33/CY7C1486V33 provides
Byte Write capability that is described in the Write Cycle
Descriptions table. Asserting the Byte Write Enable input
(BWE) with the selected Byte Write (BWX) input, will selec-
tively write to only the desired bytes. Bytes not selected during
a Byte Write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify the
Write operations.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Because CY7C1480V33/CY7C1482V33/CY7C1486V33 is a
common I/O device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so will tri-state the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a Write
cycle is detected, regardless of the state of OE.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the Write
signals (GW, BWE) are all deasserted HIGH. ADSP is ignored
if CE1 is HIGH. The address presented to the address inputs
(A) is stored into the address advancement logic and the
Address Register while being presented to the memory array.
The corresponding data is allowed to propagate to the input of
the Output Registers. At the rising edge of the next clock the
data is allowed to propagate through the output register and
onto the data bus within 3.0 ns (250-MHz device) if OE is
active LOW. The only exception occurs when the SRAM is
emerging from a deselected state to a selected state, its
outputs are always tri-stated during the first cycle of the
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active,
and (4) the appropriate combination of the Write inputs (GW,
BWE, and BWX) are asserted active to conduct a Write to the
desired byte(s). ADSC-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the memory array.
Document #: 38-05283 Rev. *C
Page 8 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
The ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to the DQs is written into the
corresponding address location in the memory core. If a Byte
Write is conducted, only the selected bytes are written. Bytes
not selected during a Byte Write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Interleaved Burst Address Table
Because CY7C1480V33/CY7C1482V33/CY7C1486V33 is a
common I/O device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so will tri-state the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a Write
cycle is detected, regardless of the state of OE.
(MODE = Floating or VDD
)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Burst Sequences
The CY7C1480V33/CY7C1482V33/CY7C1486V33 provides
a two-bit wraparound counter, fed by A1: A0, that implements
either an interleaved or linear burst sequence. The interleaved
burst sequence is designed specifically to support Intel
Pentium applications. The linear burst sequence is designed
to support processors that follow a linear burst sequence. The
burst sequence is user selectable through the MODE input.
Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
Test Conditions
ZZ > VDD – 0.2V
Min.
Max.
Unit
mA
ns
120
tZZS
ZZ > VDD – 0.2V
2tCYC
tZZREC
tZZI
ZZ recovery time
ZZ < 0.2V
2tCYC
0
ns
ZZ Active to Sleep current
ZZ Inactive to exit Sleep current
This parameter is sampled
This parameter is sampled
2tCYC
ns
tRZZI
ns
Document #: 38-05283 Rev. *C
Page 9 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Truth Table[ 2, 3, 4, 4, 5, 6]
Operation
Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Sleep Mode, Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle,Suspend Burst
None
None
H
L
X
L
X
X
H
X
H
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
None
L
X
L
L
None
L
H
H
X
L
None
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
L
X
X
X
L
X
Tri-State
Q
External
External
External
External
External
Next
L-H
L
L
L
H
X
L
L-H Tri-State
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H
L-H
D
Q
L
L
L
H
H
H
H
H
H
L
L
L
L
H
L
L-H Tri-State
L-H
L-H Tri-State
L-H
L-H Tri-State
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L-H
L-H
L-H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H Tri-State
L-H
L-H Tri-State
Q
H
X
X
L-H
L-H
D
D
WRITE Cycle,Suspend Burst
L
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the signal. is asynchronous and is not sampled with the clock.
OE
OE
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks
X
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
7. BWx represents any byte write signal.To enable any byte write BWx, a Logic LOW signal should be applied at clock rise. Any number of byte writes can be
enabled at the same time for any given write.
Document #: 38-05283 Rev. *C
Page 10 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Truth Table for Read/Write[4]
Function (CY7C1480V33)
Read
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
BWD
X
H
H
H
H
H
H
H
H
L
BWC
X
H
H
H
H
L
BWB
X
H
H
L
BWA
X
H
L
Read
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Bytes B, A
L
L
H
L
L
L
Write Byte C – (DQC and DQPC)
Write Bytes C, A
L
H
H
L
H
L
L
L
Write Bytes C, B
L
L
H
L
Write Bytes C, B, A
Write Byte D – (DQD and DQPD)
Write Bytes D, A
L
L
L
L
H
H
H
H
L
H
H
L
H
L
L
L
Write Bytes D, B
L
L
H
L
Write Bytes D, B, A
Write Bytes D, C
L
L
L
L
L
H
H
L
H
L
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
L
L
L
L
L
L
H
L
L
L
L
L
Write All Bytes
X
X
X
X
X
Truth Table for Read/Write[4]
Function (CY7C1482V33)
Read
GW
H
BWE
BWB
X
BWA
H
L
L
L
L
L
X
X
H
L
Read
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Bytes B, A
H
H
H
L
H
L
H
L
Write All Bytes
H
L
L
Write All Bytes
L
X
X
Document #: 38-05283 Rev. *C
Page 11 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Test MODE SELECT (TMS)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
The CY7C1480V33/CY7C1482V33 incorporates a serial
boundary scan test access port (TAP). This port operates in
accordance with IEEE Standard 1149.1-1990 but does not
have the set of functions required for full 1149.1 compliance.
These functions from the IEEE specification are excluded
because their inclusion places an added delay in the critical
speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
(See Tap Controller Block Diagram.)
The CY7C1480V33/CY7C1482V33 contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
Test Data-Out (TDO)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
TAP Controller State Diagram
0
Bypass Register
TEST-LOGIC
1
RESET
0
2
1
0
0
0
1
1
1
Selection
Circuitry
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
Instruction Register
31 30 29
Identification Register
0
S
election
TDI
TDO
Circuitr
y
0
0
.
.
. 2 1
1
1
CAPTURE-DR
CAPTURE-IR
0
0
x
.
.
.
.
. 2 1
SHIFT-DR
0
SHIFT-IR
0
Boundary Scan Register
1
1
1
1
EXIT1-DR
EXIT1-IR
TCK
TMS
0
0
TAP CONTROLLER
PAUSE-DR
0
PAUSE-IR
0
1
1
0
0
EXIT2-DR
1
EXIT2-IR
1
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
UPDATE-DR
UPDATE-IR
1
0
1
0
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
TAP Registers
Test Access Port (TAP)
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Document #: 38-05283 Rev. *C
Page 12 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Instruction Register
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
IDCODE
Boundary Scan Register
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The x36 configuration has a
73-bit-long register, and the x18 configuration has
54-bit-long register.
a
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.
SAMPLE/PRELOAD
Identification (ID) Register
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the device TAP controller is not fully 1149.1 compliant.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls
is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold time (tCS plus tCH).
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
Document #: 38-05283 Rev. *C
Page 13 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
possible to capture all other signals and simply ignore the
BYPASS
value of the CLK captured in the boundary scan register.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the
same effect as the Pause-DR command.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
[ , ]
TAP AC Switching Characteristics Over the Operating Range 8 9
Parameter
Clock
tTCYC
tTF
Description
Min.
Max.
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
20
tTH
25
25
tTL
ns
Output Times
tTDOV TCK Clock LOW to TDO Valid
tTDOX TCK Clock LOW to TDO Invalid
Set-up Times
tTMSS TMS Set-up to TCK Clock Rise
tTDIS
5
ns
ns
0
5
5
5
ns
ns
ns
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
tCH
Capture Hold after Clock Rise
Notes:
8. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
9. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
Document #: 38-05283 Rev. *C
Page 14 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ............................................... .VSS to 3.3V
Input rise and fall times................................................... 1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
Input pulse levels.................................................VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels......................................... 1.25V
Output reference levels ................................................ 1.25V
Test load termination supply voltage ............................ 1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
ZO= 50Ω
ZO= 50Ω
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.135 to 3.6V unless otherwise noted)[10]
Parameter
VOH1
Description
Output HIGH Voltage IOH = –4.0 mA, VDDQ = 3.3V
OH = –1.0 mA, VDDQ = 2.5V
Test Conditions
Min.
2.4
2.0
2.9
2.1
Max.
Unit
V
I
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage IOH = –100 µA
VDDQ = 3.3V
DDQ = 2.5V
V
V
V
Output LOW Voltage IOL = 8.0 mA
IOL = 1.0 mA
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
0.4
0.4
V
V
Output LOW Voltage IOL = 100 µA
0.2
V
V
DDQ = 2.5V
VDDQ = 3.3V
DDQ = 2.5V
0.2
V
Input HIGH Voltage
Input LOW Voltage
2.0
1.7
VDD + 0.3
VDD + 0.3
0.8
V
V
V
VIL
VDDQ = 3.3V
VDDQ = 2.5V
–0.3
–0.3
–5
V
0.7
V
IX
Input Load Current
GND < VIN < VDDQ
5
µA
Identification Register Definitions
CY7C1480V33 CY7C1482V33 CY7C1486V33
Instruction Field
Revision Number (31:29)
Device Depth (28:24)
(2M x36)
(4M x 18)
(1M x72)
Description
000
000
000
Describes the version number
Reserved for internal use
01011
01011
01011
Architecture/Memory Type(23:18)
Bus Width/Density(17:12)
Cypress JEDEC ID Code (11:1)
000000
100100
000000
010100
000000
110100
Defines memory type and architecture
Defines width and density
00000110100 00000110100 00000110100 Allows unique identification of SRAM
vendor
ID Register Presence Indicator (0)
1
1
1
Indicates the presence of an ID register
Notes:
10. All voltages referenced to V (GND).
SS
11. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
Document #: 38-05283 Rev. *C
Page 15 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Bit Size (x72)
Instruction
3
1
3
1
3
1
Bypass
ID
32
73
-
32
54
-
32
-
Boundary Scan Order-165FBGA
Boundary Scan Order-209BGA
112
Identification Codes
Instruction
EXTEST
Code
000
Description
Captures the I/O ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Boundary Scan Order (x36) (continued)
Boundary Scan Order (x36)
Bit #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
165-Ball ID
N6
Bit #
1
2
3
4
5
6
7
8
165-Ball ID
C1
D1
E1
P11
R8
P3
P4
P8
P9
P10
R9
R10
R11
N11
M11
L11
M10
L10
K11
J11
K10
J10
H11
G11
F11
E11
D10
D2
E2
F1
G1
F2
G2
J1
K1
L1
J2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
M1
N1
K2
L2
M2
R1
R2
R3
P2
R4
P6
R6
Document #: 38-05283 Rev. *C
Page 16 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Boundary Scan Order (x36) (continued)
Boundary Scan Order (x18) (continued)
Bit #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
165-Ball ID
D11
C11
G10
F10
E10
A10
B10
A9
Bit #
165-Ball ID
R9
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
R10
R11
M10
L10
K10
J10
H11
G11
F11
E11
D11
C11
A11
A10
B10
A9
B9
A8
B8
A7
B7
B6
A6
B5
B9
A8
B8
A7
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
Boundary Scan Order (x18)
Bit #
1
2
3
4
165-Ball ID
D2
A4
B3
A3
A2
E2
F2
G2
J1
B2
5
Boundary Scan Exit Order (x72)
6
K1
7
8
9
L1
M1
N1
Bit #
1
2
209-Ball ID
A1
A2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
R1
R2
R3
P2
R4
P6
R6
N6
P11
R8
P3
P4
P8
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
B1
B2
C1
C2
D1
D2
E1
E2
F1
F2
G1
G2
H1
H2
J1
P9
P10
Document #: 38-05283 Rev. *C
Page 17 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Boundary Scan Exit Order (x72) (continued)
Boundary Scan Exit Order (x72) (continued)
Bit #
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
209-Ball ID
J2
Bit #
68
69
209-Ball ID
M11
M10
L11
L10
P6
L1
L2
70
M1
M2
N1
N2
P1
P2
R2
R1
T1
T2
U1
U2
V1
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
J11
J10
H11
H10
G11
G10
F11
F10
E10
E11
D11
D10
C11
C10
B11
B10
A11
A10
A9
U8
A7
A5
A6
D6
B6
D7
K3
A8
B4
B3
C3
C4
C8
C9
B9
B8
A4
C6
B7
V2
W1
W2
T6
V3
V4
U4
W5
V6
W6
U3
U9
V5
U5
U6
W7
V7
U7
V8
V9
W11
W10
V11
V10
U11
U10
T11
T10
R11
R10
P11
P10
N11
N10
99
100
101
102
103
104
105
106
107
108
109
110
111
112
A3
Document #: 38-05283 Rev. *C
Page 18 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current..................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Supply Voltage on VDD Relative to GND........ –0.3V to +4.6V
Range
Temperature
VDD
VDDQ
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%
to VDD
DC Input Voltage....................................–0.5V to VDD + 0.5V
Electrical Characteristics Over the Operating Range[12, 13]
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
2.4
Max.
3.6
Unit
V
VDDQ
VDDQ = 3.3V
DDQ = 2.5V
VDD
V
V
2.625
V
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
V
2.0
V
Output LOW Voltage
0.4
0.4
V
V
DDQ = 2.5V, VDD = Min., IOL = 1.0 mA
Input HIGH Voltage[12] VDDQ = 3.3V
DDQ = 2.5V
V
2.0
1.7
VDD + 0.3V
VDD + 0.3V
0.8
V
V
V
Input LOW Voltage[12]
VDDQ = 3.3V
–0.3
–0.3
–5
V
VDDQ = 2.5V
0.7
V
Input Load Current
except ZZ and MODE
GND ≤ VI ≤ VDDQ
5
µA
Input Current of MODE Input = VSS
Input = VDD
–5
–30
–5
µA
µA
30
Input Current of ZZ
Input = VSS
Input = VDD
µA
5
µA
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
5
µA
VDD Operating Supply VDD = Max., IOUT = 0 mA,
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
All speeds
500
500
450
245
245
245
120
mA
mA
mA
mA
mA
mA
mA
Current
f = fMAX = 1/tCYC
ISB1
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
ISB2
Automatic CE
Power-down
Current—CMOS Inputs f = 0
VDD = Max, Device Deselected,
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
ISB3
Automatic CE
Power-down
Current—CMOS Inputs f = fMAX = 1/tCYC
V
DD = Max, Device Deselected, or 4.0-ns cycle, 250 MHz
245
245
245
135
mA
mA
mA
mA
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
All speeds
ISB4
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
Shaded areas contain advance information.
Notes:
12. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > –2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
< V
DD\
13. Power-up: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
DD
IH
DD
DDQ
Document #: 38-05283 Rev. *C
Page 19 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Thermal Resistance[14]
TQFP
Package
209-BGA
Package
fBGA
Package
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard
test methods and procedures
for measuring thermal
24.63
2.28
15.2
16.3
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
1.7
2.1
°C/W
impedance, per EIA / JESD51.
Capacitance[14]
TQFP
Max.
209-BGA
Max.
165-fBGA
Max.
Parameter
Description
Test Conditions
Unit
pF
CADDRESS
CDATA
CCTRL
CCLK
Address Input Capacitance TA = 25°C, f = 1 MHz,
6
5
8
6
5
6
5
8
6
5
6
5
8
6
5
V
DD = 3.3V
VDDQ = 2.5V
Data Input Capacitance
Control Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
pF
pF
pF
CI/O
pF
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
R = 50Ω
L
5 pF
R = 351Ω
≤ 1ns
≤ 1ns
V = 1.5V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50Ω
0
10%
L
GND
5 pF
R =1538Ω
≤ 1ns
≤ 1ns
V = 1.25V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note:
14. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05283 Rev. *C
Page 20 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Switching Characteristics Over the Operating Range[19, 20]
250 MHz
200 MHz
167 MHz
Parameter
tPOWER
Clock
tCYC
Description
VDD(Typical) to the first access[15]
Min. Max. Min. Max. Min. Max.
Unit
1
1
1
ms
Clock Cycle Time
Clock HIGH
4.0
2.0
2.0
5.0
2.0
2.0
6.0
2.4
2.4
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCO
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[16, 17, 18]
3.0
3.0
3.4
ns
ns
ns
ns
ns
ns
ns
tDOH
1.3
1.3
1.3
1.3
1.5
1.5
tCLZ
tCHZ
Clock to High-Z[16, 17, 18]
3.0
3.0
3.0
3.0
3.4
3.4
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
Set-up Times
tAS
OE LOW to Output Low-Z[16, 17, 18]
OE HIGH to Output High-Z[16, 17, 18]
0
0
0
3.0
3.0
3.4
Address Set-up Before CLK Rise
ADSC, ADSP Set-up Before CLK Rise
ADV Set-up Before CLK Rise
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
tADS
tADVS
tWES
GW, BWE, BWX Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK Rise
tDS
tCES
Hold Times
tAH
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
ADV Hold After CLK Rise
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tADH
tADVH
tWEH
GW, BWE, BWX Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
tDH
tCEH
Shaded areas contain advance information.
Notes:
15. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V (minimum) initially before a read or write operation
DD
POWER
can be initiated.
16. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
OEHZ
CHZ CLZ OELZ
17. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
OEHZ
OELZ
CHZ
CLZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
18. This parameter is sampled and not 100% tested.
19. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
20. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05283 Rev. *C
Page 21 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Switching Waveforms
Read Cycle Timing[21]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,
BWx
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV
suspends
burst.
t
t
OEV
CO
t
t
OEHZ
t
OELZ
t
CHZ
DOH
t
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A1)
Data Out (Q)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note:
21. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05283 Rev. *C
Page 22 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Switching Waveforms (continued)
Write Cycle Timing[21, 22]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
ADDRESS
BWE,
t
t
AH
AS
A1
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BW
X
t
t
WEH
WES
GW
CE
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
Data In (D)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
Note:
22.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
X
Document #: 38-05283 Rev. *C
Page 23 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Switching Waveforms (continued)
Read/Write Cycle Timing[21, 23, 24]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
BWE,
t
t
WEH
WES
BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back READs
Single WRITE
BURST READ
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
Notes:
23. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
24. GW is HIGH.
Document #: 38-05283 Rev. *C
Page 24 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Switching Waveforms (continued)
ZZ Mode Timing[27, 28]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
25. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
26. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05283 Rev. *C
Page 25 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Part and Package Type
250
CY7C1480V33-250AXC
CY7C1482V33-250AXC
A101
Lead-Free 100-lead 14 × 20 × 1.4 mm Thin Quad Flat
Pack
Commercial
CY7C1486V33-250BGC
BB209A 209-ball BGA (14 × 22 × 1.76 mm)
BB165C 165 fBGA(15 x 17 x1.4 mm)
CY7C1480V33-250BZC
CY7C1482V33-250BZC
CY7C1486V33-250BGXC
BB209A Lead-Free 209-ball BGA (14 × 22 × 1.76 mm)
BB165C Lead-Free 165 fBGA(15 x 17 x1.4 mm)
CY7C1480V33-250BZXC
CY7C1482V33-250BZXC
200
CY7C1480V33-200AXC
CY7C1482V33-200AXC
A101
Lead-Free 100-lead 14 × 20 × 1.4 mm Thin Quad Flat
Pack
CY7C1486V33-200BGC
BB209A 209-ball BGA (14 × 22 × 1.76 mm)
BB165C 165 fBGA(15 x 17 x1.4 mm)
CY7C1480V33-200BZC
CY7C1482V33-200BZC
CY7C1486V33-200BGXC
BB209A Lead-Free 209-ball BGA (14 × 22 × 1.76 mm)
BB165C Lead-Free 165 fBGA(15 x 17 x1.4 mm)
CY7C1480V33-200BZXC
CY7C1482V33-200BZXC
167
CY7C1480V33-167AXC
CY7C1482V33-167AXC
A101
Lead-Free 100-lead 14 × 20 × 1.4 mm Thin Quad Flat
Pack
CY7C1486V33-167BGC
BB209A 209-ball BGA (14 × 22 × 1.76 mm)
BB165C 165 fBGA(15 x 17x1.4 mm)
CY7C1480V33-167BZC
CY7C1482V33-167BZC
CY7C1486V33-167BGXC
BB209A Lead-Free 209-ball BGA (14 × 22 × 1.76 mm)
BB165C Lead-Free 165 fBGA(15 x 17x1.4 mm)
CY7C1480V33-167BZXC
CY7C1482V33-167BZXC
Shaded areas contain advance information.
Please contact your local sales representative for availability of these parts.
Lead-free BG packages (Ordering Code: BGX) will be available in 2005.
Notes:
27. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
28. DQs are in high-Z when exiting ZZ sleep mode
Document #: 38-05283 Rev. *C
Page 26 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
DIMENSIONS ARE IN MILLIMETERS.
ꢁ6.00 0.20
ꢁ4.00 0.ꢁ0
ꢁ.40 0.05
ꢁ00
ꢀꢁ
ꢀ0
ꢁ
0.30 0.0ꢀ
0.65
TYP.
ꢁ2° ꢁ°
(ꢀX)
SEE DETAIL
A
30
5ꢁ
3ꢁ
50
0.20 MAX.
ꢁ.60 MAX.
R 0.0ꢀ MIN.
0.20 MAX.
0° MIN.
STAND-OFF
0.05 MIN.
0.ꢁ5 MAX.
SEATING PLANE
0.25
GAUGE PLANE
R 0.0ꢀ MIN.
0.20 MAX.
0°-7°
0.60 0.ꢁ5
0.20 MIN.
ꢁ.00 REF.
51-85050-*A
DETAIL
A
Document #: 38-05283 Rev. *C
Page 27 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Package Diagrams (continued)
209-Ball FBGA (14 x 22 x 1.76 mm) BB209A
51-85167-**
Document #: 38-05283 Rev. *C
Page 28 of 30
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Package Diagrams (continued)
165-Ball FBGA (15 x 17 x 1.40 mm) BB165C
PIN ꢁ CORNER
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
PIN ꢁ CORNER
Ø0.25 M C A B
Ø0.45 0.05(ꢁ65X)
ꢁ
2
3
4
5
6
7
ꢀ
9
ꢁ0
ꢁꢁ
ꢁꢁ ꢁ0
9
ꢀ
7
6
5
4
3
2
ꢁ
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
ꢁ.00
5.00
ꢁ0.00
B
ꢁ5.00 0.ꢁ0
0.ꢁ5(4X)
SEATING PLANE
C
51-85165-*A
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05283 Rev. *C
Page 29 of 30
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Document History Page
Document Title: CY7C1480V33/CY7C1482V33/CY7C1486V3372-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
Document Number: 38-05283
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
114670
118281
08/06/02
01/21/03
PKS
HGK
New Data Sheet
*A
Changed tCO from 2.4 to 2.6 ns for 250 MHz
Updated features on page 1 for package offering
Removed 30-MHz offering
Updated Ordering Information
Changed Advanced Information to Preliminary
*B
233368
See ECN
NJY
Changed timing diagrams
Changed logic block diagrams
Modified Functional Description
Modified “Functional Overview” section
Added boundary scan order for all packages
Included thermal numbers and capacitance values for all packages
Included IDD and ISB values
Removed 250-MHz speed grade offering and included 225-MHz speed bin
Changed package outline for 165FBGA package and 209-ball BGA package
Removed 119-BGA package offering
*C
299452
See ECN
SYT
Removed 225-MHz offering and included 250-MHz speed bin
Changed tCYC from 4.4 ns to 4.0 ns for 250-MHz Speed Bin
Changed ΘJA from 16.8 to 24.63 °C/W and ΘJC from 3.3 to 2.28 °C/W for 100
TQFP Package on Page # 20
Added lead-free information for 100-Pin TQFP, 165 FBGA and 209 BGA
Packages.
Added comment of ‘Lead-free BG packages availability’ below the Ordering
Information
Document #: 38-05283 Rev. *C
Page 30 of 30
相关型号：
CY7C1481BV33-133BZI
Cache SRAM, 2MX36, 6.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
CYPRESS
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