CY7C1487V33-100BGXC [CYPRESS]
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM; 72兆位（ 2M ×36 / 4M ×18 / 1M X 72 ）流通型SRAM
| 型号： | CY7C1487V33-100BGXC |
| 厂家： | 
CYPRESS |
| 描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM |
| 文件： | 总30页 (文件大小：1269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1481V33
CY7C1483V33
CY7C1487V33
72-Mbit (2M x 36/4M x 18/1M x 72)
Flow-Through SRAM
Features
Functional Description[1]
• Supports 133 MHz bus operations
• 2M x 36/4M x 18/1M x 72 common IO
The CY7C1481V33/CY7C1483V33/CY7C1487V33 is a 3.3V,
2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM
designed to interface with high speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133 MHz version). A two-bit on-chip counter captures
the first address in a burst and increments the address
automatically for the rest of the burst access. All synchronous
• 3.3V core power supply (VDD
)
• 2.5V or 3.3V I/O supply (VDDQ
• Fast clock-to-output times
— 6.5 ns (133 MHz version)
)
inputs are gated by registers controlled by
a
• Provide high-performance 2-1-1-1 access rate
• User selectable burst counter supporting Intel® Pentium®
interleaved or linear burst sequences
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
Chip Enable (CE1), depth-expansion Chip Enables (CE2 and
CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (BWx and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the
ZZ pin.
• Separate processor and controller address strobes
• Synchronous self timed write
• Asynchronous output enable
• CY7C1481V33, CY7C1483V33 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package. CY7C1487V33
available in Pb-free and non-Pb-free 209 ball FBGA
package
The CY7C1481V33/CY7C1483V33/CY7C1487V33 allows
either interleaved or linear burst sequences, selected by the
MODE input pin. A HIGH selects an interleaved burst
sequence, while a LOW selects a linear burst sequence. Burst
accesses can be initiated with the Processor Address Strobe
(ADSP) or the cache Controller Address Strobe (ADSC)
inputs. Address advancement is controlled by the Address
Advancement (ADV) input.
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode option
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
) are active. Subsequent
ADSC
The CY7C1481V33/CY7C1483V33/CY7C1487V33 operates
from a +3.3V core power supply while all outputs may operate
with either a +2.5 or +3.3V supply. All inputs and outputs are
JEDEC standard JESD8-5 compatible.
Selection Guide
133 MHz
6.5
100 MHz
8.5
Unit
ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
335
305
mA
mA
150
150
Note
1. For best practices recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation
Document #: 38-05284 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 01, 2007
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CY7C1481V33
CY7C1483V33
CY7C1487V33
Logic Block Diagram – CY7C1481V33 (2M x 36)
ADDRESS
REGISTER
A0, A1,
A
A
[1:0]
MODE
ADV
CLK
Q1
Q0
BURST
COUNTER
AND LOGIC
CLR
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D, DQP D
DQ
BYTE
WRITE REGISTER
D, DQP D
BW
D
DQ
BYTE
WRITE REGISTER
C, DQP C
DQ
BYTE
WRITE REGISTER
C, DQP C
BW
C
OUTPUT
BUFFERS
DQ s
MEMORY
ARRAY
SENSE
AMPS
DQP
DQP
DQP
DQP
A
DQ
BYTE
WRITE REGISTER
B, DQP B
B
C
D
DQ
BYTE
WRITE REGISTER
B, DQP B
BW
B
DQ
BYTE
WRITE REGISTER
A, DQP A
DQ
A, DQPA
BW
A
BYTE
BWE
WRITE REGISTER
INPUT
GW
REGISTERS
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1483V33 (4M x 18)
ADDRESS
REGISTER
A0,A1,A
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
B,DQP B
DQ
B,DQP B
WRITE DRIVER
WRITE REGISTER
BW
B
MEMORY
ARRAY
OUTPUT
BUFFERS
DQs
DQP
DQP
SENSE
AMPS
A
B
DQ
A,DQP A
DQ A,DQP A
WRITE REGISTER
WRITE DRIVER
BW
A
BWE
GW
INPUT
REGISTERS
ENABLE
REGISTER
CE
CE
1
2
3
CE
OE
ZZ
SLEEP
CONTROL
Document #: 38-05284 Rev. *H
Page 2 of 30
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CY7C1481V33
CY7C1483V33
CY7C1487V33
Logic Block Diagram – CY7C1487V33 (1M x 72)
ADDRESS
REGISTER
A0, A1,A
A[1:0]
MODE
Q1
Q0
ADV
CLK
BINARY
COUNTER
CLR
ADSC
ADSP
DQ
H
, DQP
H
DQ
H
, DQP
H
BW
BW
H
G
WRITE DRIVER
WRITE DRIVER
DQ
G
, DQP
G
DQ
F
, DQP
F
WRITE DRIVER
WRITE DRIVER
DQ
F
, DQP
F
DQ
F
, DQP
F
BW
BW
BW
BW
F
E
WRITE DRIVER
WRITE DRIVER
DQ
E
, DQP
E
DQ
E
, DQP
E
WRITE DRIVER
WRITE DRIVER
MEMORY
ARRAY
DQ
D
, DQP
D
DQ
D
, DQP
D
D
WRITE DRIVER
WRITE DRIVER
DQ
C
, DQP
C
DQ
C
, DQP
C
C
WRITE DRIVER
WRITE DRIVER
OUTPUT
BUFFERS
OUTPUT
REGISTERS
SENSE
AMPS
DQs
DQP
DQP
DQP
DQP
DQP
DQP
DQP
DQP
A
B
C
D
E
E
DQ
B
, DQP
B
DQ
B
, DQP
B
WRITE DRIVER
BW
BW
B
WRITE DRIVER
DQ
A
, DQP
A
DQ
A
, DQP
A
F
WRITE DRIVER
A
WRITE DRIVER
G
H
BWE
INPUT
GW
REGISTERS
ENABLE
REGISTER
PIPELINED
ENABLE
CE1
CE2
CE3
OE
SLEEP
CONTROL
ZZ
Document #: 38-05284 Rev. *H
Page 3 of 30
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CY7C1481V33
CY7C1483V33
CY7C1487V33
Pin Configurations
100-Pin TQFP Pinout
DQPC
1
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
VDDQ
VSSQ
NC
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
DQC
VDDQ
VSSQ
DQC
3
4
5
6
DQC
7
NC
DQC
8
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
DQC
9
10
11
9
VSSQ
VDDQ
DQC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
12
DQC
13
NC
14
VDD
15
NC
VDD
ZZ
CY7C1483V33
(4M x 18)
CY7C1481V33
(2Mx 36)
NC
16
VDD
ZZ
VSS
17
DQD
18
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
DQD
19
20
21
VDDQ
VSSQ
DQD
22
DQD
23
DQD
24
DQD
25
26
27
NC
VSSQ
VDDQ
DQD
DQD
29
VSSQ
VDDQ
NC
NC
NC
VSSQ
VDDQ
NC
NC
NC
28
DQPD
30
Document #: 38-05284 Rev. *H
Page 4 of 30
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CY7C1481V33
CY7C1483V33
CY7C1487V33
Pin Configurations (continued)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1481V33 (2M x 36)
1
2
A
3
CE1
4
BWC
5
BWB
6
CE3
7
8
9
ADV
10
A
11
NC
NC/288M
NC/144M
DQPC
BWE
GW
VSS
VSS
ADSC
A
B
C
D
A
CE2
VDDQ
VDDQ
BWD
VSS
BWA
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
ADSP
VDDQ
VDDQ
A
NC/576M
DQPB
DQB
NC
DQC
NC/1G
DQB
DQC
VDD
DQC
DQC
DQC
NC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
DQB
DQB
ZZ
E
F
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
NC
DQD
NC
A
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
TDI
A1
TDO
A0
MODE
A
A
A
TMS
TCK
A
A
A
A
R
CY7C1483V33 (4M x 18)
1
2
A
3
CE1
4
BWB
5
NC
6
CE3
7
8
9
ADV
10
A
11
A
NC/288M
NC/144M
NC
BWE
GW
VSS
VSS
ADSC
A
B
C
D
A
CE2
VDDQ
VDDQ
NC
VSS
VDD
BWA
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
ADSP
VDDQ
VDDQ
A
NC/576M
DQPA
DQA
NC
NC/1G
NC
NC
DQB
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQA
DQA
DQA
ZZ
E
F
NC
NC
G
H
J
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
NC
NC
K
L
NC
NC
DQB
DQPB
NC
NC
NC
A
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
A
M
N
P
TDI
A1
TDO
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05284 Rev. *H
Page 5 of 30
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CY7C1481V33
CY7C1483V33
CY7C1487V33
Pin Configurations (continued)
209-Ball FBGA (14 x 22 x 1.76 mm) Pinout
CY7C1487V33 (1M × 72)
1
2
3
4
5
6
7
8
9
10
11
DQG
DQG
DQG
A
B
C
D
E
F
DQG
DQG
CE3
DQB
DQB
CE2
ADSC
BW
DQB
DQB
A
ADSP
ADV
A
A
BWSB
NC/288M
BWSC
BWSH
VSS
BWSF
BWSG
BWSD
DQG
DQG
NC/144M
NC/576M
GW
BWSE
NC
CE1
BWSA DQB
DQB
DQB
DQG
NC/1G OE
VSS
NC
DQB
DQPG DQPC
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD
VDD
VSS
VDD
DQPF DQPB
DQC
DQC
VSS
DQF
DQF
VSS
VDDQ
VSS
NC
NC
NC
NC
VSS
NC
NC
VSS
G
H
J
DQC
DQC
DQC
VDDQ
VSS
VDDQ
VSS
DQF
DQF
DQF
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
A
DQC
DQC
NC
DQF
DQF
NC
VDDQ
DQC
NC
VDDQ
VDDQ
CLK
VDDQ
NC
DQF
NC
K
L
NC
NC
DQH
DQH
DQH
VDDQ
VSS
VDDQ
VSS
VDDQ
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
DQA
DQA
DQA
M
N
P
R
T
VSS
VDDQ
VSS
VDDQ
NC
DQH
DQH
DQH
VSS
VDD
VSS
DQA
DQA
DQA
VDDQ
DQH
DQH
DQPD
DQD
DQD
NC
ZZ
DQA
DQA
DQPA
DQE
DQE
VSS
VDDQ
VSS
A
VDDQ
VDD
NC
A
DQPH
DQD
DQD
DQD
DQD
VDDQ
VDD
DQPE
DQE
DQE
DQE
DQE
VSS
NC
A
MODE
A
U
V
W
A
A
A
A
A1
A
DQD
DQD
A
A
A
A
DQE
DQE
TDI
TDO
TCK
A0
A
TMS
Document #: 38-05284 Rev. *H
Page 6 of 30
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CY7C1481V33
CY7C1483V33
CY7C1487V33
Pin Definitions
Pin Name
IO
Description
A0, A1, A
Input-
Synchronous
Address Inputs Used to Select One of the Address Locations. Sampled at the
rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are
sampled active. A[1:0] feed the two-bit counter.
BWA,BWB,BWC,BWD,
BWE,BWF,BWG,BWH
Input-
Synchronous
Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes
to the SRAM. Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global Write Enable Input, Active LOW. When asserted LOW on the rising edge
of CLK, a global write is conducted (ALL bytes are written, regardless of the values
on BWX and BWE).
CLK
CE1
Input-
Clock
Clock Input. Captures all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW during a burst operation.
Input-
Synchronous
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE and CE to select or deselect the device. ADSP is ignored
if
2 3
CE is sampled only when a new external address is loaded.
CE1 is HIGH.
1
CE2
CE3
OE
Input-
Synchronous
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select or deselect the device. CE2 is sampled only
when a new external address is loaded.
Input-
Synchronous
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select or deselect the device. CE3 is sampled only
when a new external address is loaded.
Input-
Output Enable, Asynchronous Input, Active LOW. Controls the direction of the IO
Asynchronous pins. When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins
are tri-stated, and act as input data pins. OE is masked during the first clock of a read
cycle when emerging from a deselected state.
ADV
Input-
Synchronous
Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it
automatically increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active
LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is
deasserted HIGH
ADSC
Input-
Synchronous
Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active
LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A[1:0] are also loaded into the burst counter. When ADSP and
.
ADSC are both asserted, only ADSP is recognized
BWE
ZZ
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
Input-
ZZ “Sleep” Input, Active HIGH. When asserted HIGH, places the device in a
Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal operation,
this pin must be LOW or left floating. ZZ pin has an internal pull down.
IO-
Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained in
the memory location specified by the addresses presented during the previous clock
rise of the read cycle. The direction of the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed
in a tri-state condition.The outputs are automatically tri-stated during the data portion
of a write sequence, during the first clock when emerging from a deselected state,
and when the device is deselected, regardless of the state of OE.
DQs
Synchronous
IO-
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs.
During write sequences, DQPx is controlled by BWX correspondingly.
DQPX
Synchronous
MODE
Input-Static
Selects Burst Order. When tied to GND, selects linear burst sequence. When tied
to VDD or left floating, selects interleaved burst sequence. This is a strap pin and must
remain static during device operation. Mode Pin has an internal pull up.
Document #: 38-05284 Rev. *H
Page 7 of 30
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CY7C1481V33
CY7C1483V33
CY7C1487V33
Pin Definitions (continued)
Pin Name
IO
Power Supply
Description
VDD
VDDQ
VSS
Power supply inputs to the core of the device.
IO Power Supply Power supply for the IO circuitry.
Ground
Ground for the core of the device.
Ground for the IO circuitry.
[2}
VSSQ
TDO
I/O Ground
JTAG Serial
Output
Synchronous
Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If
the JTAG feature is not used, this pin should be left unconnected. This pin is not
available on TQFP packages.
TDI
JTAG Serial Input Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG
Synchronous
feature is not used, this pin can be left floating or connected to VDD through a pull up
resistor. This pin is not available on TQFP packages.
TMS
JTAG Serial Input Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG
Synchronous
JTAG Clock
-
feature is not used, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
TCK
NC
Clock Input to the JTAG Circuit. If the JTAG feature is not used, this pin must be
connected to VSS. This pin is not available on TQFP packages.
No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are
address expansion pins and are not internally connected to the die.
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data is
available at the data outputs a maximum to tCDV after clock
rise. ADSP is ignored if CE1 is HIGH.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (tCDV) is 6.5 ns (133-MHz device).
The CY7C1481V33/CY7C1483V33/CY7C1487V33 supports
secondary cache in systems using either a linear or inter-
leaved burst sequence. The interleaved burst order supports
Pentium and i486™ processors. The linear burst sequence is
suited for processors that use a linear burst sequence. The
burst order is user selectable, and is determined by sampling
the MODE input. Accesses can be initiated with either the
Processor Address Strobe (ADSP) or the Controller Address
Strobe (ADSC). Address advancement through the burst
sequence is controlled by the ADV input. A two-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the
rest of the burst access.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BWE, and BWX) are ignored during this first clock
cycle. If the write inputs are asserted active (see “Truth Table
for Read/Write” on page 11 for appropriate states that indicate
a write) on the next clock rise, the appropriate data is latched
and written into the device. Byte writes are supported. All IOs
are tri-stated during a byte write. Because this is a common IO
device, the asynchronous OE input signal must be deasserted
and the I/Os must be tri-stated before the presentation of data
to DQs. As a safety precaution, the data lines are tri-stated
after a write cycle is detected, regardless of the state of OE.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self timed write circuitry.
Single Write Accesses Initiated by ADSC
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active
LOW.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQs will be written
into the specified address location. Byte writes are supported.
Note
2. Applicable for TQFP package. For BGA package V serves as ground for the core and the IO circuitry.
SS
Document #: 38-05284 Rev. *H
Page 8 of 30
[+] Feedback
CY7C1481V33
CY7C1483V33
CY7C1487V33
All IOs are tri-stated when a write is detected, even a byte
write. Because this is a common IO device, the asynchronous
OE input signal must be deasserted and the IOs must be
tri-stated before the presentation of data to DQs. As a safety
precaution, the data lines are tri-stated once a write cycle is
detected, regardless of the state of OE.
The device must be deselected before entering the “sleep”
mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD
)
Burst Sequences
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Address
A1: A0
The CY7C1481V33/CY7C1483V33/CY7C1487V33 provides
an on-chip two-bit wraparound burst counter inside the SRAM.
The burst counter is fed by A[1:0], and can follow either a linear
or interleaved burst order. The burst order is determined by the
state of the MODE input. A LOW on MODE selects a linear
burst sequence. A HIGH on MODE selects an interleaved
burst order. Leaving MODE unconnected causes the device to
default to a interleaved burst sequence.
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Sleep Mode
Linear Burst Address Table
(MODE = GND)
The ZZ input pin is asynchronous. Asserting ZZ places the
SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed.
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed.
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
Test Conditions
ZZ > VDD – 0.2V
Min
Max
Unit
mA
ns
150
tZZS
ZZ > VDD – 0.2V
2tCYC
tZZREC
tZZI
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
ZZ active to sleep current
ZZ Inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2tCYC
ns
tRZZI
0
ns
Document #: 38-05284 Rev. *H
Page 9 of 30
[+] Feedback
CY7C1481V33
CY7C1483V33
CY7C1487V33
Truth Table
The truth table for CY7C1481V33, CY7C1483V33, and CY7C1487V33 follows.[3, 4, 5, 6, 7]
ADDRESS
Cycle Description
CE1 CE2 CE3 ZZ
ADSP
ADSC ADV WRITE OE CLK
DQ
Used
Deselected Cycle,
Power Down
None
H
L
L
L
X
X
L
X
X
H
X
X
L
L
L
L
L
X
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L-H Tri-State
Deselected Cycle,
Power Down
None
None
None
None
L
L
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
Deselected Cycle,
Power Down
X
L
Deselected Cycle,
Power Down
H
H
Deselected Cycle,
Power Down
X
L
Sleep Mode, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
None
External
External
External
External
External
Next
X
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
X
X
X
L
X
X
X
X
X
X
L
X
X
X
L
X
L
X
Tri-State
Q
L-H
L
L
L
H
X
L
L-H Tri-State
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H
L-H
D
Q
L
L
L
H
H
H
H
H
H
L
L
L
L
H
L
L-H Tri-State
L-H
L-H Tri-State
L-H
L-H Tri-State
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L-H
L-H
L-H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H Tri-State
L-H
L-H Tri-State
Q
H
X
X
L-H
L-H
D
D
L
Notes
3. X = Do Not Care, H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks after
X
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to enable the outputs to tri-state. OE is a do not
care for the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as outputs when OE is active (LOW).
Document #: 38-05284 Rev. *H
Page 10 of 30
[+] Feedback
CY7C1481V33
CY7C1483V33
CY7C1487V33
Truth Table for Read/Write
The read-write truth table for CY7C1481V33 follows.[3, 8]
Function
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
BWD
X
H
H
H
H
H
H
H
H
L
BWC
X
H
H
H
H
L
BWB
X
H
H
L
BWA
X
H
L
Read
Read
Write Byte A (DQA, DQPA)
L
Write Byte B(DQB, DQPB)
L
H
L
Write Bytes A, B (DQA, DQB, DQPA, DQPB)
Write Byte C (DQC, DQPC)
L
L
L
H
H
L
H
L
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
Write Bytes C, B (DQC, DQB, DQPC, DQPB)
Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB, DQPA)
Write Byte D (DQD, DQPD)
L
L
L
L
H
L
L
L
L
L
H
H
H
H
L
H
H
L
H
L
Write Bytes D, A (DQD, DQA, DQPD, DQPA)
Write Bytes D, B (DQD, DQA, DQPD, DQPA)
Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB, DQPA)
Write Bytes D, B (DQD, DQB, DQPD, DQPB)
Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC, DQPA)
Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB, DQPA)
Write All Bytes
L
L
L
L
H
L
L
L
L
L
L
H
H
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
Write All Bytes
X
X
X
X
X
Truth Table for Read/Write
The read-write truth table for CY7C1483V33 follows.[3, 8]
Function
GW
H
BWE
BWB
BWA
Read
Read
H
L
L
L
L
X
X
H
H
L
X
H
L
H
Write Byte A - (DQA and DQPA)
Write Byte B - (DQB and DQPB)
Write All Bytes
H
H
H
L
H
L
Write All Bytes
L
X
X
Truth Table for Read/Write
The read-write truth table for CY7C1487V33 follows.[3, 8]
[9]
Function
GW
H
BWE
BWx
Read
H
L
L
L
X
X
Read
H
All BW = H
Write Byte x – (DQx and DQPx)
Write All Bytes
H
L
All BW = L
X
H
Write All Bytes
L
Notes
8. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. An appropriate write is performed based on which byte write is active.
X
9. BWx represents any byte write signal BW .To enable any byte write BW a Logic LOW signal must be applied at clock rise. Any number of byte writes can be
X
x ,
enabled at the same time for any given write.
Document #: 38-05284 Rev. *H
Page 11 of 30
[+] Feedback
CY7C1481V33
CY7C1483V33
CY7C1487V33
ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1481V33/CY7C1483V33/CY7C1487V33 incorpo-
rates a serial boundary scan test access port (TAP). This port
operates in accordance with IEEE Standard 1149.1-1990 but
does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC standard 3.3V or 2.5V IO logic levels.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information about loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
(See TAP Controller Block Diagram.)
The CY7C1481V33/CY7C1483V33/CY7C1487V33 contains
a TAP controller, instruction register, boundary scan register,
bypass register, and ID register.
Test Data-Out (TDO)
The TDO output ball serially clocks data-out from the registers.
Whether the output is active depends on the current state of
the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of
any register. (See TAP Controller State Diagram.)
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, tie TCK LOW (VSS) to
prevent device clocking. TDI and TMS are internally pulled up
and may be unconnected. They may alternatively be
connected to VDD through a pull up resistor. TDO must be left
unconnected. At power up, the device comes up in a reset
state, which does not interfere with the operation of the device.
TAP Controller Block Diagram
0
Bypass Register
TAP Controller State Diagram
2
1
0
0
0
Selection
Circuitry
Selection
Circuitry
TEST-LOGIC
1
Instruction Register
31 30 29
Identification Register
RESET
0
TDI
TDO
.
.
. 2 1
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
x
.
.
.
.
. 2 1
1
1
CAPTURE-DR
CAPTURE-IR
Boundary Scan Register
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
TCK
1
1
TAP CONTROLLER
EXIT1-DR
EXIT1-IR
TM S
0
0
PAUSE-DR
0
PAUSE-IR
1
0
Performing a TAP Reset
1
0
0
To perform a RESET, force TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating.
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
0
1
0
At power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls, as shown in the “TAP Controller Block
Diagram” on page 12. At power up, the instruction register is
loaded with the IDCODE instruction. It is also loaded with the
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. You can leave this
Document #: 38-05284 Rev. *H
Page 12 of 30
[+] Feedback
CY7C1481V33
CY7C1483V33
CY7C1487V33
IDCODE instruction if the controller is placed in a reset state,
as described in the previous section.
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller must be moved into the Update-IR state.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
enable fault isolation of the board level serial test data path.
EXTEST
EXTEST is a mandatory 1149.1 instruction, which is to be
executed whenever the instruction register is loaded with all
zeros. EXTEST is not implemented in this SRAM TAP
controller, and therefore this device is not compliant to 1149.1.
The TAP controller does recognize an all-zero instruction.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction is loaded. There is one difference between the two
instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The x36 configuration has a
IDCODE
73-bit-long register, and the x18 configuration has
a
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and
enables the IDCODE to be shifted out of the device when the
TAP controller enters the Shift-DR state.
54-bit-long register.
The boundary scan register is loaded with the contents of the
RAM I/ ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the IO ring.
The IDCODE instruction is loaded into the instruction register
at power up or whenever the TAP controller is in a test logic
reset state.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in “Identification Register Defini-
tions” on page 15.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the device TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls
is captured in the boundary scan register.
TAP Instruction Set
Overview
Be aware that the TAP controller clock can only operate at a
frequency up to 10 MHz, while the SRAM clock operates more
than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that during the
Capture-DR state, an input or output may undergo a transition.
The TAP may then try to capture a signal while in transition
(metastable state). This does not harm the device, but there is
no guarantee as to the value that may be captured.
Repeatable results may not be possible.
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in “Identification
Codes” on page 16. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus
hold time (tCS plus tCH).
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the IO
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the IO
ring when these instructions are executed.
The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.
Instructions are loaded into the TAP controller during the
Shift-IR state, when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
Document #: 38-05284 Rev. *H
Page 13 of 30
[+] Feedback
CY7C1481V33
CY7C1483V33
CY7C1487V33
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Note that because the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction has the same
effect as the Pause-DR command.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TM SS
TDIS
TM SH
Test M ode Select
(TM S)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range[10,11]
Parameter
Clock
Description
Min
Max
Unit
tTCYC
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
tTF
20
tTH
20
20
tTL
ns
Output Times
tTDOV
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
10
ns
ns
tTDOX
0
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
5
5
5
ns
ns
tTDIS
tCS
Hold Times
tTMSH
tTDIH
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
tCH
Capture Hold after Clock Rise
Notes
10. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
11. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 n.s.
R
F
Document #: 38-05284 Rev. *H
Page 14 of 30
[+] Feedback
CY7C1481V33
CY7C1483V33
CY7C1487V33
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ................................................ VSS to 3.3V
Input rise and fall times................................................... 1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
Input pulse levels.................................................VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels......................................... 1.25V
Output reference levels ................................................ 1.25V
Test load termination supply voltage ............................ 1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.25V
1.5V
50Ω
50Ω
TDO
TDO
ZO= 50Ω
20pF
ZO= 50Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.135V to 3.6V unless otherwise noted)[12]
Parameter
VOH1
Description
Conditions
VDDQ = 3.3V
Min
2.4
2.0
2.9
2.1
Max
Unit
V
Output HIGH Voltage IOH = –4.0 mA
I
OH = –1.0 mA
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage IOH = –100 µA
V
V
Output LOW Voltage IOL = 8.0 mA
0.4
0.4
0.2
0.2
V
I
OL = 1.0 mA
V
Output LOW Voltage IOL = 100 µA
V
VDDQ = 2.5V
V
Input HIGH Voltage
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
2.0
1.7
VDD + 0.3
V
VDD + 0.3
V
VIL
Input LOW Voltage
–0.3
–0.3
–5
0.8
0.7
5
V
VDDQ = 2.5V
V
IX
Input Load Current
GND < VIN < VDDQ
µA
Identification Register Definitions
Bit# 24 is “1” in the ID Register definitions for both 2.5V and 3.3V versions of the device.
CY7C1481V33 CY7C1483V33 CY7C1487V33
Instruction Field
Description
(2M x 36)
000
(4M x18)
000
(1M x72)
000
Revision Number (31:29)
Device Depth (28:24)
Describes the version number
Reserved for internal use
01011
01011
01011
Architecture/Memory Type(23:18)
Bus Width/Density (17:12)
Cypress JEDEC ID Code (11:1)
000001
000001
000001
110100
Defines memory type and architecture
Defines width and density
100100
010100
00000110100
00000110100
00000110100 Enables unique identification of SRAM
vendor
ID Register Presence Indicator (0)
1
1
1
Indicates the presence of an ID register
Note
12. All voltages refer to V (GND).
SS
Document #: 38-05284 Rev. *H
Page 15 of 30
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CY7C1481V33
CY7C1483V33
CY7C1487V33
Scan Register Sizes
Register Name
Bit Size (X36)
Bit Size (X18)
Bit Size (X72)
Instruction
3
3
3
Bypass
1
32
73
-
1
32
54
-
1
32
-
ID
Boundary Scan Order -165FBGA
Boundary Scan Order -209 BGA
112
Identification Codes
Instruction
EXTEST
Code
000
Description
Captures IO ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Boundary Scan Exit Order (2M x 36)
Bit #
1
165-Ball ID
C1
Bit #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
165-Ball ID
R3
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
165-Ball ID
L10
K11
J11
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
165-Ball ID
B8
A7
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
2
D1
P2
3
E1
R4
4
D2
P6
K10
J10
5
E2
R6
6
F1
N6
H11
G11
F11
7
G1
F2
P11
R8
8
9
G2
J1
P3
E11
D10
D11
C11
G10
F10
E10
A10
B10
A9
10
11
12
13
14
15
16
17
18
19
20
P4
K1
P8
L1
P9
J2
P10
R9
M1
N1
R10
R11
N11
M11
L11
M10
K2
L2
M2
R1
B9
R2
A8
Document #: 38-05284 Rev. *H
Page 16 of 30
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CY7C1481V33
CY7C1483V33
CY7C1487V33
Boundary Scan Exit Order (4M x 18)
Bit #
1
165-Ball ID
D2
Bit #
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
165-Ball ID
R8
Bit #
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
165-Ball ID
C11
A11
A10
B10
A9
2
E2
P3
3
F2
P4
4
G2
P8
5
J1
P9
6
K1
P10
R9
B9
7
L1
A8
8
M1
N1
R10
R11
M10
L10
K10
J10
H11
G11
F11
E11
D11
B8
9
A7
10
11
12
13
14
15
16
17
18
R1
B7
R2
B6
R3
A6
P2
B5
R4
A4
P6
B3
R6
A3
N6
A2
P11
B2
Document #: 38-05284 Rev. *H
Page 17 of 30
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CY7C1481V33
CY7C1483V33
CY7C1487V33
Boundary Scan Exit Order (1M x 72)
Bit #
1
209-Ball ID
A1
Bit #
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
209-Ball ID
T1
Bit #
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
209-Ball ID
V10
U11
U10
T11
Bit #
85
209-Ball ID
C11
C10
B11
B10
A11
A10
A9
2
A2
T2
86
3
B1
U1
87
4
B2
U2
88
5
C1
C2
D1
D2
E1
V1
T10
R11
R10
P11
P10
N11
N10
M11
M10
L11
89
6
V2
90
7
W1
W2
T6
91
8
92
U8
9
93
A7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
E2
V3
94
A5
F1
V4
95
A6
F2
U4
96
D6
G1
G2
H1
H2
J1
W5
V6
97
B6
98
D7
W6
U3
L10
99
K3
P6
100
101
102
103
104
105
106
107
108
109
110
111
112
A8
U9
J11
B4
J2
V5
J10
B3
L1
U5
H11
H10
G11
G10
F11
C3
L2
U6
C4
M1
M2
N1
N2
P1
W7
V7
C8
C9
U7
B9
V8
F10
E10
E11
D11
D10
B8
V9
A4
P2
W11
W10
V11
C6
R2
R1
B7
A3
Document #: 38-05284 Rev. *H
Page 18 of 30
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CY7C1481V33
CY7C1483V33
CY7C1487V33
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage........................................... >2001V
(MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch Up Current .................................................... >200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND........ –0.3V to +4.6V
Supply Voltage on VDDQ Relative to GND ......–0.3V to +VDD
Ambient
Temperature
Range
VDD
VDDQ
Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V – 5%
to VDD
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
Industrial
–40°C to +85°C
Electrical Characteristics
Over the Operating Range[13, 14]
Parameter
VDD
Description
Power Supply Voltage
IO Supply Voltage
Test Conditions
Min
3.135
3.135
2.375
2.4
Max
3.6
Unit
V
VDDQ
For 3.3V I/O
For 2.5V I/O
VDD
2.625
V
V
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
For 3.3V I/O, IOH = –4.0 mA
For 2.5V I/O, IOH = –1.0 mA
For 3.3V I/O, IOL = 8.0 mA
For 2.5V I/O, IOL = 1.0 mA
V
2.0
V
0.4
0.4
V
V
Input HIGH Voltage[13] For 3.3V I/O
2.0
1.7
VDD + 0.3V
VDD + 0.3V
0.8
V
For 2.5V I/O
V
Input LOW Voltage[13]
For 3.3V I/O
For 2.5V I/O
–0.3
–0.3
–5
V
0.7
V
Input Leakage Current GND ≤ VI ≤ VDDQ
Except ZZ and MODE
5
µA
Input Current of MODE Input = VSS
Input = VDD
–30
–5
µA
µA
5
Input Current of ZZ
Input = VSS
Input = VDD
µA
30
5
µA
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled
–5
µA
VDD Operating Supply VDD = Max, IOUT = 0 mA,
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
335
305
200
200
mA
mA
mA
mA
Current
f = fMAX = 1/tCYC
ISB1
ISB2
ISB3
ISB4
Automatic CE
Power Down
Current—TTL Inputs
Max VDD, Device Deselected, 7.5-ns cycle, 133 MHz
VIN ≥ VIH or VIN ≤ VIL, f = fMAX,
10-ns cycle, 100 MHz
inputs switching
Automatic CE
Power Down
Current—CMOS Inputs f = 0, inputs static
Max VDD, Device Deselected, All speeds
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
150
mA
Automatic CE
Power Down
Current—CMOS Inputs f = fMAX, inputs switching
Max VDD, Device Deselected, 7.5-ns cycle, 133 MHz
VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V,
200
200
mA
mA
10-ns cycle, 100 MHz
Automatic CE
Max VDD, Device Deselected, All Speeds
165
mA
Power Down
Current—TTL Inputs
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
Notes
13. Overshoot: V (AC) < V +1.5V (pulse width less than t
/2). Undershoot: V (AC) > –2V (pulse width less than t
/2).
IH
DD
CYC
IL
CYC
14. T
: assumes a linear ramp from 0V to V (min) within 200 ms. During this time V < V and V
< V
.
Power-up
DD
IH
DD
DDQ
DD
Document #: 38-05284 Rev. *H
Page 19 of 30
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CY7C1481V33
CY7C1483V33
CY7C1487V33
Capacitance
Tested initially and after any design or process change that may affect these parameters.
100 TQFP 165 FBGA 209 FBGA
Parameter
Description
Test Conditions
Unit
Max
Max
Max
CADDRESS
CDATA
CCTRL
CCLK
Address Input Capacitance
Data Input Capacitance
Control Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
TA = 25°C, f = 1 MHz,
6
5
8
6
5
6
5
8
6
5
6
5
8
6
5
pF
pF
pF
pF
pF
V
DD = 3.3V
VDDQ = 2.5V
CI/O
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
100 TQFP
Package
165 FBGA 209 FBGA
Parameter
Description
Test Conditions
Unit
Package
Package
ΘJA
Thermal Resistance
(Junction to Ambient) test methods and procedures for
Test conditions follow standard
24.63
16.3
15.2
°C/W
measuring thermal impedance,
per EIA/JESD51.
(Junction to Case)
ΘJC
Thermal Resistance
2.28
2.1
1.7
°C/W
AC Test Loads and Waveforms
3.3V IO Test Load
R = 317Ω
3.3V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50Ω
0
10%
L
GND
5 pF
R = 351Ω
≤ 1 ns
≤ 1 ns
V = 1.5V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5V IO Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
R = 1538Ω
≤ 1 ns
≤ 1 ns
V = 1.25V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Document #: 38-05284 Rev. *H
Page 20 of 30
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CY7C1481V33
CY7C1483V33
CY7C1487V33
Switching Characteristics
Over the Operating Range.[15, 16]
133 MHz
100 MHz
Unit
Parameter
Description
Min
Max
Min
Max
tPOWER
Clock
tCYC
VDD(Typical) to the First Access[17]
1
1
ms
Clock Cycle Time
Clock HIGH
7.5
2.5
2.5
10
3.0
3.0
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCDV
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[18, 19, 20]
6.5
8.5
ns
ns
ns
ns
ns
ns
ns
tDOH
2.5
3.0
2.5
3.0
tCLZ
tCHZ
Clock to High-Z[18, 19, 20]
3.8
3.0
4.5
3.8
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
Setup Times
tAS
OE LOW to Output Low-Z[18, 19, 20]
OE HIGH to Output High-Z[18, 19, 20]
0
0
3.0
4.0
Address Setup Before CLK Rise
ADSP, ADSC Setup Before CLK Rise
ADV Setup Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
tADS
tADVS
tWES
GW, BWE, BWX Setup Before CLK Rise
Data Input Setup Before CLK Rise
Chip Enable Setup
tDS
tCES
Hold Times
tAH
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
GW, BWE, BWX Hold After CLK Rise
ADV Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tADH
tWEH
tADVH
tDH
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
tCEH
Notes
15. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
16. Test conditions shown in (a) of “AC Test Loads and Waveforms” on page 20 unless otherwise noted.
17. This part has an internal voltage regulator; t
is the time that the power must be supplied above V (minimum) initially, before a read or write operation can
POWER
DD
be initiated.
18. t
, t
, t
, and t
are specified with AC test conditions shown in part (b) of “AC Test Loads and Waveforms” on page 20. Transition is measured ±200 mV
OEHZ
CHZ CLZ OELZ
from steady-state voltage.
19. At any supplied voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
OEHZ
OELZ
CHZ
CLZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z before Low-Z under the same system conditions.
20. This parameter is sampled and not 100% tested.
Document #: 38-05284 Rev. *H
Page 21 of 30
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CY7C1481V33
CY7C1483V33
CY7C1487V33
Timing Diagrams
Figure 1. Read Cycle Timing[21]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
ADDRESS
t
t
WES
WEH
GW, BWE, BWX
Deselect Cycle
t
t
CES
CEH
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
t
CDV
OEV
OELZ
t
t
OEHZ
CHZ
t
DOH
t
CLZ
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2
+
3)
Q(A2)
Q(A2
+
1)
Q(A2
+
2)
Q(A1)
Data Out (Q)
High-Z
t
CDV
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note
21. On this diagram, when CE is LOW: CE is LOW, CE is HIGH, and CE is LOW. When CE is HIGH: CE is HIGH, CE is LOW, or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05284 Rev. *H
Page 22 of 30
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CY7C1481V33
CY7C1483V33
CY7C1487V33
Timing Diagrams (continued)
Figure 2. Write Cycle Timing[21, 22]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE, BWX
GW
t
t
WEH
WES
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
ADV suspends burst
OE
t
t
DH
DS
Data in (D)
High-Z
D(A2)
D(A2
+
1)
D(A2
+
1)
D(A2
+
2)
D(A2
+
3)
D(A3)
D(A3
+
1)
D(A3
+
2)
D(A1)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
Extended BURST WRITE
Single WRITE
DON’T CARE
UNDEFINED
Note
22.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW, and BW LOW.
X
Document #: 38-05284 Rev. *H
Page 23 of 30
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CY7C1481V33
CY7C1483V33
CY7C1487V33
Timing Diagrams (continued)
Figure 3. Read/Write Cycle Timing[21, 23, 24]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
DS
t
OELZ
t
High-Z
D(A3)
D(A5)
D(A6)
Data In (D)
t
OEHZ
CDV
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
Back-to-Back READs
Single WRITE
BURST READ
DON’T CARE
UNDEFINED
Notes
23. The data bus (Q) remains in High-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.
24. GW is HIGH.
Document #: 38-05284 Rev. *H
Page 24 of 30
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CY7C1481V33
CY7C1483V33
CY7C1487V33
Timing Diagrams (continued)
Figure 4. ZZ Mode Timing[25, 26]
CLK
ZZ
t
t
ZZ
ZZREC
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
25. Device must be deselected when entering ZZ mode. See “Truth Table” on page 10 for all possible signal conditions to deselect the device.
26. DQs are in High-Z when exiting ZZ sleep mode.
Document #: 38-05284 Rev. *H
Page 25 of 30
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CY7C1481V33
CY7C1483V33
CY7C1487V33
Ordering Information
Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative
or visit www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Part and Package Type
Ordering Code
133 CY7C1481V33-133AXC
CY7C1483V33-133AXC
CY7C1481V33-133BZC
CY7C1483V33-133BZC
CY7C1481V33-133BZXC
CY7C1483V33-133BZXC
CY7C1487V33-133BGC
CY7C1487V33-133BGXC
CY7C1481V33-133AXI
CY7C1483V33-133AXI
CY7C1481V33-133BZI
CY7C1483V33-133BZI
CY7C1481V33-133BZXI
CY7C1483V33-133BZXI
CY7C1487V33-133BGI
CY7C1487V33-133BGXI
100 CY7C1481V33-100AXC
CY7C1483V33-100AXC
CY7C1481V33-100BZC
CY7C1483V33-100BZC
CY7C1481V33-100BZXC
CY7C1483V33-100BZXC
CY7C1487V33-100BGC
CY7C1487V33-100BGXC
CY7C1481V33-100AXI
CY7C1483V33-100AXI
CY7C1481V33-100BZI
CY7C1483V33-100BZI
CY7C1481V33-100BZXI
CY7C1483V33-100BZXI
CY7C1487V33-100BGI
CY7C1487V33-100BGXI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
Commercial
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free
lndustrial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free
Commercial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free
lndustrial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free
Document #: 38-05284 Rev. *H
Page 26 of 30
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CY7C1483V33
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Package Diagrams
Figure 5. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050
16.00 0.20
14.00 0.10
1.40 0.05
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
1. JEDEC STD REF MS-026
0.25
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
0.20 MIN.
1.00 REF.
51-85050-*B
DETAIL
A
Document #: 38-05284 Rev. *H
Page 27 of 30
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CY7C1481V33
CY7C1483V33
CY7C1487V33
Package Diagrams (continued)
Figure 6. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
1
Ø0.25 M C A B
Ø0.45 0.05(165X)
2
3
4
5
6
7
8
9
10
11
11 10
9
8
7
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
1.00
5.00
10.00
B
15.00 0.10
0.15(4X)
SEATING PLANE
C
51-85165-*A
Document #: 38-05284 Rev. *H
Page 28 of 30
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CY7C1483V33
CY7C1487V33
Package Diagrams (continued)
Figure 7. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167
51-85167-**
i486 is a trademark and Intel and Pentium are registered trademarks of Intel Corporation. All products and company names
mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05284 Rev. *H
Page 29 of 30
© Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1481V33
CY7C1483V33
CY7C1487V33
Document History Page
Document Title: CY7C1481V33/CY7C1483V33/CY7C1487V33, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
Document Number: 38-05284
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
**
114671
118283
08/12/02
01/27/03
PKS
New Data Sheet
*A
HGK
Updated Ordering Information
Updated the features for package offering
Changed from Advance Information to Preliminary
*B
233368
See ECN
NJY
Changed timing diagrams
Changed logic block diagrams
Modified Functional Description
Modified “Functional Overview” section
Added boundary scan order for all packages
Included thermal numbers and capacitance values for all packages
Included IDD and ISB values
Removed 150-MHz speed grade offering
Changed package outline for 165FBGA package and 209-ball BGA
package
Removed 119-BGA package offering
*C
*D
*E
299452
323080
416193
See ECN
See ECN
See ECN
SYT
PCI
Removed 117-MHz Speed Bin
Changed ΘJA from 16.8 to 24.63 °C/W and ΘJC from 3.3 to 2.28 °C/W for
100 TQFP Package on Page # 21
Added lead-free information for 100-Pin TQFP, 165 FBGA and 209 BGA
Packages
Added comment of ‘Lead-free BG packages availability’ below the
Ordering Information
Address expansion pins/balls in the pinouts for all packages are modified
as per JEDEC standard
Added Address Expansion pins in the Pin Definitions Table
Modified VOL, VOH test conditions
Removed comment of ‘Lead-free BG packages availability’ below the
Ordering Information
Updated Ordering Information Table
NXR
Changed address of Cypress Semiconductor Corporation on Page# 1
from “3901 North First Street” to “198 Champion Court”
Changed the description of IX from Input Load Current to Input Leakage
Current on page# 19
Changed the IX current values of MODE on page # 19 from -5 µA and 30
µA
to -30 µA and 5 µA
Changed the IX current values of ZZ on page # 19 from -30 µA and 5 µA
to -5 µA and 30 µA
Changed VIH < VDD to VIH < VDD on page # 19
Replaced Package Name column with Package Diagram in the Ordering
Information table
*F
470723
See ECN
See ECN
VKN
VKN
Converted from Preliminary to Final
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP
AC Switching Characteristics table
Updated the Ordering Information table
*G
*H
486690
Corrected the typo in the 209-Ball FBGA pinout.
(Corrected the ball name H9 to VSS from VSSQ).
1062041
See ECN VKN/KKVTMP Added footnote #2 related to VSSQ
Document #: 38-05284 Rev. *H
Page 30 of 30
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