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CY7C199_06 [CYPRESS]

32K x 8 Static RAM; 32K x 8静态RAM
CY7C199_06
型号： CY7C199_06
厂家： CYPRESS    CYPRESS
描述：

32K x 8 Static RAM
32K x 8静态RAM
文件： 总11页 (文件大小：315K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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CY7C199  
32K x 8 Static RAM  
Functional Description  
Features  
• High speed  
The CY7C199 is a high-performance CMOS static RAM  
organized as 32,768 words by 8 bits. Easy memory expansion  
is provided by an active LOW Chip Enable (CE) and active  
LOW Output Enable (OE) and tri-state drivers. This device has  
an automatic power-down feature, reducing the power  
consumption by 81% when deselected. The CY7C199 is in the  
standard 300-mil-wide DIP, SOJ, and LCC packages.  
— 12 ns  
• Fast tDOE  
• CMOS for optimum speed/power  
• Low active power  
— 495 mW (Max, “L” version)  
• Low standby power  
An active LOW Write Enable signal (WE) controls the  
writing/reading operation of the memory. When CE and WE  
inputs are both LOW, data on the eight data input/output pins  
(I/O0 through I/O7) is written into the memory location  
addressed by the address present on the address pins (A0  
through A14). Reading the device is accomplished by selecting  
the device and enabling the outputs, CE and OE active LOW,  
while WE remains inactive or HIGH. Under these conditions,  
the contents of the location addressed by the information on  
address pins are present on the eight data input/output pins.  
— 0.275 mW (Max, “L” version)  
• 2V data retention (“L” version only)  
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• Available in pb-free 28-pin TSOP I and 28-pin (300-Mil)  
Molded DIP  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and Write Enable  
(WE) is HIGH. A die coat is used to improve alpha immunity.  
Pin Configurations  
Logic Block Diagram  
DIP  
Top View  
A
A
V
CC  
28  
27  
26  
1
2
3
4
5
6
5
WE  
A
4
6
A
A
7
8
A
3
25  
24  
A
9
A
2
A
10  
A
11  
23  
22  
A
1
7
OE  
A
A
A
I/O  
I/O  
I/O  
21  
20  
19  
18  
17  
16  
15  
A
12  
13  
14  
8
9
10  
11  
12  
13  
0
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CE  
I/O  
I/O  
I/O  
0
1
2
3
4
5
6
INPUT BUFFER  
7
0
1
2
6
5
4
A
0
A
I/O  
I/O  
1
A
GND  
14  
2
3
A
3
A
4
22  
23  
OE  
A
32K x 8  
ARRAY  
21  
20  
A
0
A
5
1
CE  
I/O  
I/O  
I/O  
I/O  
I/O  
A
6
A
A
A
24  
2
3
4
19  
18  
17  
16  
7
6
A
7
25  
26  
27  
28  
1
A
8
5
4
3
A
9
TSOP I  
Top View  
(not to scale)  
WE  
V
CC  
15  
14  
13  
A
A
A
A
A
5
6
7
GND  
I/O  
CE  
WE  
2
3
POWER  
DOWN  
2
COLUMN  
DECODER  
I/O  
1
12  
11  
4
5
8
9
I/O  
A
0
14  
I/O  
7
OE  
10  
9
A
6
10  
A
A
13  
12  
A
7
11  
8
Selection Guide  
–12  
12  
–15  
15  
–20  
20  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
160  
155  
90  
10  
150  
mA  
L
L
Maximum CMOS Standby Current  
10  
10  
mA  
0.05  
Cypress Semiconductor Corporation  
Document #: 38-05160 Rev. *B  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised August 3, 2006  
CY7C199  
DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V  
Output Current into Outputs (LOW)............................. 20 mA  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Static Discharge Voltage.......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
Storage Temperature .................................–65°C to +150°C  
Ambient Temperature with  
Power Applied.............................................–55°C to +125°C  
Latch-up Current.................................................... > 200 mA  
Operating Range  
Supply Voltage to Ground Potential  
(Pin 28 to Pin 14) ........................................... –0.5V to +7.0V  
Range  
Ambient Temperature[2]  
VCC  
DC Voltage Applied to Outputs  
Commercial  
0°C to +70°C  
5V ± 10%  
in High-Z State[1] ....................................–0.5V to VCC + 0.5V  
Electrical Characteristics Over the Operating Range [3]  
-12  
-15  
-20  
Parameter  
VOH  
Description  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Test Conditions  
VCC = Min., IOH=–4.0 mA  
VCC = Min., IOL=8.0 mA  
Min.  
Max.  
Min.  
Max.  
Min.  
Max. Unit  
2.4  
2.4  
2.4  
V
VOL  
0.4  
0.4  
0.4  
V
V
VIH  
2.2  
VCC  
+
2.2  
VCC  
+
2.2  
VCC +  
0.3V  
0.8  
+5  
0.3V  
0.3V  
0.8  
+5  
VIL  
IIX  
Input LOW Voltage  
–0.5  
–5  
–0.5  
–5  
0.8  
+5  
+5  
–0.5  
–5  
V
Input Leakage Current GND < VI < VCC  
µA  
µA  
IOZ  
Output Leakage Current GND < VO < VCC, Output  
Disabled  
–5  
+5  
–5  
–5  
+5  
ICC  
VCC Operating Supply VCC = Max.,  
Com’l  
L
160  
30  
155  
90  
150  
30  
mA  
mA  
Current  
I
OUT = 0 mA,  
f = fMAX = 1/tRC  
ISB1  
Automatic CE  
Power-down Current—  
Max.VCC, CE> VIH, Com’l  
30  
5
mA  
mA  
VIN > VIH or  
L
TTL Inputs  
VIN < VIL, f = fMAX  
ISB2  
Automatic CE  
Max. VCC  
,
Com’l  
L
10  
10  
10  
mA  
mA  
Power-down Current— CE > VCC – 0.3V  
CMOS Inputs IN > VCC – 0.3V  
or VIN < 0.3V, f = 0  
0.05  
V
Notes:  
1. V (min.) = –2.0V for pulse durations of less than 20 ns.  
IL  
2. T is the “instant on” case temperature.  
A
3. See the last page of this specification for Group A subgroup testing information.  
Document #: 38-05160 Rev. *B  
Page 2 of 11  
CY7C199  
Capacitance[4]  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
Max.  
Unit  
pF  
CIN  
TA = 25°C, f = 1 MHz,  
CC = 5.0V  
8
8
V
COUT  
pF  
AC Test Loads and Waveforms[5]  
R1 481Ω  
R1 481Ω  
5V  
5V  
ALL INPUT PULSES  
90%  
OUTPUT  
OUTPUT  
3.0V  
GND  
90%  
10%  
10%  
R2  
255 Ω  
30 pF  
R2  
255Ω  
5 pF  
≤tr  
≤tr  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
(a)  
(b)  
Equivalent to:  
THÉVENIN EQUIVALENT  
167Ω  
OUTPUT  
1.73V  
Data Retention Characteristics Over the Operating Range (L-version only)  
Parameter  
VDR  
ICCDR  
Description  
VCC for Data Retention  
Conditions[6]  
Min.  
Max.  
Unit  
V
2.0  
Data Retention Current  
VCC = VDR = 2.0V,  
CE > VCC – 0.3V,  
IN > VCC – 0.3V or VIN < 0.3V  
10  
µA  
ns  
[4]  
tCDR  
Chip Deselect to Data Retention Time  
Operation Recovery Time  
0
V
[5]  
tR  
200  
µs  
Data Retention Waveform  
DATA RETENTION MODE  
> 2V  
3.0V  
3.0V  
V
V
CC  
DR  
t
t
R
CDR  
CE  
Notes:  
4. Tested initially and after any design or process changes that may affect these parameters.  
5. t < 3 ns for the -12 and the -15 speeds. t < 5 ns for the -20 and slower speeds.  
R
R
6. No input may exceed V + 0.5V.  
CC  
Document #: 38-05160 Rev. *B  
Page 3 of 11  
CY7C199  
Switching Characteristics Over the Operating Range [3,7]  
-12  
-15  
-20  
Parameter  
Description  
Min.  
12  
Max.  
Min.  
15  
3
Max.  
Min.  
20  
3
Max.  
Unit  
Read Cycle  
tRC  
Read Cycle Time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
Data Hold from Address Change  
CE LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low-Z[8]  
OE HIGH to High-Z[8, 9]  
CE LOW to Low-Z[8]  
CE HIGH to High-Z[8, 9]  
CE LOW to Power-up  
CE HIGH to Power-down  
12  
15  
20  
tOHA  
3
tACE  
12  
5
15  
7
20  
9
tDOE  
tLZOE  
0
3
0
0
3
0
0
3
0
tHZOE  
5
5
7
7
9
9
tLZCE  
tHZCE  
tPU  
tPD  
12  
15  
20  
Write Cycle[10, 11]  
tWC  
tSCE  
tAW  
Write Cycle Time  
12  
9
15  
10  
10  
0
20  
15  
15  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CE LOW to Write End  
Address Set-up to Write End  
Address Hold from Write End  
Address Set-up to Write Start  
WE Pulse Width  
9
tHA  
0
tSA  
0
0
0
tPWE  
tSD  
8
9
15  
10  
0
Data Set-up to Write End  
Data Hold from Write End  
WE LOW to High-Z[9]  
8
9
tHD  
0
0
tHZWE  
7
7
10  
tLZWE  
WE HIGH to Low-Z[8]  
3
3
3
Notes:  
7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V,  
input pulse levels of 0 to 3.0V, and output loading of the specified I /I and 30-pF load capacitance.  
OL OH  
8. At any given temperature and voltage condition, t  
is less than t  
, t  
is less than t  
, and t  
is less than t  
for any given device.  
HZCE  
LZCE HZOE  
LZOE  
HZWE  
LZWE  
9. t  
, t  
, and t  
are specified with C = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.  
HZOE HZCE  
HZWE L  
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a  
write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.  
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t  
and t .  
SD  
HZWE  
Document #: 38-05160 Rev. *B  
Page 4 of 11  
CY7C199  
Switching Waveforms  
Read Cycle No. 1[12, 13]  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Read Cycle No. 2 [13, 14]  
t
RC  
CE  
OE  
t
ACE  
t
t
HZOE  
t
DOE  
HZCE  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
DATA VALID  
t
LZCE  
t
PD  
t
PU  
V
ICC  
CC  
SUPPLY  
CURRENT  
50%  
50%  
ISB  
Notes:  
12. Device is continuously selected. OE, CE = V .  
IL  
13. WE is HIGH for read cycle.  
14. Address valid prior to or coincident with CE transition LOW.  
Document #: 38-05160 Rev. *B  
Page 5 of 11  
CY7C199  
Switching Waveforms (continued)  
Write Cycle No. 1 (WE Controlled)[10, 15, 16]  
t
WC  
ADDRESS  
CE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
OE  
t
SD  
t
HD  
DATA VALID  
DATA I/O  
IN  
t
HZOE  
Write Cycle No. 2 (CE Controlled)[10, 15, 16]  
t
WC  
ADDRESS  
CE  
t
SCE  
t
SA  
t
t
HA  
AW  
WE  
t
t
HD  
SD  
DATA I/O  
DATA VALID  
IN  
Notes:  
15. Data I/O is high impedance if OE = V  
.
IH  
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.  
Document #: 38-05160 Rev. *B  
Page 6 of 11  
CY7C199  
Switching Waveforms (continued)  
Write Cycle No. 3 (WE Controlled OE LOW)[11, 16]  
t
WC  
ADDRESS  
CE  
t
t
HA  
AW  
t
SA  
WE  
t
t
HD  
SD  
DATA I/O  
DATA VALID  
IN  
t
t
LZWE  
HZWE  
Typical DC and AC Characteristics  
NORMALIZED SUPPLY CURRENT  
vs. AMBIENT TEMPERATURE  
OUTPUT SOURCE CURRENT  
vs. OUTPUT VOLTAGE  
NORMALIZED SUPPLY CURRENT  
vs. SUPPLY  
VOLTAGE  
120  
100  
80  
1.4  
1.2  
1.4  
1.2  
1.0  
0.8  
0.6  
I
CC  
I
CC  
1.0  
0.8  
0.6  
V
CC  
=5.0V  
60  
T =25°C  
A
V
IN  
=5.0V  
T =25°C  
A
40  
V
V
IN  
=5.0V  
=5.0V  
0.4  
CC  
0.4  
20  
0
0.2  
0.0  
0.2  
0.0  
I
SB  
I
SB  
–55  
25  
125  
0.0  
1.0  
2.0  
3.0  
4.0  
4.0  
4.5  
5.0  
5.5  
6.0  
AMBIENT TEMPERATURE (°C)  
OUTPUT VOLTAGE (V)  
SUPPLY VOLTAGE (V)  
NORMALIZED ACCESS TIME  
vs. AMBIENT TEMPERATURE  
OUTPUT SINK CURRENT  
vs. OUTPUT VOLTAGE  
NORMALIZED ACCESS TIME  
vs. SUPPLY VOLTAGE  
140  
120  
1.6  
1.4  
1.4  
1.3  
1.2  
100  
80  
1.2  
1.0  
1.1  
1.0  
60  
T =25°C  
A
V
CC  
=5.0V  
T =25°C  
A
V
CC  
=5.0V  
40  
0.8  
20  
0
0.9  
0.8  
0.6  
–55  
0.0  
1.0  
2.0  
3.0  
4.0  
25  
125  
4.0  
4.5  
5.0  
5.5  
6.0  
AMBIENT TEMPERATURE (°C)  
OUTPUT VOLTAGE (V)  
SUPPLY VOLTAGE (V)  
Document #: 38-05160 Rev. *B  
Page 7 of 11  
CY7C199  
Typical DC and AC Characteristics (continued)  
TYPICALPOWER-ON CURRENT  
vs.SUPPLY VOLTAGE  
TYPICAL ACCESS TIMECHANGE  
vs. OUTPUT LOADING  
NORMALIZED I vs. CYCLETIME  
CC  
3.0  
2.5  
2.0  
1.5  
30.0  
25.0  
20.0  
15.0  
1.25  
1.00  
0.75  
0.50  
V
=5.0V  
CC  
T =25°C  
A
V
IN  
=0.5V  
V
=4.5V  
1.0  
0.5  
10.0  
5.0  
CC  
T =25°C  
A
0.0  
0.0  
0.0  
1.0  
2.0  
3.0  
4.0  
5.0  
0
200 400  
600 800 1000  
10  
20  
30  
40  
SUPPLY VOLTAGE (V)  
CAPACITANCE (pF)  
CYCLE FREQUENCY (MHz)  
Truth Table  
CE  
H
L
WE  
X
OE  
X
Inputs/Outputs  
High Z  
Mode  
Power  
Deselect/Power-down  
Read  
Standby (ISB  
Active (ICC  
Active (ICC  
Active (ICC  
)
H
L
Data Out  
Data In  
High Z  
)
L
L
X
Write  
)
L
H
H
Deselect, Output disabled  
)
Ordering Information  
Speed  
Package  
Diagram  
Operating  
Range  
(ns)  
Ordering Code  
CY7C199-12ZXC  
Package Type  
12  
51-85071 28-pin TSOP I (Pb-free)  
51-85071 28-pin TSOP I (Pb-free)  
Commercial  
Commercial  
15  
CY7C199-15ZXC  
CY7C199L-15ZXC  
CY7C199-20PXC  
20  
51-85014 28-pin (300-Mil) Molded DIP (Pb-free)  
Commercial  
Document #: 38-05160 Rev. *B  
Page 8 of 11  
CY7C199  
Package Diagrams  
28-pin (300-Mil) PDIP (51-85014)  
SEE LEAD END OPTION  
14  
1
MIN.  
DIMENSIONS IN INCHES [MM]  
MAX.  
REFERENCE JEDEC MO-095  
PACKAGE WEIGHT: 2.15 gms  
0.260[6.60]  
0.295[7.49]  
15  
28  
0.030[0.76]  
0.080[2.03]  
SEATING PLANE  
1.345[34.16]  
1.385[35.18]  
0.290[7.36]  
0.325[8.25]  
0.120[3.05]  
0.140[3.55]  
0.140[3.55]  
0.190[4.82]  
0.009[0.23]  
0.012[0.30]  
0.115[2.92]  
0.160[4.06]  
3° MIN.  
0.015[0.38]  
0.060[1.52]  
0.055[1.39]  
0.065[1.65]  
0.310[7.87]  
0.385[9.78]  
0.090[2.28]  
0.110[2.79]  
0.015[0.38]  
0.020[0.50]  
SEE LEAD END OPTION  
51-85014-*D  
LEAD END OPTION  
(LEAD #1, 14, 15 & 28)  
Document #: 38-05160 Rev. *B  
Page 9 of 11  
CY7C199  
Package Diagrams (continued)  
28-pin TSOP Type 1 (8x13.4 mm) (51-85071)  
51-85071-*G  
All products and company names mentioned in this document are the trademarks of their respective holders.  
Document #: 38-05160 Rev. *B  
Page 10 of 11  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY7C199  
Document History Page  
Document Title: CY7C199 32K x 8 Static RAM  
Document Number: 38-05160  
Issue  
Date  
Orig. of  
Change  
REV.  
**  
ECN NO.  
109971  
121730  
492500  
Description of Change  
Change from Spec number: 38-00239 to 38-05160  
Updated Product Offering table  
10/28/01  
01/09/02  
See ECN  
SZV  
DFP  
NXR  
*A  
*B  
Removed 8 ns, 10 ns, 25 ns , 35 ns, 45 ns speed bins  
Removed 28-Lead (300-Mil) CerDIP, 28-Pin Rectangular Leadless Chip  
Carrier, 28-Lead MoldedSOIC, 28-Lead MoldedSOJ packages fromproduct  
offering  
Changed the description of IIX from Input Load Current to Input Leakage  
Current in DC Electrical Characteristics table  
Removed IOS parameter from DC Electrical Characteristics Table  
Updated Ordering Information Table  
Document #: 38-05160 Rev. *B  
Page 11 of 11  

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CYPRESS

CY7C2245KV18-450BZXI

 QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
CYPRESS

CY7C225

 512 x 8 Registered PROM
CYPRESS

CY7C225-25DC

 OTP ROM, 512X8, 20ns, CMOS, CDIP24, 0.300 INCH, SLIM, CERDIP-24
CYPRESS

CY7C225-25DI

 OTP ROM, 512X8, 12ns, CMOS, CDIP24, 0.300 INCH, SLIM, HERMETIC SEALED, CERDIP-24
CYPRESS

CY7C225-25JC

 OTP ROM, 512X8, 20ns, CMOS, PQCC28, PLASTIC, LCC-28
CYPRESS
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