CY7C4265V-10ASC [CYPRESS]
32K/64Kx18 Low Voltage Deep Sync FIFOs; 32K / 64Kx18低压深同步FIFO的
| 型号： | CY7C4265V-10ASC |
| 厂家： | 
CYPRESS |
| 描述： | 32K/64Kx18 Low Voltage Deep Sync FIFOs |
| 文件： | 总20页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
285V
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
32K/64Kx18 Low Voltage Deep Sync FIFOs
Features
Functional Description
The CY7C4255/65/75/85V are high-speed, low-power, first-in
• 3.3V operation for low power consumption and easy
integration into low-voltage systems
• High-speed, low-power, first-in first-out (FIFO)
memories
• 8K x 18 (CY7C4255V)
• 16K x 18 (CY7C4265V)
first-out (FIFO) memories with clocked read and write interfac-
es. All are 18 bits wide and are pin/functionally compatible to
the CY7C42X5V Synchronous FIFO family. The
CY7C4255/65/75/85V can be cascaded to increase FIFO
depth. Programmable features include Almost Full/Almost
Empty flags. These FIFOs provide solutions for a wide variety of
data buffering needs, including high-speed data acquisition, multipro-
cessor interfaces, and communications buffering.
• 32K x 18 (CY7C4275V)
• 64K x 18 (CY7C4285V)
• 0.35 micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
times)
• Low power
— ICC = 30 mA
— ISB = 4 mA
These FIFOs have 18-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and a write enable
pin (WEN).
When WEN is asserted, data is written into the FIFO on the rising
edge of the WCLK signal. While WEN is held active, data is continu-
ally written into the FIFO on each cycle. The output port is controlled
in a similar manner by a free-running read clock (RCLK) and a read
enable pin (REN). In addition, the CY7C4255/65/75/85V have an
output enable pin (OE). The read and write clocks may be tied togeth-
er for single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock frequencies
up to 67 MHz are achievable.
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, HalfFull, andprogrammableAlmostEmpty
and Almost Full status flags
• Retransmit function
• Output Enable (OE) pin
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
• Independent read and write enable pins
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• 64-pin 10x10 STQFP
• Pin-compatible density upgrade to CY7C42X5V-ASC
families
• Pin-compatible 3.3V solutions for CY7C4255/65/75/85
Depth expansion is possible using the cascade input (WXI,
RXI), cascade output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of the
next device, and the WXO and RXO pins of the last device should be
connected to the WXI and RXI pins of the first device. The FL pin of
the first device is tied to VSS and the FL pin of all the remaining devic-
es should be tied to VCC
.
D
0 – 17
Logic Block Diagram
INPUT
REGISTER
WCLK
WEN
FLAG
PROGRAM
REGISTER
WRITE
CONTROL
High
FF
EF
Density
Dual-Port
RAM Array
FLAG
LOGIC
PAE
PAF
SMODE
8Kx9
16Kx9
32Kx9
64Kx9
WRITE
POINTER
READ
POINTER
RS
RESET
LOGIC
FL/RT
THREE-STATE
OUTPUTREGISTER
READ
CONTROL
WXI
WXO/HF
RXI
EXPANSION
LOGIC
OE
Q
0 – 17
RXO
4275V–1
RCLK
REN
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-06012 Rev. *A
Revised December 26, 2002
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Pin Configuration
STQFP
Top View
Q
48
47
D
15
D
14
D
13
D
12
1
2
14
Q
13
GND
46
45
3
4
Q
12
Q
V
44
43
42
41
11
D
D
5
6
7
8
11
10
CC
CY7C4255V
CY7C4265V
CY7C4275V
CY7C4285V
Q
10
D
9
Q
9
D
D
8
7
6
GND
40
39
9
10
Q
8
D
D
D
D
D
D
38
37
36
11
12
13
Q
7
5
Q
6
4
3
Q
5
35
34
14
15
GND
2
Q
4
1
D
0
33
V
CC
16
4275V–3
The Empty and Full flags are synchronous, i.e., they change
state relative to either the read clock (RCLK) or the write clock
(WCLK). When entering or exiting the Empty states, the flag is
updated exclusively by the RCLK. The flag denoting Full states
is updated exclusively by WCLK. The synchronous flag archi-
tecture guarantees that the flags will remain valid from one
clock cycle to the next. The Almost Empty/Almost Full flags
become synchronous if the VCC/SMODE is tied to VSS. All
configurations are fabricated using an advanced 0.35µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Functional Description (continued)
The CY7C4255/65/75/85V provides five status pins. These
pins are decoded to determine one of five states: Empty, Al-
most Empty, Half Full, Almost Full, and Full (see Table 2). The
Half Full flag shares the WXO pin. This flag is valid in the
stand-alone and width-expansion configurations. In the depth
expansion, this pin provides the expansion out (WXO) infor-
mation that is used to signal the next FIFO when it will be
activated.
Selection Guide
7C4255/65/75/85V-10
100
7C4255/65/75/85V-15
7C4255/65/75/85V-25
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
66.7
10
15
4
40
15
25
6
8
10
3.5
0
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
0
1
8
10
30
35
15
30
Active Power Supply
Current (ICC1) (mA)
Commercial
Industrial
30
CY7C4255V
CY7C4265V
CY7C4275V
32K x 18
CY7C4285V
64K x 18
Density
8K x 18
16K x 18
Package
64-pin 10x10 TQFP
64-pin 10x10 TQFP
64-pin 10x10 TQFP
64-pin 10x10 TQFP
Document #: 38-06012 Rev. *A
Page 2 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Pin Definitions
Signal Name
Description
I/O
Function
D0–17
Q0–17
WEN
REN
Data Inputs
Data Outputs
Write Enable
Read Enable
Write Clock
I
O
I
Data inputs for an 18-bit bus.
Data outputs for an 18-bit bus.
Enables the WCLK input.
Enables the RCLK input.
I
WCLK
I
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not
Full. When LD is asserted, WCLK writes data into the programmable flag-offset
register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-
offset register.
WXO/HF
Write Expansion
Out/Half Full Flag
O
Dual-Mode Pin:
Single device or width expansion – Half Full status flag.
Cascaded – Write Expansion Out signal, connected to WXI of next device.
EF
Empty Flag
Full Flag
O
O
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
FF
PAE
Programmable
Almost Empty
When PAE is LOW, the FIFO is almost empty based on the almost-empty offset
value programmed into the FIFO. PAE is asynchronous when VCC/SMODE is tied
to VCC; it is synchronized to RCLK when VCC/SMODE is tied to VSS
.
PAF
Programmable
Almost Full
O
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when VCC/SMODE is tied to
VCC; it is synchronized to WCLK when VCC/SMODE is tied to VSS
.
LD
Load
I
I
When LD is LOW, D0–17 (Q0–17) are written (read) into (from) the programmable-
flag-offset register.
FL/RT
First Load/
Retransmit
Dual-Mode Pin:
Cascaded – The first device in the daisy chain will have FL tied to VSS; all other
devices will have FL tied to VCC. In standard mode or width expansion, FL is tied
to VSS on all devices.
Not Cascaded – Tied to VSS. Retransmit function is also available in stand-alone
mode by strobing RT.
WXI
RXI
RXO
RS
Write Expansion
Input
I
I
Cascaded – Connected to WXO of previous device.
Not Cascaded – Tied to VSS
.
Read Expansion
Input
Cascaded – Connected to RXO of previous device.
Not Cascaded – Tied to VSS
.
Read Expansion
Output
O
I
Cascaded – Connected to RXI of next device.
Reset
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are con-
nected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
VCC/SMODE Synchronous
Almost Empty/
I
Dual-Mode Pin:
Asynchronous Almost Empty/Almost Full flags – tied to VCC
Synchronous Almost Empty/Almost Full flags – tied to VSS
(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)
.
Almost Full Flags
.
Document #: 38-06012 Rev. *A
Page 3 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Maximum Ratings[1]
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >2001V
(per MIL–STD–883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature ................................–65°C to +150°C
Ambient Temperature with
Power Applied............................................ –55°C to +125°C
Operating Range
Ambient
Supply Voltage to Ground Potential.........–0.5V to VCC+0.5V
[3]
Range
Commercial
Industrial[2]
Temperature
0°C to +70°C
–40°C to +85°C
VCC
DC Voltage Applied to Outputs
in High Z State .........................................–0.5V to VCC+0.5V
3.3V ±300 mV
3.3V ±300 mV
DC Input Voltage ..........................................−0.5V to VCC+0.5V
Electrical Characteristics Over the Operating Range[4]
7C4255/65/75/
85V-10
7C4255/65/75/
85V-15
7C4255/65/75/
85V-25
Parameter
Description
Test Conditions
Min.
Max.
Min.
Max.
Min.
Max.
Unit
VOH
Output HIGH
Voltage
VCC = Min., IOH = –1.0 mA
VCC = 3.0V. IOH = –2.0
mA
2.4
2.4
2.4
V
VOL
Output LOW
Voltage
VCC = Min.,IOL = 4.0 mA
VCC = 3.0V.,IOL = 8.0 mA
0.4
VCC
0.8
0.4
VCC
0.8
0.4
VCC
0.8
V
V
[5]
VIH
Input HIGH
Voltage
2.0
–0.5
–10
–10
2.0
–0.5
–10
–10
2.0
–0.5
–10
–10
[5]
VIL
Input LOW
Voltage
V
IIX
Input Leakage
Current
VCC = Max.
+10
+10
30
+10
+10
+10
+10
30
µA
µA
IOZL
IOZH
Output OFF,
High Z Current
OE > VIH,
VSS < VO < VCC
[6]
ICC1
Active Power
Supply Current
Com’l
Ind
30
35
4
mA
mA
mA
mA
[7]
ISB
AverageStandby
Current
Com’l
Ind
4
4
4
Capacitance[8]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 3.3V
5
7
pF
pF
COUT
Notes:
1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
2.
TA is the “instant on” case temperature.
3. VCC range for commercial -10 ns is 3.3V ±150mV.
4. See the last page of this specification for Group A subgroup testing information.
5. The VIH and VIL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the
previous device or VSS
.
6. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs
are unloaded.
7. All inputs = VCC – 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz), and FL/RT which is at VSS. All outputs are unloaded.
8. Tested initially and after any design changes that may affect these parameters.
Document #: 38-06012 Rev. *A
Page 4 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
AC Test Loads and Waveforms (-15 -25)[9, 10]
R1=330Ω
3.3V
ALL INPUT PULSES
OUTPUT
3.0V
GND
90%
90%
10%
R2=510Ω
10%
C
L
≤ 3 ns
≤ 3 ns
INCLUDING
JIG AND
SCOPE
4275V–4
4287V–5
Equivalent to:
THÉVENIN EQUIVALENT
200
Ω
OUTPUT
2.0V
AC Test Loads and Waveforms (-10)
ALL INPUT PULSES
V
/2
CC
3.0V
GND
90%
10%
90%
10%
50Ω
≤ 3 ns
≤ 3 ns
I/O
Z0=50Ω
4275V–6
4275V–7
Switching Characteristics Over the Operating Range
7C4255/65/75/85V 7C4255/65/75/85V 7C4255/65/75/85V
-10 -15 -25
Parameter
tS
Description
Clock Cycle Frequency
Min.
Max.
100
8
Min.
Max.
66.7
10
Min.
Max.
40
Unit
MHz
ns
tA
Data Access Time
2
10
4.5
4.5
3.5
0
2
15
6
2
25
10
10
6
15
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
ns
Clock HIGH Time
ns
Clock LOW Time
6
ns
Data Set-Up Time
4
ns
tDH
Data Hold Time
0
1
ns
tENS
tENH
tRS
Enable Set-Up Time
Enable Hold Time
3.5
0
4
6
ns
0
1
ns
Reset Pulse Width[11]
Reset Recovery Time
Reset to Flag and Output Time
Retransmit Pulse Width
Retransmit Recovery Time
Output Enable to Output in Low Z[12]
Output Enable to Output Valid
10
8
15
10
25
15
ns
tRSR
tRSF
tPRT
tRTR
tOLZ
ns
10
7
15
10
25
12
ns
60
90
0
60
90
0
60
90
0
ns
ns
ns
tOE
3
3
3
ns
Notes:
9. CL = 30 pF for all AC parameters except for tOHZ
.
10. CL = 5 pF for tOHZ
.
11. Pulse widths less than minimum values are not allowed.
12. Values guaranteed by design, not currently tested.
Document #: 38-06012 Rev. *A
Page 5 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Switching Characteristics Over the Operating Range (continued)
7C4255/65/75/85V 7C4255/65/75/85V 7C4255/65/75/85V
-10 -15 -25
Parameter
tOHZ
Description
Output Enable to Output in High Z[12]
Write Clock to Full Flag
Min.
Max.
7
Min.
Max.
8
Min.
Max.
12
Unit
ns
3
3
3
tWFF
8
10
15
ns
tREF
Read Clock to Empty Flag
8
10
15
ns
tPAFasynch
Clock to Programmable Almost-Full
Flag[13] (Asynchronous mode,
15
16
20
ns
VCC/SMODE tied to VCC
)
tPAFsynch
tPAEasynch
tPAEsynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODEtied to
8
15
8
10
16
10
15
20
15
ns
ns
ns
VSS
)
Clock to Programmable Almost-Empty
Flag[13] (Asynchronous mode, VCC/SMODE
tied to VCC
)
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODEtied to
VSS
)
tHF
Clock to Half-Full Flag
Clock to Expansion Out
Expansion in Pulse Width
Expansion in Set-Up Time
12
6
16
10
20
15
ns
ns
ns
ns
ns
tXO
tXI
4.5
4
6.5
5
10
10
10
tXIS
tSKEW1
Skew Time between Read Clock and
Write Clock for Full Flag
5
6
tSKEW2
tSKEW3
Skew Time between Read Clock and
Write Clock for Empty Flag
5
6
10
18
ns
ns
Skew Time between Read Clock and
Write Clock for Programmable Almost
Empty and Programmable Almost Full
Flags (Synchronous Mode only)
10
15
Note:
13. tPAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tPAF(E)
.
Document #: 38-06012 Rev. *A
Page 6 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Switching Waveforms
Write Cycle Timing
t
CLK
t
t
CLKL
CLKH
WCLK
t
t
DH
DS
D –D
0
17
t
ENH
t
ENS
WEN
FF
NO OPERATION
t
t
WFF
WFF
[14]
t
SKEW1
RCLK
REN
4275V–8
Read Cycle Timing
t
CLK
t
t
CLKL
CLKH
RCLK
t
t
ENH
ENS
REN
EF
NO OPERATION
t
REF
t
REF
t
A
VALID DATA
Q
–Q
17
0
t
OLZ
t
OHZ
t
OE
OE
[15]
SKEW2
t
WCLK
WEN
4275V–9
Notes:
14. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
15. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge.
Document #: 38-06012 Rev. *A
Page 7 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Switching Waveforms (continued)
Reset Timing [16]
t
RS
RS
t
RSR
REN, WEN,
LD
t
t
t
RSF
RSF
RSF
EF,PAE
FF,PAF,
HF
[17]
OE=1
Q
Q
0 – 17
OE=0
4275V–10
First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
t
DS
D –D
D
0
(FIRSTVALIDWRITE)
D
1
D
2
D
3
D
4
0
17
t
ENS
[18]
FRL
t
WEN
t
SKEW2
RCLK
t
REF
EF
REN
–Q
[19]
t
A
t
A
Q
D
D
1
0
17
0
t
OLZ
t
OE
OE
4275V–11
Notes:
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
18. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2
or tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW).
19. The first word is always available the cycle after EF goes HIGH.
Document #: 38-06012 Rev. *A
Page 8 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Switching Waveforms (continued)
Empty Flag Timing
WCLK
t
t
DS
DS
D0
D1
D –D
0
17
t
t
ENH
ENH
t
t
ENS
ENS
WEN
[18]
FRL
t
[18]
FRL
t
RCLK
t
t
t
REF
t
REF
t
SKEW2
REF
SKEW2
EF
REN
OE
t
A
D0
Q
–Q
17
0
4275V–12
Full FlagTiming
NO WRITE
NO WRITE
WCLK
[14]
[14]
t
t
DS
DATA WRITE
t
SKEW1
SKEW1
DATA WRITE
D –D
0
17
t
t
t
WFF
WFF
WFF
FF
WEN
RCLK
t
t
ENH
ENH
t
t
ENS
ENS
REN
OE
LOW
t
A
t
A
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
Q
–Q
17
0
4275V–13
Document #: 38-06012 Rev. *A
Page 9 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Switching Waveforms (continued)
Half-Full Flag Timing
t
t
CLKL
CLKH
WCLK
WEN
t
t
ENH
ENS
t
HF
HALF FULL + 1
OR MORE
HALF
HALF FULL OR LESS
FULL OR LESS
HF
t
HF
RCLK
REN
t
ENS
4275V–14
Programmable Almost Empty Flag Timing
t
t
CLKL
CLKH
WCLK
WEN
t
t
ENH
ENS
t
PAE
[20]
N + 1 WORDS
IN FIFO
PAE
n WORDS IN FIFO
t
PAE
RCLK
REN
t
ENS
4275V–15
Note:
20. PAE is offset = n. Number of data words into FIFO already = n.
Document #: 38-06012 Rev. *A
Page 10 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Switching Waveforms (continued)
Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW))
t
t
CLKL
CLKH
WCLK
WEN
PAE
t
t
ENS ENH
21
Note
N + 1 WORDS
IN FIFO
Note
23
t
PAE synch
[22]
t
t
SKEW3
PAE synch
RCLK
REN
t
ENS
t
t
ENS ENH
4275V–16
Programmable Almost Full Flag Timing
t
t
CLKL
CLKH
Note 24
WCLK
WEN
t
t
ENS ENH
t
PAF
FULL– M WORDS
[25]
PAF
[26]
IN FIFO
FULL– (M+1) WORDS
[27]
IN FIFO
t
PAF
RCLK
REN
t
ENS
4275V–17
Notes:
21. PAE offset − n.
22.
tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the
rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK.
23. If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW.
24. PAF offset = m. Number of data words written into FIFO already = 8192 − (m + 1) for the CY7C4255V, 16384 − (m + 1) for the CY7C4265V, 32768 − (m +
1) for the CY7C4275V, and 65536 − (m + 1) for the CY7C4285V.
25. PAF is offset = m.
26. 8192 − m words in CY7C4255V, 16384 − m words in CY7C4265V, 32768 − m words in CY7C4275V, and 65536 − m words in CY7C4285V.
27. 8192− (m + 1) words in CY7C4255V, 16384 − (m + 1) words in CY7C4265V, 32768 − (m + 1) words in CY7C4275V, and 65536 − (m + 1) words in CY7C4285V.
Document #: 38-06012 Rev. *A
Page 11 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Switching Waveforms (continued)
Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW))
28
Note
t
t
CLKL
CLKH
WCLK
t
t
ENH
ENS
WEN
PAF
t
PAF
FULL– M WORDS
IN FIFO
[26]
FULL – M + 1 WORDS
IN FIFO
t
[29]
PAF synch
t
SKEW3
RCLK
REN
t
ENS
t
t
ENH
ENS
4275V–18
Write Programmable Registers
t
CLK
t
t
CLKL
CLKH
WCLK
LD
t
t
ENS
ENH
t
ENS
WEN
t
t
DH
DS
PAE OFFSET
D –D
0
17
D
D –
0
PAE OFFSET
PAF OFFSET
11
4275V–19
Notes:
28. If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LOW.
29. tSKEW3 is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge
of RCLK and the rising edge of WCLK is less than tSKEW3, then PAF may not change state until the next WCLK rising edge.
Document #: 38-06012 Rev. *A
Page 12 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Switching Waveforms (continued)
Read Programmable Registers
t
CLK
t
t
CLKL
CLKH
RCLK
LD
t
t
ENS
ENH
t
ENS
WEN
t
A
UNKNOWN
PAE OFFSET
PAF OFFSET
PAE OFFSET
Q
–Q
17
0
4275V–20
Write ExpansionOut Timing
t
CLKH
WCLK
Note 31
Note 30
t
XO
WXO
t
XO
t
ENS
WEN
4275V–21
Read Expansion Out Timing
t
CLKH
WCLK
Note 31
t
XO
RXO
REN
t
XO
t
ENS
4275V–22
Write Expansion In Timing
t
XI
WXI
t
XIS
WCLK
4275V–23
Notes:
30. Write to Last Physical Location.
31. Read from Last Physical Location.
Document #: 38-06012 Rev. *A
Page 13 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Switching Waveforms (continued)
Read Expansion In Timing
t
XI
RXI
t
XIS
RCLK
4275V–24
Retransmit Timing [32, 33, 34]
FL/RT
t
PRT
t
RTR
REN/WEN
EF/FF
and all
async flags
HF/PAE/PAF
4275V–25
Notes:
32. Clocks are free-running in this case.
33. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR
34. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after tRTR to update these flags.
.
Document #: 38-06012 Rev. *A
Page 14 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
normal read/write operation. When the LD pin is set LOW, and
WEN is LOW, the next offset register in sequence is written.
Architecture
The CY7C4255/65/75/85V consists of an array of
8K/16K/32K/64K words of 18 bits each (implemented by a
dual-port array of SRAM cells), a read pointer, a write pointer,
control signals (RCLK, WCLK, REN, WEN, RS), and flags (EF,
PAE, HF, PAF, FF). The CY7C4255/65/75/85V also includes
the control signals WXI, RXI, WXO, RXO for depth expansion.
The contents of the offset registers can be read on the output
lines when the LD pin is set LOW and REN is set LOW; then,
data can be read on the LOW-to-HIGH transition of the read
clock (RCLK).
Table 1. Write Offset Register
LD WEN WCLK[35]
Selection
Resetting the FIFO
0
0
Writing to offset registers:
Empty Offset
Full Offset
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition sig-
nified by EF being LOW. All data outputs go LOW after the
falling edge of RS only if OE is asserted. In order for the FIFO
to reset to its default state, the user must not read or write while
RS is LOW.
0
1
1
1
0
1
No Operation
Write Into FIFO
No Operation
FIFO Operation
When the WEN signal is active (LOW), data present on the
D0–17 pins is written into the FIFO on each rising edge of the
WCLK signal. Similarly, when the REN signal is active LOW,
data in the FIFO memory will be presented on the Q0–17 out-
puts. New data will be presented on each rising edge of RCLK
while REN is active LOW and OE is LOW. REN must set up
tENS before RCLK for it to be a valid read function. WEN must
occur tENS before WCLK for it to be a valid write function.
Flag Operation
The CY7C4255/65/75/85V devices provide five flag pins to in-
dicate the condition of the FIFO contents. Empty and Full are
synchronous. PAE and PAF are synchronous if VCC/SMODE
An output enable (OE) pin is provided to three-state the Q0–17
outputs when OE is deasserted. When OE is enabled (LOW),
data in the output register will be available to the Q0–17 outputs
after tOE. If devices are cascaded, the OE function will only
output data on the FIFO that is read enabled.
is tied to VSS
.
Full Flag
The Full Flag (FF) will go LOW when device is Full. Write op-
erations are inhibited whenever FF is LOW regardless of the
state of WEN. FF is synchronized to WCLK, i.e., it is exclusive-
ly updated by each rising edge of WCLK.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and under flow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0–17 outputs
even after additional reads occur.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW, regard-
less of the state of REN. EF is synchronized to RCLK, i.e., it is
exclusively updated by each rising edge of RCLK.
Programming
The CY7C4255/65/75/85V devices contain two 16-bit offset
registers. Data present on D0–15 during a program write will
determine the distance from Empty (Full) that the Almost Emp-
ty (Almost Full) flags become active. If the user elects not to
program the FIFO’s flags, the default offset values are used
(see Table 2). When the Load LD pin is set LOW and WEN is
set LOW, data on the inputs D0–15 is written into the Empty
offset register on the first LOW-to-HIGH transition of the write
clock (WCLK). When the LD pin and WEN are held LOW then
data is written into the Full offset register on the second LOW-
to-HIGH transition of the write clock (WCLK). The third transi-
tion of the write clock (WCLK) again writes to the Empty offset
register (see Table 1). Writing all offset registers does not have
to occur at one time. One or two offset registers can be written
and then, by bringing the LD pin HIGH, the FIFO is returned to
Note:
Programmable Almost Empty/Almost Full Flag
The CY7C4255/65/75/85V features programmable Almost
Empty and Almost Full Flags. Each flag can be programmed
(described in the Programming section) a specific distance
from the corresponding boundary flags (Empty or Full). When
the FIFO contains the number of words or fewer for which the
flags have been programmed, the PAF or PAE will be assert-
ed, signifying that the FIFO is either Almost Full or Almost
Empty. See Table 2 for a description of programmable flags.
When the SMODE pin is tied LOW, the PAF flag signal transi-
tion is caused by the rising edge of the write clock and the PAE
flag transition is caused by the rising edge of the read clock.
35. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Document #: 38-06012 Rev. *A
Page 15 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Table 2. Flag Truth Table
Number of Words in FIFO
7C4265V – 16K x 18 7C4275V – 32K x 18 7C4285V – 64K x 18 FF
PA
F
PA
E
7C4255V – 8K x 18
HF
H
EF
L
0
0
0
0
H
H
H
H
H
H
H
H
L
L
1 to n[36]
1 to n[36]
1 to n[36]
1 to n[36]
H
H
(n+1) to 4096
(n+1) to 8192
(n+1) to 16384
(n+1) to 32768
H
H
H
H
4097 to (8192–(m+1)) 8193 to (16384
–(m+1))
16385 to
32769 to (65536
L
H
(32768–(m+1))
–(m+1))
(8192–m)[37] to 8192
(16384–m)[37] to
16384
(32768–m)[37] to
32767
(65536–m)[37] to
65535
H
L
L
L
L
L
H
H
H
H
8192
16384
32768
65536
cycle. Data written to the FIFO after activation of RT are trans-
mitted also.
Retransmit
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The full depth of the FIFO can be repeatedly retransmitted.
Width Expansion Configuration
The Retransmit (RT) input is active in the stand-alone and
width expansion modes. The retransmit feature is intended for
use when a number of writes equal to or less than the depth
of the FIFO have occurred and at least one word has been
read since the last RS cycle. A HIGH pulse on RT resets the
internal read pointer to the first physical location of the FIFO.
WCLK and RCLK may be free running but must be disabled
during and tRTR after the retransmit pulse. With every valid
read cycle after retransmit, previously accessed data is read
and the read pointer is incremented until it is equal to the write
pointer. Flags are governed by the relative locations of the
read and write pointers and are updated during a retransmit
The CY7C4255/65/75/85V can be expanded in width to pro-
vide word widths greater than 18 in increments of 18. During
width expansion mode all control line inputs are common and
all flags are available. Empty (Full) flags should be created by
ANDing the Empty (Full) flags of every FIFO; the PAE and PAF
flags can be detected from any one device. This technique will
avoid reading data from, or writing data to the FIFO that is
“staggered” by one clock cycle due to the variations in skew
between RCLK and WCLK. Figure 1 demonstrates a 36-word
width by using two CY7C4255/65/75/85Vs.
RESET(RS)
RESET(RS)
DATA IN (D)
36
18
18
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
WRITE CLOCK(WCLK)
WRITE ENABLE(WEN)
LOAD (LD)
PROGRAMMABLE(PAE)
HALF FULL FLAG (HF)
PROGRAMMABLE (PAF)
7C4255V
7C4265V
7C4275V
7C4285V
7C4255V
7C4265V
7C4275V
7C4285V
EMPTY FLAG (EF)
EF
FF
FF
EF
DATA OUT (Q)
18
36
FULL FLAG (FF)
18
FIRST LOAD (FL)
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (RXI)
4275V–24
Figure 1. Block Diagram of 8K/16K/32K/64K x 18 Low-Voltage Synchronous FIFO Memory Used in a Width Expansion
Configuration
Notes:
36. n = Empty Offset (Default Values: CY7C4255/65/75/85V n = 127).
37. m = Full Offset (Default Values: CY7C4255/65/75/85V n = 127).
Document #: 38-06012 Rev. *A
Page 16 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
3. The Write Expansion Out (WXO) pin of each device must
be tied to the Write Expansion In (WXI) pin of the next
device.
Depth Expansion Configuration
(with Programmable Flags)
The CY7C4255/65/75/85V can easily be adapted to applica-
tions requiring more than 8K/16K/32K/64K words of buffering.
Figure 2 shows Depth Expansion using three CY7C4255/65/
75/85Vs. Maximum depth is limited only by signal loading. Fol-
low these steps:
4. The Read Expansion Out (RXO) pin of each device must be
tied to the Read Expansion In (RXI) pin of the next device.
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in the Depth Expan-
sion Configuration.
1. The first device must be designated by grounding the First
Load (FL) control input.
7. EF, FF, PAE, and PAF are created with composite flags by
ORing together these respective flags for monitoring. The
composite PAE and PAF flags are not precise.
2. All other devices must have FL in the HIGH state.
WXO RXO
7C4255V
7C4265V
7C4275V
7C4285V
VCC
FL
FF
PAF
EF
PAE
WXI RXI
WXO RXO
7C4255V
7C4265V
7C4275V
7C4285V
DATAIN (D)
DATA OUT (Q)
VCC
FL
FF
PAF
EF
PAE
WXI RXI
WRITE CLOCK(WCLK)
WRITE ENABLE(WEN)
READCLOCK(RCLK)
READENABLE(REN)
WXO RXO
7C4255V
7C4265V
7C4275V
7C4285V
RESET(RS)
OUTPUTENABLE (OE)
LOAD (LD)
FF
EF
FF
EF
PAE
PAE
PAF
PAF
WXI RXI
FIRST LOAD (FL)
4275V–25
Figure 2. Block Diagram of 8K/16K/32K/64K x 18 Low-Voltage Synchronous FIFO Memory
with Programmable Flags used in Depth Expansion Configuration
Document #: 38-06012 Rev. *A
Page 17 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Ordering Information
8Kx18 Low-Voltage Deep Sync FIFO
Speed
(ns)
10
Package
Name
Package
Operating
Range
Ordering Code
CY7C4255V–10ASC
CY7C4255V–15ASC
CY7C4255V–25ASC
Type
A64
A64
A64
64-Lead 10x10 Thin Quad Flatpack
64-Lead 10x10 Thin Quad Flatpack
64-Lead 10x10 Thin Quad Flatpack
Commercial
Commercial
Commercial
15
25
16Kx18 Low-Voltage Deep Sync FIFO
Speed
Package
Name
Package
Type
Operating
Range
(ns)
Ordering Code
CY7C4265V–10ASC
CY7C4265V–15ASC
CY7C4265V–25ASC
10
A64
A64
A64
64-Lead 10x10 Thin Quad Flatpack
64-Lead 10x10 Thin Quad Flatpack
64-Lead 10x10 Thin Quad Flatpack
Commercial
Commercial
Commercial
15
25
32Kx18 Low-Voltage Deep Sync FIFO
Speed
Package
Name
Package
Type
Operating
Range
(ns)
Ordering Code
CY7C4275V–10ASC
CY7C4275V–15ASC
10
A64
A64
64-Lead 10x10 Thin Quad Flatpack
64-Lead 10x10 Thin Quad Flatpack
Commercial
Commercial
15
64Kx18 Low-Voltage Deep Sync FIFO
Speed
Package
Name
Package
Type
Operating
Range
(ns)
Ordering Code
CY7C4285V–10ASC
CY7C4285V–15ASI
CY7C4285V–25ASC
10
A64
A64
A64
64-Lead 10x10 Thin Quad Flatpack
64-Lead 10x10 Thin Quad Flatpack
64-Lead 10x10 Thin Quad Flatpack
Commercial
Industrial
15
25
Commercial
Document #: 38-06012 Rev. *A
Page 18 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Package Diagrams
64-Pin Thin Plastic Quad Flat Pack (10 x 10 x 1.4 mm) A64
51-85051-A
Document #: 38-06012 Rev. *A
Page 19 of 20
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Document Title: CY7C4255V, CY7C4265V, CY7C4275V, CY7C4285V 32K/64K x 18 Low Voltage Deep Sync FIFOs
Document Number: 38-06012
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
106473
122264
Description of Change
09/10/01
12/26/02
SZV
RBI
Change from Spec number: 38-00654 to 38-06012
Power up requirements added to Maximum Ratings Information
*A
Document #: 38-06012 Rev. *A
Page 20 of 20
相关型号：
CY7C4265V-15ASCT
FIFO, 16KX18, 10ns, Synchronous, CMOS, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, STQFP-64
CYPRESS
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