CY7C4804V25-166C [CYPRESS]
FIFO, 4KX80, 4ns, Synchronous, CMOS, PBGA288, 19 X 19 MM, 1 MM PITCH, FBGA-288;
| 型号： | CY7C4804V25-166C |
| 厂家： | 
CYPRESS |
| 描述： | FIFO, 4KX80, 4ns, Synchronous, CMOS, PBGA288, 19 X 19 MM, 1 MM PITCH, FBGA-288 先进先出芯片 |
| 文件： | 总5页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C4808V25
CY7C4806V25
CY7C4804V25
5/0251
ADVANCE INFORMATION
2.5V 4K/16K/64K x 80 Unidirectional
Synchronous FIFO w/Bus Matching
• Bus matching on both ports: x80, x40, x20, x10
• Free-running CLKA and CLKB. Clocks may be asyn-
chronous or coincident
Features
• High-speed, low-power, unidirectional, first-in first-out
(FIFO) memories w/bus matching capabilities
• CY standard or First-Word Fall-Through modes
• 64K x 80 (CY7C4808V25)
• 16K x 80 (CY7C4806V25)
• 4K x 80 (CY7C4804V25)
• 2.5V ± 125 mV power supply
• Serial and parallel programming of Almost Empty/Full
flags, each with 3 default values (8, 16, 64)
• Master and Partial reset capability
• Retransmit capability
• Fabricated using Cypress 0.21-micron CMOS Technol-
ogy for optimum speed/power
• Individual clock frequency up to 200 MHz (5 ns
read/write cycle times)
• All I/Os are 1.5V HSTL
• Big or Little Endian format on Port B
• 288FBGA 19 mmx 19 mm(1.0-mmball pitch)packaging
• Width and depth expansion capability
• High-speed access with tA = 3.5
Preliminary Top Level Block Diagram
MBF
CLKA
CSA
IM
CLKB
Port A
Control
Logic
MailBox
Register
CSB
ENA
ENB
Port B
Control
Logic
MBA
MBB
BE/FWFT
SIZE1A
SIZE2A
4K/16K/64K
x80
SIZE1B
SIZE2B
RT/SPM
OE
Dual Ported
Memory
80
Read
Pointer
Write
Pointer
A79–0
80
B79–0
4K/16K/64K
x80
Dual Ported
Memory
FIFO
Reset
Logic
MRS
PRS
Status
FF/IR
AF
Flag Logic
EF/OR
AE
TDO
Programmable Flag
Offset Registers
FS0/SD
FS1/SEN
JTAG/BIST Controller
TDI
TCK
TMS TRST
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134
•
•
•
•
408-943-2600
December 16, 1999
CY7C4808V25
CY7C4806V25
CY7C4804V25
ADVANCE INFORMATION
ing subsequent words does necessitate a formal read request.
FWFT mode is primarily used for cascading 2 or more FIFOs.
Functional Description
The CY7C480XV25 family of FIFOs is high-speed, low-power,
CMOS Synchronous (clocked) FIFO memories, meaning each
port employs a synchronous interface. All data transfers
through a port are gated to the LOW-to-HIGH transition of the
clock on either port by the enable signal. The clocks for each
port are independent of one another and can be asynchronous
or coincident. The enable for each port is arranged to provide
a simple unidirectional interface between microprocessors
and/or buses with synchronous control.
The FIFO has an EF_OR flag on port B and FF_IR flag on Port
A. The EF and FF functions are selected in the CY Standard
Mode. EF indicates whether or not the FIFO memory is empty.
FF shows whether or not the memory is full. The IR and OR
functions are selected in the First-Word Fall-Through mode. IR
indicates whether or not the FIFO has memory locations avail-
able. OR shows whether the FIFO has data available for read-
ing or not. It marks the presence of valid data on the outputs.
The FIFO has a programmable Almost Empty flag (AE) and a
programmable Almost Full flag (AF). AE indicates the number
of words left in the FIFO memory is at the user-defined
amount. AF indicates the number of words written into the
FIFO memory has achieved a predetermined amount.
Two kinds of reset are available on the CY7C480XV25: Master
Reset and Partial Reset. Master Reset initializes the read and
write pointers to the first location of the memory array, config-
ures the FIFO for Big Endian or Little Endian byte arrange-
ment, selects the CY standard or First-Word Fall-Through
(FWFT) mode, and determines the configuration of the pro-
grammable flags. The flags can be programmed either in serial
mode or in parallel mode. The FIFO also comes with three
possible default flag offset settings: 8, 16, or 64.
FF_IR and AF flags are synchronized to port A clock that
writes data into its array. EF_OR and AE flags are synchro-
nized to Port B clock that reads data from its array. Program-
mable offsets for AE and AF are loaded in parallel via Port A
or in serial via the SD input. The Serial Programming Mode pin
(SPM) makes this selection. Three default offsets setting are
also provided. The AE threshold can be set at 8, 16 or 64
locations from the empty boundary and AF threshold can be
set at 8, 16, or 64 locations from the full boundary. All these
choices are made using the FS0 and FS1 inputs during Master
Reset.
Partial Reset also sets the read and write pointers to the first
location of the memory. Unlike Master Reset, any settings ex-
isting prior to Partial Reset (i.e., programming method and par-
tial flag default offsets) are retained. Partial Reset is useful
since it permits flushing of the FIFO memory without changing
any configuration settings.
The CY7C480XV25 have two modes of operation: CY Stan-
dard Mode or First-Word Fall-Through Mode (FWFT). In the
CY Standard Mode, the first word written to an empty FIFO is
deposited into the memory array. A read operation is required
to access that word (along with all other words residing in
memory). In the FWFT Mode, the first long-word (80-bit-wide)
written to an empty FIFO appears automatically on the out-
puts, and no read operation is required. Nevertheless, access-
Two or more devices may be used in parallel to create wider
data paths. If, at any time, the FIFO is not actively performing
a function, the chip will automatically power down. During the
Power-Down state, supply current consumption (ICC) is at a
minimum. Initiating any operation (by activating control inputs)
will immediately take the device out of the Power-Down state.
The CY7C480XV25 FIFOs are characterized for operation
from 0°C to 70°C commercial, and from –40°C to 85°C indus-
trial.
Selection Guide
CY7C480XV25-200
CY7C480XV25-166
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
200
3.5
5
166
4
6
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
0.6
0.6
3.5
0.6
0.6
4
CY7C4808V25
CY7C4806V25
CY7C4804V25
4K x 80
Density
64K x 80
16K x 80
Package
288 FBGA
288 FBGA
288 FBGA
2
CY7C4808V25
CY7C4806V25
CY7C4804V25
ADVANCE INFORMATION
Pin Description
Pin
Description
VCC_IO
GND_io
VCC_INT
GND_int
Vref
Power supply for I/Os
Ground pins for I/Os
Power supply for internal logic
Ground pins for internal logic
Reference voltage
Master reset
MR
PR
Partial reset
A0–A79
B0–B79
ENA
Input data bus
Output data bus
Port A enable pin
Port B enable pin
Port A Mailbox select
Port B Mailbox select
Port A chip select
Port B chip select
Output enable
ENB
MBA
MBB
CSA
CSB
OE
CLKA
Port A clock
CLKB
Port B clock
BE_FWFT
SIZE1A, SIZE2A
SIZE1B, SIZE2B
RT_SPM
Big/Little Endian and CY Standard/First-Word Fall-Through mode select pin
Port A bus size configuration pins
Port B bus size configuration pins
Retransmit pin/serial programming select
JTAG pins
TDI, TDO, TCK, TMS,
TRST
FS1_SEN, FS0_SD
Programmable flags configuration pins
Empty/output ready flag (Port B)
EF_OR
FF_IR
AE
Full/input ready flag (Port A)
Programmable almost empty flag (Port B)
Programmable almost full flag (Port A)
AF
3
CY7C4808V25
CY7C4806V25
CY7C4804V25
ADVANCE INFORMATION
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.....................................................>200 mA
Storage Temperature ...................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
2.5V ± 125 mV
2.5V ± 125 mV
DC Voltage Applied to Outputs
in High Z State .........................................–0.5V to VCC+0.5V
–40°C to +85°C
DC Input Voltage......................................–0.5V to VCC+0.5V
Output Current into Outputs (LOW) .............................20 mA
DC Specifications (All I/Os will be at HSTL level)
CY7C480XV25
Parameter
VCC _INT
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
2.4
Max.
Unit
2.6
1.9
1.0
1.9
0.7
1.6
0.9
+10
V
V
VCC_IO
VREF
VOH
VOL
VIH
1.4
Input Reference Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Typical value = 0.75V
IOH > 16 mA
0.7
V
1
V
IOL > 1–16 mA
VSS
0.7
V
V
VIL
– 0.3
–10
V
IIX
Input Leakage
Current
µA
IOZL,IOZH
ICC
Output OFF,
High Z Current
–10
+10
100
10
µA
mA
mA
Active Power Supply
Current
VCC _INT = Max.
IOUT = 0 mA
ISB
Average Standby
Current
AC Specifications (A 50Ω load terminated into 0.75V is used with VCC of 2.5V ± 125 mV)
CY7C4D80XV25
Parameter
Description
Max. Frequency
Min.
Max.
Unit
FMAX
tCYC
tSD
200
MHz
ns
Clock Cycle Time
Input Data Set-Up Time
Input Data Hold Time
Access Time
5
0.6
0.6
3.5
ns
tHD
ns
tA
ns
4
CY7C4808V25
CY7C4806V25
CY7C4804V25
ADVANCE INFORMATION
Timing Parameters
7C480XV25–200
7C480XV25–166
Max.
Parameter
fS
Min.
Max.
Min.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
200
166
tCLK
5
2.5
2.5
0.6
1.5
2
6
3
tCLKH
tCLKL
tDS
3
0.6
2
tENS
tRSTS
tFSS
2
2
5
tBES
2
5
tSMPS
tSDS
tSENS
tFWS
tDH
2
5
1.5
1.5
0
2
2
0
0.6
0
0.6
0
tENH
tRSTH
tFSH
0
0
0
0
tBEH
tSPMH
tSDH
tSENH
tSPH
0
0
0
0
0
0
0
0
0
0
tSKEW1
tSKEW2
tA
2.5
2.5
5
5
3.5
3
4
4
4
4
4
4
4
4
4
4
4
tWFF
tREF
3
tPAE
3
tPAF
3
tPMF
3
tPMR
tMDV
3.5
3.5
4
tRSF
tEN
1.5
1.5
tDIS
tPRT
25
45
25
45
tRTR
Document #: 38-00874-A
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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