CY8C21323-24LQXI [CYPRESS]
Multifunction Peripheral, CMOS, QFN-24;
| 型号： | CY8C21323-24LQXI |
| 厂家： | 
CYPRESS |
| 描述： | Multifunction Peripheral, CMOS, QFN-24 时钟 |
| 文件： | 总47页 (文件大小：1216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY8C21123/CY8C21223/CY8C21323
PSoC® Programmable System-on-Chip™
Features
■ Powerful Harvard-architecture processor:
❐ M8C processor speeds up to 24 MHz
❐ Low power at high speed
■ Additional system resources:
❐ I2C master, slave and multi-master to 400 kHz
❐ Watchdog and sleep timers
❐ Operating voltage: 2.4 V to 5.25 V
❐ User-configurable low-voltage detection (LVD)
❐ Operating voltages down to 1.0 V using on-chip switch mode
pump (SMP)
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
❐ Industrial temperature range: –40 °C to +85 °C
■ Advanced peripherals (PSoC® blocks):
❐ Four analog type “E” PSoC blocks provide:
• Two comparators with digital to analog converter (DAC)
references
Logic Block Diagram
Port 1 Port 0
• Single or dual 10-Bit 8-to-1 analog to digital converter
(ADC)
❐ Four digital PSoC blocks provide:
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width
modulators (PWMs)
PSoC
CORE
SystemBus
• CRC and PRS modules
Global Digital Interconnect
❐ Full duplex UART, SPI master or slave: Connectable to all
Global Analog Interconnect
Flash
CPUCore
general-purpose I/O (GPIO) pins
❐ Complex peripherals by combining blocks
SROM
SRAM
■ Flexible on-chip memory:
Sleep and
Watchdog
Interrupt
Controller
(M8C)
❐ 4 KB flash program storage 50,000 erase/write cycles
❐ 256 bytes SRAM data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
Clock Sources
(Includes IMO and ILO)
❐ Flexible protection modes
❐ EEPROM emulation in flash
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref .
■ Complete development tools:
Digital
PSoC Block
Array
Analog
PSoC Block
Array
❐ Free development software (PSoC Designer™)
❐ Full-featured, in-circuit emulator (ICE) and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128-KB trace memory
■ Precision, programmable clocking:
❐ Internal ±5% 24- / 48-MHz main oscillator
❐ Internal low-speed, low-power oscillator for watchdog and
sleep functionality
Sw itch
Mode
Pump
POR and LVD
System Resets
Internal
Voltage
Ref .
Digital
Clocks
I2C
■ Programmable pin configurations:
❐ 25-mA sink, 10-mA source on all GPIOs
SYSTEM RESOURCES
❐ Pull-up, pull-down, high Z, strong, or open-drain drive modes
on all GPIOs
❐ Up to eight analog inputs on all GPIOs
❐ Configurable interrupt on all GPIOs
■
Errata: When the device is operated within 0 °C to 70 °C, the frequency tolerance is reduced to ±2.5%, but if operated at extreme temperature (below 0 °C or above 70 °C),
frequency tolerance deviates from ±2.5% to ±5%. For information on silicon errata, see “Errata” on page 43.
Cypress Semiconductor Corporation
Document Number: 38-12022 Rev. AB
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 14, 2017
CY8C21123/CY8C21223/CY8C21323
Contents
PSoC Functional Overview ..............................................3
PSoC Core ..................................................................3
Digital System .............................................................3
Analog System ............................................................4
Additional System Resources .....................................4
PSoC Device Characteristics ......................................5
Getting Started ..................................................................5
Application Notes ........................................................5
Development Kits ........................................................5
Training .......................................................................5
CYPros Consultants ....................................................5
Solutions Library ..........................................................5
Technical Support .......................................................5
Development Tool Selection ...........................................6
Software ......................................................................6
Designing with PSoC Designer .......................................7
Select Components .....................................................7
Configure Components ...............................................7
Organize and Connect ................................................7
Generate, Verify, and Debug .......................................7
Pin Information .................................................................8
8-Pin Part Pinout .........................................................8
16-Pin Part Pinout .......................................................8
20-Pin Part Pinout .....................................................10
24-Pin Part Pinout .....................................................11
Register Reference .........................................................12
Register Conventions ................................................12
Register Mapping Tables ..........................................12
Electrical Specifications ................................................16
Absolute Maximum Ratings .......................................16
Operating Temperature ............................................17
DC Electrical Characteristics .....................................17
AC Electrical Characteristics .....................................23
Packaging Information ...................................................31
Packaging Dimensions ..............................................31
Thermal Impedances ................................................35
Solder Reflow Specifications .....................................35
Ordering Information ......................................................36
Ordering Code Definitions ........................................36
Acronyms ........................................................................37
Acronyms Used .........................................................37
Reference Documents ....................................................37
Document Conventions .................................................38
Units of Measure .......................................................38
Numeric Conventions ................................................38
Glossary ..........................................................................38
Errata ...............................................................................43
Part Numbers Affected ..............................................43
CY8C21123 Qualification Status ...............................43
CY8C21123 Errata Summary ....................................43
Document History Page .................................................44
Sales, Solutions, and Legal Information ......................47
Worldwide Sales and Design Support .......................47
Products ....................................................................47
PSoC® Solutions .......................................................47
Cypress Developer Community .................................47
Technical Support .....................................................47
Document Number: 38-12022 Rev. AB
Page 2 of 47
CY8C21123/CY8C21223/CY8C21323
PSoC Functional Overview
The PSoC family consists of many programmable
Digital System
system-on-chip controller devices. These devices are designed
to replace multiple traditional MCU-based system components
with a low cost single-chip programmable component. A PSoC
device includes configurable blocks of analog and digital logic,
and programmable interconnect. This architecture allows you to
create customized peripheral configurations, to match the
requirements of each individual application. Additionally, a fast
CPU, Flash program memory, SRAM data memory, and
configurable I/O are included in a range of convenient pinouts.
The digital system consists of four digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user modules. Digital peripheral configurations
include:
■ PWMs (8- and 16-bit)
■ PWMs with dead band (8- and 16-bit)
■ Counters (8- to 32-bit)
The PSoC architecture, as shown in Figure 1, consists of four
main areas: the Core, the System Resources, the Digital
System, and the Analog System. Configurable global bus
resources allow the combining of all device resources into a
complete custom system. Each PSoC device includes four digital
blocks. Depending on the PSoC package, up to two analog
comparators and up to 16 GPIO are also included. The GPIO
provide access to the global digital and analog interconnects.
■ Timers (8- to 32-bit)
■ UART 8-bit with selectable parity (up to two)
■ SPI master and slave
■ I2C slave, master, multi-master (one available as a system
resource)
PSoC Core
■ Cyclical redundancy checker/generator (8-bit)
■ IrDA (up to two)
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and internal main
oscillator (IMO), and internal low-speed oscillator (ILO). The
CPU core, called the M8C, is a powerful processor with speeds
up to 24 MHz. The M8C is a four MIPS 8-bit Harvard-architecture
microprocessor.
■ Pseudo random sequence generators (8- to 32-bit)
The digital blocks can be connected to any GPIO through a
series of global bus that can route any signal to any pin. The
busses also allow for signal multiplexing and performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
System Resources provide additional capability, such as digital
clocks or I2C functionality for implementing an I2C master, slave,
MultiMaster, an internal voltage reference that provides an
absolute value of 1.3 V to a number of PSoC subsystems, an
SMP that generates normal operating voltages off a single
battery cell, and various system resets supported by the M8C.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This provides an optimum
choice of system resources for your application. Family
resources are shown in Table 1 on page 5.
Figure 1. Digital System Block Diagram
The digital system consists of an array of digital PSoC blocks,
which can be configured into any number of digital peripherals.
The digital blocks can be connected to the GPIO through a series
of global bus that can route any signal to any pin. This frees
designs from the constraints of a fixed peripheral controller.
Port1
Port0
ToSystemBus
DigitalClocks
FromCore
ToAnalog
System
The analog system consists of four analog PSoC blocks,
supporting comparators and analog-to-digital conversion up to
10 bits of precision.
DIGITAL SYSTEM
DigitalPSoCBlockArray
Row 0
4
DBB00
DBB01
DCB02 DCB03
4
8
8
8
8
GlobalDigital
Interconnect
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Document Number: 38-12022 Rev. AB
Page 3 of 47
CY8C21123/CY8C21223/CY8C21323
Analog System
Additional System Resources
The analog system consists of four configurable blocks to allow
creation of complex analog signal flows. Analog peripherals are
very flexible and may be customized to support specific
application requirements. Some of the more common PSoC
analog functions (most available as user modules) are:
System resources, some of which listed in the previous sections,
provide additional capability useful to complete systems.
Additional resources include a switch mode pump, low voltage
detection, and power on reset. The merits of each system
resource are.
■ Analog-to-digital converters (single or dual, with 8-bit or 10-bit
resolution)
■ Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■ Pin-to-pin comparators (one)
■ Single-ended comparators (up to 2) with absolute (1.3 V)
reference or 8-bit DAC reference
■ TheI2Cmoduleprovides100and400kHzcommunicationover
two wires. Slave, master, and multi-master modes are all
supported.
■ 1.3 V reference (as a system resource)
In most PSoC devices, analog blocks are provided in columns of
three, which includes one CT (continuous time) and two SC
(switched capacitor) blocks. The CY8C21x23 devices provide
limited functionality Type “E” analog blocks. Each column
contains one CT block and one SC block.
■ LVD interrupts can signal the application of falling voltage
levels, while the advanced POR (power on reset) circuit
eliminates the need for a system supervisor.
■ An internal 1.3 V voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
The number of blocks on the device family is listed in Table 1 on
page 5.
■ An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2 V battery cell, providing a
low cost boost converter.
Figure 2. CY8C21x23 Analog System Block Diagram
Array Input
Configuration
ACI0[1:0]
ACI1[1:0]
ACOL1MUX
Array
ACE00
ASE10
ACE01
ASE11
Document Number: 38-12022 Rev. AB
Page 4 of 47
CY8C21123/CY8C21223/CY8C21323
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks, and 12, 6, or 4
analog blocks. Table 1 lists the resources available for specific PSoC device groups. The PSoC device covered by this datasheet is
highlighted.
Table 1. PSoC Device Characteristics
PSoC Part
Number
Digital
I/O
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Analog
Analog
SRAM
Size
Flash
Size
Outputs Columns Blocks
CY8C29x66
CY8C28xxx
up to 64
up to 44
4
16
up to 12
up to 44
4
4
12
2 K
1 K
32 K
16 K
up to 3
up to 12
up to 4
up to 6
up to
12 + 4
[1]
CY8C27x43
CY8C24x94
CY8C24x23A
CY8C23x33
CY8C22x45
CY8C21x45
CY8C21x34
CY8C21x23
CY8C20x34
CY8C20xx6
up to 44
up to 56
up to 24
up to 26
up to 38
up to 24
up to 28
up to 16
up to 28
up to 36
2
1
1
1
2
1
1
1
0
0
8
4
4
4
8
4
4
4
0
0
up to 12
up to 48
up to 12
up to 12
up to 38
up to 24
up to 28
4
2
2
2
0
0
0
0
0
0
4
2
2
2
4
4
2
2
0
0
12
6
256
1 K
256
256
1 K
512
512
256
512
16 K
16 K
4 K
6
4
8 K
[1]
6
16 K
8 K
[1]
6
[1]
4
8 K
[1]
up to
8
4
4 K
[1,2]
up to 28
up to 36
3
8 K
[1,2]
3
up to
2 K
up to
32 K
Getting Started
The quickest way to understand PSoC silicon is to read this
datasheet and then use the PSoC Designer Integrated Devel-
opment Environment (IDE). This datasheet is an overview of the
PSoC integrated circuit and presents specific pin, register, and
electrical specifications.
Training
Free PSoC technical training (on demand, webinars, and
workshops) is available online at http://www.cypress.com. The
training covers a wide variety of topics and skill levels to assist
you in your designs.
For in depth information, along with detailed programming
details, see the Technical Reference Manual for this PSoC
device.
CYPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to http://www.cypress.com and refer to
CYPros Consultants.
For up to date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web
at http://www.cypress.com.
Application Notes
Solutions Library
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They can be found at
http://www.cypress.com.
Visit our growing library of solution focused designs at
http://www.cypress.com. Here you can find various application
designs that include firmware and hardware design files that
enable you to complete your designs quickly.
Development Kits
Technical Support
PSoC Development Kits are available online from Cypress at
http://www.cypress.com and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
For assistance with technical issues, search KnowledgeBase
articles and forums at http://www.cypress.com. If you cannot find
an answer to your question, call technical support at
1-800-541-4736.
Notes
1. Limited analog functionality.
2. Two analog blocks and one CapSense .
®
Document Number: 38-12022 Rev. AB
Page 5 of 47
CY8C21123/CY8C21223/CY8C21323
Development Tool Selection
Software
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write I/O
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
PSoC Designer
At the core of the PSoC development software suite is
PSoC Designer. Utilized by thousands of PSoC developers, this
robust software has been facilitating PSoC designs for years.
PSoC Designer is available free of charge at
http://www.cypress.com. PSoC Designer comes with a free C
compiler.
PSoC Designer Software Subsystems
You choose a base device to work with and then select different
onboard analog and digital components called user modules that
use the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters. You configure the user modules
for your chosen application and connect them to each other and
to the proper pins. Then you generate your project. This prepop-
ulates your project with APIs and libraries that you can use to
program your application.
In-Circuit Emulator
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices. The emulator consists of a
base unit that connects to the PC by way of a USB port. The base
unit is universal and operates with all PSoC devices. Emulation
pods for each device family are available separately. The
emulation pod takes the place of the PSoC device in the target
board and performs full speed (24MHz) operation.
The tool also supports easy development of multiple configura-
tions and dynamic reconfiguration. Dynamic reconfiguration
allows for changing configurations at run time. Code Generation
Tools PSoC Designer supports multiple third-party C compilers
and assemblers. The code generation tools work seamlessly
within the PSoC Designer interface and have been tested with a
full range of debugging tools. The choice is yours.
Standard Cypress PSoC IDE tools are available for debugging
the CY8C20x36A/66A family of parts. However, the additional
trace length and a minimal ground plane in the Flex-Pod can
create noise problems that make it difficult to debug the design.
A custom bonded On-Chip Debug (OCD) device is available in a
48-pin QFN package. The OCD device is recommended for
debugging designs that have high current and/or high analog
accuracy requirements. The QFN package is compact and is
connected to the ICE through a high density connector.
Assemblers. The assemblers allow assembly code to be
merged seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube in-circuit emulator and
PSoC MiniProg. PSoC programmer is available free of charge at
http://www.cypress.com/psocprogrammer.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all the features of C tailored to
the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Document Number: 38-12022 Rev. AB
Page 6 of 47
CY8C21123/CY8C21223/CY8C21323
Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. You perform the
selection, configuration, and routing so that you have complete
control over all on-chip resources.
Generate, Verify, and Debug
The PSoC development process can be summarized in the
following four steps:
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the "Generate
Configuration Files" step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides application programming interfaces
(APIs) with high-level functions to control and respond to
hardware events at run time and interrupt service routines that
you can adapt as needed.
1. Select User Modules
2. Configure User Modules
3. Organize and Connect
4. Generate, Verify, and Debug
Select Components
PSoC Designer provides a library of pre-built, pre-tested
hardware peripheral components called "user modules." User
modules make selecting and implementing peripheral devices,
both analog and digital, simple.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer's Debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full speed. PSoC Designer debugging capabil-
ities rival those of systems costing many times more. In addition
Configure Components
Each of the User Modules you select establishes the basic
register settings that implement the selected function. They also
provide parameters and properties that allow you to tailor their
precise configuration to your particular application. For example,
a PWM User Module configures one or more
to traditional single-step, run-to-breakpoint and watch-variable
features, the debug interface provides a large trace buffer and
allows you to define complex breakpoint events that include
monitoring address and data bus values, memory locations and
external signals.
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to corre-
spond to your chosen application. Enter values directly or by
selecting values from drop-down menus. All the user modules
are documented in datasheets that may be viewed directly in
PSoC Designer or on the Cypress website. These user module
datasheets explain the internal operation of the User Module and
provide performance specifications. Each datasheet describes
the use of each user module parameter, and other information
you may need to successfully implement your design.
Document Number: 38-12022 Rev. AB
Page 7 of 47
CY8C21123/CY8C21223/CY8C21323
Pin Information
This section describes, lists, and illustrates the CY8C21x23 PSoC device pins and pinout configurations. Every port pin (labeled with
a “P”) is capable of Digital I/O. However, VSS, VDD, SMP, and XRES are not capable of Digital I/O.
8-Pin Part Pinout
Table 2. Pin Definitions – CY8C21123 8-Pin SOIC
Type
Figure 3. CY8C21123 8-Pin SOIC
Pin
No.
Pin
Name
Description
Digital Analog
A, I, P0[5]
A, I, P0[3]
1
2
3
8
7
6
5
VDD
1
I/O
I/O
I/O
I
I
P0[5] Analog column mux input
P0[4], A, I
P0[2], A, I
SOIC
2
3
4
5
6
7
8
P0[3] Analog column mux input
P1[1] I2C serial clock (SCL), ISSP-SCLK[3]
I2C SCL, P1[1]
VSS
P1[0], I2C SDA
4
Power
Power
VSS
Ground connection
I/O
I/O
I/O
P1[0] I2C serial data (SDA), ISSP-SDATA[3]
I
I
P0[2] Analog column mux input
P0[4] Analog column mux input
VDD
Supply voltage
LEGEND: A = Analog, I = Input, and O = Output.
16-Pin Part Pinout
Table 3. Pin Definitions – CY8C21223 16-Pin SOIC
Type
Figure 4. CY8C21223 16-Pin SOIC
Pin
No.
Pin
Name
Description
Digital Analog
A, I, P0[7]
A, I, P0[5]
A, I, P0[3]
A, I, P0[1]
SMP
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
I/O
I/O
I/O
I/O
I
I
I
I
P0[7] Analog column mux input
P0[5] Analog column mux input
P0[3] Analog column mux input
P0[1] Analog column mux input
P0[6], A, I
P0[4], A, I
P0[2], A, I
P0[0], A, I
P1[4], EXTCLK
P1[2]
2
3
4
5
SOIC
VSS
I2C SCL, P1[1]
VSS
Power
Power
SMP SMP connection to required external
components
P1[0], I2C SDA
6
VSS
P1[1] I2C SCL, ISSP-SCLK[3]
VSS Ground connection
Ground connection
7
I/O
8
Power
9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P1[0] I2C SDA, ISSP-SDATA[3]
10
11
12
13
14
15
16
P1[2]
P1[4] Optional external clock input (EXTCLK)
P0[0] Analog column mux input
P0[2] Analog column mux input
P0[4] Analog column mux input
P0[6] Analog column mux input
I
I
I
I
Power
VDD
Supply voltage
LEGEND A = Analog, I = Input, and O = Output.
Note
3. These are the ISSP pins, which are not high Z at POR (power on reset). See the PSoC Technical Reference Manual for details.
Document Number: 38-12022 Rev. AB
Page 8 of 47
CY8C21123/CY8C21223/CY8C21323
Table 4. Pin Definitions – CY8C21223 16-Pin QFN with no E-Pad [4]
Type
Figure 5. CY8C21223 16-Pin QFN
Pin
No.
Pin
Name
Description
Digital Analog
1
2
3
4
5
6
7
8
9
I/O
I/O
I/O
I/O
I/O
I/O
I
I
P0[3]
P0[1]
P1[7]
P1[5]
P1[3]
P1[1]
VSS
Analog column mux input
Analog column mux input
I2C SCL
AI, P0[3]
AI, P0[1]
P0[4], VREF
XRES
P1[4]
1
2
3
4
12
11
) 10
9
I2C SDA
QFN
Top View
(
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[6]
I2C SCL, ISSP-SCLK[5]
Ground connection
I2C SDA, ISSP-SDATA[5]
Power
I/O
I/O
I/O
P1[0]
P1[6]
P1[4]
XRES
10
11
EXTCLK
Input
Active high external reset with internal
pull-down
12
13
14
15
16
I/O
I
P0[4]
VDD
VREF
Power
Supply voltage
I/O
I/O
I
I
P0[7]
P0[5]
NC
Analog column mux input
Analog column mux input
No Connection. Pin must be left floating
LEGEND A = Analog, I = Input, and O = Output.
Notes
4. The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
must be electrically floated and not connected to any other signal.
5. These are the ISSP pins, which are not high Z at POR (power on reset). See the PSoC Technical Reference Manual for details.
Document Number: 38-12022 Rev. AB
Page 9 of 47
CY8C21123/CY8C21223/CY8C21323
20-Pin Part Pinout
Table 5. Pin Definitions – CY8C21323 20-Pin SSOP
Type
Figure 6. CY8C21323 20-Pin SSOP
Pin
No.
Pin
Name
Description
Digital Analog
A, I, P0[7]
A, I, P0[5]
A, I, P0[3]
A, I, P0[1]
VSS
VDD
20
19
18
17
16
15
14
13
12
11
1
2
1
2
3
4
5
6
7
8
9
I/O
I/O
I/O
I/O
I
I
I
I
P0[7]
P0[5]
P0[3]
P0[1]
VSS
Analog column mux input
Analog column mux input
Analog column mux input
Analog column mux input
Ground connection[6]
I2C SCL
P0[6], A, I
P0[4], A, I
P0[2], A, I
P0[0], A, I
XRES
3
4
5
SSOP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
6
Power
Power
Input
P1[6]
7
I/O
I/O
I/O
I/O
P1[7]
P1[5]
P1[3]
P1[1]
VSS
P1[4], EXTCLK
P1[2]
8
I2C SDA
I2C SCL, P1[1]
VSS
9
P1[0], I2C SDA
10
I2C SCL, ISSP-SCLK[7]
Ground connection[6]
I2C SDA, ISSP-SDATA[7]
10
11
12
13
14
15
I/O
I/O
I/O
I/O
P1[0]
P1[2]
P1[4]
P1[6]
Optional EXTCLK input
XRES Active high external reset with internal
pull-down
16
17
18
19
20
I/O
I/O
I/O
I/O
I
I
I
I
P0[0]
P0[2]
P0[4]
P0[6]
VDD
Analog column mux input
Analog column mux input
Analog column mux input
Analog column mux input
Supply voltage
Power
LEGEND A = Analog, I = Input, and O = Output.
Notes
6. All V pins should be brought out to one common GND plane.
SS
7. These are the ISSP pins, which are not high Z at POR (power on reset). See the PSoC Technical Reference Manual for details.
Document Number: 38-12022 Rev. AB
Page 10 of 47
CY8C21123/CY8C21223/CY8C21323
24-Pin Part Pinout
Table 6. Pin Definitions – CY8C21323 24-Pin QFN[8]
Type
Figure 7. CY8C21323 24-Pin QFN
Pin
No.
Pin
Name
Description
Digital Analog
1
2
I/O
I
P0[1]
SMP
Analog column mux input
Power
Power
SMP connection to required external
components
Ground connection[9]
I2C SCL
I2C SDA
3
4
5
6
7
8
9
VSS
A, I, P0[1]
SMP
18
17
16
15
14
13
P0[4], A, I
P0[2], A, I
1
2
3
4
5
6
I/O
I/O
I/O
I/O
P1[7]
P1[5]
P1[3]
P1[1]
NC
VSS
QFN
(Top View)
P0[0], A, I
NC
XRES
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, ISSP-SCLK[10]
P1[6]
No connection. Pin must be left floating
Ground connection[9]
I2C SDA, ISSP-SDATA[10]
Power
Input
VSS
10
11
12
13
14
I/O
I/O
I/O
I/O
P1[0]
P1[2]
P1[4]
P1[6]
Optional (EXTCLK) input
XRES Active high external reset with internal
pull-down
15
16
17
18
19
20
21
22
23
24
NC
No connection. Pin must be left floating
Analog column mux input
Analog column mux input
Analog column mux input
Analog column mux input
Supply voltage
I/O
I/O
I/O
I/O
I
I
I
I
P0[0]
P0[2]
P0[4]
P0[6]
VDD
Power
Power
VSS
Ground connection[9]
I/O
I/O
I/O
I
I
I
P0[7]
P0[5]
P0[3]
Analog column mux input
Analog column mux input
Analog column mux input
LEGEND A = Analog, I = Input, and O = Output.
Notes
8. The center pad on the QFN package must be connected to ground (V ) for best mechanical, thermal, and electrical performance. If not connected to ground, it
SS
must be electrically floated and not connected to any other signal.
9. All V pins should be brought out to one common GND plane.
SS
10. These are the ISSP pins, which are not high Z at POR (power on reset). See the PSoC Technical Reference Manual for details.
Document Number: 38-12022 Rev. AB
Page 11 of 47
CY8C21123/CY8C21223/CY8C21323
Register Reference
This section lists the registers of the CY8C21x23 PSoC device.
For detailed register information, refer the PSoC Technical
Reference Manual.
Register Mapping Tables
The PSoC device has a total register address space of
512 bytes. The register space is referred to as I/O space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines the bank you are currently in. When the XOI bit is set,
you are in Bank 1.
Register Conventions
The register conventions specific to this section are listed in the
following table.
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
Table 7. Register Conventions
Convention
Description
Read register or bit(s)
R
W
L
Write register or bit(s)
Logical register or bit(s)
Clearable register or bit(s)
Access is bit specific
C
#
Document Number: 38-12022 Rev. AB
Page 12 of 47
CY8C21123/CY8C21223/CY8C21323
Table 8. Register Map Bank 0 Table: User Space
Addr
Addr
(0,Hex)
40
Addr
Addr
Name
Access
Name
Access
Name
ASE10CR0
Access
Name
Access
(0,Hex)
(0,Hex)
(0,Hex)
PRT0DR
00
RW
RW
RW
RW
RW
RW
RW
RW
80
RW
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
PRT0IE
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
ASE11CR0
RW
PRT1GS
PRT1DM2
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
I2C_CFG
RW
#
I2C_SCR
I2C_DR
RW
#
I2C_MSCR
INT_CLR0
INT_CLR1
RW
RW
INT_CLR3
INT_MSK3
RW
RW
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
DCB03DR2
DCB03CR0
#
AMX_IN
RW
RW
#
INT_MSK0
INT_MSK1
INT_VC
RW
RW
RC
W
W
RW
#
PWM_CR
CMP_CR0
CMP_CR1
RES_WDT
#
W
RW
#
RW
DEC_CR0
DEC_CR1
RW
RW
#
ADC0_CR
ADC1_CR
#
#
W
RW
#
#
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
RW
RW
RW
RW
W
RW
#
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Document Number: 38-12022 Rev. AB
Page 13 of 47
CY8C21123/CY8C21223/CY8C21323
Table 8. Register Map Bank 0 Table: User Space (continued)
Addr
Addr
Addr
Addr
Name
Access
Name
Access
Name
RDI0RI
Access
Name
Access
(0,Hex)
(0,Hex)
(0,Hex)
(0,Hex)
30
70
B0
RW
RW
RW
RW
RW
RW
RW
F0
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
RDI0SYN
RDI0IS
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
ACE00CR1
ACE00CR2
RW
RW
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
ACE01CR1
ACE01CR2
RW
RW
CPU_F
RL
CPU_SCR1
CPU_SCR0
#
#
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Table 9. Register Map Bank 1 Table: Configuration Space
Addr
Addr
Addr
(1,Hex)
80
Addr
Name
Access
Name
Access
Name
Access
Name
Access
(1,Hex)
(1,Hex)
(1,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
PRT0DM0
00
RW
RW
RW
RW
RW
RW
RW
RW
40
ASE10CR0
RW
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
ASE11CR0
RW
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
RW
RW
RW
RW
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Document Number: 38-12022 Rev. AB
Page 14 of 47
CY8C21123/CY8C21223/CY8C21323
Table 9. Register Map Bank 1 Table: Configuration Space (continued)
Addr
Addr
Addr
Addr
Name
Access
Name
Access
Name
Access
Name
Access
(1,Hex)
(1,Hex)
(1,Hex)
(1,Hex)
1C
5C
9C
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
RW
RW
RW
RW
RW
RW
RW
R
DBB00FN
RW
RW
RW
CLK_CR0
RW
RW
RW
RW
RW
DBB00IN
CLK_CR1
DBB00OU
ABF_CR0
AMD_CR0
CMP_GO_EN
DBB01FN
DBB01IN
DBB01OU
RW
RW
RW
VLT_CMP
ADC0_TR
ADC1_TR
RW
RW
AMD_CR1
ALT_CR0
RW
RW
DCB02FN
DCB02IN
DCB02OU
RW
RW
RW
IMO_TR
ILO_TR
BDG_TR
ECO_TR
W
W
RW
W
CLK_CR3
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
RW
RW
RW
RW
RW
DCB03FN
DCB03IN
DCB03OU
RW
RW
RW
RDI0RI
RW
RW
RW
RW
RW
RW
RW
RDI0SYN
RDI0IS
ACE00CR1
ACE00CR2
RW
RW
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
ACE01CR1
ACE01CR2
RW
RW
CPU_F
RL
FLS_PR1
RW
CPU_SCR1
CPU_SCR0
#
#
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Document Number: 38-12022 Rev. AB
Page 15 of 47
CY8C21123/CY8C21223/CY8C21323
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C21x23 PSoC device. For up to date electrical specifications,
check if you have the latest datasheet by visiting the web at http://www.cypress.com.
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted.
Refer to Table 24 on page 25 for the electrical specifications on the IMO using SLIMO mode.
Figure 11. Voltage versus IMO Frequency
Figure 10. Voltage versus CPU Frequency
5.25
4.75
5.25
4.75
SLIMO
Mode=1
SLIMO
Mode=0
3.60
3.00
2.40
SLIMO
Mode=1
SLIMO SLIMO
Mode=1 Mode=1
SLIMO
Mode=0
3.00
2.40
93kHz
12MHz
CPUFrequency
24MHz
93kHz
6MHz
IMOFrequency
3MHz
12MHz
24MHz
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 10. Absolute Maximum Ratings
Symbol
Description
Storage temperature
Min
Typ
Max
Units
Notes
T
T
–55
–
+100
°C
Higher storage temperatures
reduce data retention time.
Recommended storage
STG
temperature is +25 °C ± 25 °C.
Extended duration storage
temperatures higher than 65 °C
degrade reliability.
Bake temperature
–
125
–
See
package
label
°C
BAKETEMP
t
Bake time
See
package
label
72
Hours
BAKETIME
T
Ambient temperature with power applied
–40
–
–
–
–
–
–
–
+85
°C
V
A
V
V
V
Supply voltage on V relative to V
SS
–0.5
+6.0
DD
IO
DD
DC input voltage
V
V
– 0.5
– 0.5
V
V
+ 0.5
+ 0.5
V
SS
SS
DD
DD
DC voltage applied to tristate
Maximum current into any port pin
Electro static discharge voltage
Latch-up current
V
IOZ
MIO
I
–25
+50
mA
V
ESD
LU
2000
–
–
Human body model ESD
200
mA
Document Number: 38-12022 Rev. AB
Page 16 of 47
CY8C21123/CY8C21223/CY8C21323
Operating Temperature
Table 11. Operating Temperature
Symbol
Description
Min
–40
–40
Typ
–
Max
+85
Units
°C
Notes
T
T
Ambient temperature
Junction temperature
A
–
+100
°C
The temperature rise from
ambient to junction is package
specific. SeeTable 36 on page
35. You must limit the power
consumption to comply with this
requirement.
J
DC Electrical Characteristics
DC Chip-Level Specifications
Table 12 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –
40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 12. DC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
V
Supply voltage
2.40
–
5.25
V
See DC POR and LVD
specifications,
DD
Table 19 on page 21.
I
I
I
Supply current, IMO = 24 MHz
Supply current, IMO = 6 MHz
Supply current, IMO = 6 MHz
–
–
–
3
4
2
mA Conditions are V = 5.0 V,
DD
DD
25 °C, CPU = 3 MHz, SYSCLK
doubler disabled. VC1 = 1.5 MHz
VC2 = 93.75 kHz
VC3 = 0.366 kHz
1.2
1.1
mA Conditions are V = 3.3 V,
DD3
DD
25 °C, CPU = 3 MHz, clock doubler
disabled. VC1 = 375 kHz
VC2 = 23.4 kHz
VC3 = 0.091 kHz
1.5
mA Conditions are V = 2.55 V,
DD27
DD
25 °C, CPU = 3 MHz, clock doubler
disabled. VC1 = 375 kHz VC2 =
23.4 kHz
VC3 = 0.091 kHz
I
I
Sleep (mode) current with POR, LVD, sleep
timer, WDT, and internal slow
oscillator active. Mid temperature range.
–
–
2.6
2.8
4
5
µA
µA
V
= 2.55 V, 0 °C to 40 °C
SB27
SB
DD
Sleep (mode) current with POR, LVD, sleep
timer, WDT, and internal slow
oscillator active.
V
= 3.3 V, –40 °C T 85 °C
DD
A
V
V
Reference voltage (bandgap)
Reference voltage (bandgap)
Analog ground
1.28
1.16
1.30
1.30
1.32
V
V
V
Trimmed for appropriate V . V
DD DD
= 3.0 V to 5.25 V
REF
1.330
Trimmed for appropriate V . V
REF27
DD DD
= 2.4 V to 3.0 V
AGND
V
– 0.003
V
V
+ 0.003
REF
REF
REF
Document Number: 38-12022 Rev. AB
Page 17 of 47
CY8C21123/CY8C21223/CY8C21323
DC GPIO Specifications
Table 13 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –
40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C and
are for design guidance only.
Table 13. 5-V and 3.3-V DC GPIO Specifications
Symbol
Description
Min
4
Typ
5.6
5.6
–
Max
Units
k
Notes
R
Pull-up resistor
8
8
–
PU
PD
OH
R
Pull-down resistor
High output level
4
k
V
V
– 1.0
V
I
= 10 mA, V = 4.75 to 5.25 V (8 total
OH DD
DD
loads, 4 on even port pins (for example,
P0[2], P1[4]), 4 on odd port pins (for
example, P0[3], P1[5])).
80 mA maximum combined I budget.
OH
V
Low output level
–
–
0.75
V
I
= 25 mA, V = 4.75 to 5.25 V (8 total
OL DD
OL
loads, 4 on even port pins (for example,
P0[2], P1[4]), 4 on odd port pins (for
example, P0[3], P1[5])).
150 mA maximum combined I budget.
OL
I
I
High level source current
Low level sink current
10
25
–
–
–
–
mA
mA
V
= V – 1.0 V, see the limitations of the
OH DD
OH
total current in the note for V
OH
V
= 0.75 V, see the limitations of the total
OL
OL
current in the note for V
OL
V
V
V
Input low level
–
2.1
–
–
–
0.8
V
V
V
V
= 3.0 to 5.25
= 3.0 to 5.25
IL
IH
H
DD
DD
Input high level
Input hysteresis
60
1
–
–
mV
nA
pF
I
Input leakage (absolute value)
Capacitive load on pins as input
–
Gross tested to 1 µA
IL
C
–
3.5
10
Package and pin dependent.
Temp = 25 °C
IN
C
Capacitive load on pins as output
–
3.5
10
pF
Package and pin dependent.
Temp = 25 °C
OUT
Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4 V to 3.0 V and
–40 °C TA 85 °C. Typical parameters apply to 2.7 V at 25 °C and are for design guidance only.
Table 14. 2.7-V DC GPIO Specifications
Symbol
Description
Min
4
Typ
5.6
5.6
–
Max
Units
k
Notes
R
Pull-up resistor
8
8
–
PU
R
Pull-down resistor
High output level
4
k
PD
V
V
– 0.4
V
I
= 2.5 mA (6.25 Typ), V = 2.4 to
OH DD
OH
DD
3.0 V (16 mA maximum, 50 mA Typ
combined I budget).
OH
V
Low output level
–
–
–
–
0.75
–
V
I
= 10 mA, V = 2.4 to 3.0 V (90 mA
OL DD
OL
maximum combined I budget).
OL
I
I
High level source current
Low level sink current
2.5
10
mA
mA
V
= V – 0.4 V, see the limitations of the
OH DD
OH
total current in the note for V
OH
–
V
= 0.75 V, see the limitations of the total
OL
OL
current in the note for V
OL
V
V
V
Input low level
–
2.0
–
–
–
0.75
–
V
V
V
V
= 2.4 to 3.0
= 2.4 to 3.0
IL
IH
H
DD
DD
Input high level
Input hysteresis
60
1
–
mV
nA
pF
I
Input leakage (absolute value)
Capacitive load on pins as input
–
–
Gross tested to 1 µA
IL
C
–
3.5
10
Package and pin dependent.
Temp = 25 °C
IN
C
Capacitive load on pins as output
–
3.5
10
pF
Package and pin dependent.
Temp = 25 °C
OUT
Document Number: 38-12022 Rev. AB
Page 18 of 47
CY8C21123/CY8C21223/CY8C21323
DC Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively.
Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 15. 5-V DC Amplifier Specifications
Symbol
Description
Min
–
Typ
2.5
10
Max
15
–
Units
mV
Notes
V
Input offset voltage (absolute value)
Average input offset voltage drift
Input leakage current (port 0 analog pins)
Input capacitance (port 0 analog pins)
OSOA
TCV
–
µV/°C
pA
OSOA
EBOA
I
–
200
4.5
–
Gross tested to 1 µA
C
–
9.5
pF
Package and pin dependent.
Temp = 25 °C
INOA
V
Common mode voltage range
0.0
–
V
– 1
DD
V
CMOA
G
Open loop gain
80
–
–
–
dB
µA
OLOA
I
Amplifier supply current
10
30
SOA
Table 16. 3.3-V DC Amplifier Specifications
Symbol
Description
Min
–
Typ
2.5
10
Max
15
–
Units
mV
Notes
V
Input offset voltage (absolute value)
Average input offset voltage drift
Input leakage current (port 0 analog pins)
Input capacitance (port 0 analog pins)
OSOA
TCV
–
µV/°C
pA
OSOA
EBOA
I
–
200
4.5
–
Gross tested to 1 µA
C
–
9.5
pF
Package and pin dependent.
Temp = 25 °C
INOA
V
Common mode voltage range
Open loop gain
0
80
–
–
–
V
– 1
DD
V
CMOA
G
–
dB
µA
OLOA
I
Amplifier supply current
10
30
SOA
Table 17. 2.7V DC Amplifier Specifications
Symbol
Description
Min
–
Typ
2.5
10
Max
15
–
Units
mV
Notes
V
Input offset voltage (absolute value)
Average input offset voltage drift
Input leakage current (port 0 analog pins)
Input capacitance (port 0 analog pins)
OSOA
TCV
–
µV/°C
pA
OSOA
EBOA
I
–
200
4.5
–
Gross tested to 1 µA
C
–
9.5
pF
Package and pin dependent.
Temp = 25 °C
INOA
V
Common mode voltage range
Open loop gain
0
80
–
–
–
V
– 1
DD
V
CMOA
G
–
dB
µA
OLOA
I
Amplifier supply current
10
30
SOA
Document Number: 38-12022 Rev. AB
Page 19 of 47
CY8C21123/CY8C21223/CY8C21323
DC Switch Mode Pump Specifications
Table 18 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –
40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 18. DC Switch Mode Pump (SMP) Specifications
Symbol
Description
Min
Typ
Max Units
Notes
[11]
V
V
V
5 V output voltage from pump
4.75
5.0
5.25
3.60
2.80
V
V
V
Configuration of footnote. Average,
neglecting ripple. SMP trip voltage is set to
5.0 V.
PUMP5V
[11]
3.3 V output voltage from pump
2.6 V output voltage from pump
Available output current
3.00
2.45
3.25
2.55
Configuration of footnote. Average,
PUMP3V
PUMP2V
PUMP
neglecting ripple. SMP trip voltage is set to
3.25 V.
[11]
Configuration of footnote. Average,
neglecting ripple. SMP trip voltage is set to
2.55 V.
[11]
I
Configuration of footnote.
V
V
V
= 1.8 V, V
= 1.5 V, V
= 1.3 V, V
= 5.0 V
= 3.25 V
= 2.55 V
5
8
8
–
–
–
–
–
–
mA SMP trip voltage is set to 5.0 V.
mA SMP trip voltage is set to 3.25 V.
mA SMP trip voltage is set to 2.55 V.
[11]
BAT
BAT
BAT
PUMP
PUMP
PUMP
V
V
V
V
Input voltage range from battery
Input voltage range from battery
Input voltage range from battery
1.8
1.0
1.0
1.2
–
–
–
–
–
5
5.0
3.3
2.8
–
V
Configuration of footnote. SMP trip
BAT5V
voltage is set to 5.0 V.
[11]
V
Configuration of footnote.
voltage is set to 3.25 V.
SMP trip
SMP trip
0 °C T
BAT3V
[11]
V
Configuration of footnote.
voltage is set to 2.55 V.
BAT2V
[11]
Minimum input voltage from battery to start
pump
V
Configuration of footnote.
A
BATSTART
100. 1.25 V at T = –40 °C.
A
[11]
V
V
V
Line regulation (over Vi range)
–
%V
Configuration of footnote.
V is the
O
PUMP_Line
PUMP_Load
PUMP_Ripple
O
“V Value for PUMPTrip” specified by the
DD
VM[2:0] setting in the DC POR and LVD
Specification, Table 19 on page 21.
[11]
Load regulation
–
5
–
%V
Configuration of footnote.
V is the
O
O
“V Value for PUMPTrip” specified by the
DD
VM[2:0] setting in the DC POR and LVD
Specification, Table 19 on page 21.
[11]
Output voltage ripple (depends on cap/load)
–
100
50
–
–
–
mVpp Configuration of footnote.
5 mA.
Load is
[11]
E
E
Efficiency
Efficiency
35
35
%
Configuration of footnote.
Load is
3
2
5 mA. SMP trip voltage is set to 3.25 V.
80
%
For I load = 1 mA, V = 2.55 V,
PUMP
V
= 1.3 V, 10 uH inductor, 1 uF
BAT
capacitor, and Schottky diode.
F
Switching frequency
Switching duty cycle
–
–
1.3
50
–
–
MHz
%
PUMP
DC
PUMP
Note
11. L = 2 mH inductor, C = 10 mF capacitor, D = Schottky diode. Refer to Figure 12 on page 21.
1
1
1
Document Number: 38-12022 Rev. AB
Page 20 of 47
CY8C21123/CY8C21223/CY8C21323
Figure 12. Basic Switch Mode Pump Circuit
D1
VPUMP
V
DD
L1
C1
SMP
V ss
+
VBAT
PSoC
Battery
DC POR and LVD Specifications
Table 19 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –
40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 19. DC POR and LVD Specifications
Symbol
Description
value for PPOR trip
Min
Typ
Max
Units
Notes
V
V
must be greater than or equal to
DD
DD
V
V
V
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
–
–
–
2.36
2.82
4.55
2.40
2.95
4.70
V
V
V
2.5 V during startup, reset from the
XRES pin, or reset from watchdog.
PPOR0
PPOR1
PPOR2
V
value for LVD trip
DD
[12]
V
V
V
V
V
V
V
V
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.40
2.85
2.95
3.06
4.37
4.50
4.62
4.71
2.45
2.92
3.02
3.13
4.48
4.64
4.73
4.81
2.51
2.99
V
V
V
V
V
V
V
V
LVD0
LVD1
LVD2
LVD3
LVD4
LVD5
LVD6
LVD7
[13]
3.09
3.20
4.55
4.75
4.83
4.95
V
value for PUMP trip
DD
[14]
V
V
V
V
V
V
V
V
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.45
2.96
3.03
3.18
4.54
4.62
4.71
4.89
2.55
3.02
3.10
3.25
4.64
4.73
4.82
5.00
2.62
V
V
V
V
V
V
V
V
PUMP0
PUMP1
PUMP2
PUMP3
PUMP4
PUMP5
PUMP6
PUMP7
3.09
3.16
[15]
3.32
4.74
4.83
4.92
5.12
Notes
12. Always greater than 50 mV above V
13. Always greater than 50 mV above V
14. Always greater than 50 mV above V
15. Always greater than 50 mV above V
(PORLEV = 00) for falling supply.
(PORLEV = 01) for falling supply.
PPOR
PPOR
.
.
LVD0
LVD3
Document Number: 38-12022 Rev. AB
Page 21 of 47
CY8C21123/CY8C21223/CY8C21323
DC Programming Specifications
Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –
40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 20. DC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
V
V
V
V
V
for programming and erase
4.5
5.0
5.5
V
This specification applies to
the functional requirements
of external programmer tools
DDP
DD
Low V for verify
2.4
5.1
2.5
5.2
–
2.6
5.3
V
V
V
This specification applies to
the functional requirements
of external programmer tools
DDLV
DD
High V for verify
This specification applies to
the functional requirements
of external programmer tools
DDHV
DD
Supply voltage for flash write operations
2.70
5.25
This specification applies to
this device when it is
executing internal flash
writes
DDIWRITE
I
Supply current during programming or verify
Input low voltage during programming or verify
Input high voltage during programming or verify
–
–
5
–
–
–
25
0.8
–
mA
V
DDP
V
V
ILP
2.2
–
V
IHP
I
Input current when applying V to P1[0] or P1[1]
0.2
mA
Driving internal pull-down
resistor
ILP
ILP
during programming or verify
I
Input current when applying V
during programming or verify
to P1[0] or P1[1]
IHP
–
–
–
1.5
mA
Driving internal pull-down
resistor
IHP
V
V
Output low voltage during programming or verify
Output high voltage during programming or verify
Flash endurance (per block)
–
–
–
V
+ 0.75
SS
V
V
–
OLV
V
– 1.0
V
DD
OHV
DD
[16]
Flash
Flash
Flash
50,000
–
Erase/write cycles per block
Erase/write cycles
ENPB
ENT
DR
[17]
0
0
0
0
Flash endurance (total)
1,800,000
10
–
–
–
Flash data retention
–
–
Years
DC I2C Specifications
Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –
40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 21. DC I2C Specifications[18]
Symbol
Description
Min
Typ
–
Max
Units
Notes
V
V
Input low level
Input high level
–
–
0.3 × V
V
V
V
2.4 V V 3.6 V
ILI2C
DD
DD
–
0.25 × V
–
4.75 V V 5.25 V
DD
DD
0.7 × V
–
2.4 V V 5.25 V
IHI2C
DD
DD
Notes
16. The 50,000 cycle flash endurance per block is guaranteed if the flash is operating within one voltage range. Voltage ranges are 2.4 V to 3.0 V, 3.0 V to 3.6 V,
and 4.75 V to 5.25 V.
17. A maximum of 36 × 50,000 block endurance cycles is allowed. This may be balanced between operations on 36 × 1 blocks of 50,000 maximum cycles each, 36 × 2
blocks of 25,000 maximum cycles each, or 36 × 4 blocks of 12,500 maximum cycles each (and so forth to limit the total number of cycles to 36 × 50,000 and that no
single block ever sees more than 50,000 cycles).For the full industrial range, you must employ a temperature sensor user module (FlashTemp) and feed the result to
®
the temperature argument before writing. Refer to the application note, Design Aids — Reading and Writing PSoC Flash – AN2015 for more information on Flash APIs.
2
18. All GPIO meet the DC GPIO V and V specifications mentioned in section DC GPIO Specifications on page 18. The I C GPIO pins also meet the mentioned specs.
IL
IH
Document Number: 38-12022 Rev. AB
Page 22 of 47
CY8C21123/CY8C21223/CY8C21323
AC Electrical Characteristics
AC Chip-Level Specifications
Table 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –
40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 22. 5-V and 3.3-V AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
[19]
[20,21]
F
IMO frequency for 24 MHz
22.8
24
MHz Trimmed for 5 V or 3.3 V
operation using factory trim
values. Refer to Figure 11 on
page 16.
IMO24
25.2
SLIMO mode = 0.
[20,21]
[20]
F
F
IMO frequency for 6 MHz
5.5
6
MHz Trimmedfor3.3Voperationusing
factory trim values. See Figure 11
on page 16.
IMO6
6.5
SLIMO mode = 1.
CPU frequency (5 V nominal)
CPU frequency (3.3 V nominal)
0.0937
24
MHz 12 MHz only for
SLIMO mode = 0.
CPU1
24.6
[21]
F
F
0.0937
0
12
48
MHz SLIMO Mode = 0.
CPU2
12.3
0
[20,22]
Digital PSoC block frequency
(5 V nominal)
MHz Refer to the section AC Digital
Block Specifications on page 26.
BLK5
49.2
[22]
F
Digital PSoC block frequency
(3.3 V nominal)
0
24
MHz
BLK33
24.6
F
F
ILO frequency
15
5
32
–
64
kHz
32K1
ILO untrimmed frequency
100
kHz After a reset and before the M8C
starts to run, the ILO is not
trimmed. See the system resets
section of the PSoC Technical
Reference Manual for details on
this timing.
32K_U
t
External reset pulse width
24 MHz duty cycle
10
40
–
50
–
60
80
–
µs
%
XRST
DC24M
DC
ILO duty cycle
20
50
%
ILO
Step24M
Fout48M
24 MHz trim step size
48 MHz output frequency
–
50
kHz
[20,21]
46.8
48.0
MHz Trimmed. Using factory trim
values.
49.2
F
Maximum frequency of signal on row input or
row output.
–
–
12.3
MHz
MAX
SR
Power supply slew rate
–
–
–
250
100
V/ms
V
slew rate during power-up.
DD
POWER_UP
t
Time from end of POR to CPU executing code
16
ms Power-up from 0 V. See the
system resets section of the
PSoC Technical Reference
Manual.
POWERUP
[23]
t
24-MHz IMO cycle-to-cycle jitter (RMS)
–
–
200
300
700
900
ps
jit_IMO
24-MHz IMO long term N cycle-to-cycle jitter
ps
N = 32
[23]
(RMS)
[23]
24-MHz IMO period jitter (RMS)
–
100
400
ps
Notes
19. Errata: When the device is operated within 0 °C to 70 °C, the frequency tolerance is reduced to ±2.5%, but if operated at extreme temperature (below 0 °C or above
70 °C), frequency tolerance deviates from ±2.5% to ±5%. For more information, see “Errata” on page 43.
20. 4.75 V < V < 5.25 V.
DD
21. 3.0 V < V < 3.6 V. Refer to the application note, Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation – AN2012 for more information on trimming
DD
for operation at 3.3 V.
22. See the individual user module datasheets for information on maximum frequencies for user modules.
23. Refer to the application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information on jitter specifications.
Document Number: 38-12022 Rev. AB
Page 23 of 47
CY8C21123/CY8C21223/CY8C21323
Table 23. 2.7-V AC Chip-Level Specifications
Symbol Description
IMO frequency for 12 MHz
Min
Typ
Max
Units
Notes
0
[24,25]
F
11.5
12
MHz Trimmed for 2.7 V operation
using factory trim values. See
Figure 11 on page 16.
IMO12
12.7
SLIMO mode = 1.
[24,25]
F
IMO frequency for 6 MHz
5.5
6
MHz Trimmed for 2.7 V operation
using factory trim values. See
Figure 11 on page 16.
IMO6
6.5
SLIMO mode = 1.
[24]
F
F
CPU frequency (2.7 V nominal)
0.093
0
3
MHz 24 MHz only for
SLIMO mode = 0.
CPU1
3.15
[24,25]
Digital PSoC block frequency (2.7 V nominal)
12
MHz Refer to the section AC Digital
Block Specifications on page 26.
BLK27
12.5
F
F
ILO frequency
8
5
32
–
96
kHz
32K1
ILO untrimmed frequency
100
kHz After a reset and before the M8C
starts to run, the ILO is not
trimmed. See the system resets
section of the PSoC Technical
Reference Manual for details on
this timing.
32K_U
t
External reset pulse width
ILO duty cycle
10
20
–
–
50
–
–
µs
%
XRST
DC
80
ILO
F
Maximum frequency of signal on row input or row
output
12.3
MHz
MAX
SR
Power supply slew rate
–
–
–
250
100
V/ms
V
slew rate during power-up.
POWER_UP
DD
t
Time from end of POR to CPU executing code
16
ms Power-up from 0 V. See the
system resets section of the
PSoC Technical Reference
Manual.
POWERUP
[26]
t
12-MHz IMO cycle-to-cycle jitter (RMS)
–
–
400
600
1000
1300
ps
jit_IMO
12-MHz IMO long term N cycle-to-cycle jitter
ps
N = 32
[26]
(RMS)
[26]
12-MHz IMO period jitter (RMS)
–
100
500
ps
Notes
24. 2.4 V < V < 3.0 V.
DD
25. Refer to the application note Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation – AN2012 for more information on maximum frequency
for user modules.
26. Refer to the application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information on jitter specifications.
Document Number: 38-12022 Rev. AB
Page 24 of 47
CY8C21123/CY8C21223/CY8C21323
AC General Purpose I/O Specifications
Table 24 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –
40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 24. 5-V and 3.3-V AC GPIO Specifications
Symbol
Description
GPIO operating frequency
Min
0
Typ
–
Max
12
18
18
–
Units
Notes
F
MHz Normal strong mode
GPIO
tRiseF
tFallF
tRiseS
tFallS
Rise time, normal strong mode, Cload = 50 pF
Fall time, normal strong mode, Cload = 50 pF
Rise time, slow strong mode, Cload = 50 pF
Fall time, slow strong mode, Cload = 50 pF
3
–
ns
ns
ns
ns
V
V
V
V
= 4.5 V to 5.25 V, 10% to 90%
= 4.5 V to 5.25 V, 10% to 90%
= 3 V to 5.25 V, 10% to 90%
= 3 V to 5.25 V, 10% to 90%
DD
DD
DD
DD
2
–
10
10
27
22
–
Table 25. 2.7-V AC GPIO Specifications
Symbol
Description
GPIO operating frequency
Min
0
Typ
–
Max
3
Units
Notes
F
MHz Normal strong mode
GPIO
tRiseF
tFallF
tRiseS
tFallS
Rise time, normal strong mode, Cload = 50 pF
Fall time, normal strong mode, Cload = 50 pF
Rise time, slow strong mode, Cload = 50 pF
Fall time, slow strong mode, Cload = 50 pF
6
–
50
ns
ns
ns
ns
V
V
V
V
= 2.4 V to 3.0 V, 10% to 90%
= 2.4 V to 3.0 V, 10% to 90%
= 2.4 V to 3.0 V, 10% to 90%
= 2.4 V to 3.0 V, 10% to 90%
DD
DD
DD
DD
6
–
50
18
18
40
40
120
120
Figure 13. GPIO Timing Diagram
90%
GPIO
Pin
10%
TRiseF
TRi seS
TFallF
TFallS
AC Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical
parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the analog continuous time PSoC block.
Table 26. 5-V and 3.3-V AC Amplifier Specifications
Symbol
Description
Min
–
Typ
–
Max
100
300
Units
ns
t
t
Comparator mode response time, 50 mVpp signal centered on Ref
Comparator mode response time, 2.5 V input, 0.5 V overdrive
COMP1
COMP2
–
–
ns
Table 27. 2.7-V AC Amplifier Specifications
Symbol
Description
Min
–
Typ
–
Max
600
300
Units
ns
t
t
Comparator mode response time, 50 mVpp signal centered on Ref
Comparator mode response time, 1.5 V input, 0.5 V overdrive
COMP1
COMP2
–
–
ns
Document Number: 38-12022 Rev. AB
Page 25 of 47
CY8C21123/CY8C21223/CY8C21323
AC Digital Block Specifications
Table 28 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –
40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 28. 5-V and 3.3-V AC Digital Block Specifications
Function
Description
Min
Typ
Max
Unit
Notes
All functions Block input clock frequency
V
V
4.75 V
–
–
–
–
50.4
25.2
MHz
MHz
DD
DD
< 4.75 V
Timer
Input clock frequency
No capture, V 4.75 V
–
–
–
–
–
–
–
50.4
25.2
25.2
–
MHz
MHz
MHz
ns
DD
No capture, V < 4.75 V
DD
With capture
[27]
Capture pulse width
Input clock frequency
50
Counter
Dead Band
No enable input, V 4.75 V
–
–
–
–
–
–
–
50.4
25.2
25.2
–
MHz
MHz
MHz
ns
DD
No enable input, V < 4.75 V
DD
With enable input
Enable input pulse width
Kill pulse width
[27]
50
Asynchronous restart mode
Synchronous restart mode
Disable mode
20
–
–
–
–
–
–
ns
ns
ns
[27]
50
50
[27]
Input clock frequency
V
V
4.75 V
–
–
–
50.4
25.2
MHz
MHz
DD
< 4.75 V
–
DD
CRCPRS
(PRS
Mode)
Input clock frequency
V
V
4.75 V
–
–
–
–
–
–
50.4
25.2
25.2
MHz
MHz
MHz
DD
< 4.75 V
DD
CRCPRS
(CRC
Input clock frequency
Mode)
SPIM
SPIS
Input clock frequency
–
–
–
8.2
MHz
The SPI serial clock (SCLK) frequency is equal to
the input clock frequency divided by 2.
Input clock (SCLK) frequency
–
–
4.1
–
MHz
ns
The input clock is the SPI SCLK in SPIS mode.
[27]
Width of SS_negated between
transmissions
50
Transmitter
Receiver
Input clock frequency
The baud rate is equal to the input clock frequency
divided by 8.
V
V
V
4.75 V, 2 stop bits
4.75 V, 1 stop bit
< 4.75 V
–
–
–
–
–
–
50.4
25.2
25.2
MHz
MHz
MHz
DD
DD
DD
Input clock frequency
The baud rate is equal to the input clock frequency
divided by 8.
V
V
V
4.75 V, 2 stop bits
–
–
–
–
–
–
50.4
25.2
25.2
MHz
MHz
MHz
DD
DD
DD
4.75 V, 1 stop bit
< 4.75 V
Note
27. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 38-12022 Rev. AB
Page 26 of 47
CY8C21123/CY8C21223/CY8C21323
Table 29. 2.7-V AC Digital Block Specifications
Function
All
Description
Min
Typ
Max
Units
Notes
Block input clock frequency
–
–
12.7
MHz 2.4 V < V < 3.0 V.
DD
functions
[28]
Timer
Capture pulse width
100
–
–
–
–
–
–
ns
Input clock frequency, with or without capture
Enable input pulse width
Input clock frequency, no enable input
Input clock frequency, enable input
Kill pulse width:
–
100
–
12.7
–
MHz
ns
Counter
12.7
12.7
MHz
MHz
–
Dead band
Asynchronous restart mode
Synchronous restart mode
Disable mode
20
100
100
–
–
–
–
–
–
–
–
ns
ns
–
ns
Input clock frequency
12.7
12.7
MHz
MHz
CRCPRS
(PRS mode)
Input clock frequency
–
CRCPRS
(CRC mode)
Input clock frequency
Input clock frequency
–
–
–
–
12.7
6.35
MHz
SPIM
MHz The SPI serial clock (SCLK)
frequency is equal to the input clock
frequency divided by 2.
SPIS
Input clock (SCLK) frequency
Width of SS_ Negated between transmissions
Input clock frequency
–
100
–
–
–
–
4.1
–
MHz
ns
Transmitter
Receiver
12.7
MHz The baud rate is equal to the input
clock frequency divided by 8.
Input clock frequency
–
–
12.7
MHz The baud rate is equal to the input
clock frequency divided by 8.
Note
28. 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
Document Number: 38-12022 Rev. AB
Page 27 of 47
CY8C21123/CY8C21223/CY8C21323
AC External Clock Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or
2.7 V at 25 °C and are for design guidance only.
Table 30. 5-V AC External Clock Specifications
Symbol
Description
Min
0.093
20.6
20.6
150
Typ
–
Max
24.6
5300
–
Units
MHz
ns
Notes
F
Frequency
High period
Low period
OSCEXT
–
–
–
–
–
ns
Power-up IMO to switch
–
–
µs
Table 31. 3.3-V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
F
Frequency with CPU clock divide by 1
0.093
–
12.3
MHz Maximum CPU frequency is 12 MHz at
3.3 V. With the CPU clock divider set to
1, the external clock must adhere to the
maximum frequency and duty cycle
requirements.
OSCEXT
F
Frequency with CPU clock divide by 2 or
greater
0.186
–
24.6
MHz If the frequency of the external clock is
greater than 12 MHz, the CPU clock
divider must be setto 2 or greater. In this
case, the CPU clock divider ensures
that the fifty percent duty cycle
OSCEXT
requirement is met.
–
–
–
High period with CPU clock divide by 1
Low period with CPU clock divide by 1
Power-up IMO to switch
41.7
41.7
150
–
–
–
5300
ns
ns
µs
–
–
Table 32. 2.7-V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
0
F
Frequency with CPU clock divide by 1
0.093
–
6.06
MHz Maximum CPU frequency is 3 MHz at
2.7 V. With the CPU clock divider set to
1, the external clock must adhere to the
maximum frequency and duty cycle
requirements.
OSCEXT
F
Frequency with CPU clock divide by 2 or
greater
0.186
–
12.12
MHz If the frequency of the external clock is
greater than 3 MHz, the CPU clock
divider must be set to 2 or greater. In this
case, the CPU clock divider ensures
that the fifty percent duty cycle
OSCEXT
requirement is met.
–
–
–
High period with CPU clock divide by 1
Low period with CPU clock divide by 1
Power-up IMO to switch
83.4
83.4
150
–
–
–
5300
ns
ns
µs
–
–
Document Number: 38-12022 Rev. AB
Page 28 of 47
CY8C21123/CY8C21223/CY8C21323
AC Programming Specifications
Table 33 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –
40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C
and are for design guidance only.
Table 33. AC Programming Specifications
Symbol
Description
Min
1
Typ
–
Max
20
20
–
Units
ns
Notes
t
t
t
t
Rise time of SCLK
Fall time of SCLK
RSCLK
1
–
ns
FSCLK
SSCLK
HSCLK
Data set up time to falling edge of SCLK
Data hold time from falling edge of SCLK
Frequency of SCLK
40
40
0
–
ns
–
–
ns
F
–
8
MHz
ms
ms
ns
SCLK
t
t
t
t
t
Flash erase time (block)
–
10
80
–
–
ERASEB
WRITE
Flash block write time
–
–
Data out delay from falling edge of SCLK
Data out delay from falling edge of SCLK
Flash erase time (bulk)
–
50
70
–
3.0 V 3.6.
DSCLK3
DSCLK2
ERASEALL
DD
–
–
ns
2.4 V 3.0.
DD
–
20
ms
Erase all blocks and
protection fields at once.
[30]
t
t
Flash block erase + flash block write time
Flash block erase + flash block write time
–
–
–
–
180
360
ms
ms
0 °C Tj 100 °C.
–40 °C Tj 0 °C.
PROGRAM_HOT
PROGRAM_COLD
[30]
AC I2C Specifications
Table 34 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –
40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 34. AC Characteristics of the I2C SDA and SCL Pins for VCC 3.0 V
Standard Mode
Fast Mode
Symbol
Description
Units
Min
Max
Min
Max
F
SCL clock frequency
0
100
0
400
–
kHz
µs
SCLI2C
t
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
4.0
–
0.6
HDSTAI2C
t
t
t
t
t
t
t
t
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
4.7
4.0
4.7
0
–
–
–
–
1.3
0.6
0.6
0
–
–
–
–
µs
µs
µs
µs
LOWI2C
HIGHI2C
SUSTAI2C
HDDATI2C
SUDATI2C
SUSTOI2C
BUFI2C
0
0
0
0
0
[29]
Data setup time
250
4.0
4.7
–
–
–
ns
100
Setup time for STOP condition
–
–
–
0.6
1.3
0
–
–
µs
µs
ns
Bus free time between a STOP and START condition
Pulse width of spikes are suppressed by the input filter
50
SPI2C
Notes
2
2
29. A fast-mode I C-bus device can be used in a standard-mode I C-bus system, but the requirement t
250 ns must then be met. This automatically becomes
SUDAT
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next
2
data bit to the SDA line t
+ t
= 1000 + 250 = 1250 ns (according to the standard-mode I C-bus specification) before the SCL line is released.
rmax
SUDAT
30. For the full industrial range, you must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
®
Refer to the application note, Design Aids — Reading and Writing PSoC Flash – AN2015 for more information on Flash APIs.
Document Number: 38-12022 Rev. AB
Page 29 of 47
CY8C21123/CY8C21223/CY8C21323
Table 35. 2.7-V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode Not Supported)
Standard Mode
Fast Mode
Symbol
Description
Units
Min
Max
Min
Max
F
SCL clock frequency
0
100
–
–
–
kHz
µs
SCLI2C
t
Hold time (repeated) START Condition. After this period, the first clock
pulse is generated.
4.0
–
–
HDSTAI2C
t
t
t
t
t
t
t
t
Low period of the SCL clock
4.7
4.0
4.7
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
µs
µs
µs
µs
ns
µs
µs
ns
LOWI2C
High period of the SCL clock
HIGHI2C
SUSTAI2C
HDDATI2C
SUDATI2C
SUSTOI2C
BUFI2C
Setup time for a repeated START condition
Data hold time
Data setup time
250
4.0
4.7
–
Setup time for STOP condition
Bus free time between a STOP and START condition
Pulse width of spikes are suppressed by the input filter.
SPI2C
Figure 14. Definition for Timing for Fast/Standard Mode on the I2C Bus
I2C_SDA
I2C_SCL
TSUDATI2C
THDSTAI2C
TSPI2C
TSUSTAI2C
TBUFI2C
THDDATI2C
THIGHI2C TLOWI2C
TSUSTOI2C
P
S
S
Sr
Repeated START Condition
STOP Condition
START Condition
Document Number: 38-12022 Rev. AB
Page 30 of 47
CY8C21123/CY8C21223/CY8C21323
Packaging Information
This section illustrates the packaging specifications for the CY8C21x23 PSoC device, along with the thermal impedances for each
package and minimum solder reflow peak temperature.
Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of
the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com.
Packaging Dimensions
Figure 15. 8-pin SOIC (150 Mils) S0815/SZ815/SW815 Package Outline, 51-85066
51-85066 *H
Document Number: 38-12022 Rev. AB
Page 31 of 47
CY8C21123/CY8C21223/CY8C21323
Figure 16. 16-Pin (150-Mil) SOIC
51-85068 *E
Figure 17. 16-Pin QFN with no E-Pad
001-09116 *J
Document Number: 38-12022 Rev. AB
Page 32 of 47
CY8C21123/CY8C21223/CY8C21323
Figure 18. 20-pin SSOP (210 Mils) O20.21 Package Outline, 51-85077
51-85077 *F
Figure 19. 24-Pin (4 4) QFN (Punched)
51-85203 *D
Document Number: 38-12022 Rev. AB
Page 33 of 47
CY8C21123/CY8C21223/CY8C21323
Figure 20. 24-Pin (4 4) QFN (Sawn)
001-13937 *F
Important Note For information on the preferred dimensions for mounting QFN packages, refer the application note,
Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages available at http://www.amkor.com.
Note that pinned vias for thermal conduction are not required for the low power 24, 32, and 48-pin QFN PSoC devices.
Document Number: 38-12022 Rev. AB
Page 34 of 47
CY8C21123/CY8C21223/CY8C21323
Thermal Impedances
Table 36. Thermal Impedances per Package
[31]
Package
8-pin SOIC
16-pin SOIC
16-pin QFN
20-pin SSOP
Typical
JA
186 °C/W
125 °C/W
46 °C/W
117 °C/W
40 °C/W
[32]
24-pin QFN
Solder Reflow Specifications
Table 37 shows the solder reflow temperature limits that must not be exceeded.
Table 37. Solder Reflow Specifications
Package
8-pin SOIC
16-pin SOIC
16-pin QFN
20-pin SSOP
24-pin QFN
Maximum Peak Temperature (T ) Maximum Time above T – 5 °C
C C
260 °C
260 °C
260 °C
260 °C
260 °C
30 seconds
30 seconds
30 seconds
30 seconds
30 seconds
Notes
31. T = T + POWER × JA
J
A
32. To achieve the thermal impedance specified for the QFN package, refer to "Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF)
Packages" available at http://www.amkor.com.
33. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220+/-5 °C with Sn-Pb or 245+/-5 °C with Sn-Ag-Cu
paste. Refer to the solder manufacturer specifications.
Document Number: 38-12022 Rev. AB
Page 35 of 47
CY8C21123/CY8C21223/CY8C21323
Ordering Information
The following table lists the CY8C21x23 PSoC device’s key package features and ordering codes.
Table 38. CY8C21x23 PSoC Device Key Features and Ordering Information
Switch
Mode
Pump
Flash
(Bytes) (Bytes)
RAM
Temperature
Range
Package
Ordering Code
8-Pin (150-Mil) SOIC
CY8C21123-24SXI
CY8C21123-24SXIT
4 K
4 K
4 K
4 K
256
256
256
256
No
No
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
4
4
4
4
4
4
4
4
6
6
4
4
8
8
0
0
0
0
No
No
No
No
8-Pin (150-Mil) SOIC
(Tape and Reel)
16-Pin (150-Mil) SOIC CY8C21223-24SXI
Yes
Yes
12
12
16-Pin (150-Mil) SOIC
CY8C21223-24SXIT
(Tape and Reel)
16-Pin (3 × 3) QFN with
CY8C21223-24LGXI
no E-Pad
4 K
4 K
4 K
256
256
256
No
No
No
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
4
4
4
4
4
4
12
16
16
8
8
8
0
0
0
Yes
Yes
Yes
20-Pin (210-Mil) SSOP CY8C21323-24PVXI
20-Pin (210-Mil) SSOP
CY8C21323-24PVXIT
(Tape and Reel)
24-Pin (4 × 4) QFN
CY8C21323-24LFXI
(Punched)
4 K
4 K
256
256
Yes
Yes
–40 °C to +85 °C
–40 °C to +85 °C
4
4
4
4
16
16
8
8
0
0
Yes
Yes
24-Pin (4 × 4) QFN
(Punched) (Tape and
Reel)
CY8C21323-24LFXIT
24-Pin (4 × 4) QFN
(Sawn)
CY8C21323-24LQXI
CY8C21323-24LQXIT
4 K
4 K
256
256
Yes
Yes
–40 °C to +85 °C
–40 °C to +85 °C
4
4
4
4
16
16
8
8
0
0
Yes
Yes
24-Pin (4 × 4) QFN
(Sawn) (Tape and Reel)
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Ordering Code Definitions
CY 8 C 21 xxx-24xx
Package Type:
SX = SOIC Pb-Free
PVX = SSOP Pb-Free
Thermal Rating:
C = Commercial
I = Industrial
LGX = QFN (sawn, 3 × 3 mm), Pb-Free
LFX = QFN (punched, 4 × 4 mm), Pb-Free
LQX = QFN (sawn, 4 × 4 mm), Pb-Free
E = Extended
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Document Number: 38-12022 Rev. AB
Page 36 of 47
CY8C21123/CY8C21223/CY8C21323
Acronyms
Acronyms Used
Table 39 lists the acronyms that are used in this document.
Table 39. Acronyms Used in this Datasheet
Acronym
AC
Description
alternating current
Acronym
Description
printed circuit board
PCB
PGA
ADC
API
analog-to-digital converter
application programming interface
complementary metal oxide semiconductor
central processing unit
programmable gain amplifier
power on reset
POR
CMOS
CPU
CRC
CT
PPOR
PRS
precision power on reset
pseudo-random sequence
Programmable System-on-Chip
pulse width modulator
quad flat no leads
cyclic redundancy check
continuous time
PSoC®
PWM
QFN
DAC
DC
digital-to-analog converter
direct current
SC
switched capacitor
EEPROM electrically erasable programmable read-only
memory
SLIMO
slow IMO
GPIO
ICE
general purpose I/O
SMP
SOIC
SPITM
SRAM
SROM
SSOP
UART
USB
switch mode pump
in-circuit emulator
small-outline integrated circuit
serial peripheral interface
static random access memory
supervisory read only memory
shrink small-outline package
universal asynchronous reciever / transmitter
universal serial bus
IDE
integrated development environment
internal low speed oscillator
internal main oscillator
input/output
ILO
IMO
I/O
IrDA
ISSP
LVD
MCU
MIPS
infrared data association
in-system serial programming
low voltage detect
WDT
watchdog timer
microcontroller unit
XRES
external reset
million instructions per second
Reference Documents
CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34,
CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip Technical
Reference Manual (TRM) (001-14463)
Design Aids – Reading and Writing PSoC® Flash – AN2015 (001-40459)
Adjusting PSoC® Trims for 3.3 V and 2.7 V Operation – AN2012 (001-17397)
Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 (001-14503)
Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com.
Document Number: 38-12022 Rev. AB
Page 37 of 47
CY8C21123/CY8C21223/CY8C21323
Document Conventions
Units of Measure
Table 40 lists the units of measures.
Table 40. Units of Measure
Symbol
dB
Unit of Measure
Symbol
Unit of Measure
decibels
mH
µH
µs
millihenry
°C
degree Celsius
microfarad
picofarad
kilohertz
microhenry
microsecond
millisecond
nanosecond
picosecond
microvolt
µF
pF
ms
ns
kHz
MHz
rt-Hz
k
megahertz
root hertz
kilohm
ps
µV
mV
mVpp
V
millivolt
ohm
millivolts peak-to-peak
µA
microampere
milliampere
nanoampere
pikoampere
volt
mA
nA
W
watt
mm
%
millimeter
percent
pA
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals.
Glossary
active high
1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks
The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks.
These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more.
analog-to-digital Adevice that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts
(ADC)
a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation.
Application
programming
interface (API)
A series of software routines that comprise an interface between a computer application and lower level services
and functions (for example, user modules and libraries).APIs serve as building blocks for programmers that create
software applications.
asynchronous
A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
bandgap
reference
A stable voltage reference design that matches the positive temperature coefficient of VT with the negative
temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference.
bandwidth
1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is
sometimes represented more specifically as, for example, full width at half maximum.
Document Number: 38-12022 Rev. AB
Page 38 of 47
CY8C21123/CY8C21223/CY8C21323
Glossary (continued)
bias
1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to
operate the device.
block
buffer
1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or
an analog PSoC block.
1. A storage area for data that is used to compensate for a speed difference, when transferring data from one
device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which
data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received
from an external device.
3. An amplifier used to lower the output impedance of a system.
bus
1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing
patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented using vector
notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock
The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to
synchronize different logic blocks.
comparator
compiler
An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy
predetermined amplitude requirements.
A program that translates a high level language, such as C, into machine language.
configuration
space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’.
crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less
sensitive to ambient temperature than other circuit components.
cyclicredundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift
check (CRC)
register. Similar calculations may be used for a variety of other purposes such as data compression.
data bus
A bi-directional set of signals used by a computer to convey information from a memory location to the central
processing unit and vice versa. More generally, a set of signals used to convey data between digital functions.
debugger
A hardware and software system that allows you to analyze the operation of the system under development. A
debugger usually allows the developer to step through the firmware one step at a time, set break points, and
analyze memory.
dead band
A period of time when neither of two or more signals are in their active state or in transition.
digital blocks
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator,
pseudo-random number generator, or SPI.
digital-to-analog Adevice that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC)
(DAC) converter performs the reverse operation.
Document Number: 38-12022 Rev. AB
Page 39 of 47
CY8C21123/CY8C21223/CY8C21323
Glossary (continued)
duty cycle
emulator
The relationship of a clock period high time to its low time, expressed as a percent.
Duplicates (provides an emulation of) the functions of one system with a different system, so that the second
system appears to behave like the first system.
External Reset
(XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop
and return to a pre-defined state.
Flash
An electrically programmable and erasable, non-volatile technology that provides you the programmability and
data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is
OFF.
Flash block
The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash
space that may be protected. A Flash block holds 64 bytes.
frequency
gain
The number of cycles or events per unit of time, for a periodic function.
The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually
expressed in dB.
I2C
Atwo-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated
Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in
the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building
control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5 V and pulled high
with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode.
ICE
The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging
device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt
A suspension of a process, such as the execution of a computer program, caused by an event external to that
process, and performed in such a way that the process can be resumed.
interrupt service A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many
routine (ISR)
interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends
with the RETI instruction, returning the device to the point in the program where it left normal program execution.
jitter
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low-voltagedetect A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a selected threshold.
(LVD)
M8C
An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by
interfacing to the Flash, SRAM, and register space.
master device
A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in
width, the master device is the one that controls the timing for data exchanges between the cascaded devices
and an external interface. The controlled device is called the slave device.
Document Number: 38-12022 Rev. AB
Page 40 of 47
CY8C21123/CY8C21223/CY8C21323
Glossary (continued)
microcontroller
An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a
microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the
realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This
in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for
general-purpose computation as is a microprocessor.
mixed-signal
modulator
noise
The reference to a circuit containing both analog and digital techniques and components.
A device that imposes a signal on a carrier.
1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator
parity
A circuit that may be crystal controlled and is used to generate a clock frequency.
A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the
digits of the binary data either always even (even parity) or always odd (odd parity).
Phase-locked
loop (PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference
signal.
pinouts
The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their
physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between
schematic and PCB design (both being computer generated files) and may also involve pin names.
port
A group of pins, usually eight.
Power on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is one type of
hardware reset.
PSoC®
Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark
of Cypress.
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
An output in the form of duty cycle which varies as a function of the applied measurand.
modulator (PWM)
RAM
An acronym for random access memory. A data-storage device from which data can be read out and new data
can be written in.
register
reset
A storage device with a specific capacity, such as a bit or byte.
A means of bringing a system back to a know state. See hardware reset and software reset.
ROM
An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot
be written in.
serial
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time
The time it takes for an output signal or value to stabilize after the input has changed from one value to another.
Document Number: 38-12022 Rev. AB
Page 41 of 47
CY8C21123/CY8C21223/CY8C21323
Glossary (continued)
shift register
slave device
A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.
A device that allows another device to control the timing for data exchanges between two devices. Or when
devices are cascaded in width, the slave device is the one that allows another device to control the timing of data
exchanges between the cascaded devices and an external interface. The controlling device is called the master
device.
SRAM
SROM
An acronym for static random access memory. A memory device where you can store and retrieve data at a high
rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged
until it is explicitly altered or until power is removed from the device.
An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate
circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code,
operating from Flash.
stop bit
A signal following a character or block that prepares the receiving device to receive the next character or block.
synchronous
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
tri-state
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any
value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit,
allowing another output to drive the same net.
UART
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits.
user modules
Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower
level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming
Interface) for the peripheral function.
user space
The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal
program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during
the initialization phase of the program.
VDD
A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V.
A name for a power net meaning "voltage source." The most negative power supply signal.
VSS
watchdog timer
A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.
Document Number: 38-12022 Rev. AB
Page 42 of 47
CY8C21123/CY8C21223/CY8C21323
Errata
This section describes the errata for the CY8C21x23 PSoC® programmable system-on-chip family. Details include errata trigger
conditions, scope of impact, available workarounds, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
Part Number
Ordering Information
CY8C21123-24SXI
CY8C21123-24SXIT
CY8C21223-24SXI
CY8C21223-24SXIT
CY8C21323-24PVXI
CY8C21323-24PVXIT
CY8C21323-24LFXI
CY8C21323-24LFXIT
CY8C21323-24LQXI
CY8C21323-24LQXIT
CY8C21123
CY8C21123 Qualification Status
Product Status: Production
CY8C21123 Errata Summary
The following table defines the errata applicability to available CY8C21123 family devices. An "X" indicates that the errata pertains to
the selected device.
Note Errata items, in the table below, are hyperlinked. Click on any item entry to jump to its description.
Items
Part Number
Silicon Revision
Fix Status
[1.] Internal Main Oscillator (IMO) Tolerance Deviation at
Temperature Extremes
No silicon fix is planned.
Workaround is required.
CY8C21123
A
1. Internal Main Oscillator (IMO) Tolerance Deviation at Temperature Extremes
■ Problem Definition
Asynchronous Digital Communications Interfaces may fail framing beyond 0 to 70 °C. This problem does not affect end-product
usage between 0 and 70 °C.
■ Parameters Affected
The IMO frequency tolerance. The worst case deviation when operated below 0 °C and above +70 °C and within the upper
and lower datasheet temperature range is ±5%.
■ Trigger Condition(S)
The asynchronous Rx/Tx clock source IMO frequency tolerance may deviate beyond the data sheet limit of ±2.5% when
operated beyond the temperature range of 0 to +70 °C.
■ Scope of Impact
This problem may affect UART, IrDA, and FSK implementations.
■ Workaround
Implement a quartz crystal stabilized clock source on at least one end of the asynchronous digital communications interface.
■ Fix Status
No silicon fix is planned. The workaround mentioned above should be used.
Document Number: 38-12022 Rev. AB
Page 43 of 47
CY8C21123/CY8C21223/CY8C21323
Document History Page
Document Title: CY8C21123/CY8C21223/CY8C21323, PSoC® Programmable System-on-Chip™
Document Number: 38-12022
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
133248
208900
212081
227321
NWJ
NWJ
See ECN New silicon and document (Revision **).
See ECN Add new part, new package and update all ordering codes to Pb-free.
See ECN Expand and prepare Preliminary version.
See ECN Update specs., data, format.
*A
*B
*C
NWJ
CMS Team
Updated Overview and Electrical Spec. chapters, along with 24-pin pinout.
See ECN
*D
235973
SFV
Added CMP_GO_EN register (1,64h) to mapping table.
Update datasheet standards per SFV memo. Fix device table. Add part
See ECN numbers to pinouts and fine tune. Change 20-pin SSOP to CY8C21323. Add
Reflow Temp. table. Update diagrams and specs.
*E
*F
290991
301636
HMT
HMT
See ECN DC Chip-Level Specification changes. Update links to new CY.com Portal.
Obtained clearer 16 SOIC package. Update Thermal Impedances and Solder
Reflow tables. Re-add pinout ISSP notation. FixADC type-o. Fix TMP register
names. Update Electrical Specifications. Add CY logo. Update CY copyright.
Make datasheet Final.
*G
*H
*I
324073
2588457
2618175
HMT
See ECN
KET / HMI /
AESA
New package information on page 9. Converted datasheet to new template.
Added 16-Pin OFN package diagram.
10/22/2008
Added Note in Ordering Information Section. Changed title from PSoC
Mixed-Signal Array to PSoC Programmable System-on-Chip. Updated
‘Development Tools’ and ‘Designing with PSoC Designer’ sections on pages
OGNE /
PYRS
12/09/2008
5 and 6
MAXK /
AESA
*J
2682782
2699713
04/03/2009 Corrected 16 COL pinout.
*K
MAXK
JVY
04/29/2009 Minor ECN to correct paragraph style of 16 COLPinout. No change in content.
Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as
follows:
Modified FIMO6 and TWRITE specifications.
Replaced TRAMP time) specification with SRPOWER_UP (slew rate) specifi-
cation.
*L
*M
*N
*O
2762497
2792630
2901653
2928895
09/11/2009
Added note [11] to Flash Endurance specification.
Added IOH, IOL, DCILO, F32K_U, TPOWERUP, TERASEALL, TPROGRAM_HOT, and
T
PROGRAM_COLD specifications..
Updated ordering information for CY8C21223-24LGXI to indicate availability
of XRES pin.
TTO
NJF
YJI
10/26/2009
03/30/2010
05/06/2010
Changed 16-pin COL to 16-pin QFN in the datasheet.
Added Contents.
Updated links in Sales, Solutions, and Legal Information
Updated Cypress website links.
Added TBAKETEMP and TBAKETIME parameters in Absolute Maximum Ratings
Updated 5-V and 3.3-V AC Chip-Level Specifications
Updated Notes in Packaging Information and package diagrams.
Updated Ordering Code Definitions
No technical updates.
Included with EROS spec.
Document Number: 38-12022 Rev. AB
Page 44 of 47
CY8C21123/CY8C21223/CY8C21323
Document History Page (continued)
Document Title: CY8C21123/CY8C21223/CY8C21323, PSoC® Programmable System-on-Chip™
Document Number: 38-12022
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
Added PSoC Device Characteristics table.
Added DC I2C Specifications table.
Added F32K_U max limit.
Added Tjit_IMO specification, removed existing jitter specifications.
Updated Units of Measure, Acronyms, Glossary, and References sections.
Updated solder reflow specifications.
No specific changes were made to AC Digital Block Specifications table and
I2C Timing Diagram. They were updated for clearer understanding.
Updated Figure 13 since the labelling for y-axis was incorrect.
Template and styles update.
*P
3044869
NJF
YJI
10/01/2010
Updated 16-pin SOIC and 20-pin SSOP package diagrams.
05/23/2011 Updated Development Tool Selection and Designing with PSoC Designer
sections.
*Q
*R
3263669
3383787
The text “Pin must be left floating” is included under Description of NC pin in
09/26/2011 Table 6 on page 11.
GIR
Updated Table 37 on page 35 for improved clarity.
*S
*T
*U
3558729
3598261
3649990
RJVB
03/22/2012 Updated 16-pin SOIC package.
LURE /
XZNG
04/24/2012 Changed the PWM description string from “8- to 32-bit” to “8- and 16-bit”.
BVI / YLIU
06/19/2012 Updated description of NC pin as “No Connection. Pin must be left floating”
Updated Packaging Information:
spec 51-85068 – Changed revision from *D to *E.
*V
3873870
3993321
UVS
01/18/2013
spec 001-09116 – Changed revision from *F to *G.
spec 51-85203 – Changed revision from *C to *D.
*W
UVS
05/07/2013 Added Errata.
Added Errata footnotes (Note 19).
Updated Features:
Replaced 2.5% with 5% under “Precision, programmable clocking”.
Updated Electrical Specifications:
Updated AC Electrical Characteristics:
Updated AC Chip-Level Specifications:
Added Note 19 and referred the same note in FIMO24 parameter.
07/18/2013 Updated minimum and maximum values of FIMO24 parameter.
Updated AC Digital Block Specifications:
*X
4067216
UVS
Replaced all instances of maximum value “49.2” with “50.4” and “24.6” with
“25.2” in Table 28.
Updated Packaging Information:
spec 51-85066 – Changed revision from *E to *F.
spec 001-09116 – Changed revision from *G to *H.
Updated to new template.
Updated Errata:
Updated CY8C21123 Errata Summary:
*Y
4479648
RJVB
08/20/2014
Updated details in “Fix Status” column in the table.
Updated details in “Fix Status” bulleted point below the table.
Document Number: 38-12022 Rev. AB
Page 45 of 47
CY8C21123/CY8C21223/CY8C21323
Document History Page (continued)
Document Title: CY8C21123/CY8C21223/CY8C21323, PSoC® Programmable System-on-Chip™
Document Number: 38-12022
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
Updated Pin Information:
Updated 20-Pin Part Pinout:
Updated Table 5:
Added Note 6 and referred the same note in description of pin 5 and pin 10.
Updated 24-Pin Part Pinout:
Updated Table 6:
*Z
4623500
DIMA
01/14/2015
Added Note 9 and referred the same note in description of pin 3, pin 9 and
pin 21.
Updated Packaging Information:
spec 51-85066 – Changed revision from *F to *G.
spec 51-85077 – Changed revision from *E to *F.
Completing Sunset Review.
Updated Ordering Information, Ordering Code Definitions, and Errata.
Updated figure title in Figure 19.
01/18/2016 Updated Table 38.
Updated Figure 15 (spec 51-85066 *G to *H) in Packaging Information.
Added Figure 20 (spec 001-13937 *F) in Packaging Information.
AA
AB
5090662
ARVI
5773393 AESATMP9 06/14/2017 Updated logo and copyright.
Document Number: 38-12022 Rev. AB
Page 46 of 47
CY8C21123/CY8C21223/CY8C21323
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
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Community | Forums | Blogs | Video | Training
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© Cypress Semiconductor Corporation, 2004-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
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Document Number: 38-12022 Rev. AB
Revised June 14, 2017
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