CY8C24423A-12PVXE [CYPRESS]
PSoC㈢ Mixed-Signal Array; 的PSoC ™混合信号阵列
| 型号： | CY8C24423A-12PVXE |
| 厂家： | 
CYPRESS |
| 描述： | PSoC㈢ Mixed-Signal Array |
| 文件： | 总33页 (文件大小：455K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PSoC® Mixed-Signal Array
Final Data Sheet
Automotive:
CY8C24223A and CY8C24423A
Features
■
■
Powerful Harvard Architecture Processor
■
■
Precision, Programmable Clocking
■
Additional System Resources
2
❐
❐
❐
❐
❐
M8C Processor Speeds to 12 MHz
8x8 Multiply, 32-Bit Accumulate
Low Power at High Speed
4.75V to 5.25V Operating Voltage
Extended Temp. Range: -40°C to +125°C
❐
❐
Internal ±4% 24 MHz Oscillator
High-Accuracy 24 MHz with Optional 32 kHz
Crystal and PLL
❐
I C™ Slave, Master, and Multi-Master to
400 kHz
❐
❐
❐
❐
Watchdog and Sleep Timers
User-Configurable Low Voltage Detection
Integrated Supervisory Circuit
On-Chip Precision Voltage Reference
❐
❐
Optional External Oscillator, up to 24 MHz
Internal Oscillator for Watchdog and Sleep
Flexible On-Chip Memory
Advanced Peripherals (PSoC Blocks)
❐
4K Bytes Flash Program Storage 100 Erase/
Write Cycles
256 Bytes SRAM Data Storage
In-System Serial Programming (ISSP)
Partial Flash Updates
❐
6 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
4 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
■
Complete Development Tools
❐
Free Development Software
(PSoC Designer™)
❐
❐
❐
❐
❐
Full-Featured, In-Circuit Emulator and
Programmer
Flexible Protection Modes
❐
❐
❐
Full Speed Emulation
Complex Breakpoint Structure
128K Bytes Trace Memory
❐
■
Programmable Pin Configurations
❐
❐
25 mA Sink on All GPIO
Pull Up, Pull Down, High Z, Strong, or Open
Drain Drive Modes on All GPIO
Up to 10 Analog Inputs on GPIO
Two 30 mA Analog Outputs on GPIO
Configurable Interrupt on All GPIO
- Full-Duplex UART
- Multiple SPI™ Masters or Slaves
- Connectable to all GPIO Pins
Complex Peripherals by Combining Blocks
❐
❐
❐
❐
Analog
Drivers
PSoC® Functional Overview
Port 2 Port 1 Port 0
PSoC CORE
The PSoC® family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of conve-
nient pinouts and packages.
System Bus
Global Digital Interconnect
SRAM
Global Analog Interconnect
Flash 4K
SROM
256 Bytes
Sleep and
Watchdog
CPUCore(M8C)
Interrupt
Controller
Multiple Clock Sources
(IncludesIMO,ILO,PLL,andECO)
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
the device resources to be combined into a complete custom
system. The PSoC automotive CY8C24x23A group can have
up to three IO ports that connect to the global digital and analog
interconnects, providing access to 4 digital blocks and 6 analog
blocks.
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref
Analog
Block
Array
Digital
Block Array
(1 Row,
4 Blocks)
(2 Columns,
6 Blocks)
Analog
Input
Muxing
The PSoC Core
The PSoC Core is a powerful engine that supports a rich fea-
ture set. The core includes a CPU, memory, clocks, and config-
urable GPIO (General Purpose IO).
POR and LVD
System Resets
Internal
Voltage
Ref.
Digital
Clocks
Multiply
Accum .
I2C
Decimator
SYSTEM RESOURCES
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CY8C24x23A Automotive Data Sheet
PSoC® Overview
The M8C CPU core is a powerful processor with speeds up to
12 MHz, providing a two MIPS 8-bit Harvard architecture micro-
processor. The CPU utilizes an interrupt controller with 11 vec-
tors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Digital peripheral configurations include those listed below.
■ PWMs (8 to 32 bit)
■ PWMs with Dead Band (8 to 32 bit)
■ Counters (8 to 32 bit)
■ Timers (8 to 32 bit)
■ UART 8 bit with selectable parity
■ SPI Master and Slave
Memory includes 4 KB of Flash for program storage and 256
bytes of SRAM for data storage. Program Flash utilizes four
protection levels on blocks of 64 bytes, allowing customized
software IP protection.
■ I2C Slave and Multi-Master (1 available as a System
Resource)
The PSoC device incorporates flexible internal clock genera-
tors, including a 24 MHz IMO (internal main oscillator) accurate
to 4% over temperature and voltage. A low power 32 kHz ILO
(internal low speed oscillator) is provided for the Sleep timer
and WDT. If crystal accuracy is desired, the ECO (32.768 kHz
external crystal oscillator) is available for use as a Real Time
Clock (RTC) and can optionally generate a crystal-accurate 24
MHz system clock using a PLL. The clocks, together with pro-
grammable clock dividers (as a System Resource), provide the
flexibility to integrate almost any timing requirement into the
PSoC device.
■ Cyclical Redundancy Checker/Generator (8 to 32 bit)
■ IrDA
■ Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the con-
straints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the opti-
mum choice of system resources for your application. Family
resources are shown in the table titled “PSoC Device Charac-
teristics” on page 3.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external interfac-
ing. Every pin also has the capability to generate a system inter-
rupt on high level, low level, and change from last read.
The Analog System
The Analog System is composed of 6 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and
can be customized to support specific application requirements.
Some of the more common PSoC analog functions (most avail-
able as user modules) are listed below.
The Digital System
The Digital System is composed of 4 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references.
■ Analog-to-digital converters (up to 2, with 6- to 14-bit resolu-
tion, selectable as Incremental, Delta Sigma, and SAR)
Port 1
Port 2
Port 0
■ Filters (2 and 4 pole band-pass, low-pass, and notch)
■ Amplifiers (up to 2, with selectable gain to 48x)
■ Instrumentation amplifiers (1 with selectable gain to 93x)
■ Comparators (up to 2, with 16 selectable thresholds)
■ DACs (up to 2, with 6- to 9-bit resolution)
To System Bus
Digital Clocks
From Core
To Analog
System
DIGITAL SYSTEM
■ Multiplying DACs (up to 2, with 6- to 9-bit resolution)
Digital PSoC Block Array
■ High current output drivers (two with 30 mA drive as a PSoC
Row 0
8
4
8
Core resource)
8
8
DBB00
DBB01
DCB02 DCB03
■ 1.3V reference (as a System Resource)
■ DTMF Dialer
4
■ Modulators
■ Correlators
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
■ Peak Detectors
■ Many other topologies possible
Digital System Block Diagram
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CY8C24x23A Automotive Data Sheet
PSoC® Overview
Analog blocks are arranged in a column of three, which
includes one CT (Continuous Time) and two SC (Switched
Capacitor) blocks, as shown in the figure below.
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems. Addi-
tional resources include a multiplier, decimator, switch mode
pump, low voltage detection, and power on reset. Brief state-
ments describing the merits of each system resource are pre-
sented below.
P0[7]
P0[5]
P0[6]
P0[4]
■ Digital clock dividers provide three customizable clock fre-
quencies for use in applications. The clocks can be routed to
both the digital and analog systems. Additional clocks can be
generated using digital PSoC blocks as clock dividers.
P0[3]
P0[1]
P0[2]
P0[0]
■ A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math as well
as digital filters.
P2[6]
P2[4]
P2[3]
P2[1]
■ The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
P2[2]
P2[0]
■ The I2C module provides 100 and 400 kHz communication
over two wires. Slave, master, and multi-master modes are
all supported.
■ Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
■ An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
Block Array
PSoC Device Characteristics
ACB00
ASC10
ASD20
ACB01
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks. The following table lists the resources
available for specific PSoC device groups. The PSoC device
covered by this data sheet is highlighted below.
ASD11
ASC21
PSoC Device Characteristics
Analog Reference
PSoC Part
Number
Interface to
Digital System
Reference
Generators
Ref Hi
Ref Lo
AGND
AGNDIn
Ref In
Bandgap
up to
64
CY8C29x66
4
16
12
4
4
12
2K
32K
up to
44
256
Bytes
CY8C27x43
CY8C24x94
CY8C24x23
2
1
1
8
4
4
12
48
12
4
2
2
4
2
2
12
6
16K
16K
4K
M8C Interface (Address Bus, Data Bus, Etc.)
49
1K
up to
24
256
Bytes
Analog System Block Diagram
6
up to
24
256
Bytes
CY8C24x23A
CY8C21x34
CY8C21x23
1
1
1
4
4
4
12
28
8
2
0
0
2
2
2
6
4K
8K
4K
up to
28
512
Bytes
4a
4a
256
Bytes
16
a. Limited analog functionality.
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CY8C24x23A Automotive Data Sheet
PSoC® Overview
Getting Started
Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
development environment for the Programmable System-on-
Chip (PSoC) devices. The PSoC Designer IDE and application
runs on Windows NT 4.0, Windows 2000, Windows Millennium
(Me), or Windows XP. (Reference the PSoC Designer Func-
tional Flow diagram below.)
The quickest path to understanding the PSoC silicon is by read-
ing this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an over-
view of the PSoC integrated circuit and presents specific pin,
register, and electrical specifications. For in-depth information,
along with detailed programming information, reference the
PSoC™ Mixed-Signal Array Technical Reference Manual.
PSoC Designer helps the customer to select an operating con-
figuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest PSoC device data sheets on
the web at http://www.cypress.com/psoc.
Development Kits
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
at http://www.onfulfillment.com/cypressstore/ contains develop-
ment kits, C compilers, and all accessories for PSoC develop-
ment. Click on PSoC (Programmable System-on-Chip) to view
a current list of available items.
Context
Graphical Designer
PSoC
Sensitive
Interface
Help
Designer
Tele-Training
Free PSoC "Tele-training" is available for beginners and taught
by a marketing or application engineer over the phone. Five
training classes are available to accelerate the learning curve
including introduction, designing, debugging, advanced design,
advanced analog, as well as application-specific classes cover-
ing topics like PSoC and the LIN bus. For days and times of the
tele-training, see http://www.cypress.com/support/training.cfm.
Importable
Design
Database
PSoC
Configuration
Sheet
Device
Database
Consultants
PSoC
Designer
Core
Application
Database
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant, go to the following Cypress support web site:
http://www.cypress.com/support/cypros.cfm.
Manufacturing
Information
File
Engine
Project
Database
User
Modules
Technical Support
Library
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support/login.cfm.
Application Notes
Emulation
Pod
In-Circuit
Emulator
Device
Programmer
A long list of application notes will assist you in every aspect of
your design effort. To view the PSoC application notes, go to
the http://www.cypress.com web site and select Application
Notes under the Design Resources list located in the center of
the web page. Application notes are sorted by date by default.
PSoC Designer Subsystems
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CY8C24x23A Automotive Data Sheet
PSoC® Overview
Debugger
PSoC Designer Software Subsystems
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Device Editor
The Device Editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic configu-
ration allows for changing configurations at run time.
Online Help System
PSoC Designer sets up power-on initialization tables for
selected PSoC block configurations and creates source code
for an application framework. The framework contains software
to operate the selected components and, if the project uses
more than one operating configuration, contains routines to
switch between different sets of PSoC block configurations at
run time. PSoC Designer can print out a configuration sheet for
a given project configuration for use during application pro-
gramming in conjunction with the Device Data Sheet. Once the
framework is generated, the user can add application-specific
code to flesh out the framework. It’s also possible to change the
selected components and regenerate the framework.
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is avail-
able for development support. This hardware has the capability
to program single devices.
Design Browser
The Design Browser allows users to select and import precon-
figured designs into the user’s project. Users can easily browse
a catalog of preconfigured designs to facilitate time-to-design.
Examples provided in the tools include a 300-baud modem, LIN
Bus master and slave, fan controller, and magnetic card reader.
The emulator consists of a base unit that connects to the PC by
way of the parallel or USB port. The base unit is universal and
will operate with all PSoC devices. Emulation pods for each
device family are available separately. The emulation pod takes
the place of the PSoC device in the target board and performs
full speed (12 MHz) operation.
Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble, com-
pile, link, and build.
Assembler. The macro assembler allows the assembly code
to be merged seamlessly with C code. The link libraries auto-
matically use absolute addressing or can be compiled in relative
mode, and linked with other software modules to get absolute
addressing.
C Language Compiler. A C language compiler is available
that supports Cypress MicroSystems’ PSoC family devices.
Even if you have never worked in the C language before, the
product quickly allows you to create complete C programs for
the PSoC family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
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CY8C24x23A Automotive Data Sheet
PSoC® Overview
Designing with User Modules
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture
a unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that determine its function and
connectivity to other blocks, multiplexers, buses and to the IO
pins. Iterative development cycles permit you to adapt the hard-
ware as well as the software. This substantially lowers the risk
of having to select a different part to meet the final design
requirements.
Device Editor
Placement
and
Parameter
-ization
User
Module
Selection
Source
Code
Generator
Generate
Application
Application Editor
Source
Code
Editor
To speed the development process, the PSoC Designer Inte-
grated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library con-
tains over 50 common peripherals such as ADCs, DACs Tim-
ers, Counters, UARTs, and other not-so common peripherals
such as DTMF Generators and Bi-Quad analog filter sections.
Project
Manager
Build
Manager
Build
All
Debugger
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters
that allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Mod-
ule configures one or more digital PSoC blocks, one for each 8
bits of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides high-
level functions to control and respond to hardware events at
run-time. The API also provides optional interrupt service rou-
tines that you can adapt as needed.
Event &
Breakpoint
Manager
Interface
to ICE
Storage
Inspector
User Module and Source Code Development Flows
The next step is to write your main program, and any sub-rou-
tines using PSoC Designer’s Application Editor subsystem.
The Application Editor includes a Project Manager that allows
you to open the project source code files (including all gener-
ated code files) from a hierarchal view. The source code editor
provides syntax coloring and advanced edit features for both C
and assembly language. File search capabilities include simple
string searches and recursive “grep-style” patterns. A single
mouse click invokes the Build Manager. It employs a profes-
sional-strength “makefile” system to automatically analyze all
file dependencies and run the compiler and assembler as nec-
essary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in
a console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.
The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the set-
ting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. You pick the user modules you
need for your project and map them onto the PSoC blocks with
point-and-click simplicity. Next, you build signal chains by inter-
connecting user modules to each other and the IO pins. At this
stage, you also configure the clock source connections and
enter parameter values directly or by selecting values from
drop-down menus. When you are ready to test the hardware
configuration or move on to developing code for the project, you
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
the device to your specification and provides the high-level user
module API functions.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger down-
loads the HEX image to the In-Circuit Emulator (ICE) where it
runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
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CY8C24x23A Automotive Data Sheet
PSoC® Overview
Document Conventions
Table of Contents
For an in depth discussion and more information on your PSoC
device, obtain the PSoC Mixed-Signal Array Technical Refer-
ence Manual. This document encompasses and is organized
into the following chapters and sections.
Acronyms Used
The following table lists the acronyms that are used in this doc-
ument.
1.
2.
3.
Pin Information ............................................................. 8
Acronym
AC
Description
alternating current
1.1 Pinouts ................................................................... 8
1.1.1 20-Pin Part Pinout ..................................... 8
1.1.2 28-Pin Part Pinout ..................................... 9
ADC
API
analog-to-digital converter
application programming interface
central processing unit
continuous time
CPU
CT
Register Reference ..................................................... 10
2.1 Register Conventions ........................................... 10
2.1.1 Abbreviations Used .................................. 10
2.2 Register Mapping Tables ..................................... 10
DAC
DC
digital-to-analog converter
direct current
ECO
EEPROM
FSR
GPIO
GUI
external crystal oscillator
electrically erasable programmable read-only memory
full scale range
Electrical Specifications ............................................ 13
3.1 Absolute Maximum Ratings ................................ 14
3.2 Operating Temperature ....................................... 14
3.3 DC Electrical Characteristics ................................ 15
3.3.1 DC Chip-Level Specifications ................... 15
3.3.2 DC General Purpose IO Specifications .... 15
3.3.3 DC Operational Amplifier Specifications ... 16
3.3.4 DC Low Power Comparator Specifications 16
3.3.5 DC Analog Output Buffer Specifications ... 17
3.3.6 DC Analog Reference Specifications ....... 18
3.3.7 DC Analog PSoC Block Specifications ..... 19
3.3.8 DC POR and LVD Specifications ............. 19
3.3.9 DC Programming Specifications ............... 20
3.4 AC Electrical Characteristics ................................ 21
3.4.1 AC Chip-Level Specifications ................... 21
3.4.2 AC General Purpose IO Specifications .... 23
3.4.3 AC Operational Amplifier Specifications ... 24
3.4.4 AC Low Power Comparator Specifications 24
3.4.5 AC Digital Block Specifications ................. 26
3.4.6 AC Analog Output Buffer Specifications ... 27
3.4.7 AC External Clock Specifications ............. 27
3.4.8 AC Programming Specifications ............... 27
3.4.9 AC I2C Specifications ............................... 28
general purpose IO
graphical user interface
human body model
HBM
ICE
in-circuit emulator
ILO
internal low speed oscillator
internal main oscillator
input/output
IMO
IO
IPOR
LSb
imprecise power on reset
least-significant bit
LVD
low voltage detect
MSb
PC
most-significant bit
program counter
PLL
phase-locked loop
POR
PPOR
PSoC™
PWM
SC
power on reset
precision power on reset
Programmable System-on-Chip™
pulse width modulator
switched capacitor
SRAM
static random access memory
4.
Packaging Information ............................................... 29
4.1 Packaging Dimensions ......................................... 29
4.2 Thermal Impedances .......................................... 30
4.3 Capacitance on Crystal Pins ............................... 30
4.4 Solder Reflow Peak Temperature ........................ 31
Units of Measure
A units of measure table is located in the Electrical Specifica-
tions section. Table 3-1 on page 13 lists all the abbreviations
used to measure the PSoC devices.
5.
6.
Ordering Information .................................................. 32
5.1 Ordering Code Definitions ................................... 32
Numeric Naming
Sales and Company Information ............................... 33
Hexidecimal numbers are represented with all letters in upper-
case with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’ or ‘b’ are decimal.
6.1 Revision History .................................................. 33
6.2 Copyrights and Flash Code Protection ................ 33
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1. Pin Information
This chapter describes, lists, and illustrates the CY8C24x23A automotive PSoC device pins and pinout configurations.
1.1
Pinouts
The CY8C24x23A automotive PSoC device is available in a variety of packages which are listed and illustrated in the following
tables. Every port pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, and XRES are not capable of Digital IO.
1.1.1
20-Pin Part Pinout
Table 1-1. 20-Pin Part Pinout (SSOP)
Type
CY8C24223A 20-Pin PSoC Device
Pin
No.
Pin
Name
Description
Digital Analog
1
2
3
4
5
6
7
8
9
IO
IO
IO
IO
I
P0[7]
P0[5]
P0[3]
P0[1]
Vss
Analog column mux input.
A, I,P0[7]
A,IO, P0[5]
A,IO, P0[3]
A,I, P0[1]
Vdd
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
IO
IO
I
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
P0[6], A,I
P0[4], A,I
P0[2], A,I
Vss
P0[0], A,I
XRES
P1[6]
Power
Power
Ground connection.
SSOP
I2CSCL,P1[7]
I2C SDA,P1[5]
P1[3]
IO
IO
IO
IO
P1[7]
P1[5]
P1[3]
P1[1]
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
P1[4],EXTCLK
P1[2]
P1[0],XTALout,I2CSDA
I2CSCL,XTALin,P1[1]
Vss
Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*.
10
10
11
Vss
Ground connection.
IO
IO
P1[0]
Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA*.
12
P1[2]
13
14
15
IO
IO
P1[4]
P1[6]
XRES
Optional External Clock Input (EXTCLK).
Input
Active high external reset with internal pull
down.
16
17
18
19
20
IO
IO
IO
IO
I
I
I
I
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Analog column mux input.
Analog column mux input.
Analog column mux input.
Analog column mux input.
Supply voltage.
Power
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset).
See the PSoC Mixed-Signal Array Technical Reference Manual for details.
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CY8C24x23A Automotive Data Sheet
1. Pin Information
1.1.2
28-Pin Part Pinout
Table 1-2. 28-Pin Part Pinout (SSOP)
Type
CY8C24423A 28-Pin PSoC Device
Pin
No.
Pin
Name
Description
Digital Analog
1
IO
IO
IO
IO
IO
IO
IO
IO
I
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
Vss
Analog column mux input.
A, I,P0[7]
A,IO, P0[5]
A,IO, P0[3]
A,I, P0[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Vdd
P0[6], A, I
P0[4], A, I
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
IO
IO
I
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
3
P0[2], A, I
P0[0], A, I
P2[6],Ex ternalVRef
P2[4],Ex ternalAGND
P2[2], A, I
4
P2[7]
P2[5]
5
6
A,I, P2[3]
A, I,P2[1]
7
I
I
Direct switched capacitor block input.
Direct switched capacitor block input.
Ground connection.
SSOP
8
Vss
P2[0], A, I
XRES
P1[6]
9
Power
Power
Input
I2CSCL,P1[7]
I2CSDA,P1[5]
P1[3]
10
11
12
13
IO
IO
IO
IO
P1[7]
P1[5]
P1[3]
P1[1]
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
P1[4],EXTCLK
P1[2]
P1[0],XTALout,I2CSDA
I2CSCL,XTALin,P1[1]
Vss
Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*.
14
15
Vss
Ground connection.
IO
P1[0]
Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA*.
16
17
18
19
IO
IO
IO
P1[2]
P1[4]
P1[6]
XRES
Optional External Clock Input (EXTCLK).
Active high external reset with internal pull
down.
20
21
22
23
24
25
26
27
28
IO
IO
IO
IO
IO
IO
IO
IO
I
I
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND).
External Voltage Reference (VRef).
Analog column mux input.
I
I
I
I
Analog column mux input.
Analog column mux input.
Analog column mux input.
Power
Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset).
See the PSoC Mixed-Signal Array Technical Reference Manual for details.
October 9, 2006
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2. Register Reference
This chapter lists the registers of the CY8C24x23A automotive PSoC device. For detailed register information, reference the PSoC
Mixed-Signal Array Technical Reference Manual.
2.1
Register Conventions
2.2
Register Mapping Tables
The PSoC device has a total register address space of 512
bytes. The register space is referred to as IO space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI
bit is set the user is in Bank 1.
2.1.1
Abbreviations Used
The register conventions specific to this section are listed in the
following table.
Note In the following register mapping tables, blank fields are
Reserved and should not be accessed.
Convention
Description
Read register or bit(s)
R
W
L
Write register or bit(s)
Logical register or bit(s)
Clearable register or bit(s)
Access is bit specific
C
#
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CY8C24x23A Automotive Data Sheet
2. Register Reference
Register Map Bank 0 Table: User Space
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
RW
RW
RW
RW
RW
RW
RW
RW
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
RW
RW
RW
RW
RW
RW
RW
RW
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
RW
#
RW
#
RW
RW
INT_CLR3
INT_MSK3
RW
RW
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
DCB03DR2
DCB03CR0
#
AMX_IN
RW
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL_X
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
W
RW
#
ARF_CR
CMP_CR0
ASY_CR
CMP_CR1
RW
#
#
#
W
RW
#
RW
#
W
RW
#
MUL_Y
MUL_DH
MUL_DL
ACC_DR1
ACC_DR0
ACC_DR3
ACC_DR2
#
W
RW
#
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
RW
RW
RW
RW
RW
RW
RW
CPU_F
RL
CPU_SCR1
CPU_SCR0
#
#
Blank fields are Reserved and should not be accessed.
# Access is bit specific.
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CY8C24x23A Automotive Data Sheet
2. Register Reference
Register Map Bank 1 Table: Configuration Space
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
RW
RW
RW
RW
RW
RW
RW
RW
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
RW
RW
RW
RW
RW
RW
RW
RW
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
RW
RW
RW
RW
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
OSC_GO_EN DD
RW
RW
RW
RW
RW
RW
RW
R
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
DBB00FN
DBB00IN
DBB00OU
RW
RW
RW
CLK_CR0
CLK_CR1
ABF_CR0
AMD_CR0
RW
RW
RW
RW
DBB01FN
DBB01IN
DBB01OU
RW
RW
RW
VLT_CMP
AMD_CR1
ALT_CR0
RW
RW
DCB02FN
DCB02IN
DCB02OU
RW
RW
RW
IMO_TR
ILO_TR
BDG_TR
ECO_TR
W
W
RW
W
DCB03FN
DCB03IN
DCB03OU
RW
RW
RW
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
RW
RW
RW
RW
RW
RW
RW
CPU_F
RL
CPU_SCR1
CPU_SCR0
#
#
Blank fields are Reserved and should not be accessed.
# Access is bit specific.
October 9, 2006
Document No. 38-12029 Rev. *C
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3. Electrical Specifications
This chapter presents the DC and AC electrical specifications of the CY8C24x23A automotive PSoC device. For the most up to date
electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.
Specifications are valid for -40oC ≤ T ≤ 125oC and T ≤ 135oC, except where noted.
A
J
5.25
4.75
Valid
Operating
Region
3.00
93 kHz
12 MHz
24 MHz
CPUFrequency
Figure 3-1. Voltage versus CPU Frequency
The following table lists the units of measure that are used in this chapter.
Table 3-1: Units of Measure
Symbol
Unit of Measure
Symbol
Unit of Measure
o
degree Celsius
µW
microwatts
C
dB
fF
decibels
mA
ms
mV
nA
ns
milli-ampere
milli-second
milli-volts
femto farad
hertz
Hz
KB
1024 bytes
1024 bits
kilohertz
nanoampere
nanosecond
nanovolts
Kbit
kHz
kΩ
nV
Ω
kilohm
ohm
MHz
MΩ
µA
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microvolts
pA
pF
pp
ppm
ps
picoampere
picofarad
peak-to-peak
parts per million
picosecond
µF
µH
µs
sps
σ
samples per second
sigma: one standard deviation
volts
µV
µVrms
microvolts root-mean-square
V
October 9, 2006
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CY8C24x23A Automotive Data Sheet
3. Electrical Specifications
3.1
Absolute Maximum Ratings
Table 3-2. Absolute Maximum Ratings
Symbol
Description
Min
-55
Typ
+25
Max
+125
Units
Notes
o
o
T
Storage Temperature
Higher storage temperatures will reduce data
retention time. Recommended storage temper-
ature is +25°C ± 25°C. Storage temperatures
STG
C
o
above 65 C will degrade reliability. Maximum
combined storage and operational time at
+125°C is 7000 hours.
T
Ambient Temperature with Power Applied
-40
–
+125
A
C
Vdd
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
-0.5
–
–
+5.75
V
V
V
Vss - 0.5
Vdd + 0.5
IO
V
DC Voltage Applied to Tri-state
Vss - 0.5
-25
–
–
Vdd + 0.5
+25
V
IOZ
MIO
I
Maximum Current into any Port Pin
mA
ESD
LU
Electro Static Discharge Voltage
Latch-up Current
2000
–
–
–
–
V
Human Body Model ESD.
200
mA
3.2
Operating Temperature
Table 3-3. Operating Temperature
Symbol
Description
Min
Typ
Max
Units
Notes
o
T
Ambient Temperature
Junction Temperature
-40
–
–
+125
A
C
C
o
T
-40
+135
The temperature rise from ambient to junction is
package specific. See “Thermal Impedances”
on page 30. The user must limit the power con-
sumption to comply with this requirement.
J
October 9, 2006
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CY8C24x23A Automotive Data Sheet
3. Electrical Specifications
3.3
DC Electrical Characteristics
3.3.1
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 3-4. DC Chip-Level Specifications
Symbol
Description
Min
4.75
Typ
Max
5.25
Units
Notes
Vdd
Supply Voltage
Supply Current
–
5
V
o
I
–
8
mA
DD
Conditions are Vdd = 5.25V, -40 C ≤ T ≤ 125
A
o
C, CPU = 3 MHz, SYSCLK doubler disabled,
VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75
kHz, analog power = off.
I
Sleep (Mode) Current with POR, LVD, Sleep Timer, and
–
–
–
4
4
6
13
µA
µA
µA
Conditions are with internal slow speed oscilla-
SB
a
o
o
WDT.
tor, Vdd = 5.25V, -40 C ≤ T ≤ 55 C. Analog
A
power = off.
I
Sleep (Mode) Current with POR, LVD, Sleep Timer, and
100
15
Conditions are with internal slow speed oscilla-
SBH
a
o
o
WDT at high temperature.
tor, Vdd = 5.25V, 55 C < T ≤ 125 C. Analog
A
power = off.
I
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
Conditions are with properly loaded, 1 µW max,
SBXTL
a
o
and external crystal.
32.768 kHz crystal. Vdd = 5.25V, -40 C ≤ T
≤
A
o
55 C. Analog power = off.
I
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
–
6
100
µA
Conditions are with properly loaded, 1µW max,
SBXTLH
a
o
and external crystal at high temperature.
32.768 kHz crystal. Vdd = 5.25V, 55 C < T
≤
A
o
125 C. Analog power = off.
V
Reference Voltage (Bandgap)
1.25
1.3
1.35
V
Trimmed for appropriate Vdd.
REF
a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar functions
enabled.
3.3.2
DC General Purpose IO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance.
Table 3-5. DC GPIO Specifications
Symbol
Description
Min
Typ
5.6
Max
Units
kΩ
Notes
R
Pull up Resistor
4
4
8
8
–
PU
PD
OH
R
Pull down Resistor
High Output Level
5.6
–
kΩ
V
3.5
V
IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads,
4 on even port pins (for example, P0[2], P1[4]),
4 on odd port pins (for example, P0[3], P1[5])).
V
Low Output Level
–
–
0.75
0.8
V
IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads,
4 on even port pins (for example, P0[2], P1[4]),
4 on odd port pins (for example, P0[3], P1[5])).
Total IOL budget of 150 mA.
OL
V
V
V
I
Input Low Level
Input High Level
Input Hysterisis
–
–
V
Vdd = 4.75 to 5.25
Vdd = 4.75 to 5.25
IL
IH
H
2.2
–
–
V
60
1
–
mV
nA
pF
pF
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
Capacitive Load on Pins as Output
–
–
Gross tested to 1 µA.
IL
o
C
C
–
3.5
3.5
10
10
IN
Package and pin dependent. Temp = 25 C.
o
–
OUT
Package and pin dependent. Temp = 25 C.
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CY8C24x23A Automotive Data Sheet
3. Electrical Specifications
3.3.3
DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.
Table 3-6. DC Operational Amplifier Specifications
Symbol
Description
Min
Typ
1.6
Max
Units
mV
Notes
V
Input Offset Voltage (absolute value) Low Power
Input Offset Voltage (absolute value) Mid Power
Input Offset Voltage (absolute value) High Power
Input Offset Voltage Drift
–
–
–
–
11
9
OSOA
1.3
1.2
7.0
mV
mV
9
o
TCV
I
35.0
–
OSOA
µV/ C
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
Common Mode Voltage Range
–
–
200
4.5
pA
Gross tested to 1 µA.
EBOA
o
C
10
pF
V
INOA
Package and pin dependent. Temp = 25 C.
V
0.0
0.5
–
–
Vdd
The common-mode input voltage range is mea-
sured through an analog output buffer. The
specification includes the limitations imposed
by the characteristics of the analog output
buffer.
CMOA
Common Mode Voltage Range (high power or high
opamp bias)
Vdd - 0.5
G
Open Loop Gain
Specification is applicable at high power. For all
other bias modes (except high power, high
opamp bias), minimum is 60 dB.
OLOA
OHIGHOA
OLOWOA
SOA
Power = Low
–
–
–
80
80
80
dB
dB
dB
Power = Medium
Power = High
V
V
High Output Voltage Swing (worst case internal load)
Power = Low
Vdd - 0.2
Vdd - 0.2
Vdd - 0.5
–
–
–
–
–
–
V
V
V
Power = Medium
Power = High
Low Output Voltage Swing (worst case internal load)
Power = Low
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
Power = Medium
Power = High
I
Supply Current (including associated AGND buffer)
Power = Low
–
–
–
–
–
–
–
150
300
600
1200
2400
4600
80
200
400
800
1600
3200
6400
–
µA
µA
µA
µA
µA
µA
dB
Power = Low, Opamp Bias = High
Power = Medium
Power = Medium, Opamp Bias = High
Power = High
Power = High, Opamp Bias = High
Supply Voltage Rejection Ratio
PSRR
Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤ VIN
≤ Vdd.
OA
3.3.4
DC Low Power Comparator Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 3-7. DC Low Power Comparator Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
V
I
Low power comparator (LPC) reference voltage range
0.2
–
–
Vdd - 1
V
REFLPC
LPC supply current
LPC voltage offset
10
40
30
µA
SLPC
V
–
2.5
mV
OSLPC
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CY8C24x23A Automotive Data Sheet
3. Electrical Specifications
3.3.5
DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 3-8. DC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
mV
Notes
V
Input Offset Voltage (Absolute Value)
–
3
18
–
OSOB
TCV
Input Offset Voltage Drift
–
+6
–
µV/°C
OSOB
CMOB
V
Common-Mode Input Voltage Range
Output Resistance
0.5
–
Vdd - 1.0
V
Ω
V
R
1
–
–
OUTOB
V
V
High Output Voltage Swing (Load = 32 ohms to Vdd/2)
0.5 x Vdd + 1.1
–
–
OHIGHOB
OLOWOB
SOB
Low Output Voltage Swing (Load = 32 ohms to Vdd/2)
–
0.5 x Vdd - 1.3
V
I
Supply Current Including Bias Cell (No Load)
Power = Low
–
–
–
1.1
2.6
64
5.1
8.8
–
mA
mA
dB
Power = High
PSRR
Supply Voltage Rejection Ratio
OB
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CY8C24x23A Automotive Data Sheet
3. Electrical Specifications
3.3.6
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Table 3-9. DC Analog Reference Specifications
Symbol
Description
Bandgap Voltage Reference
Min
Typ
Max
Units
BG
–
1.25
1.30
1.35
V
V
a
AGND = Vdd/2
Vdd/2 - 0.02
2.4
Vdd/2
Vdd/2 + 0.02
2.8
CT Block Power = High
a
–
–
–
–
–
–
AGND = 2 x BandGap
2.6
V
V
V
V
V
CT Block Power = High
a
AGND = P2[4] (P2[4] = Vdd/2)
CT Block Power = High
P2[4] - 0.02
1.23
P2[4]
1.30
2.08
0.000
P2[4] + 0.02
1.37
a
AGND = BandGap
CT Block Power = High
a
AGND = 1.6 x BandGap
1.98
2.14
CT Block Power = High
a
AGND Column to Column Variation (AGND = Vdd/2)
CT Block Power = High
-0.035
0.035
RefHi = Vdd/2 + BandGap
Ref Control Power = High
V
V
V
V
V
V
V
Vdd/2 + 1.15
3.65
Vdd/2 +1.30
3.9
Vdd/2 +1.45
4.15
–
–
–
–
–
–
–
–
–
–
RefHi = 3 x BandGap
Ref Control Power = High
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)
Ref Control Power = High
P2[6] + 2.4
P2[4] + 1.24
P2[4] + P2[6] - 0.1
3.9
P2[6] + 2.6
P2[4] +1.30
P2[4] + P2[6]
4.16
P2[6] + 2.8
P2[4] + 1.36
P2[4] + P2[6] + 0.1
4.42
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
Ref Control Power = High
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
Ref Control Power = High
RefHi = 3.2 x BandGap
Ref Control Power = High
RefLo = Vdd/2 – BandGap
Ref Control Power = High
Vdd/2 - 1.45
1.15
Vdd/2 - 1.3
1.3
1.15
RefLo = BandGap
Ref Control Power = High
1.45
V
V
V
V
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
Ref Control Power = High
2.4 - P2[6]
P2[4] - 1.45
P2[4] - P2[6] - 0.1
2.6 - P2[6]
1.3
2.8 - P2[6]
P2[4] - 1.15
P2[4] - P2[6] + 0.1
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
Ref Control Power = High
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
Ref Control Power = High
P2[4] - P2[6]
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.05V.
October 9, 2006
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CY8C24x23A Automotive Data Sheet
3. Electrical Specifications
3.3.7
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 3-10. DC Analog PSoC Block Specifications
Symbol
Description
Min
Typ
12.24
80
Max
Units
kΩ
fF
Notes
R
C
Resistor Unit Value (Continuous Time)
–
–
–
–
CT
SC
Capacitor Unit Value (Switch Cap)
3.3.8
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Mixed-Signal Array Technical
Reference Manual for more information on the VLT_CR register.
Table 3-11. DC POR and LVD Specifications
Symbol
PPOR2R
PPOR2
PH2
Description
Vdd Value for PPOR Trip (positive ramp)
PORLEV[1:0] = 10b
Min
Typ
Max
Units
Notes
V
V
V
4.55
4.70
V
V
Vdd Value for PPOR Trip (negative ramp)
PORLEV[1:0] = 10b
4.55
0
PPOR Hysteresis
PORLEV[1:0] = 10b
–
–
mV
Vdd Value for LVD Trip
VM[2:0] = 110b
V
V
4.62
4.73
4.83
V
V
LVD6
VM[2:0] = 111b
4.710
4.814
4.950
LVD7
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CY8C24x23A Automotive Data Sheet
3. Electrical Specifications
3.3.9
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 3-12. DC Programming Specifications
Symbol
Vdd
Description
Min
4.75
Typ
Max
Units
Notes
Supply Voltage for Flash Write Operations
–
–
V
IWRITE
I
Supply Current During Programming or Verify
Input Low Voltage During Programming or Verify
Input High Voltage During Programming or Verify
–
10
–
25
0.8
–
mA
V
DDP
V
V
–
ILP
2.2
–
–
V
IHP
I
Input Current when Applying Vilp to P1[0] or P1[1] During
Programming or Verify
–
0.2
mA
Driving internal pull-down resistor.
Driving internal pull-down resistor.
ILP
I
Input Current when Applying Vihp to P1[0] or P1[1] During
Programming or Verify
–
–
1.5
mA
IHP
V
V
Output Low Voltage During Programming or Verify
Output High Voltage During Programming or Verify
–
–
–
–
–
–
Vss + 0.75
V
OLV
3.5
100
6,400
15
Vdd
–
V
OHV
a
Flash
Flash
Flash
–
Erase/write cycles per block.
Erase/write cycles.
ENPB
ENT
DR
Flash Endurance (per block)
a,b
–
–
Flash Endurance (total)
c
–
Years
Flash Data Retention
a. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer
to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
b. A maximum of 64 x 100 block endurance cycles is allowed.
c. Flash data retention based on the use condition of ≤ 7000 hours at TA ≤ 125°C and the remaining time at TA ≤ 65°C.
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CY8C24x23A Automotive Data Sheet
3. Electrical Specifications
3.4
AC Electrical Characteristics
3.4.1
AC Chip-Level Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 3-13. AC Chip-Level Specifications
Symbol
IMO24
CPU1
48M
Description
Min
22.95
Typ
Max
24.96
Units
MHz
Notes
F
F
F
F
F
F
Internal Main Oscillator Frequency for 24 MHz
24
12
–
Trimmed. Utilizing factory trim values.
CPU Frequency (5V Nominal)
Digital PSoC Block Frequency
Digital PSoC Block Frequency
Internal Low Speed Oscillator Frequency
External Crystal Oscillator
0.09
–
12.48
–
MHz
MHz
MHz
kHz
Not allowed.
a
0
24
32
24M
24.96
15
–
64
32K1
32.768
–
kHz
Accuracy is capacitor and crystal dependent.
50% duty cycle.
32K2
F
PLL Frequency
–
23.986
–
MHz
Is a multiple (x732) of crystal frequency.
PLL
Jitter24M2
24 MHz Period Jitter (PLL)
PLL Lock Time
–
–
–
800
10
ps
T
0.5
ms
PLLSLEW
T
PLL Lock Time for Low Gain Setting
0.5
–
50
ms
PLLSLEWS-
LOW
T
T
External Crystal Oscillator Startup to 1%
–
–
1700
2800
ms
ms
OS
2620
3800
External Crystal Oscillator Startup to 100 ppm
OSACC
Jitter32k
32 kHz Period Jitter
–
100
–
ns
T
External Reset Pulse Width
10
–
µs
XRST
DC24M
24 MHz Duty Cycle
40
–
50
50
300
–
60
–
%
Step24M
24 MHz Trim Step Size
kHz
ps
Jitter24M1P 24 MHz Period Jitter (IMO) Peak-to-Peak
–
Jitter24M1R 24 MHz Period Jitter (IMO) Root Mean Squared
–
600
ps
F
Maximum frequency of signal on row input or row output.
Supply Ramp Time
–
–
12.48
MHz
MAX
T
0
–
–
µs
RAMP
a. See the individual user module data sheets for information on maximum frequencies for user modules.
PLL
Enable
T
24 MHz
PLLSLEW
FPLL
PLL
Gain
0
Figure 3-2. PLL Lock Timing Diagram
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3. Electrical Specifications
PLL
Enable
T
24 MHz
PLLSLEWLOW
FPLL
PLL
Gain
1
Figure 3-3. PLL Lock for Low Gain Setting Timing Diagram
32K
Select
32 kHz
T
OS
F32K2
Figure 3-4. External Crystal Oscillator Startup Timing Diagram
Jitter24M1
F24M
Figure 3-5. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter32k
F32K2
Figure 3-6. 32 kHz Period Jitter (ECO) Timing Diagram
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CY8C24x23A Automotive Data Sheet
3. Electrical Specifications
3.4.2
AC General Purpose IO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 3-14. AC GPIO Specifications
Symbol
Description
GPIO Operating Frequency
Min
Typ
Max
12.48
Units
MHz
Notes
Normal Strong Mode
F
0
–
GPIO
TRiseF
TFallF
TRiseS
TFallS
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
2
2
9
9
–
22
22
–
ns
ns
ns
ns
Vdd = 4.75 to 5.25V, 10% - 90%
Vdd = 4.75 to 5.25V, 10% - 90%
Vdd = 4.75 to 5.25V, 10% - 90%
Vdd = 4.75 to 5.25V, 10% - 90%
–
27
22
–
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
Figure 3-7. GPIO Timing Diagram
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CY8C24x23A Automotive Data Sheet
3. Electrical Specifications
3.4.3
AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Note Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Table 3-15. AC Operational Amplifier Specifications
Symbol
SR
Description
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low
Min
Typ
Max
Units
Notes
ROA
0.15
–
V/µs
Power = Low, Opamp Bias = High
Power = Medium
0.15
0.15
1.7
V/µs
V/µs
V/µs
V/µs
V/µs
Power = Medium, Opamp Bias = High
Power = High
–
–
–
1.7
Power = High, Opamp Bias = High
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low
6.5
SR
FOA
0.01
0.01
0.01
0.5
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
Power = Low, Opamp Bias = High
Power = Medium
Power = Medium, Opamp Bias = High
Power = High
–
–
–
0.5
Power = High, Opamp Bias = High
Gain Bandwidth Product
4.0
BW
OA
Power = Low
0.75
0.75
0.75
3.1
MHz
MHz
MHz
MHz
MHz
MHz
Power = Low, Opamp Bias = High
Power = Medium
Power = Medium, Opamp Bias = High
Power = High
–
–
3.1
Power = High, Opamp Bias = High
5.4
3.4.4
AC Low Power Comparator Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 3-16. AC Low Power Comparator Specifications
Symbol
Description
Min
Typ
Max
Units
µs
Notes
T
LPC response time
–
–
50
≥ 50 mV overdrive comparator reference set
RLPC
within V
.
REFLPC
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CY8C24x23A Automotive Data Sheet
3. Electrical Specifications
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
dBV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
Figure 3-8. Typical AGND Noise with P2[4] Bypass
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequen-
cies, increased power level reduces the noise spectrum level.
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
0.01
0.1
1
10
100
Freq (kHz)
Figure 3-9. Typical Opamp Noise
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CY8C24x23A Automotive Data Sheet
3. Electrical Specifications
3.4.5
AC Digital Block Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 3-17. AC Digital Block Specifications
Function
All Functions
Timer
Description
Maximum Block Clocking Frequency
Capture Pulse Width
Min
Typ
Max
24.96
Units
MHz
Notes
a
–
–
ns
50
–
Maximum Frequency, No Capture
Maximum Frequency, With Capture
Enable Pulse Width
–
–
–
24.96
24.96
–
MHz
MHz
ns
4.75V < Vdd < 5.25V.
–
a
Counter
50
–
Maximum Frequency, No Enable Input
Maximum Frequency, Enable Input
Kill Pulse Width:
–
–
24.96
24.96
MHz
MHz
4.75V < Vdd < 5.25V.
–
Dead Band
Asynchronous Restart Mode
Synchronous Restart Mode
20
50
–
–
–
–
ns
ns
a
a
Disable Mode
–
–
ns
50
–
Maximum Frequency
–
–
24.96
24.96
MHz
MHz
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
CRCPRS
Maximum Input Clock Frequency
–
(PRS Mode)
CRCPRS
(CRC Mode)
Maximum Input Clock Frequency
Maximum Input Clock Frequency
–
–
–
–
–
24.96
4.1
MHz
MHz
SPIM
Maximum data rate at 4.1 MHz due to 2 x over
clocking.
SPIS
Maximum Input Clock Frequency
–
–
2.05
–
MHz
ns
a
Width of SS_ Negated Between Transmissions
50
–
Transmitter
Receiver
Maximum Input Clock Frequency
–
8.2
MHz
Maximum data rate at 3.08 MHz due to 8 x over
clocking.
Maximum Input Clock Frequency
–
16
24.96
MHz
Maximum data rate at 3.08 MHz due to 8 x over
clocking.
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
October 9, 2006
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CY8C24x23A Automotive Data Sheet
3. Electrical Specifications
3.4.6
AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 3-18. AC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
T
Rising Settling Time to 0.1%, 1V Step, 100pF Load
ROB
Power = Low
–
–
–
–
3
3
µs
Power = High
µs
T
Falling Settling Time to 0.1%, 1V Step, 100pF Load
SOB
Power = Low
–
–
–
–
3
3
µs
µs
Power = High
SR
SR
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
ROB
FOB
Power = Low
0.6
0.6
–
–
–
–
V/µs
V/µs
Power = High
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Power = Low
Power = High
0.6
0.6
–
–
–
–
V/µs
V/µs
BW
BW
Small Signal Bandwidth, 20mV , 3dB BW, 100pF Load
pp
OB
OB
0.8
0.8
–
–
–
–
MHz
MHz
Power = Low
Power = High
Large Signal Bandwidth, 1V , 3dB BW, 100pF Load
pp
300
300
–
–
–
–
kHz
kHz
Power = Low
Power = High
3.4.7
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 3-19. AC External Clock Specifications
Symbol
Description
Min
Typ
Max
24.24
Units
MHz
Notes
F
Frequency
0
–
OSCEXT
–
–
–
High Period
Low Period
20.6
20.6
150
–
–
–
–
–
–
ns
ns
µs
Power Up IMO to Switch
3.4.8
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 3-20. AC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
ns
Notes
T
Rise Time of SCLK
Fall Time of SCLK
1
–
20
20
–
RSCLK
FSCLK
SSCLK
HSCLK
SCLK
T
T
T
F
T
T
T
1
–
ns
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
40
40
0
–
ns
–
–
ns
–
8
MHz
ms
ms
ns
Flash Erase Time (Block)
–
15
30
–
–
ERASEB
WRITE
DSCLK
Flash Block Write Time
–
–
Data Out Delay from Falling Edge of SCLK
–
45
October 9, 2006
Document No. 38-12029 Rev. *C
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CY8C24x23A Automotive Data Sheet
3. Electrical Specifications
2
3.4.9
AC I C Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 3-21. AC Characteristics of the I2C SDA and SCL Pins
Standard Mode
Min Max
100
Fast Mode
Min Max
Symbol
SCLI2C
Description
SCL Clock Frequency
Units
kHz
Notes
F
T
0
0
400
–
Hold Time (repeated) START Condition. After this
period, the first clock pulse is generated.
4.0
–
0.6
µs
HDSTAI2C
T
T
T
T
T
T
T
T
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Set-up Time for a Repeated START Condition
Data Hold Time
4.7
4.0
4.7
0
–
–
–
–
–
–
–
–
1.3
0.6
0.6
0
–
µs
µs
µs
µs
ns
µs
µs
ns
LOWI2C
–
HIGHI2C
SUSTAI2C
HDDATI2C
SUDATI2C
SUSTOI2C
BUFI2C
–
–
a
Data Set-up Time
250
4.0
–
100
0.6
Set-up Time for STOP Condition
–
Bus Free Time Between a STOP and START Condition 4.7
1.3
0
–
Pulse Width of spikes are suppressed by the input fil-
ter.
–
50
SPI2C
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
SDA
TSPI2C
T
LOWI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
SCL
TSUSTOI2C
TSUSTAI2C
THDDATI2C
THDSTAI2C
THIGHI2C
S
Sr
P
S
Figure 3-10. Definition for Timing for Fast/Standard Mode on the I2C Bus
October 9, 2006
Document No. 38-12029 Rev. *C
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4. Packaging Information
This chapter illustrates the packaging specifications for the CY8C24x23A automotive PSoC device, along with the thermal imped-
ances for each package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
4.1
Packaging Dimensions
51-85077 *C
Figure 4-1. 20-Lead (210-Mil) SSOP
October 9, 2006
Document No. 38-12029 Rev. *C
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CY8C24x23A Automotive Data Sheet
4. Packaging Information
51-85079 *C
Figure 4-2. 28-Lead (210-Mil) SSOP
4.2
Thermal Impedances
Table 4-1. Thermal Impedances per Package
Package
Typical θJA
*
o
20 SSOP
28 SSOP
117 C/W
o
101 C/W
* T = T + POWER x θJA
J
A
4.3
Capacitance on Crystal Pins
Table 4-2: Typical Package Capacitance on Crystal Pins
Package
20 SSOP
28 SSOP
Package Capacitance
2.6 pF
2.8 pF
October 9, 2006
Document No. 38-12029 Rev. *C
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CY8C24x23A Automotive Data Sheet
4. Packaging Information
4.4
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 4-3. Solder Reflow Peak Temperature
Package
Minimum Peak Temperature*
Maximum Peak Temperature
o
o
20 SSOP
240 C
260 C
o
o
28 SSOP
240 C
260 C
o
*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 C
o
with Sn-Pb or 245 ± 5 C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
October 9, 2006
Document No. 38-12029 Rev. *C
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5. Ordering Information
The following table lists the CY8C24x23A automotive PSoC device group’s key package features and ordering codes.
Table 5-1. CY8C24x23A Automotive PSoC Key Features and Ordering Information
20 Pin (210 Mil) SSOP
CY8C24223A-12PVXE
CY8C24223A-12PVXET
CY8C24423A-12PVXE
CY8C24423A-12PVXET
4K
4K
4K
4K
256
256
256
256
No
No
No
No
-40C to +125C
-40C to +125C
-40C to +125C
-40C to +125C
4
4
4
4
6
6
6
6
16
16
24
24
8
8
2
2
2
2
Yes
Yes
Yes
Yes
20 Pin (210 Mil) SSOP
(Tape and Reel)
28 Pin (210 Mil) SSOP
10
10
28 Pin (210 Mil) SSOP
(Tape and Reel)
5.1
Ordering Code Definitions
CY 8 C 24 xxx-12xx
Package Type:
Thermal Rating:
C = Commercial
I = Industrial
PX = PDIP Pb-Free
SX = SOIC Pb-Free
PVX = SSOP Pb-Free
LFX = QFN Pb-Free
LKX = QFN Pb-Free
AX = TQFP Pb-Free
E = Extended
Speed: 12 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
October 9, 2006
Document No. 38-12029 Rev. *C
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6. Sales and Company Information
To obtain information about Cypress Semiconductor or PSoC sales and technical support, reference the following information.
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134
408.943.2600
Web Links:
Company Information – http://www.cypress.com
Sales – http://www.cypress.com/aboutus/sales_locations.cfm
Technical Support – http://www.cypress.com/support/login.cfm
6.1
Revision History
Table 6-1. CY8C24x23A Automotive Data Sheet Revision History
Document Title:
Document Number: 38-12029
Revision ECN # Issue Date Origin of Change
** 238268
CY8C24223A and CY8C24423A Automotive PSoC Mixed-Signal Array Final Data Sheet
Description of Change
See ECN
See ECN
See ECN
See ECN
SFV
HMT
HMT
HMT
First release of CY8C24x23A Automotive Preliminary Data Sheet.
*A
*B
*C
271471
286089
512475
Update per SFV memo. Input MWR changes, including removing SMP. Change to Final.
Update characterization data. Fine tune pinouts. Add Reflow Peak Temp. table.
Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add ISSP note to pinout tables.
Update typical and recommended Storage Temperature per extended temp. specs. Update CY brand-
ing and QFN convention. Update copyright and trademarks.
Distribution: External/Public
Posting: None
6.2
Copyrights and Flash Code Protection
Copyrights
© Cypress Semiconductor Corp. 2004-2006. All rights reserved. PSoC Designer™, Programmable System-on-Chip™, and PSoC Express are trademarks and PSoC® is
a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations.
The information contained herein is subject to change without notice. Cypress Semiconductor assumes no responsibility for the use of any circuitry other than circuitry
embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products
for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of
Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress
Semiconductor against all charges. Cypress Semiconductor products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety
applications, unless pursuant to an express written agreement with Cypress Semiconductor.
Flash Code Protection
Note the following details of the Flash code protection features on Cypress Semiconductor PSoC devices.
Cypress Semiconductor products meet the specifications contained in their particular data sheets. Cypress Semiconductor believes that its family of products is one of the
most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress Semiconductor, that can breach the
code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress Semiconductor nor any other semiconductor
manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
Cypress Semiconductor is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress
Semiconductor are committed to continuously improving the code protection features of our products.
October 9, 2006
© Cypress Semiconductor Corp. 2004-2006 — Document No. 38-12029 Rev. *C
33
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