CYD04S18V-133BBI [CYPRESS]
FLEx18⑩ 3.3V 64K/128K/256K/512K x 18 Synchronous Dual-Port RAM; FLEx18 ™ 3.3V 64K / 128K / 256K / 512K ×18同步双端口RAM
| 型号： | CYD04S18V-133BBI |
| 厂家： | 
CYPRESS |
| 描述： | FLEx18⑩ 3.3V 64K/128K/256K/512K x 18 Synchronous Dual-Port RAM |
| 文件： | 总26页 (文件大小：587K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
FLEx18™ 3.3V 64K/128K/256K/512K x 18
Synchronous Dual-Port RAM
Functional Description
Features
• True dual-ported memory cells that allow simultaneous
access of the same memory location
The FLEx18™ family includes 1-Mbit, 2-Mbit, 4-Mbit and
9-Mbit pipelined, synchronous, true dual-port static RAMs that
are high-speed, low-power 3.3V CMOS. Two ports are
provided, permitting independent, simultaneous access to any
location in memory. The result of writing to the same location
by more than one port at the same time is undefined. Registers
on control, address, and data lines allow for minimal set-up
and hold time.
• Synchronous pipelined operation
• Organization of 1 Mbit, 2 Mbits, 4 Mbits and 9 Mbits
devices
• Pipelined output mode allows fast operation
• 0.18-micron CMOS for optimum speed and power
• High-speed clock to data access
During a Read operation, data is registered for decreased
cycle time. Each port contains a burst counter on the input
address register. After externally loading the counter with the
initial address, the counter will increment the address inter-
nally (more details to follow). The internal Write pulse width is
independent of the duration of the R/W input signal. The
internal Write pulse is self-timed to allow the shortest possible
cycle times.
• 3.3V low power
— Active as low as 225 mA (typ)
— Standby as low as 55 mA (typ)
• Mailbox function for message passing
• Global master reset
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
• Separate byte enables on both ports
• Commercial and industrial temperature ranges
• IEEE 1149.1-compatible JTAG boundary scan
• 256-ball FBGA (1 mm pitch)
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
• Counter wrap-around control
— Internal mask register controls counter wrap-around
— Counter-interrupt flags to indicate wrap-around
— Memory block retransmit operation
• Counter readback on address lines
• Mask register readback on address lines
The CYD09S18V device in this family has limited features.
Please see Address Counter and Mask Register Operations
on page 5 for details.
• Dual Chip Enables on both ports for easy depth
expansion
Seamless Migration to Next Generation Dual Port Family
• Seamless migration to next-generation dual-port family
Cypress offers a migration path for all devices in this family to
the next-generation devices in the Dual-Port family with a
compatible footprint. Please contact Cypress Sales for more
details.
Table 1. Product Selection Guide
1 Mbit
2 Mbit
4 Mbit
9 Mbit
Density
(64K x 18)
CYD01S18V
167
(128K x 18)
(256K x 18)
(512K x 18)
Part Number
CYD02S18V
167
CYD04S18V
167
CYD09S18V
133
Max. Speed (MHz)
Max. Access Time – Clock to Data (ns)
Typical operating current (mA)
Package
4.0
4.0
4.0
4.7
225
225
225
270
256FBGA
256FBGA
256FBGA
256FBGA
(17 mm x 17 mm) (17 mm x 17 mm) (17 mm x 17 mm) (17 mm x 17 mm)
Cypress Semiconductor Corporation
Document #: 38-06077 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised May 5, 2005
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Logic Block Diagram[1]
FTSEL
L
FTSEL
R
CONFIG Block
CONFIG Block
PORTSTD(1:0)
PORTSTD(1:0)
L
R
DQ (17:0)
R
DQ (17:0)
L
BE (1:0)
BE (1:0)
R
L
CE0
CE1
CE0
R
L
IO
Control
IO
Control
CE1
R
L
OE
OE
R
L
R/W
R/W
R
L
Dual Ported Array
Arbitration Logic
BUSY
BUSY
L
R
A (18:0)
A (18:0)
L
R
CNT/MSK
CNT/MSK
L
R
ADS
ADS
L
R
CNTEN
CNTEN
R
L
Address &
Counter Logic
Address &
Counter Logic
CNTRST
CNTRST
L
R
RET
RET
L
R
CNTINT
L
CNTINT
R
C
C
L
R
WRP
L
WRP
R
TRST
TMS
TDI
Mailboxes
INT
INT
R
L
JTAG
TDO
TCK
MRST
READY
LowSPD
RESET
LOGIC
READY
L
R
R
LowSPD
L
Note:
1. CYD01S18V has 16 address bits, CYD02S18V has 17 address bits, CY04S18V has 18 address bits and CYD09S18V has 19 address bits.
Document #: 38-06077 Rev. *C
Page 2 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Pin Configurations
256-ball BGA Top View
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
NC
NC
DQ17
DQ16
DQ13
DQ12
DQ9
DQ9
DQ12
DQ13
DQ16
DQ17
R
NC
NC
NC
A
B
C
D
E
F
L
L
L
L
L
L
L
R
R
R
R
NC
NC
NC
NC
NC
NC
DQ15
DQ14
DQ11
DQ10
DQ10
DQ11
R
DQ14
DQ15
NC
NC
NC
NC
A1
NC
NC
A0
L
L
R
R
R
NC
[2,5]
NC
[2,5]
NC
[2,5]
NC
[2,5]
REV
[2,4]
TRST
[2,5]
NC
[2,5]
RET
[2,3]
RET
L
L
R
INT
L
MRST
VTTL
INT
R
[2,3]
VREF
[2,4]
VREF
[2,4]
WRP
R
[2,3]
FTSELL
[2,3]
LowSPDL
[2,4]
LowSPDR
[2,4]
FTSELR
[2,3]
WRP
[2,3]
L
R
L
A0
L
A1
L
VSS
VTTL
VSS
R
R
CE0
[10]
CE1
[9]
CE1
[9]
CE0
[10]
L
L
R
R
A2
L
A3
L
VDDIO
VDDIO
L
VDDIO
VSS
VCORE VCORE VDDIO
VDDIO
R
VDDIO
A3
A5
A7
A9
A2
A4
A6
A8
L
L
R
R
R
R
R
R
R
R
R
R
CNTINTL
[11]
CNTINTR
[11]
A4
L
A5
L
NC
VDDIO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
VDDIO
NC
L
R
R
BUSY
R
[2,5]
BUSY
L
REV
L
A6
L
A7
L
NC
VSS
NC
G
H
J
[2,5]
[2,3]
A8
L
A9
L
C
L
VTTL
VCORE
VCORE
VSS
VCORE
VCORE
VTTL
C
R
PortSTD1L
[2,4]
PortSTD1R
[2,4]
A10
A11
VSS
VSS
VSS
A11
A10
A12
A14
L
L
R
R
A12
A14
A13
A15
OE
L
BE1
L
VDDIO
L
VSS
VDDIO
R
BE1
R
OE
R
A13
A15
K
L
L
L
R
R
ADS
[10]
BE0
ADS
[10]
L
R
R
BE0
L
VDDIO
L
VSS
VDDIO
R
L
L
R
R
REV
L
[2,4]
REV
R
[2,4]
A16
[6]
A17
[7]
A17
[7]
A16
[6]
L
L
R
R
RW
VDDIO
L
VDDIO
L
VDDIO
VCORE VCORE VDDIO
VDDIO
R
VDDIO
R
RW
R
M
N
P
R
L
L
R
CNT/
MSKL
[9]
REV
CNT/
MSKR
[9]
R
VREFL
[2,4]
VREFR
[2,4]
A18
[8]
A18
[8]
PortSTD0L
[2,4]
READYL
[2,5]
READYR
[2,5]
PortSTD0R
[2,4]
REV
L
L
R
NC
NC
NC
NC
VTTL
TMS
VTTL
TDO
NC
NC
NC
NC
[2,3]
[2,3]
NC
[2,5]
NC
[2,5]
NC
[2,5]
NC
[2,5]
CNTENL
[10]
CNTENR
[10]
CNTRSTL
[9]
CNTRSTR
[9]
NC
NC
NC
TCK
TDI
NC
NC
NC
NC
NC
NC
DQ6
L
DQ5
L
DQ2
L
DQ1
L
DQ1
R
DQ2
DQ5
R
DQ6
R
NC
NC
NC
R
DQ8
L
DQ7
L
DQ4
L
DQ3
L
DQ0
L
DQ0
R
DQ3
DQ4
R
DQ7
R
DQ8
R
T
R
Notes:
2. This ball will represent a next generation FLEx18-E Dual-Port feature. For more information about this feature, contact Cypress Sales.
3. Connect this ball to VDDIO. For more information about this next generation FLEx18-E Dual-Port feature contact Cypress Sales.
4. Connect this ball to VSS. For more information about this next generation FLEx18-E Dual-Port feature, contact Cypress Sales.
5. Leave this ball unconnected. For more information about this feature, contact Cypress Sales.
6. Leave this ball unconnected for a 64K x 18.
7. Leave this ball unconnected for a 128K x 18 and 64K x 18.
8. Leave this ball unconnected for a 256K x 18, 128K x 18 and 64K x 18.
9. These balls are not applicable for CYD09S18V device. They need to be tied to VDDIO.
10. These balls are not applicable for CYD09S18V device. They need to be tied to VSS.
11. These balls are not applicable for CYD09S18V device. They need to be no connected.
Document #: 38-06077 Rev. *C
Page 3 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Pin Definitions
Left Port
A0L–A18L
Right Port
A0R–A18R
Description
Address Inputs.
BE0L–BE1L
BE0R–BE1R
Byte Enable Inputs. Asserting these signals enables Read and Write operations to
the corresponding bytes of the memory array.
[2,5]
[2,5]
BUSYL
BUSYR
Port Busy Output. When the collision is detected, a BUSY is asserted.
Input Clock Signal.
CL
CR
[10]
[10]
CE0L
CE0R
Active Low Chip Enable Input.
[9]
[9]
CE1L
CE1R
Active High Chip Enable Input.
DQ0L–DQ17L
OEL
DQ0R–DQ17R
OER
Data Bus Input/Output.
Output Enable Input. This asynchronous signal must be asserted LOW to enable
the DQ data pins during Read operations.
INTL
INTR
Mailbox Interrupt Flag Output. The mailbox permits communications between ports.
The upper two memory locations can be used for message passing. INTL is asserted
LOW when the right port writes to the mailbox location of the left port, and vice versa.
An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox.
[2,4]
[2,4]
LowSPDL
LowSPDR
Port Low Speed Select Input. When operating at less than 100 MHz, the LowSPD
disables the port DLL.
[2,4]
[2,4]
PORTSTD[1:0]L
R/WL
PORTSTD[1:0]R
R/WR
Port Address/Control/Data I/O Standard Select Input.
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to read from the
dual-port memory array.
[2,5]
[2,5]
READYL
READYR
Port Ready Output. This signal will be asserted when a port is ready for normal
operation.
[9]
[9]
CNT/MSKL
CNT/MSKR
Port Counter/Mask Select Input. Counter control input.
Port Counter Address Load Strobe Input. Counter control input.
Port Counter Enable Input. Counter control input.
Port Counter Reset Input. Counter control input.
[10]
[10]
ADSL
ADSR
[10]
[10]
CNTENL
CNTENR
[9]
[9]
CNTRSTL
CNTRSTR
[11]
[11]
CNTINTL
CNTINTR
Port Counter Interrupt Output. This pin is asserted LOW when the unmasked
portion of the counter is incremented to all “1s”.
[2,3]
[2,3]
WRPL
WRPR
Port Counter Wrap Input. After the burst counter reaches the maximum count, if
WRP is low, the unmasked counter bits will be set to 0. If high, the counter will be
loaded with the value stored in the mirror register.
[2,3]
[2,3]
RETL
RETR
Port Counter Retransmit Input. Counter control input.
Flow-Through Mode Select Input.
[2,3]
[2,3]
FTSELL
FTSELR
[2,4]
[2,4]
VREFL
VREFR
Port External High-Speed IO Reference Input.
Port IO Power Supply.
VDDIOL
VDDIOR
REVL[2,4]
REVR[2,4]
Reserved pins for future features.
MRST
Master Reset Input. MRST is an asynchronous input signal and affects both ports.
A master reset operation is required at power-up.
TRST[2,5]
TMS
JTAG Reset Input.
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine.
State machine transitions occur on the rising edge of TCK.
TDI
JTAG Test Data Input. Data on the TDI input will be shifted serially into selected
registers.
TCK
TDO
JTAG Test Clock Input.
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is
normally three-stated except when captured data is shifted out of the JTAG TAP.
Document #: 38-06077 Rev. *C
Page 4 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Pin Definitions (continued)
Left Port
Right Port
Description
VSS
Ground Inputs.
[12]
VCORE
Core Power Supply.
LVTTL Power Supply.
VTTL
Master Reset
Address Counter and Mask Register
Operations
The FLEx18 family devices undergo a complete reset by
taking its MRST input LOW. The MRST input can switch
asynchronously to the clocks. The MRST initializes the
internal burst counters to zero, and the counter mask registers
to all ones (completely unmasked). The MRST also forces the
Mailbox Interrupt (INT) flags and the Counter Interrupt
(CNTINT) flags HIGH. The MRST must be performed on the
FLEx18 family devices after power-up.
This section describes the features only apply to 1-Mbit,
2-Mbit, and 4-Mbit devices. It does not apply to a 9-Mbit
device. Each port of these devices has a programmable burst
address counter. The burst counter contains three registers: a
counter register, a mask register, and a mirror register.[17]
The counter register contains the address used to access the
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST) operations.
Mailbox Interrupts
The mask register value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is changed only
by the Mask Load and Mask Reset operations, and by the
MRST. The mask register defines the counting range of the
counter register. It divides the counter register into two
regions: zero or more “0s” in the most significant bits define
the masked region, one or more “1s” in the least significant bits
define the unmasked region. Bit 0 may also be “0,” masking
the least significant counter bit and causing the counter to
increment by two instead of one.
The upper two memory locations may be used for message
passing and permit communications between ports. Table
shows the interrupt operation for both ports of CYD09S18V.
The highest memory location, 7FFFF is the mailbox for the
right port and 7FFFE is the mailbox for the left port. Table
shows that in order to set the INTR flag, a Write operation by
the left port to address 7FFFF will assert INTR LOW. At least
one byte has to be active for a Write to generate an interrupt.
A valid Read of the 7FFFF location by the right port will reset
INTR HIGH. At least one byte has to be active in order for a
Read to reset the interrupt. When one port Writes to the other
port’s mailbox, the INT of the port that the mailbox belongs to
is asserted LOW. The INT is reset when the owner (port) of the
mailbox Reads the contents of the mailbox. The interrupt flag
is set in a flow-thru mode (i.e., it follows the clock edge of the
writing port). Also, the flag is reset in a flow-thru mode (i.e., it
follows the clock edge of the reading port).
The mirror register is used to reload the counter register on
increment operations (see “retransmit,” below). It always
contains the value last loaded into the counter register, and is
changed only by the Counter Load, and Counter Reset opera-
tions, and by the MRST.
Table 3 summarizes the operation of these registers and the
required input control signals. The MRST control signal is
asynchronous. All the other control signals in Table 3
(CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the
port’s CLK. All these counter and mask operations are
independent of the port’s chip enable inputs (CE0 and CE1).
Each port can read the other port’s mailbox without resetting
the interrupt. And each port can write to its own mailbox
without setting the interrupt. If an application does not require
message passing, INT pins should be left open.
Table 2. Interrupt Operation Example [1, 13, 14, 15, 16]
Left Port
Right Port
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
R/WL
CEL
L
A0L–18L
7FFFF
X
INTL
X
R/WR
CER
X
A0R–18R
X
INTR
L
L
X
X
H
X
H
L
X
X
L
7FFFF
7FFFE
X
H
X
X
L
L
X
Reset Left INTL Flag
L
7FFFE
H
X
X
X
Notes:
12. This family of Dual-Ports does not use V
, and these pins are internally NC. The next generation Dual-Port family, the FLEx18-E™, will use V
of 1.5V
CORE
CORE
or 1.8V. Please contact local Cypress FAE for more information.
13. CE is internal signal. CE = LOW if CE = LOW and CE = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK
0
1
and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
14. OE is “Don’t Care” for mailbox operation.
15. At least one of BE0, BE1 must be LOW.
16. A18x is a NC for CYD04S18V, therefore the Interrupt Addresses are 3FFFF and 3FFFE. A18x and A17x are NC for CYD02S18V, therefore the Interrupt addresses
are 1FFFF and 1FFFE; A18x, A17x and A16x are NC for CYD01S18V, therefore the Interrupt Addresses are FFFF and FFFE.
17. This section describes the CYD04S18V, CYD02S18V, CYD01S18V 18, 17, and 16 address bits.
Document #: 38-06077 Rev. *C
Page 5 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port) [18, 19]
CLK MRST CNT/MSK CNTRST
ADS CNTEN
Operation
Description
X
L
X
X
X
X
Master Reset
Reset address counter to all 0s and mask
register to all 1s.
H
H
H
H
L
X
L
X
L
Counter Reset
Counter Load
Reset counter unmasked portion to all 0s.
H
Load counter with external address value
presented on address lines.
H
H
H
L
H
Counter Readback Read out counter internal value on address
lines.
H
H
H
H
H
H
H
H
L
Counter Increment Internally increment address counter value.
H
Counter Hold
Constantly hold the address value for
multiple clock cycles.
H
H
L
L
L
X
L
X
L
Mask Reset
Mask Load
Reset mask register to all 1s.
H
Load mask register with value presented on
the address lines.
H
H
L
L
H
H
L
H
X
Mask Readback
Reserved
Readoutmaskregistervalueonaddress lines.
H
Operation undefined
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and utilize the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN is asserted and the ADS is deasserted, the
address counter will increment on each LOW to HIGH
transition of that port’s clock signal. This will Read/Write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array, and will loop back to the start. Counter reset (CNTRST)
is used to reset the unmasked portion of the burst counter to
0s. A counter-mask register is used to control the counter
wrap.
if it is masked. If all unmasked bits are “1,” the next increment
will wrap the counter back to the initially loaded value. If an
Increment results in all the unmasked bits of the counter being
“1s,” a counter interrupt flag (CNTINT) is asserted.
The next Increment will return the counter register to its initial
value, which was stored in the mirror register. The counter
address can instead be forced to loop to 00000 by externally
connecting CNTINT to CNTRST.[20] An increment that results
in one or more of the unmasked bits of the counter being “0”
will deassert the counter interrupt flag. The example in
Figure 2 shows the counter mask register loaded with a mask
value of 0003Fh unmasking the first 6 bits with bit “0” as the
LSB and bit “16” as the MSB. The maximum value the mask
register can be loaded with is 3FFFFh. Setting the mask
register to this value allows the counter to access the entire
memory space. The address counter is then loaded with an
initial value of 8h. The base address bits (in this case, the 6th
address through the 16th address) are loaded with an address
value but do not increment once the counter is configured for
increment operation. The counter address will start at address
8h. The counter will increment its internal address value till it
reaches the mask register value of 3Fh. The counter wraps
around the memory block to location 8h at the next count.
CNTINT is issued when the counter reaches its maximum
value.
Counter Reset Operation
All unmasked bits of the counter and mirror registers are reset
to “0.” All masked bits remain unchanged. A Mask Reset
followed by a Counter Reset will reset the counter and mirror
registers to 00000, as will master reset (MRST).
Counter Load Operation
The address counter and mirror registers are both loaded with
the address value presented at the address lines.
Counter Increment Operation
Counter Hold Operation
Once the address counter register is initially loaded with an
external address, the counter can internally increment the
address value, potentially addressing the entire memory array.
Only the unmasked bits of the counter register are incre-
mented. The corresponding bit in the mask register must be
a “1” for a counter bit to change. The counter register is incre-
mented by 1 if the least significant bit is unmasked, and by 2
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are
needed, or when address is available a few cycles ahead of
data in a shared bus interface.
Notes:
18. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
19. Counter operation and mask register operation is independent of chip enables.
20. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
Document #: 38-06077 Rev. *C
Page 6 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Counter Interrupt
Mask Reset Operation
The counter interrupt (CNTINT) is asserted LOW when an
increment operation results in the unmasked portion of the
counter register being all “1s.” It is deasserted HIGH when an
Increment operation results in any other value. It is also
deasserted by Counter Reset, Counter Load, Mask Reset and
Mask Load operations, and by MRST.
The mask register is reset to all “1s,” which unmasks every bit
of the counter. Master reset (MRST) also resets the mask
register to all “1s.”
Mask Load Operation
The mask register is loaded with the address value presented
at the address lines. Not all values permit correct increment
operations. Permitted values are of the form 2n – 1 or 2n – 2.
From the most significant bit to the least significant bit,
permitted values have zero or more “0s,” one or more “1s,” or
one “0.” Thus 3FFFF, 003FE, and 00001 are permitted values,
but 3F0FF, 003FC, and 00000 are not.
Counter Readback Operation
The internal value of the counter register can be read out on
the address lines. Readback is pipelined; the address will be
valid tCA2 after the next rising edge of the port’s clock. If
address readback occurs while the port is enabled (CE0 LOW
and CE1 HIGH), the data lines (DQs) will be three-stated.
Figure 1 shows a block diagram of the operation.
Mask Readback Operation
The internal value of the mask register can be read out on the
address lines. Readback is pipelined; the address will be valid
tCM2 after the next rising edge of the port’s clock. If mask
readback occurs while the port is enabled (CE0 LOW and CE1
HIGH), the data lines (DQs) will be three-stated. Figure 1
shows a block diagram of the operation.
Retransmit
Retransmit is a feature that allows the Read of a block of
memory more than once without the need to reload the initial
address. This eliminates the need for external logic to store
and route data. It also reduces the complexity of the system
design and saves board space. An internal “mirror register” is
used to store the initially loaded address counter value. When
the counter unmasked portion reaches its maximum value set
by the mask register, it wraps back to the initial value stored in
this “mirror register.” If the counter is continuously configured
in increment mode, it increments again to its maximum value
and wraps back to the value initially stored into the “mirror
register.” Thus, the repeated access of the same data is
allowed without the need for any external logic.
Counting by Two
When the least significant bit of the mask register is “0,” the
counter increments by two. This may be used to connect the
x18 devices as a 36-bit single port SRAM in which the counter
of one port counts even addresses and the counter of the other
port counts odd addresses. This even-odd address scheme
stores one half of the 36-bit data in even memory locations,
and the other half in odd memory locations.
Document #: 38-06077 Rev. *C
Page 7 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
CNT/MSK
CNTEN
ADS
Decode
Logic
CNTRST
MRST
Bidirectional
Address
Lines
Mask
Register
Counter/
Address
Register
Address
Decode
RAM
Array
CLK
Load/Increment
17
17
From
Address
Lines
Mirror
Counter
To Readback
and Address
Decode
1
0
1
0
From
Increment
Logic
Mask
Register
17
Wrap
17
17
17
Bit 0
From
Mask
From
Counter
+1
+2
Wrap
Detect
Wrap
To
1
0
17
1
0
Counter
Figure 1. Counter, Mask, and Mirror Logic Block Diagram[1]
Document #: 38-06077 Rev. *C
Page 8 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
CNTINT
H
Example:
Load
Counter-Mask
Register = 3F
0
0
0s
0
1
1
1
1
1
1
216 215
26 25 24 23 22 21 20
Unmasked Address
Mask
Register
bit-0
Masked Address
Load
Address
Counter = 8
H
L
X
X
Xs
Xs
Xs
X
0
0
1
0
0
0
216 215
26 25 24 23 22 21 20
Address
Counter
bit-0
Max
Address
Register
X
X
X
1
1
1
1 1
1
216 215
26 25 24 23 22 21 20
Max + 1
Address
Register
H
X
X
X
0
0
1
0
0
0
216 215
26 25 24 23 22 21 20
Figure 2. Programmable Counter-Mask Register Operation[1, 21]
IEEE 1149.1 Serial Boundary Scan (JTAG)[22]
Boundary Scan Hierarchy for 9-Mbit Device
Internally, the CYD09S18V have two DIEs. Each DIE contains
all the circuitry required to support boundary scan testing. The
circuitry includes the TAP, TAP controller, instruction register,
and data registers. The circuity and operation of the DIE
boundary scan are described in detail below. The scan chain
of each DIEs are connected serially to form the scan chain of
the CYD09S18V as shown in Figure 3. TMS and TCK are
connected in parallel to each DIE to drive all TAP controllers
in unison. In many cases, each DIE will be supplied with the
same instruction. In other cases, it might be useful to supply
different instructions to each DIE. One example would be
testing the device ID of one DIE while bypassing the others.
The FLEx18 family devices incorporate an IEEE 1149.1 serial
boundary scan test access port (TAP). The TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1-compliant TAPs. The TAP
operates using JEDEC-standard 3.3V I/O logic levels. It is
composed of three input connections and one output
connection required by the test logic defined by the standard.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
devices, and may be performed while the device is operating.
An MRST must be performed on the devices after power-up.
Each pin of the FLEx18 9-Mb device is typically connected to
two DIEs. For connectivity testing with the EXTEST
instruction, it is desirable to check the internal connections
between DIEs as well as the external connections to the
package. This can be accomplished by merging the netlist of
the devices with the netlist of the user’s circuit board. To facil-
itate boundary scan testing of the devices, Cypress provides
the BSDL file for each DIE, the internal netlist of the device,
and a description of the device scan chain. The user can use
these materials to easily integrate the devices into the board’s
boundary scan environment. Further information can be found
in the Cypress application note Using JTAG Boundary Scan
For System In a Package (SIP) Dual-Port SRAMs.
Performing a Pause/Restart
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the
scan chain will output the next bit in the chain twice. For
example, if the value expected from the chain is 1010101, the
device will output a 11010101. This extra bit will cause some
testers to report an erroneous failure for the devices in a scan
test. Therefore the tester should be configured to never enter
the PAUSE-DR state.
Notes:
21. The “X” in this diagram represents the counter upper bits.
22. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance.
Document #: 38-06077 Rev. *C
Page 9 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
TDO
TDO
D2
TDI
TDO
D1
TDI
TDI
Figure 3. Scan Chain for 9-Mbit Device
Table 4. Identification Register Definitions
Instruction Field
Revision Number (31:28)
Cypress Device ID (27:12)
Value
Description
0h
Reserved for version number.
C090h
C091h
C093h
034h
1
Defines Cypress part number for CYD04S18V and CYD09S18V DIE
Defines Cypress part number for CYD02S18V
Defines Cypress part number for CYD01S18V
Cypress JEDEC ID (11:1)
ID Register Presence (0)
Allows unique identification of the DP family device vendor.
Indicates the presence of an ID register.
Table 5. Scan Register Sizes
Register Name
Instruction
Bit Size
4
1
Bypass
Identification
Boundary Scan
32
n[23]
Table 6. Instruction Identification Codes
Instruction
EXTEST
Code
Description
0000
1111
1011
0111
0100
Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
Places the BYR between TDI and TDO.
BYPASS
IDCODE
HIGHZ
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
Places BYR between TDI and TDO. Forces all device output drivers to a High-Z state.
Controls boundary to 1/0. Places BYR between TDI and TDO.
CLAMP
SAMPLE/PRELOAD 1000
Captures the input/output ring contents. Places BSR between TDI and TDO.
Resets the non-boundary scan logic. Places BYR between TDI and TDO.
NBSRST
1100
RESERVED
All other codes Other combinations are reserved. Do not use other than the above.
Note:
23. See details in the device BSDL file.
Document #: 38-06077 Rev. *C
Page 10 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Maximum Ratings[24]
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage...........................................> 2000V
(JEDEC JESD22-A114-2000B)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.....................................................> 200 mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Operating Range
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential............... –0.5V to +4.6V
Ambient
Temperature
[12]
Range
VDDIO/VTTL
VCORE
DC Voltage Applied to
Commercial 0°C to +70°C 3.3V±165 mV 1.8V±100 mV
Outputs in High-Z State...........................–0.5V to VDD +0.5V
DC Input Voltage...............................–0.5V to VDD + 0.5V[25]
Industrial
–40°Cto+85°C 3.3V±165 mV 1.8V±100 mV
Electrical Characteristics Over the Operating Range
-167
-133
-100
Parameter
VOH
VOL
VIH
Description
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
Output HIGH Voltage (VDD = Min., IOH= –4.0 mA) 2.4
Output LOW Voltage (VDD = Min., IOL= +4.0 mA)
2.4
2.4
V
V
0.4
0.4
0.4
Input HIGH Voltage
Input LOW Voltage
2.0
2.0
2.0
V
VIL
0.8
10
10
0.8
10
10
0.8
10
10
V
IOZ
Output Leakage Current
–10
–10
–10
–10
–10
µA
µA
IIX1
Input Leakage Current Except TDI, TMS, MRST –10
Input Leakage Current TDI, TMS, MRST –1.0
IIX2
0.1 –1.0
225 300
0.1 –1.0
225 300
0.1 mA
mA
ICC
Operating Current for
(VDD = Max.,IOUT = 0 mA),
Outputs Disabled
CYD01S18V
CYD02S18V
CYD04S18V
CYD09S18V
270 400
90 115
200 310 mA
mA
[26]
ISB1
Standby Current (Both Ports TTL Level)
90
160 210
55 75
160 210
115
CEL and CER ≥ VIH, f = fMAX
[26]
ISB2
Standby Current (One Port TTL Level)
160 210
55 75
mA
mA
mA
CEL | CER ≥ VIH, f = fMAX
[26]
ISB3
Standby Current (Both Ports CMOS Level)
CEL and CER ≥ VDD – 0.2V, f = 0
[26]
ISB4
Standby Current (One Port CMOS Level)
160 210
75
CEL | CER ≥ VIH, f = fMAX
ISB5
Operating Current (VDDIO =
Max, Iout=0mA,f=0)
Outputs Disabled
CYD09S18V
75
0
mA
mA
[12]
ICORE
Core Operating Current for (VDD = Max.,
0
0
0
0
0
IOUT = 0 mA), Outputs Disabled
Capacitance[27]
Part Number
Parameter
CIN
Description
Test Conditions
Max.
Unit
CYD01S18V
CYD02S18V
CYD04S18V
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VDD = 3.3V
13
10
pF
pF
COUT
CYD09S18V
CIN
Input Capacitance
Output Capacitance
22
20
pF
pF
COUT
Notes:
24. The voltage on any input or I/O pin can not exceed the power pin during power-up.
25. Pulse width < 20 ns.
26. I
27. C
, I
, I
and I
are not applicable for CYD09S18V because it can not be powered down by using chip enable pins.
also references C
I/O
SB1 SB2 SB3
SB4
OUT
Document #: 38-06077 Rev. *C
Page 11 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
AC Test Load and Waveforms
3.3V
Z0 = 50Ω
R = 50Ω
OUTPUT
R1 = 590Ω
OUTPUT
C = 10 pF
C = 5 pF
R2 = 435Ω
VTH = 1.5V
(a) Normal Load (Load 1)
(b) Three-state Delay (Load 2)
3.0V
90%
10%
90%
10%
ALL INPUT PULSES
Vss
< 2 ns
< 2 ns
Switching Characteristics Over the Operating Range
-167
-133
-100
CYD01S18V
CYD02S18V
CYD04S18V
CYD01S18V
CYD02S18V
CYD04S18V
CYD09S18V
CYD09S18V
Parameter
fMAX2
Description
Maximum Operating Frequency
Clock Cycle Time
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
167
133
133
100
tCYC2
6.0
2.7
2.7
7.5
3.0
3.0
7.5
3.0
3.0
10
4.0
4.0
tCH2
Clock HIGH Time
tCL2
Clock LOW Time
[28]
tR
Clock Rise Time
2.0
2.0
2.0
2.0
2.0
2.0
3.0
3.0
[28]
tF
Clock Fall Time
tSA
Address Set-up Time
Address Hold Time
Byte Select Set-up Time
Byte Select Hold Time
Chip Enable Set-up Time
Chip Enable Hold Time
R/W Set-up Time
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
NA
NA
2.5
0.6
2.5
0.6
NA
NA
NA
NA
NA
NA
NA
NA
3.0
0.6
3.0
0.6
NA
NA
3.0
0.6
3.0
0.6
NA
NA
NA
NA
NA
NA
NA
NA
tHA
tSB
tHB
tSC
tHC
tSW
tHW
tSD
R/W Hold Time
Input Data Set-up Time
Input Data Hold Time
ADS Set-up Time
tHD
tSAD
tHAD
tSCN
tHCN
tSRST
tHRST
tSCM
tHCM
tOE
ADS Hold Time
CNTEN Set-up Time
CNTEN Hold Time
CNTRST Set-up Time
CNTRST Hold Time
CNT/MSK Set-up Time
CNT/MSK Hold Time
Output Enable to Data Valid
OE to Low Z
4.0
4.4
4.7
5.0
[29, 30]
tOLZ
0
0
0
0
Notes:
28. Except JTAG signals (t and t < 10 ns [max.]).
r
f
29. This parameter is guaranteed by design, but it is not production tested.
30. Test conditions used are Load 2.
Document #: 38-06077 Rev. *C
Page 12 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Switching Characteristics Over the Operating Range (continued)
-167
-133
-100
CYD01S18V
CYD02S18V
CYD04S18V
CYD01S18V
CYD02S18V
CYD04S18V
CYD09S18V
CYD09S18V
Parameter
Description
OE to High Z
Min.
Max.
4.0
Min.
Max.
4.4
Min.
Max.
4.7
Min.
Max.
5.0
Unit
ns
[29, 30]
tOHZ
0
0
0
0
tCD2
tCA2
tCM2
Clock to Data Valid
4.0
4.4
4.7
5.0
ns
Clock to Counter Address Valid
4.0
4.4
NA
NA
ns
Clock to Mask Register Readback
Valid
4.0
4.4
NA
NA
ns
tDC
Data Output Hold After Clock HIGH
Clock HIGH to Output High Z
Clock HIGH to Output Low Z
Clock to INT Set Time
1.0
0
1.0
0
1.0
0
1.0
0
ns
ns
ns
ns
ns
ns
ns
[29,30]
tCKHZ
4.0
4.0
6.7
6.7
5.0
5.0
4.4
4.4
7.5
7.5
5.7
5.7
4.7
4.7
7.5
7.5
NA
NA
5.0
5.0
10
[29, 30]
tCKLZ
1.0
0.5
0.5
0.5
0.5
1.0
0.5
0.5
0.5
0.5
1.0
0.5
0.5
NA
NA
1.0
0.5
0.5
NA
NA
tSINT
tRINT
Clock to INT Reset Time
10
tSCINT
tRCINT
Clock to CNTINT Set Time
Clock to CNTINT Reset time
NA
NA
Port to Port Delays
tCCS
Clock to Clock Skew
5.2
6.0
6.0
8.0
ns
Master Reset Timing
tRS
Master Reset Pulse Width
5.0
6.0
5.0
5.0
6.0
5.0
5.0
6.0
5.0
5.0
8.5
5.0
cycles
ns
tRS
Master Reset Set-up Time
tRSR
tRSF
tRSINT
Master Reset Recovery Time
Master Reset to Outputs Inactive
cycles
ns
10.0
10.0
10.0
10.0
10.0
NA
10.0
NA
Master Reset to Counter and Mailbox
Interrupt Flag Reset Time
ns
JTAG Timing and Switching Waveforms
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Parameter
fJTAG
tTCYC
tTH
Description
Min.
Max.
Unit
MHz
ns
Maximum JTAG TAP Controller Frequency
TCK Clock Cycle Time
10
100
40
40
10
10
10
10
TCK Clock HIGH Time
ns
tTL
TCK Clock LOW Time
ns
tTMSS
tTMSH
tTDIS
tTDIH
tTDOV
tTDOX
TMS Set-up to TCK Clock Rise
TMS Hold After TCK Clock Rise
TDI Set-up to TCK Clock Rise
TDI Hold After TCK Clock Rise
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
ns
ns
ns
ns
30
ns
0
ns
Document #: 38-06077 Rev. *C
Page 13 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
tTH
tTL
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
Switching Waveforms
Master Reset
tRS
MRST
tRSF
ALL
ADDRESS/
DATA
tRSS
INACTIVE
LINES
tRSR
ALL
OTHER
INPUTS
ACTIVE
TMS
tRSINT
CNTINT
INT
TDO
Document #: 38-06077 Rev. *C
Page 14 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Switching Waveforms (continued)
Read Cycle[13, 31, 32, 33, 34]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tSC
tHC
tSB
tHB
BE0–BE1
R/W
tSW
tSA
tHW
tHA
ADDRESS
DATAOUT
An
An+1
An+2
An+3
tDC
1 Latency
tCD2
Qn
Qn+1
Qn+2
tOHZ
tCKLZ
tOLZ
OE
t
OE
Notes:
31. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
32. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
33. The output is disabled (high-impedance state) by CE = V following the next rising edge of the clock.
IH
34. Addresses do not have to be accessed sequentially since ADS = CNTEN = V with CNT/MSK = V constantly loads the address on the rising edge of the CLK.
IL
IH
Numbers are for reference only.
Document #: 38-06077 Rev. *C
Page 15 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Switching Waveforms (continued)
Bank Select Read[35, 36]
tCYC2
tCH2
tCL2
CLK
tHA
tSA
A3
A4
ADDRESS(B1)
A5
A0
A1
A2
tHC
tSC
CE(B1)
tCD2
tCD2
tCD2
tCKHZ
tHC
tCKHZ
tSC
Q0
Q3
Q1
DATAOUT(B1)
ADDRESS(B2)
tHA
tSA
tDC
A2
tDC
A3
tCKLZ
A4
A5
A0
A1
tHC
tSC
CE(B2)
tCD2
tCKHZ
tCD2
tSC
tHC
DATAOUT(B2)
Q4
Q2
tCKLZ
tCKLZ
Read-to-Write-to-Read (OE = LOW)[34, 37, 38, 39, 40]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tSW
tHW
R/W
tSW
tHW
An
An+1
An+2
An+2
An+2
An+3
ADDRESS
tSD tHD
Dn+2
tSA
tHA
DATAIN
tCD2
tDC
tCKHZ
DATAOUT
Qn
READ
NO OPERATION
WRITE
Notes:
35. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx18 device from this data sheet. ADDRESS
(B1)
= ADDRESS
.
(B2)
36. ADS = CNTEN= BE0 – BE1 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
37. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
38. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
39. CE = OE = BE0 – BE1 = LOW; CE = R/W = CNTRST = MRST = HIGH.
0
1
40. CE = BE0 – BE1 = R/W = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
0
1
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
Document #: 38-06077 Rev. *C
Page 16 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Switching Waveforms (continued)
Read-to-Write-to-Read (OE Controlled)[34, 37, 39, 40]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tHW
tSW
R/W tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
tSA
tHA
tSD tHD
Dn+2
DATAIN
Dn+3
tCD2
tCD2
DATAOUT
Qn
Qn+4
tOHZ
OE
READ
WRITE
READ
Read with Address Counter Advance[39]
tCYC2
tCH2
tCL2
CLK
tSA
tHA
ADDRESS
An
tSAD
tHAD
ADS
tSAD
tHAD
CNTEN
tSCN
tHCN
tSCN
tHCN
tCD2
Qx–1
Qx
tDC
Qn
Qn+1
COUNTER HOLD
Qn+2
DATAOUT
Qn+3
READ
READ WITH COUNTER
READ WITH COUNTER
EXTERNAL
ADDRESS
Document #: 38-06077 Rev. *C
Page 17 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Switching Waveforms (continued)
Write with Address Counter Advance [40]
tCYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
An+1
An+2
An+3
An+4
tSAD
tHAD
ADS
CNTEN
DATAIN
tSCN
tHCN
Dn
Dn+1
Dn+1
Dn+2
Dn+3
Dn+4
tSD
tHD
WRITE EXTERNAL
ADDRESS
WRITE WITH WRITE COUNTER
COUNTER HOLD
WRITE WITH COUNTER
Document #: 38-06077 Rev. *C
Page 18 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Switching Waveforms (continued)
Counter Reset[41, 42]
tCYC2
tCH2 tCL2
CLK
tHA
Am
tSA
Ap
An
ADDRESS
INTERNAL
Ax
Ap
An
1
0
Am
ADDRESS
tHW
tSW
R/W
ADS
CNTEN
CNTRST
tHRST
tSRST
tHD
tSD
DATAIN
D0
tCD2
tCD2
[43]
DATAOUT
Q0
Qn
Q1
tCKLZ
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS An
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS Am
Notes:
41. CE = BE0 – BE1 = LOW; CE = MRST = CNT/MSK = HIGH.
0
1
42. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
43. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
Document #: 38-06077 Rev. *C
Page 19 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Switching Waveforms (continued)
Readback State of Address Counter or Mask Register[44, 45, 46, 47]
tCYC2
tCH2 tCL2
CLK
tCA2 or tCM2
tSA
tHA
EXTERNAL
An*
An
ADDRESS
A0–A16
INTERNAL
ADDRESS
An+4
An+1
An+2
An+3
An
tSAD
tHAD
ADS
CNTEN
tSCN
tHCN
tCD2
tCKHZ
Qn
tCKLZ
DATAOUT
Qn+1
Qx-1
Qn+2
Qx-2
Q
n+3
LOAD
EXTERNAL
ADDRESS
READBACK
COUNTER
INTERNAL
ADDRESS
INCREMENT
Notes:
44. CE = OE = BE0 – BE1 = LOW; CE = R/W = CNTRST = MRST = HIGH.
0
1
45. Address in output mode. Host must not be driving address bus after t
in next clock cycle.
CKLZ
46. Address in input mode. Host can drive address bus after t
.
CKHZ
47. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
Document #: 38-06077 Rev. *C
Page 20 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Switching Waveforms (continued)
Left_Port (L_Port) Write to Right_Port (R_Port) Read[48, 49, 50]
tCYC2
tCH2
tCL2
CLKL
tHA
tSA
L_PORT
ADDRESS
An
tSW
tHW
R/WL
tCKHZ
tSD
tHD
tCKLZ
L_PORT
DATAIN
Dn
tCCS
tCYC2
tCL2
CLKR
tCH2
tSA
tHA
R_PORT
ADDRESS
An
R/WR
tCD2
R_PORT
DATAOUT
Qn
tDC
Notes:
48. CE = OE = ADS = CNTEN = BE0 – BE1 = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH.
0
1
49. This timing is valid when one port is writing, and other port is reading the same location at the same time. If t
is violated, indeterminate data will be Read out.
CCS
50. If t
< minimum specified value, then R_Port will Read the most recent data (written by L_Port) only (2 * t
+ t
) after the rising edge of R_Port's clock. If
CCS
CYC2
CD2
t
> minimum specified value, then R_Port will Read the most recent data (written by L_Port) (t
+ t
) after the rising edge of R_Port's clock.
CCS
CYC2
CD2
Document #: 38-06077 Rev. *C
Page 21 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Switching Waveforms (continued)
Counter Interrupt and Retransmit[16, 43, 51, 52, 53, 54]
tCYC2
tCH2
tCL2
CLK
tSCM
tHCM
CNT/MSK
ADS
CNTEN
COUNTER
INTERNAL
ADDRESS
3FFFE
tSCINT
3FFFC
Last_Loaded
3FFFD
3FFFF
tRCINT
Last_Loaded +1
CNTINT
Notes:
51. CE = OE = BE0 – BE1 = LOW; CE = R/W = CNTRST = MRST = HIGH.
0
1
52. CNTINT is always driven.
53. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.
54. The mask register assumed to have the value of 3FFFFh.
Document #: 38-06077 Rev. *C
Page 22 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Switching Waveforms (continued)
MailBox Interrupt Timing[55, 56, 57, 58, 59]
tCYC2
tCH2
tCL2
CLKL
tSA tHA
7FFFF
L_PORT
ADDRESS
An+1
An
An+2
An+3
tSINT
tRINT
INTR
tCYC2
tCL2
tCH2
CLKR
tSA tHA
Am
R_PORT
ADDRESS
Am+1
7FFFF
Am+3
Am+4
Table 7. Read/Write and Enable Operation (Any Port)[1, 18, 60, 61, 62]
Inputs
Outputs
OE
CLK
CE0
CE1
R/W
DQ0 – DQ17
Operation
X
H
X
X
High-Z
Deselected
Deselected
Write
X
X
L
X
L
L
L
L
H
H
H
X
L
High-Z
DIN
H
DOUT
High-Z
Read
H
X
X
Outputs Disabled
Notes:
55. CE = OE = ADS = CNTEN = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH.
0
1
56. Address “7FFFF” is the mailbox location for R_Port of the 9Mb device.
57. L_Port is configured for Write operation, and R_Port is configured for Read operation.
58. At least one byte enable (BE0 – BE1) is required to be active during interrupt operations.
59. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
60. OE is an asynchronous input signal.
61. When CE changes state, deselection and Read happen after one cycle of latency.
62. CE = OE = LOW; CE = R/W = HIGH.
0
1
Document #: 38-06077 Rev. *C
Page 23 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Ordering Information
512K
×
18 (9Mb) 3.3V Synchronous CYD09S18V Dual-Port SRAM
Package
Speed
(MHz)
Operating
Ordering Code
Name
BB256
BB256
BB256
Package Type
Range
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Commercial
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Commercial
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Industrial
133 CYD09S18V-133BBC
100 CYD09S18V-100BBC
CYD09S18V-100BBI
256K
×
18 (4Mb) 3.3V Synchronous CYD04S36V Dual-Port SRAM
Package
Speed
(MHz)
Operating
Range
Ordering Code
Name
BB256
BB256
BB256
Package Type
167 CYD04S18V-167BBC
133 CYD04S18V-133BBC
CYD04S18V-133BBI
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Commercial
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Commercial
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Industrial
128K
×
18 (2Mb) 3.3V Synchronous CYD02S18V Dual-Port SRAM
Package
Speed
(MHz)
Operating
Range
Ordering Code
Name
BB256
BB256
BB256
Package Type
167 CYD02S18V-167BBC
133 CYD02S18V-133BBC
CYD02S18V-133BBI
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Commercial
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Commercial
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Industrial
64K
× 18 (1Mb) 3.3V Synchronous CYD01S18V Dual-Port SRAM
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
167 CYD01S18V-167BBC
133 CYD01S18V-133BBC
CYD01S18V-133BBI
BB256
BB256
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Commercial
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Commercial
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Industrial
Document #: 38-06077 Rev. *C
Page 24 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Package Diagram
256-Ball FBGA (17 x 17 mm) BB256
TOP VIEW
BOTTOM VIEW
Ø0.05 M C
Ø0.25 M C A B
PIN 1 CORNER
Ø0.45 0.05(256X)ꢀCPꢁD DEVICES (37K & 39K)
PIN 1 CORNER
+0.10
Ø0.50 (256X)ꢀAꢁꢁ OTHER DEVICES
ꢀ0.05
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
A
B
C
D
E
F
F
G
H
J
G
H
J
K
ꢁ
K
ꢁ
M
N
P
R
T
M
N
P
R
T
1.00
B
7.50
15.00
A
17.00 0.10
A
SEATING PꢁANE
0.20(4X)
A1
C
REFERENCE JEDEC MOꢀ192
A1 0.36 0.56
1.40 MAX. 1.70 MAX.
A
51-85108-*F
FLEx18 and FLEx18-E are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in
this document may be the trademarks of their respective holders.
Document #: 38-06077 Rev. *C
Page 25 of 26
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Document History Page
Document Title: CYD01S18V/CYD02S18V/CYD04S18V/CYD09S18V FLEx18™ 3.3V 64K/128K/256K/512K x 18
Synchronous Dual-Port RAM
Document Number: 38-06077
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
259671
289711
See ECN
See ECN
WWZ
YDT
New data sheet
*A
Change Pinout D10 from NC to VSS
Changed tRSCNTINT to tRSINT
Added tRSINT to the master reset timing diagram
Added ISB5 and changed IIX2
*B
*C
327354
365320
See ECN
See ECN
AEQ
YDT
Change Pinout C10 from REVR[2,4] to NC[2,5]
Change Pinout G5 from VDDIOL to REVL[2,3]
Added note for VCORE
Removed preliminary status
Document #: 38-06077 Rev. *C
Page 26 of 26
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