CYUSB3014-BZXIT_技术文档

CYUSB301X/CYUSB201X

EZ-USB^®FX3: SuperSpeed USB Controller

■ EZ-USB^®Software Development Kit (SDK) for code devel-

opment of firmware and PC Applications

Features

■ Universal serial bus (USB) integration

❐ Includes RTOS Framework (using ThreadX Version 5)

❐ USB 3.1, Gen 1 and USB 2.0 peripherals compliant with USB

❐ Firmware examples covering all I/O modules

❐ Visual Studio host examples using C++ and C#

3.1 Specification Revision 1.0 (TID # 340800007)

❐ 5-Gbps SuperSpeed PHY compliant with USB 3.1 Gen 1

❐ High-speed On-The-Go (HS-OTG) host and peripheral

compliant with OTG Supplement Version 2.0

■ SuperSpeed Explorer Board available for rapid prototyping

❐ Several accessory boards also available:

• Adapter boards for Xilinx/Altera FPGA development

• Adapter board for Video development

• CPLD board for concept testing and initial development

❐ Thirty-two physical endpoints

❐ Support for battery charging Specification 1.1 and accessory

charger adaptor (ACA) detection

■ General Programmable Interface (GPIF™ II)

❐ Programmable 100-MHz GPIF II enables connectivity to a

wide range of external devices

❐ 8-, 16-, 24-, and 32-bit data bus

❐ Up to16 configurable control signals

Applications

■

Digital video camcorders

Digital still cameras

Printers

■ Fully accessible 32-bit CPU

❐ ARM926EJ core with 200-MHz operation

❐ 512-KB or 256-KB embedded SRAM

Scanners

Video capture cards

Test and measurement equipment

Surveillance cameras

Personal navigation devices

Medical imaging devices

Video IP phones

■ Additional connectivity to the following peripherals

❐ SPI master at up to 33 MHz

❐ UART support of up to 4 Mbps

❐ I²C master controller at 1 MHz

❐ I²S master (transmitter only) at sampling frequencies of

32 kHz, 44.1 kHz, and 48 kHz

■ Selectable clock input frequencies

❐ 19.2, 26, 38.4, and 52 MHz

❐ 19.2-MHz crystal input support

Portable media players

Industrial cameras

Data loggers

■ Ultra low-power in core power-down mode

❐ Less than 60 µA with VBATT on and 20 µA with VBATT off

■ Independent power domains for core and I/O

❐ Core operation at 1.2 V

Data acquisition

High-performance Human Interface Devices (gesture

recognition)

❐ I2S, UART, and SPI operation at 1.8 to 3.3 V

❐ I²C operation at 1.2 V to 3.3 V

Functional Description

■ Package options

❐ 121-ball, 10- × 10-mm, 0.8-mm pitch Pb-free ball grid array

(BGA)

For a complete list of related documentation, click here.

❐ 131-ball, 4.7- × 5.1-mm, 0.4-mm pitch wafer-level chip scale

package (WLCSP)

❐ See Table 20 for details on the eight FX3 variants

Cypress Semiconductor Corporation

Document Number: 001-52136 Rev. *U

•

198 Champion Court

•

San Jose, CA 95134-1709

•408-943-2600

Revised April 20, 2017

CYUSB301X/CYUSB201X

Logic Block Diagram

Document Number: 001-52136 Rev. *U

Page 2 of 54

CYUSB301X/CYUSB201X

More Information

Cypress provides a wealth of data at www.cypress.com to help you to select the right <product> device for your design, and to help

you to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base

article KBA87889, How to design with FX3/FX3S.

■ Overview: USB Portfolio, USB Roadmap

❐ AN73609 - EZ-USB FX2LP/ FX3 Developing Bulk-Loop Ex-

ample on Linux

■ USB 3.0 Product Selectors: FX3, FX3S, CX3, HX3, West

Bridge Benicia

❐ AN77960 - Introduction to EZ-USB FX3 High-Speed USB

Host Controller

❐ AN76348 - Differences in Implementation of EZ-USB FX2LP

and EZ-USB FX3 Applications

■ Application notes: Cypress offers a large number of USB appli-

cation notes covering a broad range of topics, from basic to

advanced level. Recommended application notes for getting

started with FX3 are:

❐ AN89661 - USB RAID 1 Disk Design Using EZ-USB FX3S

■ Code Examples: < Modify as required >

❐ USB Hi-Speed

❐ USB Full-Speed

❐ AN75705 - Getting Started with EZ-USB FX3

❐ AN76405 - EZ-USB FX3 Boot Options

❐ AN70707 - EZ-USB FX3/FX3S Hardware Design Guidelines

and Schematic Checklist

❐ USB SuperSpeed

❐ AN65974 - Designing with the EZ-USB FX3 Slave FIFO In-

■ Technical Reference Manual (TRM):

❐ EZ-USB FX3 Technical Reference Manual

terface

❐ AN75779-HowtoImplementanImageSensorInterfacewith

EZ-USB FX3 in a USB Video Class (UVC) Framework

❐ AN86947 - Optimizing USB 3.0 Throughput with EZ-USB

FX3

❐ AN84868 - Configuring an FPGA over USB Using Cypress

EZ-USB FX3

■ Development Kits:

❐ CYUSB3KIT-003, EZ-USB FX3 SuperSpeed Explorer Kit

❐ CYUSB3KIT-001, EZ-USB FX3 Development Kit

■ Models: IBIS

❐ AN68829 - Slave FIFO Interface for EZ-USB FX3: 5-Bit Ad-

dress Mode

EZ-USB FX3 Software Development Kit

Cypress delivers the complete software and firmware stack for FX3, in order to easily integrate SuperSpeed USB into any embedded

application. The Software Development Kit (SDK) comes with tools, drivers and application examples, which help accelerate appli-

cation development.

GPIF™ II Designer

The GPIF II Designer is a graphical software that allows designers to configure the GPIF II interface of the EZ-USB FX3 USB 3.0

Device Controller.

The tool allows users the ability to select from one of five Cypress supplied interfaces, or choose to create their own GPIF II interface

from scratch. Cypress has supplied industry standard interfaces such as Asynchronous and Synchronous Slave FIFO, Asynchronous

and Synchronous SRAM, and Asynchronous SRAM. Designers who already have one of these pre-defined interfaces in their system

can simply select the interface of choice, choose from a set of standard parameters such as bus width (x8, 16, x32) endianess, clock

settings, and compile the interface. The tool has a streamlined three step GPIF interface development process for users who need a

customized interface. Users are able to first select their pin configuration and standard parameters. Secondly, they can design a virtual

state machine using configurable actions. Finally, users can view output timing to verify that it matches the expected timing. Once the

three step process is complete, the interface can be compiled and integrated with FX3.

Document Number: 001-52136 Rev. *U

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CYUSB301X/CYUSB201X

Contents

Functional Overview ..........................................................5

Pin Description .................................................................15

Application Examples ....................................................5

Electrical Specifications ..................................................19

Absolute Maximum Ratings .........................................19

Operating Conditions ...................................................19

DC Specifications ........................................................19

USB Interface ......................................................................6

OTG ...............................................................................6

ReNumeration ...............................................................7

EZ-Dtect ........................................................................7

VBUS Overvoltage Protection .......................................7

Carkit UART Mode ........................................................7

AC Timing Parameters .....................................................21

GPIF II Timing .............................................................21

Slave FIFO Interface ...................................................24

Host Processor Interface (P-Port) Timing ...................30

Serial Peripherals Timing ............................................37

Reset Sequence ..........................................................42

GPIF II ..................................................................................8

CPU ......................................................................................8

JTAG Interface ....................................................................8

Package Diagram ..............................................................43

Other Interfaces ..................................................................8

SPI Interface ..................................................................8

UART Interface ..............................................................9

I2C Interface ..................................................................9

I2S Interface ..................................................................9

Ordering Information ........................................................45

Ordering Code Definitions ...........................................45

Acronyms ..........................................................................46

Document Conventions ...................................................46

Boot Options .......................................................................9

Units of Measure .........................................................46

Reset ....................................................................................9

Hard Reset ....................................................................9

Soft Reset ......................................................................9

Errata .................................................................................47

Qualification Status .....................................................47

Errata Summary ..........................................................47

Clocking ............................................................................10

Document History Page ...................................................50

32-kHz Watchdog Timer Clock Input ...........................10

Sales, Solutions, and Legal Information ........................54

Worldwide Sales and Design Support .........................54

Products ......................................................................54

PSoC®Solutions .........................................................54

Cypress Developer Community ...................................54

Technical Support .......................................................54

Power .................................................................................11

Power Modes ..............................................................11

Digital I/Os .........................................................................13

GPIOs .................................................................................13

System-level ESD .............................................................13

Pin Configurations ...........................................................14

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CYUSB301X/CYUSB201X

FX3 contains 512 KB or 256 KB of on-chip SRAM (see Ordering

Information on page 45) for code and data. EZ-USB FX3 also

provides interfaces to connect to serial peripherals such as

UART, SPI, I²C, and I²S.

Functional Overview

Cypress’s EZ-USB FX3 is a SuperSpeed peripheral controller,

providing integrated and flexible features.

FX3 comes with application development tools. The software

development kit comes with firmware and host application

examples for accelerating time to market.

FX3 has a fully configurable, parallel, general programmable

interface called GPIF II, which can connect to any processor,

ASIC, or FPGA. GPIF II is an enhanced version of the GPIF in

FX2LP, Cypress’s flagship USB 2.0 product. It provides easy and

glueless connectivity to popular interfaces, such as

asynchronous SRAM, asynchronous and synchronous address

data multiplexed interfaces, and parallel ATA.

FX3 complies with the USB 3.1, Gen 1.0 specification and is also

backward compatible with USB 2.0. It also complies with the

Battery Charging Specification v1.1 and USB 2.0 OTG

Specification v2.0.

FX3 has integrated the USB 3.1 Gen 1 and USB 2.0 physical

layers (PHYs) along with a 32-bit ARM926EJ-S microprocessor

for powerful data processing and for building custom

applications. It implements an architecture that enables

375-MBps data transfer from GPIF II to the USB interface.

Application Examples

In a typical application (see Figure 1), the FX3 functions as the

main processor running the application software that connects

external hardware to the SuperSpeed USB connection.

Additionally, FX3 can function as a coprocessor connecting via

the GPIF II interface to an application processor (see Figure 2)

and operates as a subsystem providing SuperSpeed USB

connectivity to the application processor.

An integrated USB 2.0 OTG controller enables applications in

which FX3 may serve dual roles; for example, EZ-USB FX3 may

function as an OTG Host to MSC as well as HID-class devices.

Figure 1. EZ-USB FX3 as Main Processor

Crystal*

Clock

External Slave

Device

(e.g. Image

Sensor)

USB

Host

Ez-USB FX3

GPIF II

I²C

* A clock input may be provided on the

CLKIN pin instead of a crystal input

EEPROM

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CYUSB301X/CYUSB201X

Figure 2. EZ-USB FX3 as a Coprocessor

Crystal*

Clock

External Master

(e.g. MCU/CPU/

FPGA/ASIC)

USB

Host

USB

Ez-USB FX3

GPIF II

I²C

* A clock input may be provided on the

CLKIN pin instead of a crystal input

EEPROM

OTG

USB Interface

FX3 is compliant with the OTG Specification Revision 2.0. In

OTG mode, FX3 supports both A and B device modes and

supports Control, Interrupt, Bulk, and Isochronous data

transfers.

FX3 complies with the following specifications and supports the

following features:

■ Supports USB peripheral functionality compliant with USB 3.1

Specification Revision 1.0 and is also backward compatible

with the USB 2.0 Specification.

FX3 requires an external charge pump (either standalone or

integrated into a PMIC) to power VBUS in the OTG A-device

mode.

■ FX3 Hi-Speed parts (CYUSB201X) only support USB 2.0.

The Target Peripheral List for OTG host implementation consists

of MSC- and HID-class devices.

■ Complies with OTG Supplement Revision 2.0. It supports

High-Speed, Full-Speed, andLow-SpeedOTGdual-roledevice

capability. As a peripheral, FX3 is capable of SuperSpeed,

High-Speed, and Full-Speed. As a host, it is capable of

High-Speed, Full-Speed, and Low-Speed.

FX3 does not support Attach Detection Protocol (ADP).

OTG Connectivity

In OTG mode, FX3 can be configured to be an A, B, or dual-role

device. It can connect to the following:

■ Supports Carkit Pass-Through UART functionality on USB

D+/D– lines based on the CEA-936A specification.

■ ACA device

■ Supports 16 IN and 16 OUT endpoints.

■ Targeted USB peripheral

■ SRP-capable USB peripheral

■ HNP-capable USB peripheral

■ OTG host

■ Supports the USB 3.0 Streams feature. It also supports USB

Attached SCSI (UAS) device-class to optimize mass-storage

access performance.

■ As a USB peripheral, application examples show that the FX3

supports UAS, USB Video Class (UVC), and Mass Storage

Class (MSC) USB peripheral classes. All other device classes

can be supported by customer firmware; a template example

is provided as a starting point.

■ HNP-capable host

■ OTG device

■ As an OTG host, application examples show that FX3 supports

MSC and HID device classes.

Note When the USB port is not in use, disable the PHY and

transceiver to save power.

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CYUSB301X/CYUSB201X

Figure 3. System Diagram with OVP Device For VBUS

ReNumeration

Because of FX3's soft configuration, one chip can take on the

identities of multiple distinct USB devices.

POWER SUBSYSTEM

When first plugged into USB, FX3 enumerates automatically with

the Cypress Vendor ID (0x04B4) and downloads firmware and

USB descriptors over the USB interface. The downloaded

firmware executes an electrical disconnect and connect. FX3

enumerates again, this time as a device defined by the

downloaded information. This patented two-step process, called

ReNumeration, happens instantly when the device is plugged in.

EZ-USB FX3

VBUS

OTG_ID

1

2

OVP device

EZ-Dtect

SSRX-

SSRX+

SSTX-

SSTX+

D-

3

4

5

6

7

8

9

FX3 supports USB Charger and accessory detection (EZ-Dtect).

The charger detection mechanism complies with the Battery

Charging Specification Revision 1.1. In addition to supporting

this version of the specification, FX3 also provides hardware

support to detect the resistance values on the ID pin.

D+

GND

FX3 can detect the following resistance ranges:

■ Less than 10 

■ Less than 1 k

Carkit UART Mode

■ 65 k to 72 k

The USB interface supports the Carkit UART mode (UART over

D+/D–) for non-USB serial data transfer. This mode is based on

the CEA-936A specification.

■ 35 kto 39 k

■ 99.96 k to 104.4 k (102 k2%)

■ 119 k to 132 k

In the Carkit UART mode, the output signaling voltage is 3.3 V.

When configured for the Carkit UART mode, TXD of UART

(output) is mapped to the D– line, and RXD of UART (input) is

mapped to the D+ line.

■ Higher than 220 k

In the Carkit UART mode, FX3 disables the USB transceiver and

D+ and D– pins serve as pass-through pins to connect to the

UART of the host processor. The Carkit UART signals may be

routed to the GPIF II interface or to GPIO[48] and GPIO[49], as

shown in Figure on page 8.

■ 431.2 k to 448.8 k (440 k2%)

FX3's charger detects a dedicated wall charger, Host/Hub

charger, and Host/Hub.

VBUS Overvoltage Protection

In this mode, FX3 supports a rate of up to 9600 bps.

The maximum input voltage on FX3's VBUS pin is 6 V. A charger

can supply up to 9 V on VBUS. In this case, an external

overvoltage protection (OVP) device is required to protect FX3

from damage on VBUS. Figure 3 shows the system application

diagram with an OVP device connected on VBUS. Refer to

Table 8 for the operating range of VBUS and VBATT.

Figure 4. Carkit UART Pass-through Block Diagram

Carkit UART Pass-through

UART_ TXD

TXD

RXD

RXD(DP)

TXD(DM)

(

)

Carkit UART Pass-through

Interface on GPIF II

UART_RXD

DP

USB PHY

DM

GPIO[48]

(UART_TX)

Carkit UART Pass-through

Interface on GPIOs

GPIO[49]

(UART_RX)

Document Number: 001-52136 Rev. *U

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CYUSB301X/CYUSB201X

GPIF II

CPU

The high-performance GPIF II interface enables functionality

similar to, but more advanced than, FX2LP’s GPIF and Slave

FIFO interfaces.

FX3 has an on-chip 32-bit, 200-MHz ARM926EJ-S core CPU.

The core has direct access to 16 KB of Instruction Tightly

Coupled Memory (TCM) and 8 KB of Data TCM. The

ARM926EJ-S core provides a JTAG interface for firmware

debugging.

The GPIF II is a programmable state machine that enables a

flexible interface that may function either as a master or slave in

industry-standard or proprietary interfaces. Both parallel and

serial interfaces may be implemented with GPIF II.

FX3 offers the following advantages:

■ Integrates 256/512 KB of embedded SRAM for code and data

and 8 KB of Instruction cache and Data cache.

Here is a list of GPIF II features:

■ Functions as master or slave

■ ImplementsefficientandflexibleDMAconnectivitybetweenthe

2

various peripherals (such as, USB, GPIF II, I S, SPI, UART,

■ Provides 256 firmware programmable states

■ Supports 8-bit, 16-bit, 24-bit, and 32-bit parallel data bus

■ Enables interface frequencies up to 100 MHz

2

I C), requiring firmware only to configure data accesses

between peripherals, which are then managed by the DMA

fabric.

■ Allows easy application development using industry-standard

development tools for ARM926EJ-S.

■ Supports 14 configurable control pins when a 32- bit data bus

is used. All control pins can be either input/output or bidirec-

tional.

Examples of the FX3 firmware are available with the Cypress

EZ-USB FX3 Development Kit.

■ Supports 16 configurable control pins when a 16/8 data bus is

used. Allcontrolpins can be either input/outputor bi-directional.

JTAG Interface

GPIF II state transitions are based on control input signals. The

control output signals are driven as a result of the GPIF II state

transitions. The INT# output signal can be controlled by GPIF II.

Refer to the GPIFII Designer tool. The GPIF II state machine’s

behavior is defined by a GPIF II descriptor. The GPIF II

descriptor is designed such that the required interface specifica-

tions are met. 8 KB of memory (separate from the 256/512 KB of

embedded SRAM) is dedicated to the GPIF II waveform where

the GPIF II descriptor is stored in a specific format.

FX3’s JTAG interface has a standard five-pin interface to connect

to a JTAG debugger in order to debug firmware through the

CPU-core's on-chip-debug circuitry.

Industry-standard debugging tools for the ARM926EJ-S core

can be used for the FX3 application development.

Other Interfaces

FX3 supports the following serial peripherals:

Cypress’s GPIFII Designer Tool enables fast development of

GPIF II descriptors and includes examples for common

interfaces.

■ SPI

■ UART

Example implementations of GPIF II are the asynchronous slave

FIFO and synchronous slave FIFO interfaces.

2

■ I C

2

■ I S

Slave FIFO interface

2

The SPI, UART, and I S interfaces are multiplexed on the serial

peripheral port.

The Slave FIFO interface signals are shown in Figure 5. This

interface allows an external processor to directly access up to

four buffers internal to FX3. Further details of the Slave FIFO

interface are described on page 24.

The CYUSB3012 and CYUSB3014 Pin List on page 15 shows

details of how these interfaces are multiplexed. Note that when

GPIF II is configured for a 32-bit data bus width (CYUSB3012

and CYUSB3014), then the SPI interface is not available.

Note Access to all 32 buffers is also supported over the slave

FIFO interface. For details, contact Cypress Applications

Support.

SPI Interface

Figure 5. Slave FIFO Interface

FX3 supports an SPI Master interface on the Serial Peripherals

port. The maximum operation frequency is 33 MHz.

SLCS#

PKTEND

The SPI controller supports four modes of SPI communication

(see SPI Timing Specification on page 40 for details on the

FLAGB

FLAGA

modes) with the Start-Stop clock. This controller is

a

External Master

(For example,

MCU/CPU/

A[1:0]

single-master controller with a single automated SSN control. It

supports transaction sizes ranging from four bits to 32 bits.

D[31:0]

EZ-USB FX3

FPGA/ASIC)

SLWR#

SLRD#

SLOE#

Note: Multiple Flags may be configured.

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CYUSB301X/CYUSB201X

UART Interface

Boot Options

The UART interface of FX3 supports full-duplex communication.

It includes the signals noted in Table 1.

FX3 can load boot images from various sources, selected by the

configuration of the PMODE pins. Following are the FX3 boot

options:

Table 1. UART Interface Signals

Signal

TX

Description

Output signal

Input signal

Flow control

■ Boot from USB

2

■ Boot from I C

RX

■ Boot from SPI (SPI devices supported are M25P32 (32 Mbit),

M25P16 (16 Mbit), M25P80 (8 Mbit), and M25P40 (4 Mbit)) or

their equivalents

CTS

RTS

■ Boot from GPIF II ASync ADMux mode

■ Boot from GPIF II Sync ADMux mode

■ Boot from GPIF II ASync SRAM mode

The UART is capable of generating a range of baud rates, from

300 bps to 4608 Kbps, selectable by the firmware. If flow control

is enabled, then FX3's UART only transmits data when the CTS

input is asserted. In addition to this, FX3’s UART asserts the RTS

output signal, when it is ready to receive data.

Table 2. FX3 Booting Options

2

[1]

I C Interface

PMODE[2:0]

F00

Boot From

Sync ADMux (16-bit)

2

FX3’s I C interface is compatible with the I C Bus Specification

Revision 3. This I C interface is capable of operating only as I C

master; therefore, it may be used to communicate with other I C

slave devices. For example, FX3 may boot from an EEPROM

2

F01

Async ADMux (16-bit)

USB boot

2

F11

2

F0F

Async SRAM (16-bit)

connected to the I C interface, as a selectable boot option.

2

F1F

I C, On Failure, USB Boot is Enabled

2

FX3’s I C Master Controller also supports multi-master mode

functionality.

2

1FF

I C only

2

0F1

SPI, On Failure, USB Boot is Enabled

The power supply for the I C interface is VIO5, which is a

separate power domain from the other serial peripherals. This

2

gives the I C interface the flexibility to operate at a different

Reset

voltage than the other serial interfaces.

2

Hard Reset

The I C controller supports bus frequencies of 100 kHz,

400 kHz, and 1 MHz. When VIO5 is 1.2 V, the maximum

operating frequency supported is 100 kHz. When VIO5 is 1.8 V,

2.5 V, or 3.3 V, the operating frequencies supported are 400 kHz

and 1 MHz. The I C controller supports clock-stretching to

enable slower devices to exercise flow control.

A hard reset is initiated by asserting the Reset# pin on FX3. The

specific reset sequence and timing requirements are detailed in

Figure 30 on page 42 and Table 19 on page 42. All I/Os are

tristated during a hard reset. Note however, that the on-chip

bootloader has control after a hard reset and it will configure I/O

signals depending on the selected boot mode; see AN76405 -

EZ-USB® FX3™ Boot Options for more details.

2

The I C interface’s SCL and SDA signals require external pull-up

resistors. The pull-up resistors must be connected to VIO5.

2

Soft Reset

I S Interface

2

In a soft reset, the processor sets the appropriate bits in the

PP_INIT control register. There are two types of Soft Reset:

FX3 has an I S port to support external audio codec devices.

2

FX3 functions as I S Master as transmitter only. The I S interface

consists of four signals: clock line (I2S_CLK), serial data line

(I2S_SD), word select line (I2S_WS), and master system clock

(I2S_MCLK). FX3 can generate the system clock as an output

on I2S_MCLK or accept an external system clock input on

I2S_MCLK.

■ CPU Reset – The CPU Program Counter is reset. Firmware

does not need to be reloaded following a CPU Reset.

■ Whole Device Reset – This reset is identical to Hard Reset.

■ The firmware must be reloaded following a Whole Device

Reset.

2

The sampling frequencies supported by the I S interface are

32 kHz, 44.1 kHz, and 48 kHz.

Note

1. F indicates Floating.

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Page 9 of 54

CYUSB301X/CYUSB201X

Clock inputs to FX3 must meet the phase noise and jitter require-

ments specified in Table 4 on page 10.

Clocking

FX3 allows either a crystal to be connected between the XTALIN

and XTALOUT pins or an external clock to be connected at the

CLKIN pin. The XTALIN, XTALOUT, CLKIN, and CLKIN_32 pins

can be left unconnected if they are not used.

The input clock frequency is independent of the clock and data

rate of the FX3 core or any of the device interfaces. The internal

PLL applies the appropriate clock multiply option depending on

the input frequency.

Crystal frequency supported is 19.2 MHz, while the external

clock frequencies supported are 19.2, 26, 38.4, and 52 MHz.

Table 3. Crystal/Clock Frequency Selection

Crystal/Clock

FX3 has an on-chip oscillator circuit that uses an external

19.2-MHz (±100 ppm) crystal (when the crystal option is used).

An appropriate load capacitance is required with a crystal. Refer

to the specification of the crystal used to determine the appro-

priate load capacitance. The FSLC[2:0] pins must be configured

appropriately to select the crystal- or clock-frequency option. The

configuration options are shown in Table 3.

FSLC[2]

FSLC[1]

FSLC[0]

Frequency

0

1

0

1

0

1

0

1

19.2-MHz crystal

19.2-MHz input CLK

26-MHz input CLK

38.4-MHz input CLK

52-MHz input CLK

Table 4. FX3 Input Clock Specifications

Specification

Parameter

Description

100-Hz offset

1-kHz offset

10-kHz offset

100-kHz offset

1-MHz offset

Units

Min

–

30

–

Max

–75

–104

–120

–128

–130

150

70

Phase noise

dB

Maximum frequency deviation

Duty cycle

–

ppm

%

Overshoot

3

–3

3

Undershoot

Rise time/fall time

–

ns

32-kHz Watchdog Timer Clock Input

FX3 includes a watchdog timer. The watchdog timer can be used to interrupt the ARM926EJ-S core, automatically wake up the FX3

in Standby mode, and reset the ARM926EJ-S core. The watchdog timer runs a 32-kHz clock, which may be optionally supplied from

an external source on a dedicated FX3 pin.

The firmware can disable the watchdog timer. Requirements for the optional 32-kHz clock input are listed in Table 5.

Table 5. 32-kHz Clock Input Requirements

Parameter

Duty cycle

Min

40

–

Max

60

Units

%

Frequency deviation

Rise time/fall time

±200

200

ppm

ns

–

Document Number: 001-52136 Rev. *U

Page 10 of 54

CYUSB301X/CYUSB201X

■ VBATT/VBUS: This is the 3.2-V to 6-V battery power supply

for the USB I/O and analog circuits. This supply powers the

USB transceiver through FX3's internal voltage regulator.

VBATT is internally regulated to 3.3 V.

Power

FX3 has the following power supply domains:

■ IO_VDDQ: This is a group of independent supply domains for

digitalI/Os.Thevoltagelevelonthesesuppliesis1.8 Vto3.3 V.

FX3 provides six independent supply domains for digital I/Os

listed as follows (see Table 7 on page 15 for details on each of

the power domain signals):

❐ VIO1: GPIF II I/O

❐ VIO2: IO2

Power Modes

FX3 supports the following power modes:

■ Normal mode: This is the full-functional operating mode. The

internal CPU clock and the internal PLLs are enabled in this

mode.

❐ VIO3: IO3

❐ Normal operating power consumption does not exceed the

2

sum of I Core max and I USB max (see Table 7 on page

❐ VIO4: UART-/SPI/I S

CC

15 for current consumption specifications).

2

❐ VIO5: I C and JTAG (supports 1.2 V to 3.3 V)

❐ The I/O power supplies VIO2, VIO3, VIO4, and VIO5 can be

turned off when the corresponding interface is not in use.

VIO1 cannot be turned off at any time if the GPIF II interface

is used in the application.

❐ CVDDQ: This is the supply voltage for clock and reset I/O. It

should be either 1.8 V or 3.3 V based on the voltage level of

the CLKIN signal.

❐ V_DD: This isthe supplyvoltage for the logic core. The nominal

supply-voltage level is 1.2 V. This supplies the core logic

circuits. The same supply must also be used for the following:

• AVDD: This is the 1.2-V supply for the PLL, crystal oscilla-

tor, and other core analog circuits

• U3TXVDDQ/U3RXVDDQ: These are the 1.2-V supply volt-

■ Low-power modes (see Table 6 on page 11):

❐ Suspend mode with USB 3.0 PHY enabled (L1)

❐ Suspend mode with USB 3.0 PHY disabled (L2)

❐ Standby mode (L3)

❐ Core power-down mode (L4)

ages for the USB 3.0 interface.

Table 6. Entry and Exit Methods for Low-Power Modes

Low-Power Mode

Characteristics

Methods of Entry

Methods of Exit

Suspend Mode with ■ The power consumption in this mode does ■ Firmware executing on

■ D+ transitioning to low

or high

USB 3.0 PHY

Enabled (L1)

not exceed ISB

ARM926EJ-S core can put FX3 into

suspend mode. For example, on

USB suspend condition, firmware

may decide to put FX3 into suspend

mode

1

■ USB3.0PHYisenabledandisinU3mode

(one of the suspend modes defined by the

USB 3.0 specification). This one block

alone is operational with its internal clock

while all other clocks are shut down

■ D- transitioning to low

or high

■ Impedance change on

OTG_ID pin

■ External Processor, through the use

of mailbox registers, can put FX3 into

suspend mode

■ Resume condition on

SSRX±

■ All I/Os maintain their previous state

■ Power supply for the wakeup source and

core power must be retained. All other

power domains can be turned on/off

individually

■ Detection of VBUS

■ Level detect on

UART_CTS

(programmable

polarity)

■ The states of the configuration registers,

buffer memory, and all internal RAM are

maintained

■ GPIF II interface

assertion of CTL[0]

■ All transactions must be completed before

FX3 enters Suspend mode (state of

outstanding transactions are not

preserved)

■ Assertion of RESET#

■ The firmware resumes operation from

where it was suspended (except when

woken up by RESET# assertion) because

the program counter does not reset

Document Number: 001-52136 Rev. *U

Page 11 of 54

CYUSB301X/CYUSB201X

Table 6. Entry and Exit Methods for Low-Power Modes (continued)

Low-Power Mode Characteristics

Suspend Mode with ■ The power consumption in this mode does ■ Firmware executing on

Methods of Entry

Methods of Exit

■ D+ transitioning to low

or high

USB 3.0 PHY

Disabled (L2)

not exceed ISB

ARM926EJ-S core can put FX3 into

suspend mode. For example, on

USB suspend condition, firmware

may decide to put FX3 into suspend

mode

2

■ USB 3.0 PHY is disabled and the USB

■ D- transitioning to low

or high

interface is in suspend mode

■ The clocks are shut off. The PLLs are

■ Impedance change on

disabled

OTG_ID pin

■ External Processor, through the use

of mailbox registers can put FX3 into

suspend mode

■ All I/Os maintain their previous state

■ Resume condition on

SSRX±

■ USB interface maintains the previous

state

■ Detection of VBUS

■ Power supply for the wakeup source and

core power must be retained. All other

power domains can be turned on/off

individually

■ Level detect on

UART_CTS

(programmable

polarity)

■ The states of the configuration registers,

buffer memory and all internal RAM are

maintained

■ GPIF II interface

assertion of CTL[0]

■ Assertion of RESET#

■ All transactions must be completed before

FX3 enters Suspend mode (state of

outstanding transactions are not

preserved)

■ The firmware resumes operation from

where it was suspended (except when

woken up by RESET# assertion) because

the program counter does not reset

Standby Mode (L3) ■ The power consumption in this mode does ■ Firmware executing on

■ Detection of VBUS

not exceed ISB3

ARM926EJ-S core or external

processorconfigurestheappropriate

register

■ Level detect on

UART_CTS

(Programmable

■ All configuration register settings and

program/data RAM contents are

preserved. However, data in the buffers or

other parts of the data path, if any, is not

guaranteed. Therefore, the external

processor should take care that the data

needed is read before putting FX3 into this

Standby Mode

Polarity)

■ GPIF II interface

assertion of CTL[0]

■ Assertion of RESET#

■ The program counter is reset after waking

up from Standby

■ GPIO pins maintain their configuration

■ Crystal oscillator is turned off

■ Internal PLL is turned off

■ USB transceiver is turned off

■ ARM926EJ-S core is powered down.

Upon wakeup, the core re-starts and runs

the program stored in the program/data

RAM

■ Power supply for the wakeup source and

core power must be retained. All other

power domains can be turned on/off

individually

Document Number: 001-52136 Rev. *U

Page 12 of 54

CYUSB301X/CYUSB201X

Table 6. Entry and Exit Methods for Low-Power Modes (continued)

Low-Power Mode Characteristics

Core Power Down ■ The power consumption in this mode does ■ Turn off V

Methods of Entry

Methods of Exit

■ Reapply VDD

■ Assertion of RESET#

DD

Mode (L4)

not exceed ISB

4

■ Core power is turned off

■ All buffer memory, configuration registers,

and the program RAM do not maintain

state. After exiting this mode, reload the

firmware

■ In this mode, all other power domains can

be turned on/off individually

Digital I/Os

EMI

FX3 meets EMI requirements outlined by FCC 15B (USA) and

EN55022 (Europe) for consumer electronics. FX3 can tolerate

EMI, conducted by the aggressor, outlined by these specifica-

tions and continue to function as expected.

FX3 has internal firmware-controlled pull-up or pull-down

resistors on all digital I/O pins. An internal 50-k resistor pulls

the pins high, while an internal 10-k resistor pulls the pins low

to prevent them from floating. The I/O pins may have the

following states:

System-level ESD

■ Tristated (High-Z)

FX3 has built-in ESD protection on the D+, D–, and GND pins on

the USB interface. The ESD protection levels provided on these

ports are:

■ Weak pull-up (via internal 50 k)

■ Pull-down (via internal 10 k)

■ Hold (I/O hold its value) when in low-power modes

■ ±2.2-kV human body model (HBM) based on JESD22-A114

Specification

■ The JTAG TDI, TMS, and TRST# signals have fixed 50-k

internal pull-ups, and the TCK signal has a fixed 10-k

pull-down resistor.

■ ±6-kV contact discharge and ±8-kV air gap discharge based

on IEC61000-4-2 level 3A

All unused I/Os should be pulled high by using the internal

pull-up resistors. All unused outputs should be left floating. All

I/Os can be driven at full-strength, three-quarter strength,

half-strength, or quarter-strength. These drive strengths are

configured separately for each interface.

■ ±8-kVContactDischargeand±15-kVAirGapDischargebased

on IEC61000-4-2 level 4C.

This protection ensures the device continues to function after

ESD events up to the levels stated in this section.

The SSRX+, SSRX–, SSTX+, and SSTX– pins only have up to

±2.2-kV HBM internal ESD protection.

GPIOs

EZ-USB enables a flexible pin configuration both on the GPIF II

and the serial peripheral interfaces. Any unused control pins

(except CTL[15]) on the GPIF II interface can be used as GPIOs.

Similarly, any unused pins on the serial peripheral interfaces may

be configured as GPIOs. See Pin Configurations for pin

configuration options.

All GPIF II and GPIO pins support an external load of up to 16 pF

for every pin.

Document Number: 001-52136 Rev. *U

Page 13 of 54

CYUSB301X/CYUSB201X

Pin Configurations

Figure 6. FX3 121-ball BGA Ball Map (Top View)

1

2

3

4

5

6

7

8

9

10

11

NC

U3VSSQ

VIO4

U3RXVDDQ

FSLC[0]

GPIO[ 55]

GPIO[51]

VSS

SSRXM

R_USB3

VDD

SSRXP

FSLC[1]

GPIO[ 57]

GPIO[53]

GPIO[49]

GPIO[ 41]

GPIO[30]

GPIO[ 31]

GPIO[34]

VSS

SSTXP

SSTXM

CVDDQ

XTALIN

CLKIN_32

FSLC[2]

TCK

AVDD

VSS

DP

DM

A

B

C

D

E

F

G

H

J

U3TXVDDQ

RESET#

GPIO[56]

GPIO[48]

GPIO[ 46]

GPIO[25]

GPIO[ 29]

GPIO[28]

GPIO[27]

VDD

AVSS

VSS

VDD

TDO

TRST#

VIO5

O[60]

VBUS

VDD

GPIO[ 54]

GPIO[50]

GPIO[ 47]

VIO2

XTALOUT

CLKIN

R_USB2

VSS

OTG_ID

GPIO[52]

VIO3

I2C_GPIO[58] I2C_GPIO[59]

TDI

TMS

VDD

GPIO[ 1]

GPIO[4]

GPIO[ 7]

GPIO[9]

GPIO[13]

VIO1

VBATT

GPIO[ 0]

GPIO[3]

GPIO[ 6]

GPIO[8]

GPIO[12]

GPIO[11]

GPIO[ 45]

GPIO[42]

GPIO[ 39]

GPIO[36]

GPIO[33]

VSS

GPIO[ 44]

GPIO[43]

GPIO[ 40]

GPIO[37]

VSS

GPIO[ 2]

GPIO[21]

GPIO[ 20]

GPIO[19]

GPIO[18]

VDD

GPIO[ 5]

GPIO[15]

GPIO[ 24]

GPIO[14]

GPIO[17]

INT#

VSS

GPIO[22]

GPIO[ 26]

GPIO[16]

GPIO[23]

VSS

VDD

VIO1

VDD

GPIO[38]

GPIO[35]

VSS

GPIO[10]

VSS

K

L

VSS

GPIO[32]

Figure 7. FX3 131-Ball WLCSP Ball Map (Bottom View)

12

11

10

9

8

7

6

5

4

3

2

1

VSS

VIO4

VIO3

SSRXM

SSTXM

FSLC[0]

FSLC[2]

CVDDQ

AVSS

AVDD

DP

NC

VSS

DM

NC

VDD

TRST#

A

B

C

GPIO[55]

GPIO[56]

SSRXP

R_USB3

U3VSSQ

SSTXP

XTALIN

CLKIN_32

XTALOUT

CLKIN

R_USB2

OTG_ID

U3RXVDDQ

U3TXVDDQ

TDO

I2C_GPIO[58

]

I2C_GPIO[59

]

GPIO[49]

GPIO[50]

GPIO[53]

GPIO[54]

RESET#

VDD

TMS

VIO5

TCK

VSS

D

E

F

G

H

J

GPIO[57]

VSS

GPIO[48]

GPIO[46]

GPIO[43]

GPIO[40]

GPIO[38]

GPIO[34]

VSS

GPIO[51]

GPIO[47]

GPIO[44]

GPIO[41]

GPIO[37]

GPIO[33]

VDD

GPIO[52]

FSLC[1]

O[60]

TDI

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

GPIO[3]

GPIO[4]

GPIO[7]

GPIO[12]

GPIO[15]

GPIO[24]

GPIO[17]

VBATT

GPIO[1]

VBUS

GPIO[0]

GPIO[2]

VIO1

VIO2

GPIO[45]

GPIO[42]

GPIO[36]

GPIO[32]

GPIO[30]

VSS

VDD

VSS

GPIO[9]

GPIO[14]

GPIO[19]

INT#

GPIO[6]

GPIO[8]

GPIO[10]

GPIO[11]

GPIO[13]

VSS

GPIO[39]

GPIO[31]

GPIO[28]

GPIO[29]

VSS

GPIO[20]

GPIO[25]

GPIO[16]

GPIO[23]

GPIO[18]

GPIO[22]

GPIO[21]

VSS

VIO2

GPIO[27]

GPIO[26]

VIO1

GPIO[5]

VSS

GPIO[35]

VDD

K

L

VIO1

VSS

Note No ball is populated at location A9.

Figure 8. FX3 Hi-Speed 121-Ball BGA Ball Map (Top View)

1

2

3

4

5

6

7

8

9

10

11

NC

U3VSSQ

VIO4

VDD

NC

AVDD

VSS

DP

DM

A

B

C

D

E

F

G

H

J

FSLC[0]

GPIO[55]

GPIO[51]

VSS

NC

FSLC[1]

GPIO[57]

GPIO[53]

GPIO[49]

GPIO[41]

GPIO[30]

GPIO[31]

GPIO[34]

VSS

VDD

CVDDQ

XTALIN

CLKIN_32

FSLC[2]

TCK

AVSS

VSS

VDD

TDO

TRST#

VIO5

O[60]

VBUS

VDD

GPIO[54]

GPIO[50]

GPIO[47]

VIO2

VDD

RESET#

GPIO[56]

GPIO[48]

GPIO[46]

GPIO[25]

GPIO[29]

GPIO[28]

GPIO[27]

VDD

XTALOUT

CLKIN

R_USB2

VSS

OTG_ID

GPIO[52]

VIO3

I2C_GPIO[58] I2C_GPIO[59]

TDI

TMS

VDD

GPIO[1]

GPIO[4]

GPIO[7]

GPIO[9]

GPIO[13]

VIO1

VBATT

GPIO[0]

GPIO[3]

GPIO[6]

GPIO[8]

GPIO[12]

GPIO[11]

GPIO[45]

GPIO[42]

GPIO[39]

GPIO[36]

GPIO[33]

VSS

GPIO[44]

GPIO[43]

GPIO[40]

GPIO[37]

VSS

GPIO[2]

GPIO[21]

GPIO[20]

GPIO[19]

GPIO[18]

VDD

GPIO[5]

GPIO[15]

GPIO[24]

GPIO[14]

GPIO[17]

INT#

VSS

GPIO[22]

GPIO[26]

GPIO[16]

GPIO[23]

VSS

VDD

VIO1

VDD

GPIO[38]

GPIO[35]

VSS

GPIO[10]

VSS

K

L

VSS

GPIO[32]

Document Number: 001-52136 Rev. *U

Page 14 of 54

CYUSB301X/CYUSB201X

Pin Description

Table 7. CYUSB3012 and CYUSB3014 Pin List

Power

BGA WLCSP

I/O

Name

Description

Domain

GPIF II Interface

Slave FIFO Interface

DQ[0]

F10

F9

F1

F2

G1

E3

F3

J1

VIO1

I/O

GPIO[0]

GPIO[1]

GPIO[2]

GPIO[3]

GPIO[4]

GPIO[5]

GPIO[6]

GPIO[7]

GPIO[8]

GPIO[9]

GPIO[10]

GPIO[11]

GPIO[12]

GPIO[13]

GPIO[14]

GPIO[15]

GPIO[16]

GPIO[17]

GPIO[18]

GPIO[19]

GPIO[20]

GPIO[21]

GPIO[22]

GPIO[23]

GPIO[24]

GPIO[25]

GPIO[26]

GPIO[27]

GPIO[28]

GPIO[29]

GPIO[30]

GPIO[31]

GPIO[32]

INT#

DQ[0]

DQ[1]

F7

DQ[2]

G10

G9

F8

DQ[3]

DQ[4]

DQ[5]

H10

H9

J10

J9

G2

G3

H2

G4

J2

DQ[6]

DQ[7]

DQ[8]

DQ[9]

K11

L10

K10

K9

J8

DQ[10]

DQ[11]

DQ[12]

DQ[13]

DQ[14]

DQ[15]

CLK

K2

H3

L2

H4

J3

DQ[11]

DQ[12]

DQ[13]

DQ[14]

G8

J6

DQ[15]

K6

L3

H5

J4

PCLK

K8

K7

J7

CTL[0]

SLCS#

SLWR#

SLOE#

SLRD#

FLAGA

FLAGB

GPIO

CTL[1]

CTL[2]

H7

G7

G6

K6

H8

G5

H6

K5

J5

H6

K5

J5

CTL[3]

CTL[4]

CTL[5]

L6

K3

J6

CTL[6]

CTL[7]

PKTEND#

GPIO

CTL[8]

K7

J7

CTL[9]

GPIO

CTL[10]

GPIO

K8

L8

L9

J8

CTL[11]

A1

H5

G4

H4

L4

CTL[12]

A0

PMODE[0]

PMODE[1]

PMODE[0]

PMODE[1]

PMODE[2]

CTL[15]

K9

K4

PMODE[2]

L8

INT#/CTL[15]

32-bit Data 16 - bit Data Bus + 16 - bit Data

16 - bit

Data Bus +

UART+GPIO SPI+GPIO

16 - bit Data

Bus +

I2S+GPIO

GPIO

only

Bus

UART+SPI+I2S

Bus +

K2

J4

K1

J2

J3

K10

K11

K12

J9

VIO2

I/O

GPIO[33]

GPIO[34]

GPIO[35]

GPIO[36]

GPIO[37]

DQ[16]

DQ[17]

DQ[18]

DQ[19]

DQ[20]

GPIO

J10

Document Number: 001-52136 Rev. *U

Page 15 of 54

CYUSB301X/CYUSB201X

Table 7. CYUSB3012 and CYUSB3014 Pin List (continued)

Power

BGA WLCSP

I/O

Name

Description

Domain

VIO2

VIO3

VIO4

J1

H2

H3

F4

G2

G3

F3

F2

F5

E1

E5

E4

D1

D2

D3

D4

C1

C2

D5

C4

J11

H8

I/O

GPIO[38]

GPIO[39]

GPIO[40]

GPIO[41]

GPIO[42]

GPIO[43]

GPIO[44]

GPIO[45]

GPIO[46]

GPIO[47]

GPIO[48]

GPIO[49]

GPIO[50]

GPIO[51]

GPIO[52]

GPIO[53]

GPIO[54]

GPIO[55]

GPIO[56]

GPIO[57]

DQ[21]

DQ[22]

GPIO

H11

H10

H9

DQ[23]

GPIO

DQ[24]

GPIO

DQ[25]

GPIO

G11

G10

G09

F11

F10

E11

D12

D11

E10

E9

DQ[26]

GPIO

DQ[27]

GPIO

DQ[28]

UART_RT S

UART_CT S

UART_TX

UART_R X

I2S_CLK

I2S_SD

GPIO

DQ[29]

GPIO

DQ[30]

GPIO

DQ[31]

GPIO

I2S_CLK

I2S_SD

I2S_WS

UART_RTS

UART_CTS

UART_TX

UART_RX

I2S_MCLK

GPIO

I2S_WS

SPI_SCK

SPI_SSN

SPI_MIS O

SPI_MOS I

I2S_MCL K

GPIO

D10

D9

UART_RTS

UART_CTS

UART_TX

UART_RX

GPIO

SPI_SCK

SPI_SSN

SPI_MISO

SPI_MOSI

GPIO

I2S_CLK

I2S_SD

I2S_WS

I2S_MCL K

B12

C12

E12

USB Port

CYUSB301X

CYUSB201X

A3

A4

A6

A5

B3

C9

A9

A10

C8

A10

B10

A8

U3RXVD

DQ

I

SSRXM

SSRXP

SSTXM

SSTXP

R_usb3

OTG_ID

DP

SSRX-

NC

U3RXVD

DQ

I

SSRX+

SSTX-

SSTX+

NC

U3TXVD

DQ

O

B8

U3TXVD

DQ

O

B9

U3TXVD

DQ

I/O

I

Precision resistor for USB 3.0 (Connect a 200

±1% resistor between this pin and GND)

C3

A4

VBUS/

VBATT

OTG_ID

VBUS/V

BATT

I/O

D+

D–

A2

VBUS/V

BATT

DM

B3

VBUS/VBAT

T

R_usb2

Precision resistor for USB 2.0 (Connect a 6.04 k ±1% resistor between this pin and GND)

Clock and Reset

FSLC[0]

B2

C6

C7

B4

E6

D7

A7

B6

B5

F9

B7

C5

CVDDQ

AVDD

I

FSLC[0]

XTALIN

XTALOUT

FSLC[1]

FSLC[2]

CLKIN

I/O

XTALIN

AVDD

I/O

XTALOUT

FSLC[1]

CVDDQ

I

FSLC[2]

CLKIN

Document Number: 001-52136 Rev. *U

Page 16 of 54

CYUSB301X/CYUSB201X

Table 7. CYUSB3012 and CYUSB3014 Pin List (continued)

Power

BGA WLCSP

I/O

Name

Description

Domain

CVDDQ

D6

C5

C6

D8

I

CLKIN_32

RESET#

CLKIN_32

RESET#

I2C and JTAG

I²C_SCL

D9

D6

D2

VIO5

I/O

I2C_GPIO[58

]

D10

I2C_GPIO[59

]

I²C_SDA

E7

C10

B11

E8

F8

C2

C1

D5

D3

E8

VIO5

I

O

I

TDI

TDO

TDI

TDO

TRST#

TMS

TRST#

I

TMS

F6

I

TCK

D11

O

O[60]

Charger detect output

Power

–

E10

B10

–

E2

B1

–

PWR

VBATT

VDD

–

A1

VDD

–

A1

E11

D8

H11

E2

L9

C9

E1

U3VSSQ

VBUS

VSS

–

C4

H1

K1

–

VIO1

VSS

–

L4

VIO1

VSS

–

G1

–

L5

–

L7

VIO1

VSS

–

L1

–

F1

J12

H12

G12

C11

F12

B11

A11

A12

C7

C8

C10

D4

A3

VIO2

VSS

–

G11

–

VIO2

VIO3

VSS

–

E3

L1

–

B1

L6

VIO4

VSS

–

VSS

–

B6

B5

A2

C11

L11

A7

B7

C3

B8

E9

CVDDQ

–

PWR U3TXVDDQ

PWR U3RXVDDQ

–

PWR

VIO5

VSS

–

A5

AVDD

AVSS

VDD

VSS

–

A6

–

F4

–

D1

F5

–

VDD

–

Document Number: 001-52136 Rev. *U

Page 17 of 54

CYUSB301X/CYUSB201X

Table 7. CYUSB3012 and CYUSB3014 Pin List (continued)

Power

Domain

BGA WLCSP

I/O

Name

Description

B9

F11

–

E4

F6

–

PWR

–

VSS

VDD

VSS

VDD

VSS

VDD

VSS

NC

–

E5

F7

GND

–

E6

E7

G6

D7

L10

L12

H7

G7

L11

G8

G5

B4

B2

GND

–

GND

H1

L7

J11

L5

K4

L3

K3

L2

A8

–

No Connect

A11

–

NC

Document Number: 001-52136 Rev. *U

Page 18 of 54

CYUSB301X/CYUSB201X

■ Additional ESD protection levels on D+, D–, and GND pins, and

serial peripheral pins

Electrical Specifications

Absolute Maximum Ratings

■ ± 6-kV contact discharge, ± 8-kV air gap discharge based on

IEC61000-4-2 level 3A, ± 8-kV contact discharge, and ± 15-kV

air gap discharge based on IEC61000-4-2 level 4C

Exceeding maximum ratings may shorten the useful life of the

device.

Storage temperature .................................... –65 °C to +150 °C

Latch-up current .........................................................> 200 mA

Ambient temperature with

power supplied (Industrial) ............................ –40 °C to +85 °C

Maximum output short-circuit current for all I/Os

(cumulative)..................................................................–100 mA

Ambient temperature with

power supplied (Commercial) ............................. 0 °C to +70 °C

Maximum output current per I/O

(source or sink).......................... ......................................20 mA

Supply voltage to ground potential

Operating Conditions

V

, A

......................................................................1.25 V

DD VDDQ

T (ambient temperature under bias)

A

V

,V , V , V , V ................................................3.6 V

IO5

IO1 IO2

IO3

IO4

Industrial ........................................................ –40 °C to +85 °C

Commercial ....................................................... 0 °C to +70 °C

U3TX

, U3RX

...................................................1.25 V

VDDQ

DC input voltage to any input pin ........................... .V + 0.3 V

CC

V

, A

, U3TX

, U3RX

VDDQ VDDQ

DD VDDQ

DC voltage applied to

outputs in high Z state ............................................ V + 0.3 V

Supply voltage ..................................................1.15 V to 1.25 V

CC

V

supply voltage ...............................................3.2 V to 6 V

(VCC is the corresponding I/O voltage)

BATT

, V , V , V , C

VDDQ

Static discharge voltage ESD protection levels:

IO1

IO2

IO3

IO4

Supply voltage ......................................................1.7 V to 3.6 V

supply voltage ............................................ 1.15 V to 3.6 V

■ ± 2.2-kV HBM based on JESD22-A114

V

IO5

DC Specifications

Table 8. DC Specifications

Parameter

Description

Core voltage supply

Min

1.15

1.7

Max

Units

Notes

V

1.25

3.6

6

V

1.2-V typical

DD

A

Analog voltage supply

VDD

V

GPIF II I/O power supply domain

IO2 power supply domain

IO3 power supply domain

UART/SPI/I2S power supply domain

USB voltage supply

1.8-, 2.5-, and 3.3-V typical

3.7-V typical

IO1

V

1.7

IO2

1.7

IO3

1.7

IO4

3.2

BATT

BUS

USB voltage supply

4.0

6

5-V typical

1.2-V typical. A 22-µF bypass capacitor is

required on this power supply.

N/A for CYUSB201X

U3TX

USB 3.0 1.2-V supply

1.15

1.25

V

VDDQ

1.2-V typical. A 22-µF bypass capacitor is

required on this power supply.

N/A for CYUSB201X

U3RX

USB 3.0 1.2-V supply

Clock voltage supply

C

1.7

3.6

V

1.8-, 3.3-V typical

VDDQ

2

V

I C and JTAG voltage supply

1.15

1.2-, 1.8-, 2.5-, and 3.3-V typical

IO5

IH1

0.625 ×

VCC

For 2.0 V  V  3.6 V (except USB port).

CC

V

Input HIGH voltage 1

VCC + 0.3

V

VCC is the corresponding I/O voltage supply.

For 1.7 V  V 2.0 V

CC

V

Input HIGH voltage 2

Input LOW voltage

VCC – 0.4 VCC + 0.3

–0.3 0.25 × VCC

V

(except USB port). VCC is the corresponding

I/O voltage supply.

IH2

VCC is the corresponding I/O voltage supply.

IL

Document Number: 001-52136 Rev. *U

Page 19 of 54

CYUSB301X/CYUSB201X

Table 8. DC Specifications (continued)

Parameter

Description

Output HIGH voltage

Min

Max

Units

Notes

I

(max) = –100 µA tested at quarter drive

strength. VCC is the corresponding I/O

voltage supply.

OH

V

0.9 × VCC

–

V

OH

I

(min) = +100 µA tested at quarter drive

OL

Output LOW voltage

–

0.1 × VCC

V

strength. VCC is the corresponding I/O

voltage supply.

OL

All I/O signals held at V

(For I/Os with a pull-up or pull-down resistor

connected, the leakage current increases by

DDQ

Input leakage current for all pins

except

SSTXP/SSXM/SSRXP/SSRXM

I

–1

1

µA

IX

V

/R or V

/R

DDQ pu

DDQ PD

Output High-Z leakage current for all

pins except SSTXP/ SSXM/

SSRXP/SSRXM

µA All I/O signals held at V

OZ

DDQ

Core and analog voltage operating

current

I

Core

USB

–

200

60

mA Total current through A

, V

CC

VDD DD

USB voltage supply operating current

mA

–

CC

Core current: 1.5 mA

I/O current: 20 µA

USB current: 2 mA

For typical PVT (typical silicon, all power

supplies at their respective nominal levels at

25 °C)

Total suspend current during

suspend mode with USB 3.0 PHY

enabled (L1)

I

–

mA

SB1

SB2

SB3

SB4

Core current: 250 µA

I/O current: 20 µA

USB current: 1.2 mA

For typical PVT (Typical silicon, all power

supplies at their respective nominal levels at

25 °C)

Total suspend current during

suspend mode with USB 3.0 PHY

disabled (L2)

mA

µA

Core current: 60 µA

I/O current: 20 µA

USB current: 40 µA

For typical PVT (typical silicon, all power

supplies at their respective nominal levels at

25 °C)

Total standby current during standby

mode (L3)

Core current: 0 µA

I/O current: 20 µA

USB current: 40 µA

For typical PVT (typical silicon, all power

supplies at their respective nominal levels at

25 °C)

Total standby current during core

power-down mode (L4)

–

Voltage ramp rate on core and I/O

supplies

V

0.2

50

V/ms Voltage ramp must be monotonic

RAMP

Noise level permitted on V and I/O

supplies

Max p-p noise level permitted on all supplies

mV

DD

V

–

100

20

N

except A

VDD

Noise level permitted on A

supply

mV Max p-p noise level permitted on A

VDD

N_AVDD

VDD

Document Number: 001-52136 Rev. *U

Page 20 of 54

CYUSB301X/CYUSB201X

AC Timing Parameters

GPIF II Timing

Figure 9. GPIF II Timing in Synchronous Mode

tCLKH tCLKL

CLK

tCLK

tCO

tHZ

tCOE

tDS tDH

tDOH

tLZ

Data1

( OUT)

Data2

( OUT)

DQ- [31:0]

Data(IN)

tS tH

CTL(IN)

tCTLO

tCOH

CTL( OUT)

[2]

Table 9. GPIF II Timing Parameters in Synchronous Mode

Parameter Description

Frequency

Min

Max

100

–

Units

MHz

ns

Interface clock frequency

Interface clock period

Clock high time

–

10

4

tCLK

tCLKH

tCLKL

tS

–

ns

Clock low time

4

–

ns

CTL input to clock setup time

CTL input to clock hold time

Data in to clock setup time

Data in to clock hold time

2

–

ns

tH

0.5

2

–

ns

tDS

–

ns

tDH

tCO

0.5

–

ns

Clock to data out propagation delay when DQ bus is already in output direction

7

ns

Clock to data out propagation delay whenDQ lines change to output from tristate

and valid data is available on the DQ bus

tCOE

–

9

ns

tCTLO

tDOH

tCOH

tHZ

Clock to CTL out propagation delay

Clock to data out hold

Clock to CTL out hold

Clock to high-Z

–

2

0

–

0

8

–

8

–

ns

tLZ

Clock to low-Z

Note

2. All parameters guaranteed by design and validated through characterization.

Document Number: 001-52136 Rev. *U

Page 21 of 54

CYUSB301X/CYUSB201X

Figure 10. GPIF II Timing in Asynchronous Mode

tAH

tDH/

tDS/ tAS

DATA/ ADDR

DATA IN

tCHZ

tCTLassert_DQlatch

tCTLdeassert_DQlatch

CTL#

(I/P, ALE/ DLE)

tAA/tDO

tCHZ/tOEHZ

tCLZ/ tOELZ

DATA OUT

CTL#

(I/P, non ALE/ DLE

tCTLdeassert

tCTLassert

tCTLalpha

tCTLbeta

ALPHA

O/P

BETA

O/P

1

tCTLassert

tCTLdeassert

tCTL#

(O/P)

1. n is an integer >= 0

tDST

tDHT

DATA/

ADDR

tCTLdeassert_DQassert

tCTLassert_DQassert

CTL#

I/P (non DLE/ALE)

Figure 11. GPIF II Timing in Asynchronous DDR Mode

tDS

tCTLdeassert_DqlatchDDR

tCTLassert_DQlatchDDR

CTL#

(I/P)

tDS

tDH

DATA IN

Document Number: 001-52136 Rev. *U

Page 22 of 54

CYUSB301X/CYUSB201X

[3, 4]

Table 10. GPIF II Timing in Asynchronous Mode

Note The following parameters assume one state transition

Parameter Description

Min

2.3

2

Max

Units

ns

tDS

tDH

tAS

tAH

Data In to DLE setup time. Valid in DDR async mode.

Data In to DLE hold time. Valid in DDR async mode.

Address In to ALE setup time

–

ns

2.3

2

ns

Address In to ALE hold time

ns

CTL I/O asserted width for CTRL inputs without DQ input association

and for outputs.

tCTLassert

7

–

ns

CTL I/O deasserted width for CTRL inputs without DQ input associ-

ation and for outputs.

tCTLdeassert

CTL asserted pulse width for CTL inputs that signify DQ inputs valid

at the asserting edge but do not employ in-built latches (ALE/DLE) for

those DQ inputs.

tCTLassert_DQassert

tCTLdeassert_DQassert

tCTLassert_DQdeassert

20

7

–

ns

CTL deasserted pulse width for CTL inputs that signify DQ input valid

at the asserting edge but do not employ in-built latches (ALE/DLE) for

those DQ inputs.

CTL asserted pulse width for CTL inputs that signify DQ inputs valid

at the deasserting edge but do not employ in-built latches (ALE/DLE)

for those DQ inputs.

7

CTL deasserted pulse width for CTL inputs that signify DQ inputs valid

tCTLdeassert_DQdeassert at the deasserting edge but do not employ in-built latches (ALE/DLE)

for those DQ inputs.

20

7

CTL asserted pulse width for CTL inputs that employ in-built latches

(ALE/DLE) to latch the DQ inputs. In this non-DDR case, in-built

latches are always close at the deasserting edge.

tCTLassert_DQlatch

CTL deasserted pulse width for CTL inputs that employ in-built latches

(ALE/DLE) to latch the DQ inputs. In this non-DDR case, in-built

latches always close at the deasserting edge.

tCTLdeassert_DQlatch

10

CTL asserted pulse width for CTL inputs that employ in-built latches

(DLE) to latch the DQ inputs in DDR mode.

tCTLassert_DQlatchDDR

tCTLdeassert_DQlatchDDR

10

–

ns

CTL deasserted pulse width for CTL inputs that employ in-built latches

(DLE) to latch the DQ inputs in DDR mode.

DQ/CTL input to DQ output time when DQ change or CTL change

needs to be detected and affects internal updates of input and output

DQ lines.

tAA

–

30

25

ns

CTL to data out when the CTL change merely enables the output flop

update whose data was already established.

tDO

CTL designated as OE to low-Z. Time when external devices should

stop driving data.

tOELZ

tOEHZ

tCLZ

0

8

0

–

8

–

ns

CTL designated as OE to high-Z

CTL (non-OE) to low-Z. Time when external devices should stop

driving data.

tCHZ

CTL (non-OE) to high-Z

30

–

30

25

30

–

ns

tCTLalpha

tCTLbeta

tDST

CTL to alpha change at output

CTL to beta change at output

–

Addr/data setup when DLE/ALE not used

Addr/data hold when DLE/ALE not used

2

tDHT

20

–

Notes

3. All parameters guaranteed by design and validated through characterization.

4. "alpha" output corresponds to "early output" and "beta" corresponds to "delayed output". Please refer to the GPIFII Designer Tool for the use of these outputs.

Document Number: 001-52136 Rev. *U

Page 23 of 54

CYUSB301X/CYUSB201X

FLAG Usage:

Slave FIFO Interface

The FLAG signals are monitored for flow control by the external

processor. FLAG signals are outputs from FX3 that may be

configured to show empty, full, or partial status for a dedicated

thread or the current thread that is addressed.

Synchronous Slave FIFO Read Sequence Description

■ FIFO address is stable and SLCS is asserted

■ FLAG indicates FIFO not empty status

Socket Switching Delay (Tssd):

■ SLOE is asserted. SLOE is an output-enable only, whose sole

The socket-switching delay is measured from the time

EPSWITCH# is asserted by the master, with the new socket

address on the address bus, to the time the

Current_Thread_DMA_Ready flag is asserted. For the Producer

socket, the flag is asserted when it is ready to receive data in the

DMA buffer. For the Consumer socket, the flag is asserted when

it is ready to drive data out of the DMA buffer. For a synchronous

slave FIFO interface, the switching delay is measured in the

number of GPIF interface clock cycles; for an asynchronous

slave FIFO interface, in PIB clock cycles. This is applicable only

for the 5-bit Slave FIFO interface; there is no socket-switching

delay in FX3's 2-bit Slave FIFO interface, which makes use of

thread switching in the GPIF™ II state machine.

function is to drive the data bus.

■ SLRD is asserted

The FIFO pointer is updated on the rising edge of the PCLK,

while the SLRD is asserted. This starts the propagation of data

from the newly addressed location to the data bus. After a propa-

gation delay of tco (measured from the rising edge of PCLK), the

new data value is present. N is the first data value read from the

FIFO. To have data on the FIFO data bus, SLOE must also be

asserted.

The same sequence of events is applicable for a burst read.

Note For burst mode, the SLRD# and SLOE# are asserted

during the entire duration of the read. When SLOE# is asserted,

the data bus is driven (with data from the previously addressed

FIFO). For each subsequent rising edge of PCLK, while the

SLRD# is asserted, the FIFO pointer is incremented and the next

data value is placed on the data bus.

Figure 12. Synchronous Slave FIFO Read Mode

Synchronous Read Cycle Timing

t_CYC

PCLK

t_CHt_CL

ACCD

t

SLCS

t_AS

t_AH

FIFO ADDR

An

Am

t_RDH

t_RDS

SLRD

SLOE

Tssd

ACCD

t

Tssd

t_CFLG

FLAGA

(dedicated thread Flag for An )

( 1 = Not Empty 0 = Empty )

t_CFLG

FLAGB

(dedicated thread Flag for Am )

( 1 = Not Empty 0 = Empty )

t_CDH

t_OELZ

t_OEZ

t_CO

t_OEZ

High-Z

Data

driven:D_N(An

DN (An)

D ( Am)

N

Data Out

DN+2 (Am)

D^N+1(Am)

)

SLWR( HIGH)

Document Number: 001-52136 Rev. *U

Page 24 of 54

CYUSB301X/CYUSB201X

Synchronous Slave FIFO Write Sequence Description

■ FIFO address is stable and the signal SLCS# is asserted

■ External master or peripheral outputs the data to the data bus

■ SLWR# is asserted

Short Packet: A short packet can be committed to the USB host

by using the PKTEND#. The external device or processor should

be designed to assert the PKTEND# along with the last word of

data and SLWR# pulse corresponding to the last word. The

FIFOADDR lines must be held constant during the PKTEND#

assertion.

■ While the SLWR# is asserted, data is written to the FIFO and

on the rising edge of the PCLK, the FIFO pointer is incremented

Zero-Length Packet: The external device or processor can

signal a Zero-Length Packet (ZLP) to FX3 simply by asserting

PKTEND#, without asserting SLWR#. SLCS# and address must

be driven as shown in Figure 13.

■ The FIFO flag is updated after a delay of t

from the rising

WFLG

edge of the clock

The same sequence of events is also applicable for burst write

Note For the burst mode, SLWR# and SLCS# are asserted for

the entire duration, during which all the required data values are

written. In this burst write mode, after the SLWR# is asserted, the

data on the FIFO data bus is written to the FIFO on every rising

edge of PCLK. The FIFO pointer is updated on each rising edge

of PCLK.

Figure 13. Synchronous Slave FIFO Write Mode

Synchronous Write Cycle Timing

t_CYC

PCLK

t_CHt_CL

SLCS

t_AH

t_AS

Am

An

FIFO ADDR

SLWR

Tssd

t_WRS

t_WRH

t_CFLG

tFAD

FLAGA

dedicated thread FLAG for An

( 1 = Not Full0= Full)

Tssd

t_CFLG

tFAD

FLAGB

current thread FLAG for Am

( 1 = Not Full0= Full)

t_DSt_DH

t_DH

D_N(Am) D_N+1(Am)

D_N+2(Am)

D_N(An)

DataIN

High-Z

t

_PESt_PEH

PKTEND

SLOE

(HIGH)

Document Number: 001-52136 Rev. *U

Page 25 of 54

CYUSB301X/CYUSB201X

Figure 14. Synchronous Slave FIFO ZLP Write Cycle Timing

Synchronous ZLP Write Cycle Timing

t_CYC

PCLK

t_CHt_CL

SLCS

t_AH

t_AS

An

FIFO ADDR

SLWR

(HIGH)

t

_PESt_PEH

PKTEND

t_CFLG

FLAGA

dedicated thread FLAG for An

(1 = Not Full 0= Full)

FLAGB

current thread FLAG for Am

(1 = Not Full 0= Full)

High-Z

Data IN

SLOE

(HIGH)

[5]

Table 11. Synchronous Slave FIFO Parameters

Parameter

FREQ

Description

Min

–

Max

100

–

Units

Interface clock frequency

Clock period

MHz

tCYC

tCH

10

4

ns

Clock high time

–

ns

tCL

Clock low time

4

–

ns

tRDS

tRDH

tWRS

tWRH

tCO

SLRD# to CLK setup time

SLRD# to CLK hold time

SLWR# to CLK setup time

SLWR# to CLK hold time

Clock to valid data

2

–

ns

0.5

2

–

ns

–

ns

0.5

–

ns

7

ns

tDS

Data input setup time

CLK to data input hold

Address to CLK setup time

CLK to address hold time

SLOE# to data low-Z

2

–

ns

tDH

0.5

2

–

ns

tAS

–

ns

tAH

0.5

0

–

ns

tOELZ

tCFLG

tOEZ

tPES

tPEH

tCDH

tSSD

tACCD

tFAD

–

ns

CLK to flag output propagation delay

SLOE# deassert to Data Hi Z

PKTEND# to CLK setup

–

8

ns

–

8

ns

2

–

CLK to PKTEND# hold

0.5

2

–

ns

CLK to data output hold

–

ns

Socket switching delay

2

68

2

Clock cycles

Latency from SLRD# to Data

Latency from SLWR# to FLAG

2

3

Note Three-cycle latency from ADDR to DATA/FLAGS.

Note

5. All parameters guaranteed by design and validated through characterization.

Document Number: 001-52136 Rev. *U

Page 26 of 54

CYUSB301X/CYUSB201X

Asynchronous Slave FIFO Read Sequence Description

■ FIFO address is stable and the SLCS# signal is asserted.

■ SLOE# is asserted. This results in driving the data bus.

■ SLRD # is asserted.

In Figure 15, data N is the first valid data read from the FIFO. For

data to appear on the data bus during the read cycle, SLOE#

must be in an asserted state. SLRD# and SLOE# can also be

tied.

The same sequence of events is also shown for a burst read.

Note In the burst read mode, during SLOE# assertion, the data

bus is in a driven state (data is driven from a previously

addressed FIFO). After assertion of SLRD# data from the FIFO

is driven on the data bus (SLOE# must also be asserted). The

FIFO pointer is incremented after deassertion of SLRD#.

■ Data from the FIFO is driven after assertion of SLRD#. This

data is valid after a propagation delay of tRDO from the falling

edge of SLRD#.

■ FIFO pointer is incremented on deassertion of SLRD#

Figure 15. Asynchronous Slave FIFO Read Mode

Asynchronous Read Cycle Timing

SLCS

t_AS

t_AH

An

t_RDlt_RDh

Am

FIFO ADDR

SLRD

SLOE

t_FLG

t_RFLG

FLAGA

dedicated thread Flag for An

(1=Not empty 0 = Empty)

FLAGB

dedicated thread Flag for Am

(1=Not empty 0 = Empty)

t_RDO

t_OH

t_OE

t_LZ

t_OE

t_RDO

t_OH

D_N(An)

D_N(Am)

D_N+1(Am)

D_N+2(Am)

Data Out

High-Z

SLWR

(HIGH)

Document Number: 001-52136 Rev. *U

Page 27 of 54

CYUSB301X/CYUSB201X

Asynchronous Slave FIFO Write Sequence Description

Short Packet: A short packet can be committed to the USB host

by using the PKTEND#. The external device or processor should

be designed to assert the PKTEND# along with the last word of

data and SLWR# pulse corresponding to the last word. The

FIFOADDR lines must be held constant during the PKTEND#

assertion.

■ FIFO address is driven and SLCS# is asserted

■ SLWR# is asserted. SLCS# must be asserted with SLWR# or

before SLWR# is asserted

■ Data must be present on the tWRS bus before the deasserting

edge of SLWR#

Zero-Length Packet: The external device or processor can

signal a zero-length packet (ZLP) to FX3 simply by asserting

PKTEND#, without asserting SLWR#. SLCS# and the address

must be driven as shown in Figure 17 on page 29.

■ Deassertion of SLWR# causes the data to be written from the

data bus to the FIFO, and then the FIFO pointer is incremented

FLAG Usage: The FLAG signals are monitored by the external

processor for flow control. FLAG signals are FX3 outputs that

can be configured to show empty, full, and partial status for a

dedicated address or the current address.

■ The FIFO flag is updated after the tWFLG from the deasserting

edge of SLWR.

The same sequence of events is shown for a burst write.

Note that in the burst write mode, after SLWR# deassertion, the

data is written to the FIFO, and then the FIFO pointer is incre-

mented.

Figure 16. Asynchronous Slave FIFO Write Mode

Asynchronous Write Cycle Timing

SLCS

t_AS

t_AH

An

Am

FIFO ADDR

t_WRl

t_WRh

SLWR

t_FLG

t_WFLG

FLAGA

dedicated thread Flag for An

(1= Not Full0 = Full)

t_WFLG

FLAGB

dedicated thread Flag for Am

(1= Not Full0 = Full)

t_WR

t_WRH

S

High-Z

D_N(An)

D_N(Am)

D_N+1(Am)

D_N+2(Am)

t_WRPE

DATA In

t_PEh

PKTEND

SLOE

(HIGH)

tWRPE: SLWR#de- assert to PKTEND deasser=t2 ns min(

Note: PKTEND must be asserted at the same time as SLW#.R

This means that PKTEND should not be be deasserted before SL#W) R

Document Number: 001-52136 Rev. *U

Page 28 of 54

CYUSB301X/CYUSB201X

Figure 17. Asynchronous ZLP Write Cycle Timing

SLCS

t_AS

t_{A H}

An

FIFO AD DR

SLW R

( HIG H)

t_PEl

t_PEh

PKTEND

t_{W FLG}

FLAG A

dedicated thread Flag for An

(1= Not Full0 = Full)

FLAG B

dedicated thread Flag for Am

(1= Not Full0 = Full)

H igh-Z

DATA In

SLO E

( H IG H)

[6]

Table 12. Asynchronous Slave FIFO Parameters

Parameter

Description

Min

20

10

7

Max

–

Units

ns

tRDI

SLRD# low

SLRD# high

tRDh

tAS

–

Address to SLRD#/SLWR# setup time

–

tAH

SLRD#/SLWR#/PKTEND to address hold time

SLRD# to FLAGS output propagation delay

ADDR to FLAGS output propagation delay

SLRD# to data valid

2

–

tRFLG

tFLG

tRDO

tOE

–

35

22.5

25

–

OE# low to data valid

–

tLZ

OE# low to data low-Z

0

tOH

SLOE# deassert data output hold

SLWR# low

–

22.5

–

tWRI

tWRh

tWRS

tWRH

tWFLG

tPEI

20

10

7

SLWR# high

–

Data to SLWR# setup time

SLWR# to Data Hold time

–

2

–

SLWR#/PKTEND to Flags output propagation delay

PKTEND low

–

35

–

20

7.5

2

tPEh

tWRPE

PKTEND high

–

SLWR# deassert to PKTEND deassert

–

Note

6. All parameters guaranteed by design and validated through characterization.

Document Number: 001-52136 Rev. *U

Page 29 of 54

CYUSB301X/CYUSB201X

Host Processor Interface (P-Port) Timing

Asynchronous SRAM Timing

Figure 18. Non-multiplexed Asynchronous SRAM Read Timing

Socket Read – Address Transition Controlled Timing (OE# is asserted)

A[0]

tAA

tAH

tOH

HIGH

DATA

OUT

IMPEDANCE

DATA VALID

tOE

OE#

OE# Controlled Timing

ADDRESS

WE# (HIGH)

CE#

tAOS

tOHC

tRC

OE#

tOHH

tOEZ

tOE

tOLZ

HIGH

IMPEDANCE

HIGH

IMPEDANCE

HIGH

IMPEDANCE

DATA OUT

DATA

VALID

DATA

VALID

Document Number: 001-52136 Rev. *U

Page 30 of 54

CYUSB301X/CYUSB201X

Figure 19. Non-multiplexed Asynchronous SRAM Write Timing (WE# and CE# Controlled)

Write Cycle 1 WE# Controlled, OE# High During Write

tWC

ADDRESS

tCW

CE#

tAW

tAH

tDH

tWP

WE#

tAS

tWPH

OE#

tDS

VALID DATA

DATA I/O

VALID DATA

tWHZ

Write Cycle 2 CE# Controlled, OE# High During Write

tWC

ADDRESS

tAS

tCW

tCPH

CE#

tAW

tAH

tDH

tWP

WE#

OE#

tDS

VALID DATA

DATA I/O

VALID DATA

tWHZ

Document Number: 001-52136 Rev. *U

Page 31 of 54

CYUSB301X/CYUSB201X

Figure 20. Non-multiplexed Asynchronous SRAM Write Timing (WE# controlled, OE# LOW)

Write Cycle 3 WE# Controlled. OE# Low

tWC

tCW

CE#

tAW

tAH

tAS

tWP

WE#

tDS

tDH

DATA I/O

VALID DATA

tOW

tWHZ

Note: tWP must be adjusted such that tWP > tWHZ + tDS

[7]

Table 13. Asynchronous SRAM Timing Parameters

Parameter

Description

SRAM interface bandwidth

Min

–

Max

61.5

–

Units

Mbps

ns

–

tRC

Read cycle time

32.5

–

tAA

Address to data valid

30

–

ns

tAOS

tOH

Address to OE# LOW setup time

Data output hold from address change

OE# HIGH hold time

7

ns

3

–

ns

tOHH

tOHC

tOE

7.5

2

–

ns

OE# HIGH to CE# HIGH

OE# LOW to data valid

OE# LOW to LOW-Z

–

ns

–

25

–

ns

tOLZ

tWC

tCW

tAW

0

ns

Write cycle time

30

7

–

ns

CE# LOW to write end

Address valid to write end

Address setup to write start

Address hold time from CE# or WE#

WE# pulse width

–

ns

–

ns

tAS

–

ns

tAH

2

–

ns

tWP

tWPH

tCPH

tDS

20

10

7

–

ns

WE# HIGH time

–

ns

CE# HIGH time

–

ns

Data setup to write end

Data hold to write end

–

ns

tDH

2

–

ns

tWHZ

tOEZ

tOW

Write to DQ HIGH-Z output

OE# HIGH to DQ HIGH-Z output

End of write to LOW-Z output

–

22.5

–

ns

–

ns

0

ns

Note

7. All parameters guaranteed by design and validated through characterization.

Document Number: 001-52136 Rev. *U

Page 32 of 54

CYUSB301X/CYUSB201X

ADMux Timing for Asynchronous Access

Figure 21. ADMux Asynchronous Random Read

tRC

tACC

Valid Address

tAVS

tVP

Valid

Addr

Valid Data

A[0:7]/DQ[0:15]

ADV#

tAVH

WE# (HIGH)

tCEAV

tHZ

tCO

CE#

tCPH

tHZ

tOLZ

tOE

OE#

tAVOE

Note:

1. Multiple read cycles can be executed while keeping CE# low.

2. Read operation ends with either de-assertion of either OE# or CE#, whichever comes earlier.

Figure 22. ADMux Asynchronous Random Write

tWC

Valid

Addr

Address Valid

Data Valid

tDS

A[0:7]/DQ[0:15]

ADV#

tAW

tAVH

tAVS

tVP

tDH

tVPH

tCEAV

CE#

tCPH

tCW

tWP

tWPH

WE#

tAVWE

Note:

1. Multiple write cycles can be executed while keeping CE# low.

2. Write operation ends with de-assertion of either WE# or CE#, whichever comes earlier.

Document Number: 001-52136 Rev. *U

Page 33 of 54

CYUSB301X/CYUSB201X

[8]

Table 14. Asynchronous ADMux Timing Parameters

Parameter

Description

Min

Max

Units

Notes

ADMux Asynchronous READ Access Timing Parameters

Read cycle time (address valid to address

valid)

This parameter is dependent on when

the P-port processors deasserts OE#

tRC

54.5

–

ns

tACC

tCO

Address valid to data valid

CE# assert to data valid

–

2

0

–

32

34.5

–

ns

–

tAVOE

tOLZ

tOE

ADV# deassert to OE# assert

OE# assert to data LOW-Z

OE# assert to data valid

–

25

tHZ

Read cycle end to data HIGH-Z

22.5

ADMux Asynchronous WRITE Access Timing Parameters

Write cycle time (Address Valid to Address

Valid)

tWC

–

52.5

ns

–

tAW

Address valid to write end

CE# assert to write end

30

2

–

ns

–

tCW

tAVWE

tWP

ADV# deassert to WE# assert

WE# LOW pulse width

20

10

18

2

tWPH

tDS

WE# HIGH pulse width

Data valid setup to WE# deassert

Data valid hold from WE# deassert

tDH

ADMux Asynchronous Common READ/WRITE Access Timing Parameters

tAVS

tAVH

tVP

Address valid setup to ADV# deassert

Address valid hold from ADV# deassert

ADV# LOW pulse width

5

2

–

ns

–

7.5

10

15

0

tCPH

tVPH

tCEAV

CE# HIGH pulse width

ADV# HIGH pulse width

CE# assert to ADV# assert

Note

8. All parameters guaranteed by design and validated through characterization.

Document Number: 001-52136 Rev. *U

Page 34 of 54

CYUSB301X/CYUSB201X

Synchronous ADMux Timing

Figure 23. Synchronous ADMux Interface – Read Cycle Timing

tCLK

2- cycle latency from OE# to DATA

tCLKH

tCLKL

CLK

tCO

tS

tH

Valid Data

Valid Address

A[0:7]/DQ[0:31]

tS

tH

tOHZ

ADV#

CE#

tS

tAVOE

tOLZ

OE#

RDY

tKW

tCH

WE# (HIGH)

Note:

1) External P-Port processor and FX3 operate on the same clock edge

2) External processor sees RDY assert 2 cycles after OE # asserts andand sees RDY deassert a cycle after the data appears on the output

3) Valid output data appears 2 cycle after OE # asserted. The data is held until OE # deasserts

4) Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by 1 cycle for operations at less than 50 MHz (this 1 cycle latency is not supported by the bootloader)

Figure 24. Synchronous ADMux Interface – Write Cycle Timing

2-cycle latency between

WE# and data being latched

2-cycle latency between this clk edge and RDY deassertion seen by

the host

CLK

tCLK

tDS

tDH

tS

tH

Valid Address

Valid Data

A[0:7]/DQ[0:31]

tS

tH

ADV#

CE#

tS

tAVWE

tS

tH

WE#

RDY

tKW

Note:

1) External P-Port processor and FX3 operate on the same clock edge

2) External processor sees RDY assert 2 cycles after WE # asserts and deassert 3 cycles after the edge sampling the data.

3) Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by 1 cycle for operations at less than 50 MHz (this 1 cycle latency is not supported by the bootloader)

Document Number: 001-52136 Rev. *U

Page 35 of 54

CYUSB301X/CYUSB201X

Figure 25. Synchronous ADMux Interface – Burst Read Timing

2-cycle latency fromOE# to Data

tCLK

tCLKH

tCLKL

CLK

tCO

tCH

tS

tH

Valid Address

D0

D1

D2

D3

A[0:7]/DQ[0:31]

tS

tH

ADV#

CE#

tHZ

tS

tAVOE

tOLZ

OE#

RDY

tKW

Note:

1) External P-Port processor and FX3 work operate on the same clock edge

2) External processor sees RDY assert 2 cycles after OE # asserts andand sees RDY deassert a cycle after the last burst data appears on the output

3) Valid output data appears 2 cycle after OE # asserted. The last burst data is held until OE# deasserts

4) Burst size of 4 is shown. Transfer size for the operation must be a multiple of burst size. Burst size is usually power of 2. RDY will not deassert in the middle of the burst.

5) External processor cannot deassert OE in the middle of a burst. If it does so, any bytes remaining in the burst packet could get lost.

6) Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by1 cycle for operations at less than 50 MHz (this 1 cycle latency is not supported by the bootloader)

Figure 26. Sync ADMux Interface – Burst Write Timing

2-cycle latency between

WE# and data being latched

2-cycle latency between this clk edge and RDY

deassertion seen by the host

tCLKH

tCLKL

CLK

tCLK

tDS

tDH

tS

tH

D0

Valid Address

D1

D2

D3

A[0:7]/DQ[0:31]

tS

tH

ADV#

CE#

tS

tAVWE

WE#

RDY

tKW

Note:

1) External P-Port processor and FX3 operate on the same clock edge

2) External processor sees RDY assert 2 cycles after WE # asserts and deasserts 3 cycles after the edge sampling the last burst data.

3) Transfer size for the operation must be a multiple of burst size. Burst size is usually power of 2. RDY will not deassert in the middle of the burst. Burst size of 4 is shown

4) External processor cannot deassert WE in the middle of a burst. If it does so, any bytes remaining in the burst packet could get lost.

5)Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by 1 cycle for operations at less than 50 MHz (this 1 cycle latency is not supported by the bootloader)

Document Number: 001-52136 Rev. *U

Page 36 of 54

CYUSB301X/CYUSB201X

[9]

Table 15. Synchronous ADMux Timing Parameters

Parameter Description

FREQ Interface clock frequency

Min

–

Max

100

–

Unit

MHz

ns

tCLK

tCLKH

tCLKL

tS

Clock period

10

4

Clock HIGH time

–

ns

Clock LOW time

4

–

ns

CE#/WE#/DQ setup time

CE#/WE#/DQ hold time

Clock to data output hold time

Data input setup time

Clock to data input hold

ADV# HIGH to OE# LOW

ADV# HIGH to WE# LOW

CE# HIGH to Data HIGH-Z

OE# HIGH to Data HIGH-Z

OE# LOW to Data LOW-Z

Clock to RDY valid

2

–

ns

tH

0.5

0

–

ns

tCH

–

ns

tDS

2

–

ns

tDH

0.5

0

–

ns

tAVDOE

tAVDWE

tHZ

–

ns

0

–

ns

–

8

ns

tOHZ

tOLZ

tKW

–

8

ns

0

–

ns

–

8

ns

Serial Peripherals Timing

I²C Timing

Figure 27. I²C Timing Definition

Note

9. All parameters guaranteed by design and validated through characterization.

Document Number: 001-52136 Rev. *U

Page 37 of 54

CYUSB301X/CYUSB201X

[10]

Table 16. I²C Timing Parameters

Parameter

Description

Min

Max

Units

I²C Standard Mode Parameters

fSCL

SCL clock frequency

0

4

100

–

kHz

µs

ns

µs

tHD:STA

tLOW

Hold time START condition

LOW period of the SCL

HIGH period of the SCL

4.7

4

–

tHIGH

tSU:STA

tHD:DAT

tSU:DAT

tr

–

Setup time for a repeated START condition

Data hold time

4.7

0

–

Data setup time

250

–

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Setup time for STOP condition

Bus free time between a STOP and START condition

Data valid time

1000

300

–

tf

–

tSU:STO

tBUF

4

4.7

–

tVD:DAT

tVD:ACK

tSP

3.45

n/a

Data valid ACK

–

Pulse width of spikes that must be suppressed by input filter

I²C Fast Mode Parameters

n/a

fSCL

SCL clock frequency

0

0.6

1.3

0.6

0

400

–

kHz

µs

ns

µs

ns

tHD:STA

tLOW

Hold time START condition

LOW period of the SCL

–

tHIGH

tSU:STA

tHD:DAT

tSU:DAT

tr

HIGH period of the SCL

–

Setup time for a repeated START condition

Data hold time

–

Data setup time

100

–

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Setup time for STOP condition

Bus free time between a STOP and START condition

Data valid time

300

–

tf

–

tSU:STO

tBUF

0.6

1.3

–

tVD:DAT

tVD:ACK

tSP

0.9

50

Data valid ACK

–

Pulse width of spikes that must be suppressed by input filter

0

Note

10. All parameters guaranteed by design and validated through characterization.

Document Number: 001-52136 Rev. *U

Page 38 of 54

CYUSB301X/CYUSB201X

[10]

Table 16. I²C Timing Parameters

Parameter

(continued)

Description

I²C Fast Mode Plus Parameters (Not supported at I2C_VDDQ=1.2 V)

SCL clock frequency

Min

Max

Units

fSCL

0

0.26

0.5

0.26

0

1000

–

kHz

µs

ns

µs

ns

tHD:STA

tLOW

Hold time START condition

LOW period of the SCL

–

tHIGH

tSU:STA

tHD:DAT

tSU:DAT

tr

HIGH period of the SCL

–

Setup time for a repeated START condition

Data hold time

–

Data setup time

50

–

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Setup time for STOP condition

Bus-free time between a STOP and START condition

Data valid time

120

–

tf

–

tSU:STO

tBUF

0.26

0.5

–

tVD:DAT

tVD:ACK

tSP

0.45

0.55

50

Data valid ACK

–

Pulse width of spikes that must be suppressed by input filter

0

I²S Timing Diagram

Figure 28. I²S Transmit Cycle

t_T

t_TRt_TF

t_TH

t_TL

SCK

t_Thd

SA,

WS (output)

t_Td

[11]

Table 17. I²S Timing Parameters

Parameter

Description

Min

Ttr

Max

Units

ns

2

tT

I S transmitter clock cycle

–

2

tTL

tTH

tTR

tTF

tThd

tTd

I S transmitter cycle LOW period

0.35 Ttr

–

ns

2

I S transmitter cycle HIGH period

0.35 Ttr

ns

2

I S transmitter rise time

–

0

–

0.15 Ttr

–

ns

2

I S transmitter fall time

ns

2

I S transmitter data hold time

ns

2

I S transmitter delay time

0.8tT

ns

Note tT is selectable through clock gears. Max Ttr is designed for 96-kHz codec at 32 bits to be 326 ns (3.072 MHz).

Note

11. All parameters guaranteed by design and validated through characterization.

Document Number: 001-52136 Rev. *U

Page 39 of 54

CYUSB301X/CYUSB201X

SPI Timing Specification

Figure 29. SPI Timing

SSN

(output)

t_ssnh

t_sck

t_lag

t_lead

SCK

(CPOL=0,

Output)

t_rf

t_wsck

SCK

(CPOL=1,

Output)

t_sdi

t_hoi

LSB

MISO

(input)

MSB

t_d

t_dis

t_sdd

t_di

v

MOSI

(output)

LSB

MSB

SPI Master Timing for CPHA = 0

SSN

(output)

t_ssnh

t_sck

t_lag

t_lead

t_rf

SCK

(CPOL=0,

Output)

t_wsck

SCK

(CPOL=1,

Output)

t_hoi

LSB

t_sdi

MISO

(input)

MSB

t_dis

t_di

t_dv

MOSI

(output)

LSB

SPI Master Timing for CPHA = 1

Document Number: 001-52136 Rev. *U

Page 40 of 54

CYUSB301X/CYUSB201X

[12]

Table 18. SPI Timing Parameters

Parameter

Description

Min

0

Max

33

–

Units

MHz

ns

fop

Operating frequency

tsck

twsck

tlead

tlag

trf

Cycle time

30

Clock high/low time

SSN-SCK lead time

Enable lag time

Rise/fall time

13.5

–

ns

[13 ]

[13]

1/2 tsck

-5

1.5 tsck + 5

ns

[13]

0.5

–

1.5 tsck +5

ns

8

5

–

ns

tsdd

tdv

Output SSN to valid data delay time

Output data valid time

–

ns

–

ns

tdi

Output data invalid

0

ns

tssnh

tsdi

thoi

tdis

Minimum SSN high time

Data setup time input

10

8

ns

Data hold time input

0

ns

Disable data output on SSN high

0

ns

Notes

12. All parameters guaranteed by design and validated through characterization.

13. Depends on LAG and LEAD setting in the SPI_CONFIG register.

Document Number: 001-52136 Rev. *U

Page 41 of 54

CYUSB301X/CYUSB201X

Reset Sequence

FX3’s hard reset sequence requirements are specified in this section.

Table 19. Reset and Standby Timing Parameters

Parameter

tRPW

tRH

Definition

Conditions Min (ms) Max (ms)

Clock Input

Crystal Input

–

1

5

1

5

–

Minimum RESET# pulse width

Minimum high on RESET#

Clock Input

Crystal Input

tRR

Reset recovery time (after which Boot loader begins firmware download)

Time to enter standby/suspend (from the time MAIN_CLOCK_EN/

MAIN_POWER_EN bit is set)

tSBY

–

1

Clock Input

Crystal Input

–

1

5

–

tWU

tWH

Time to wakeup from standby

Minimum time before Standby/Suspend source may be reasserted

Figure 30. Reset Sequence

VDD

( core )

xVDDQ

XTALIN/

CLKIN

XTALIN/ CLKIN must be stable

before exiting Standby/Suspend

tRh

tRR

Mandatory

Reset Pulse

Hard Reset

RESET #

tWH

tWU

tRPW

tSBY

Standby/

Suspend

Source

Standby/Suspend source Is asserted

(MAIN_POWER_EN/ MAIN_CLK_EN bit

is set)

Standby/Suspend

source Is deasserted

Document Number: 001-52136 Rev. *U

Page 42 of 54

CYUSB301X/CYUSB201X

Package Diagram

Figure 31. 121-ball BGA Package Diagram

2X

0.10

C

E1

E

B

A

(datum B)

A1 CORNER

11 10

9

8

7

6

5

4

3

2

1

7

A1 CORNER

A

B

C

D

E

F

6

SD

D1

D

(datum A)

G

H

J

K

eD

L

2X

0.10 C

6

eE

TOP VIEW

SE

BOTTOM VIEW

0.20 C

DETAIL A

A1

0.08 C

C

121XØb

5

A

Ø0.15 M C A B

Ø0.08 M C

SIDE VIEW

DETAIL A

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

DIMENSIONS

SYMBOL

2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.

3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.

MIN.

-

NOM.

MAX.

1.20

-

A

-

4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.

N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX

SIZE MD X ME.

A1

D

0.15

-

10.00 BSC

E

10.00 BSC

8.00 BSC

11

D1

E1

MD

ME

N

5.

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A

PLANE PARALLEL TO DATUM C.

6.

"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND

DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.

11

121

0.30

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,

"SD" OR "SE" = 0.

b

0.25

0.35

eD

eE

SD

SE

0.80 BSC

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,

"SD" = eD/2 AND "SE" = eE/2.

0.80 BSC

0.00

A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK

METALIZED MARK, INDENTATION OR OTHER MEANS.

7.

0.00

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER

BALLS.

001-54471 *E

Document Number: 001-52136 Rev. *U

Page 43 of 54

CYUSB301X/CYUSB201X

Figure 32. 131-ball WLCSP (5.099 × 4.695 × 0.60 mm) Package Diagram

001-62221 *C

Note Underfill is required on the board design. Contact fx3@cypress.com for details.

Document Number: 001-52136 Rev. *U

Page 44 of 54

CYUSB301X/CYUSB201X

Ordering Information

Table 20. Ordering Information

Ordering Code

CYUSB3011-BZXC

CYUSB3012-BZXC

CYUSB3013-BZXC

CYUSB3014-BZXC

CYUSB3014-BZXI

CYUSB3014-FBXCT

CYUSB3014-FBXIT

CYUSB2014-BZXC

CYUSB2014-BZXI

USB

SRAM (kB) GPIF II Data Bus Width

Operating Temperature

Package Type

121-ball BGA

131-ball WLCSP

121-ball BGA

USB 3.0

USB 2.0

256

512

16-bit

32-bit

16-bit

32-bit

0 °C to +70 °C

–40°C to +85°C

0 °C to +70 °C

–40 °C to +85 °C

0 °C to +70 °C

–40 °C to +85 °C

Ordering Code Definitions

Document Number: 001-52136 Rev. *U

Page 45 of 54

CYUSB301X/CYUSB201X

Acronyms

Document Conventions

Units of Measure

Symbol

Acronym

DMA

Description

direct memory access

Unit of Measure

FIFO

first in, first out

°C

degree Celsius

GPIF

general programmable interface

host negotiation protocol

inter-integrated circuit

inter IC sound

µA

microamperes

microseconds

milliamperes

HNP

µs

2

I C

mA

Mbps

MBps

MHz

ms

ns

2

I S

Megabits per second

Megabytes per second

mega hertz

MISO

MOSI

MMC

MSC

MTP

OTG

OVP

PHY

PLL

master in, slave out

master out, slave in

multimedia card

milliseconds

nanoseconds

ohms

mass storage class

media transfer protocol

on-the-go



pF

pico Farad

overvoltage protection

physical layer

V

volts

phase locked loop

PMIC

PVT

power management IC

process voltage temperature

real-time operating system

serial clock line

RTOS

SCL

SCLK

SD

serial clock

secure digital

SD

secure digital

SDA

SDIO

SLC

serial data clock

secure digital input / output

single-level cell

SLCS

SLOE

SLRD

SLWR

SPI

Slave Chip Select

Slave Output Enable

Slave Read

Slave Write

serial peripheral interface

session request protocol

SPI slave select (Active low)

universal asynchronous receiver transmitter

USB Video Class

SRP

SSN

UART

UVC

USB

WLCSP

universal serial bus

wafer level chip scale package

Document Number: 001-52136 Rev. *U

Page 46 of 54

CYUSB301X/CYUSB201X

Errata

This section describes the errata for Revision C of the FX3. Details include errata trigger conditions, scope of impact, available

workaround, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions.

Part Numbers Affected

Part Number

CYUSB301x-xxxx

CYUSB201x-xxxx

Device Characteristics

All Variants

Qualification Status

Product Status: Production

Errata Summary

The following table defines the errata applicability to available Rev. C EZ-USB FX3 SuperSpeed USB Controller family

devices.

Items

[Part Number]

Silicon Revision

Fix Status

1. Turning off VIO1 during Normal, Suspend, and Standby

modes causes the FX3 to stop working.

CYUSB301x-xxxx

CYUSB201x-xxxx

Workaround provided

Rev. C, B, ES

2. USB enumeration failure in USB boot mode when FX3

is self-powered.

CYUSB301x-xxxx

CYUSB201x-xxxx

Workaround provided

Rev. C, B, ES

3. Extra ZLP is generated by the COMMIT action in the

GPIF II state.

CYUSB301x-xxxx

CYUSB201x-xxxx

CYUSB301x-xxxx

CYUSB201x-xxxx

4. Invalid PID Sequence in USB 2.0 ISOC data transfer.

5. USB data transfer errors are seen when ZLP is followed

by data packet within same microframe.

CYUSB301x-xxxx

CYUSB201x-xxxx

6. Bus collision is seen when the I2C block is used as a

master in the I2C Multi-master configuration.

CYUSB301x-xxxx

CYUSB201x-xxxx

Use FX3 in single-master

configuration

1. Turning off VIO1 during Normal, Suspend, and Standby modes causes the FX3 to stop working.

■Problem Definition

Turning off the VIO1 during Normal, Suspend, and Standby modes will cause the FX3 to stop working.

■Parameters Affected

N/A

■Trigger Conditions

This condition is triggered when the VIO1 is turned off during Normal, Suspend, and Standby modes.

■Scope Of Impact

FX3 stops working.

■Workaround

VIO1 must stay on during Normal, Suspend, and Standby modes.

■Fix Status

No fix. Workaround is required.

2. USB enumeration failure in USB boot mode when FX3 is self-powered.

■Problem Definition

FX3 device may not enumerate in USB boot mode when it is self-powered. The bootloader is designed for bus power mode. It

does not make use of the VBUS pin on the USB connector to detect the USB connection and expect that USB bus is connected

to host if it is powered. If FX3 is not already connected to the USB host when it is powered, then it enters into low-power mode

and does not wake up when connected to USB host.

■Parameters Affected

N/A

Document Number: 001-52136 Rev. *U

Page 47 of 54

CYUSB301X/CYUSB201X

■Trigger Conditions

This condition is triggered when FX3 is self-powered in USB boot mode.

■Scope Of Impact

Device does not enumerate

■Workaround

Reset the device after connecting to USB host.

■Fix Status

No fix. Workaround is required.

3. Extra ZLP is generated by the COMMIT action in the GPIF II state.

■Problem Definition

When COMMIT action is used in a GPIF-II state without IN_DATA action then an extra Zero Length Packet (ZLP) is committed

along with the data packets.

■Parameters Affected

N/A

■Trigger Conditions

This condition is triggered when COMMIT action is used in a state without IN_DATA action.

■Scope Of Impact

Extra ZLP is generated.

■Workaround

Use IN_DATA action along with COMMIT action in the same state.

■Fix Status

No fix. Workaround is required.

4. Invalid PID Sequence in USB 2.0 ISOC data transfer.

■Problem Definition

When the FX3 device is functioning as a high speed USB device with high bandwidth isochronous endpoints, the PID sequence

of the ISO data packets is governed solely by the isomult setting. The length of the data packet is not considered while generating

the PID sequence during each microframe. For example, even if a short packet is being sent on an endpoint with MULT set to 2;

the PID used will be DATA2

■Parameters Affected

N/A

■Trigger Conditions

This condition is triggered when high bandwidth ISOC transfer endpoints are used.

■Scope Of Impact

ISOC data transfers failure.

■Workaround

This problem can be worked around by reconfiguring the endpoint with a lower isomult setting prior to sending short packets, and

then switching back to the original value.

■Fix Status

No fix. Workaround is required.

5. USB data transfer errors are seen when ZLP is followed by data packet within same microframe.

■Problem Definition

Some data transfer errors may be seen if a Zero Length Packet is followed very quickly (within one microframe or 125 us) by

another data packet on a burst enabled USB IN endpoint operating at super speed.

■Parameters Affected

N/A

■Trigger Conditions

This condition is triggered in SuperSpeed transfer with ZLPs

■Scope Of Impact

Data failure and lower data speed.

■Workaround

The solution is to ensure that some time is allowed to elapse between a ZLP and the next data packet on burst enabled USB IN

endpoints. If this cannot be ensured at the data source, the CyU3PDmaChannelSetSuspend() API can be used to suspend the

Document Number: 001-52136 Rev. *U

Page 48 of 54

CYUSB301X/CYUSB201X

corresponding USB DMA socket on seeing the EOP condition. The channel operation can then be resumed as soon as the

suspend callback is received.

■Fix Status

No fix. Workaround is required.

6. Bus collision is seen when the I²C block is used as a master in the I²C Multi-master configuration.

■Problem definition

2

When FX3 is used as a master in the I C multi-master configuration, there can be occasional bus collisions.

■Parameters affected

NA

■Trigger Conditions

2

This condition is triggered only when the FX3 I C block operates in Multi-master configuration.

■Scope Of Impact

2

The FX3 I C block can transmit data when the I C bus is not idle leading to bus collision.

■Workaround

Use FX3 as a single master.

■Fix Status

No fix.

Document Number: 001-52136 Rev. *U

Page 49 of 54

CYUSB301X/CYUSB201X

Document History Page

Document Title: CYUSB301X/CYUSB201X, EZ-USB^®FX3: SuperSpeed USB Controller

Document Number: 001-52136

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

**

2669761

VSO /

PYRS

03/06/2009 New data sheet

*A

2758370

VSO

09/01/2009 Updated the part# from CYX01XXBB to CYUSB3011-BZXI

Changed the title from “ADVANCE” to “ADVANCE INFORMATION”

In page 1, the second bullet (Flexible Host Interface), add “32-bit, 100 MHz” to

first sub bullet.

In page 1, changed the second bullet “Flexible Host Interface” to General

Programmable Interface”.

In page 1, the second bullet (Flexible Host Interface), removed "DMA Slave

Support” and "MMC Slave support with Pass through Boot" sub bullets.

^{In page 1, third bullet, changed "50}A with Core Power" to "60 A with Core

Power"

In page 1, fifth bullet, added "at 1 MHz"

In page 1, seventh bullet, added "up to 4MHz" to UART

In page 1, Applications Section, move “Digital Still Cameras” to second line.

In page 1, Applications Section, added “Machine Vision” and Industrial

Cameras”

Added ™ to GPIF and FX3.

In page 1, updated Logic Block Diagram.

In page 2, section of “Functional Overview”, updated the whole section.

In page 2, removed the section of “Product Interface”

In page 2, removed the section of “Processor Interface (P-Port)”

In page 2, removed the section of “USB Interface (U-Port)”

In page 2, removed the section of “Other Interfaces”

In page 2, added a section of "GPIF II"

In page 2, added a section of "CPU"

In page 2, added a section of "JTAG Interface"

In page 2, added a section of "Boot Options"

In page 2, added a section of "ReNumeration"

In page 2, added a section of "Power"

In the section of “Package”, replaced “West Bridge USB 3.0 Platform” by FX3.

In the section of “Package”, added 0.8 mm pitch in front of BGA.

Added Pin List (Table 1)

*B

2779196 VSO/PYRS 09/29/2009 Features:

Added the thrid bullet “Fully accessible 32-bit ARM9 core with 512kB of

embedded SRAM”

Added the thrid line “EZ USB™ Software and DVK for easy code development”

Table 1: Pin 74, corrected to NC - No Connect.

Changed title to EZ-USB™ FX3: SuperSpeed USB Controller

*C

*D

2823531

3080927

OSG

12/08/2009 Added data sheet to the USB 3.0 EROS spec 001-51884. No technical

updates.

11/08/2010 Changed status from Advance to Preliminary

Changed part number from CYUSB3011 to CYUSB3014

Added the following sections: Power, Digital I/Os, Digital I/Os, System-level

ESD, Electrical Specifications, AC Timing Parameters, Reset Sequence,

Package Diagram

Added DC Specifications table

Updated feature list

Updated Pin List

Added support for selectable clock input frequencies.

Updated block diagram

Updated part number

Updated package diagram

Document Number: 001-52136 Rev. *U

Page 50 of 54

CYUSB301X/CYUSB201X

Document History Page (continued)

Document Title: CYUSB301X/CYUSB201X, EZ-USB^®FX3: SuperSpeed USB Controller

Document Number: 001-52136

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

*E

3204393

OSG

03/24/2011 Updated Slave FIFO protocol and added ZLP signaling protocol

Changed GPIFII asynchronous tDO parameter

Changed Async Slave FIFO tOE parameter

Changed Async Slave FIFO tRDO parameter

Added tCOE parameter to GPIFII Sync mode timing parameters

Renamed GPIFII Sync mode tDO to tCO and tDO_ss0 to tCO_ss0

Modified description of GPIFII Sync tCO (previously tDO) parameter

Changed tAH(address hold time) parameter in Async Slave FIFO modes to be

with respect to rising edge of SLWR#/SLRD# instead of falling edge.

Correspondingly, changed the tAH number.

Removed 24 bit data bus support for GPIFII.

*F

*G

*H

3219493

3235250

3217917

OSG

GSZ

OSG

04/07/2011 Minor ECN - Release to web. No content changes.

04/20/2011 Minor updates in Features.

04/06/2011 Updated GPIFII Synchronous Timing diagram. Added SPI Boot option.

Corrected values of R_USB2 and R_USB3. Corrected TCK and TRST#

pull-up/pull-down configuration. Minor updates to block diagrams.

Corrected Synchronous Slave FIFO tDH parameter.

*I

3305568

3369042

DSG

OSG

07/07/2011 Minor ECN - Correct ECN number in revision *F. No content changes.

*J

12/06/2011 Changed datasheet status from Preliminary to Final.

Changed tWRPE parameter to 2ns

Updated tRR and tRPW for crystal input

Added clarification regarding I and I

OZ

IX

Updated Sync SLave FIFO Read timing diagram

Updated SPI timing diagram

Removed tGRANULARITY parameter

Updated I2S Timing diagram and tTd parameter

Updated 121-ball BGA package diagram.

Added clarification regarding VCC in DC Specifications table

In Power Modes description, stated that VIO1 cannot be turned off at any time

if the GPIFII is used in the application

Updated Absolute Maximum Ratings

Added requirement for by-pass capacitor on U3RX

and U3TX

VDDQ

Updated tPEI parameter in Async Slave FIFO timing table

Updated Sync Slave FIFO write and read timing diagrams

Updated I2C interface tVD:ACK parameter for 1MHz operation

Clarified that CTL[15] is not usable as a GPIO

*K

*L

3534275

3649782

OSG

02/24/2012 Corrected typo in the block diagram.

08/16/2012 Changed part number to CYUSB301X.

Added 256 KB range for embedded SRAM.

Updated Functional Overview, Other Interfaces, and Clocking sections.

Added Pin List for CYUSB3011 and CYUSB3013 parts.

Updated Ordering Information with new part numbers.

*M

*N

3848148

4016006

OSG

12/20/2012 Updated 121-ball BGA package diagram to current revision.

05/31/2013 Updated Features (Added 131-ball WLCSP under Package option).

Updated Pin Configurations (Added FX3 131-ball WLCSP Ball Map (Figure 7)).

Updated Pin Description (Updated Table 7).

Updated Electrical Specifications (Included Commercial Temperature Range

related information).

Updated Operating Conditions (Included Commercial Temperature Range

related information).

Updated Package Diagram (Added 131-ball WLCSP Package Diagram

(Figure 32)).

Updated Ordering Information (Updated part numbers).

Document Number: 001-52136 Rev. *U

Page 51 of 54

CYUSB301X/CYUSB201X

Document History Page (continued)

Document Title: CYUSB301X/CYUSB201X, EZ-USB^®FX3: SuperSpeed USB Controller

Document Number: 001-52136

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

*O

4368374

RSKV

05/02/2014 Updated Package Diagram:

spec 001-62221 – Changed revision from *B to *C.

Updated to new template.

Completing Sunset Review.

*P

*Q

4474200

4668496

ANOP

DBIR

08/14/2014 Added CYUSB201x MPNs, ball map, and pin list to the datasheet.

02/24/2015 Updated Features.

Updated Logic Block Diagram.

Updated Functional Description:

Added “

Added More Information.

For a complete list of related documentation, click here.” at the end.

Updated Functional Overview:

Updated Application Examples:

Updated Figure 1.

Updated Figure 2.

Updated USB Interface:

Updated description.

Removed Figure “USB Interface Signals”.

Updated Pin Configurations:

Updated Figure 6.

Updated Reset:

Updated Hard Reset:

Updated description.

Updated Pin Description:

Updated Table 7:

Updated entire table.

Modified CVDDQ power domain description.

Removed Table “CYUSB3011 and CYUSB3013 Pin List (GPIF II with 16-bit

Data Bus Width)”.

Removed Table “CYUSB2014 Pin List (GPIF II with 32-bit Data Bus Width)”.

Updated Electrical Specifications:

Updated DC Specifications:

Added ISS parameter and its details.

Updated Slave FIFO Interface:

Updated Synchronous Slave FIFO Read Sequence Description:

Updated Figure 12.

Updated Synchronous Slave FIFO Write Sequence Description:

Updated Figure 13.

Updated Table 11.

Updated AC Timing Parameters:

Added Host Processor Interface (P-Port) Timing.

Updated Acronyms.

Added Errata.

Replaced West Bridge Benicia with FX3.

*R

*S

4703347

5160624

AMDK

03/27/2015 Updated Slave FIFO Interface:

Updated Synchronous Slave FIFO Read Sequence Description:

Updated Figure 12.

Updated Synchronous Slave FIFO Write Sequence Description:

Updated Figure 13.

Updated Table 11:

Updated minimum value of tSSD parameter.

Added tACCD, tFAD parameters and their details.

AJAI

04/07/2016 Removed ISS parameter.

Added item 6 in Errata.

Document Number: 001-52136 Rev. *U

Page 52 of 54

CYUSB301X/CYUSB201X

Document History Page (continued)

Document Title: CYUSB301X/CYUSB201X, EZ-USB^®FX3: SuperSpeed USB Controller

Document Number: 001-52136

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

*T

5306567

MDDD

06/29/2016 Updated AC Timing Parameters:

Updated GPIF II Timing:

Updated Table 9:

Changed maximum value of t parameter from 8 ns to 7 ns.

CO

Updated Slave FIFO Interface:

Updated Synchronous Slave FIFO Write Sequence Description:

Updated Table 11:

Changed maximum value of t parameter from 8 ns to 7 ns.

CO

Updated to new template.

*U

5703914

GNKK

04/20/2017 Updated the Cypress logo and copyright information.

Document Number: 001-52136 Rev. *U

Page 53 of 54

CYUSB301X/CYUSB201X

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

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closest to you, visit us at Cypress Locations.

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including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

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are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

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Document Number: 001-52136 Rev. *U

Revised April 20, 2017

Page 54 of 54

®

EZ-USB™ is a trademark and West Bridge is a registered trademark of Cypress Semiconductor Corporation.


型号：	CYUSB3014-BZXIT
厂家：	CYPRESS
描述：	IC ARM9 USB CONTROLLER 121FBGA 时钟数据传输外围集成电路
文件：	总54页 (文件大小：553K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CYUSB3014-BZXIT [CYPRESS]

相关型号：

CYUSB3014-FBXCT

CYUSB3014-FBXIT

CYUSB3014_1107

CYUSB301X

CYUSB301X_13

CYUSB3023-FBXCT

CYUSB3025-BZXI

CYUSB3025-BZXI

CYUSB302X

CYUSB3031-BZXC

CYUSB3033-BZXC

CYUSB3035