CYUSB3014-BZXI [CYPRESS]
EZ-USB FX3 SuperSpeed USB Controller UART support up to 4 Mbps; EZ- USB FX3超高速USB控制器UART支持高达4 Mbps
| 型号： | CYUSB3014-BZXI |
| 厂家： | 
CYPRESS |
| 描述： | EZ-USB FX3 SuperSpeed USB Controller UART support up to 4 Mbps |
| 文件： | 总38页 (文件大小：858K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
CYUSB3014
®
EZ-USB FX3 SuperSpeed USB Controller
■ Ultra low-power in core power-down mode
❐ Less than 60 µA with VBATT ON and 20 µA with VBATT off
Features
■ Universal serial bus (USB) integration
❐ USB 3.0 and USB 2.0 peripheral compliant with USB3.0
specification 1.0
❐ 5-Gbps USB3.0 PHY compliant with PIPE 3.0
❐ High-speed On-The-Go (HS-OTG) host and peripheral
compliant with On-The-Go Supplement Version 2.0
❐ Thirty-two physical endpoints
❐ Support for battery charging Spec 1.1 and accessory charger
adaptor (ACA) detection
■ Independent power domains for core and I/O
❐ Core operation at 1.2 V
❐ I2S, UART and SPI operation at 1.8 to 3.3V
❐ I2C operation at 1.2 V
■ 10×10mm, 0.8mmpitchPb-freeballgridarray(BGA)package
■ EZ USB® software and DVK for easy code development
Applications
■ General programmable interface (GPIF™ II)
❐ Programmable 100-MHz GPIF II interface enables
■ Digital video camcorders
■ Digital still cameras
■ Printers
connectivity to wide range of external devices
❐ 8-/16-/32-bit data bus
❐ Up to 16 configurable control signals
■ Fully accessible 32-bit CPU
■ Scanners
❐ ARM926EJ Core with 200MHz operation
❐ 512 kB Embedded SRAM
■ Video capture cards
■ Test and measurement equipment
■ Surveillance cameras
■ Personal navigation devices
■ Medical imaging devices
■ Video IP phones
■ Additional connectivity to following peripherals
❐ I2C master controller at 1 MHz
❐ I2Smaster(transmitteronly)atsamplingfrequencies32 kHz,
44.1 kHz, 48 kHz
❐ UART support up to 4 Mbps
❐ SPI master at 33 MHz
■ Selectable clock input frequencies
❐ 19.2, 26, 38.4, and 52 MHz
❐ 19.2 MHz crystal input support
■ Portable media players
■ Industrial cameras
Logic Block Diagram
FSLC[0]
FSLC[1]
FSLC[2]
JTAG
CLKIN
CLKIN_32
XTALIN
Embedded
SRAm
(512kB)
ARM926EJ -S
XTALOUT
HS/FS/LS
OTG Host
OTG_ID
SSRX -
DATA[31:0
]
SSRX +
SS
Peripheral
CTL[12:0]
SSTX -
SSTX +
32
EPs
PMODE[2:0
]
GPIF™ II
HS/FS
Peripheral
D+
D-
INT#
RESET #
EZ-Dtect™
UART
SPI
I2S
I2C
Cypress Semiconductor Corporation
Document Number 001-52136 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•408-943-2600
Revised May 17, 2011
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PRELIMINARY
CYUSB3014
Contents
Functional Overview .......................................................... 3
Digital I/Os......................................................................... 13
GPIOs................................................................................. 13
System Level ESD ............................................................ 13
Absolute Maximum Ratings ............................................ 14
Operating Conditions....................................................... 14
Application Examples.................................................... 3
USB Interface...................................................................... 4
OTG............................................................................... 4
ReNumeration ............................................................... 5
EZ-Dtect ........................................................................ 5
VBUS Overvoltage Protection....................................... 5
Carkit UART Mode ........................................................ 5
AC Timing Parameters..................................................... 16
GPIF II Timing ............................................................. 16
Slave FIFO Interface ................................................... 19
Serial Peripherals Timing ............................................ 26
GPIF II .................................................................................. 6
CPU...................................................................................... 6
JTAG Interface.................................................................... 7
Reset Sequence................................................................ 30
Pin Description ................................................................. 32
Package Diagram.............................................................. 35
Other Interfaces.................................................................. 7
UART Interface.............................................................. 7
I2C Interface.................................................................. 7
I2S Interface.................................................................. 7
SPI Interface.................................................................. 7
Ordering Information ....................................................... 35
Ordering Code Definition............................................. 35
Acronyms.......................................................................... 36
Document Conventions ................................................... 36
Boot Options....................................................................... 7
Units of Measure ......................................................... 36
Reset.................................................................................... 8
Hard Reset .................................................................... 8
Soft Reset...................................................................... 8
Document History Page................................................... 37
Sales, Solutions, and Legal Information ........................ 38
Worldwide Sales and Design Support......................... 38
Products...................................................................... 38
PSoC Solutions........................................................... 38
Clocking .............................................................................. 8
32-kHz Watchdog Timer Clock Input............................. 8
Power................................................................................... 9
Power Modes ................................................................ 9
Configuration Options ..................................................... 13
Document Number 001-52136 Rev. *H
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PRELIMINARY
CYUSB3014
EZ-USB FX3 contains 512 kB of on-chip SRAM for code and
data. EZ-USB FX3 also provides interfaces to connect to serial
peripherals such as UART, SPI, I2C, and I2S.
Functional Overview
Cypress EZ-USB FX3 is the next generation USB3.0 peripheral
controller providing highly integrated and flexible features that
enable developers to add USB3.0 functionality to any system.
EZ-USB FX3 comes with the easy to use EZ-USB tools providing
a complete solution for fast application development. The
software development kit comes with application examples for
accelerating time to market.
EZ-USB FX3 has a fully configurable, parallel, General
Programmable Interface called GPIF II, which can connect to
any processor, ASIC, or FPGA. The General Programmable
Interface GPIF II is an enhanced version of the GPIF in FX2LP,
Cypress’s flagship USB2.0 product. It provides easy and
glueless connectivity to popular interfaces such as
asynchronous SRAM, asynchronous and synchronous Address
Data Multiplexed interface, parallel ATA, and so on.
EZ-USB FX3 is fully compliant to USB3.0 v1.0 specification and
is also backward compatible with USB2.0. It is also complaint
with the Battery Charging Specification v1.1 and USB2.0 OTG
Specification v2.0.
Application Examples
EZ-USB FX3 has integrated USB3.0 and USB2.0 physical layer
(PHYs) along with a 32-bit ARM926EJ-S microprocessor for
powerful data processing and for building custom applications. It
implements an ingenious architecture which enables data
transfers of 320 MBps[1] from GPIF II to USB interface.
Figure 1 and Figure 2 show typical application diagrams for
EZ-USB FX3. Figure 1 shows a typical application diagram in
which EZ-USB FX3 functions as a co-processor and connects to
an external processor responsible for various system level
functions. Figure 2 shows a typical application diagram when
EZ-USB FX3 functions as the main processor in the system.
An integrated USB2.0 OTG controller enables applications that
need dual role usage scenarios, for example EZ-USB FX3 may
function as OTG Host to MSC and HID class devices.
Figure 1. EZ-USB FX3 as a Co-processor
POWER
SUBSYSTEM
CRYSTAL*
External Processor
EZ-USB FX3
(ARM9 Core)
USB
Port
GPIF II
USB Host
(example: MCU/CPU/ASIC/
FPGA)
Serial Interfaces
(example: I2C)
External Serial Peripheral
(example: EEPROM)
* A clock input may be provided on the
CLKIN pin instead of a crystal input
Note
1. Assuming that GPIF II is configured for 32 bit data bus synchronous interface operating at 100 MHz. This number also includes protocol overheads.
Document Number 001-52136 Rev. *H
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CYUSB3014
Figure 2. EZ-USB FX3 as Main Processor
CRYSTAL*
EXTERNAL SLAVE
DEVICE
(Eg: IMAGE SENSOR)
EZ-USB FX3
(ARM9 Core)
USB
Port
GPIF II
USB Host
I2C
* A clock input may be provided on the
CLKIN pin instead of a crystal input
EEPROM
Figure 3. USB Interface Signals
USB Interface
EZ-USB FX3
EZ-USB FX3 supports USB peripheral functionality compliant
with USB 3.0 Specification Revision 1.0 and is also backward
compatible with the USB 2.0 Specification.
VBATT
VBUS
EZ-USB FX3 is compliant with On-The-Go Supplement Revision
2.0. It supports Hi-Speed, Full-Speed, and Low Speed OTG dual
role device capability. It is SuperSpeed, High-Speed, and
Full-Speed capable as a peripheral and High-Speed, Full-Speed,
and Low-Speed capable as a host.
OTG_ID
SSRX-
SSRX+
SSTX-
SSTX+
D-
D+
EZ-USB FX3 supports Carkit Pass-Through UART functionality
on USB D+/D- lines based on the CEA-936A specification.
EZ-USB FX3 supports up to 16 IN and 16 OUT endpoints.
OTG
EZ-USB FX3 fully supports the USB3.0 Streams feature. It also
supports USB Attached SCSI (UAS) device class to optimize
mass storage access performance.
EZ-USB FX3 is compliant with the On-The-Go (OTG) Specifi-
cation Revision 2.0 .
As a USB peripheral, EZ-USB FX3 supports UAS, USB Video
Class (UVC), Mass Storage Class (MSC), and Media Transfer
Protocol (MTP) USB peripheral classes. As a USB peripheral, all
other device classes are supported only in pass through mode
when handled entirely by a host processor external to the device.
In OTG mode, EZ-USB FX3 supports both A and B device mode
and supports Control, Interrupt, Bulk, and Isochronous data
transfers.
EZ-USB FX3 requires an external charge pump (either stand
alone or integrated into a PMIC) to power VBUS in OTG A-device
mode.
As an OTG host, EZ-USB FX3 supports MSC and HID device
classes.
The Target Peripheral List for OTG host implementation consists
of MSC and HID class devices.
When the USB port is not in use, the PHY and transceiver may
be disabled for power savings.
Attach Detection Protocol (ADP) is not supported by EZ-USB
FX3.
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CYUSB3014
OTG Connectivity
VBUS Overvoltage Protection
In OTG mode, EZ-USB FX3 can be configured to be A, B, or dual
role device. It is able to connect to:
The maximum input voltage on EZ-USB FX3's VBUS pin is 6V.
A charger can supply up to 9V on VBUS, in this case, it is
necessary to have an external Over voltage Protection (OVP)
device to protect EZ-USB FX3 from damage on VBUS. Figure 4
shows the system application diagram with an OVP device
connected on VBUS. Please refer to Table 7DC Specifications
for the operating range of VBUS and VBATT.
■ ACA device
■ Targeted USB peripheral
■ SRP capable USB peripheral
■ HNP capable USB peripheral
■ OTG host
Figure 4. System Diagram with OVP Device For VBUS
■ HNP capable host
■ OTG device
POWER SUBSYSTEM
ReNumeration
Because EZ-USB FX3's configuration is soft, one chip can take
on the identities of multiple distinct USB devices.
When first plugged into USB, EZ-USB FX3 enumerates
automatically with the Cypress Vendor ID (0x04B4) and
downloads firmware and USB descriptors over the USB
interface. The downloaded firmware executes a electrical
disconnect and connect. EZ-USB FX3 enumerates again, this
time as a device defined by the downloaded information. This
patented two step process called ReNumeration happens
instantly when the device is plugged in.
EZ-USB FX3
VBUS
OTG_ID
1
2
OVP device
SSRX-
SSRX+
SSTX-
SSTX+
D-
3
4
5
6
7
8
9
D+
GND
EZ-Dtect
EZ-USB FX3 supports USB Charger and accessory detection
(EZ-Dtect). The charger detection mechanism is in compliance
with the Battery Charging Specification Revision 1.1. In addition
to supporting this version of the specification EZ-USB FX3 also
provides hardware support to detect the resistance values on the
ID pin.
Carkit UART Mode
The USB interface supports Carkit UART mode (UART over
D+/D-) for non-USB serial data transfer. This is based on the
CEA-936A specification.
The following are the resistance ranges that EZ-USB FX3 can
detect:
In Carkit UART mode, the output signaling voltage is 3.3V. When
configured for Carkit UART mode, TXD of UART (output) is
mapped to D- line, and RXD of UART (input) is mapped to D+
line.
■ Less than 10 Ω
■ Less than 1 kΩ
In Carkit mode, EZ-USB FX3 disables the USB transceiver and
D+ and D- pins serve as pass through pins to connect to the
UART of the host processor. The Carkit UART signals may be
routed to the GPIF II interface or to GPIO[48] and GPIO[49] as
shown in Figure 5 on page 6.
■ 65 kΩ to 72 kΩ
■ 35 kΩ to 39 kΩ
■ 99.96 kΩ to 104.4 kΩ (102 kΩ ± 2%)
■ 119 kΩ to 132 kΩ
A rate of up to 9600 bps is supported by EZ-USB FX3 in this
mode.
■ Higher than 220 kΩ
■ 431.2 kΩ to 448.8 kΩ (440 kΩ ± 2%)
EZ-USB FX3's charger detection feature detects a dedicated
wall charger, Host/Hub charger, and Host/Hub.
Document Number 001-52136 Rev. *H
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PRELIMINARY
CYUSB3014
Figure 5. Carkit UART Pass Through Block Diagram
Carkit UART Pass Through
Carkit UART pass through
UART_TXD
UART_RXD
TXD
RXD
RXD (DP)
TXD (DM)
interface on GPIF(TM)II
interface.
DP
USB PHY
DM
GPIO[48]
(UART_TX)
Carkit UART pass through
interface on GPIOs
GPIO[49]
(UART_RX)
Note: Access to all 32 buffer is also supported over Slave FIFO
interface. For details, please contact Cypress Applications
Support.
GPIF II
EZ-USB FX3 offers a high performance General Programmable
Interface, GPIF II. This interface enables functionality similar to
but more advanced than FX2LP's GPIF and Slave FIFO
interfaces.
Figure 6. Slave FIFO Interface
SLCS#
PKTEND
FLAGB
FLAGA
The GPIF II is a programmable state machine that enables a
flexible interface that may function either as a master or slave in
industry standard or proprietary interfaces. Both parallel and
serial interfaces may be implemented with GPIF II.
A[1:0]
External
Processor
D[31:0]
SLWR#
SLRD#
EZ-USB FX3
The features of the GPIF II are summarized as follows:
■ Functions as master or slave
SLOE#
■ Provides 256 firmware programmable states
■ Supports 8 bit, 16 bit and 32 bit parallel data bus
■ Enables interface frequencies up to 100 MHz.
Note: Multiple Flags may be configured.
■ Supports 14 configurable control pins when 32 bit data bus is
used. All control pins can be either input/output or bidirectional.
CPU
EZ-USB FX3 has an on chip 32-bit, 200 MHz ARM926EJ-S core
CPU. The core has direct access to 16kB of Instruction Tightly
Coupled Memory (TCM) and 8kB of Data TCM. The
ARM926EJ-S core provides a JTAG interface for firmware
debugging.
■ Supports 16 configurable control pins when 16/8 data bus is
used. All control pins can be either input/output or bidirectional.
GPIFII state transitions occur based on control input signals. The
control output signals are driven as a result of GPIFII state transi-
tions. The behavior of the GPIFII state machine is defined by a
GPIFII descriptor. The GPIFII descriptor is designed such that
the required interface specifications are met. 8kB of memory
(separate from the 512kB of embedded SRAM) is dedicated as
GPIF II Waveform memory where the GPIF II descriptor is stored
in a specific format.
EZ-USB FX3 also integrates 512 kB of embedded SRAM for
code and data, and 8kB of Instruction cache and Data cache.
EZ-USB FX3 implements highly efficient and flexible DMA
connectivity between the various peripherals (i.e. USB, GPIF II,
I2S, SPI,UART), requiring firmware to only configure data
accesses between peripherals which are then managed by the
DMA fabric.
Cypress’ GPIFII Designer Tool enables fast development of
GPIFII descriptors and includes examples for common inter-
faces.
EZ-USB FX3 allows for easy application development on
industry standard development tools for ARM926EJ-S.
Example implementations of GPIF II are the Asynchronous
Slave FIFO and Synchronous Slave FIFO interfaces.
Examples of EZ-USB FX3 firmware are available with the
Cypress EZ-USB FX3 Development Kit.
Slave FIFO interface
Software APIs that can be ported to an external processor are
available with the Cypress EZ-USB FX3 Software Development
Kit.
The Slave FIFO interface signals are shown in Figure 6. This
interface allows an external processor to directly access upto 4
buffers internal to EZ-USB FX3. Further details of the Slave FIFO
interface are described on page 19
Document Number 001-52136 Rev. *H
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Both SCL and SDA signals of the I2C interface require external
pull-up resistors. The pull-up resistors must be connected to
VIO5.
JTAG Interface
EZ-USB FX3’s JTAG interface provides a standard five-pin
interface for connecting to a JTAG debugger to debug firmware
through the CPU-core's on-chip-debug circuitry.
2
I S Interface
EZ-USB FX3 has an I2S port to support external audio codec
devices. EZ-USB FX3 functions as I2S Master as transmitter
only. The I2S interface consists of four signals: clock line
(I2S_CLK), serial data line (I2S_SD), word select line (I2S_WS),
and master system clock (I2S_MCLK). EZ-USB FX3 can
generate the system clock as an output on I2S_MCLK or accept
an external system clock input on I2S_MCLK.
Industry standard debugging tools for the ARM926EJ-S core can
be used for EZ-USB FX3 application development.
Other Interfaces
EZ-USB FX3 supports the following serial peripherals:
■ UART
■ I2C
The sampling frequencies supported by the I2S interface are
32 kHz, 44.1 kHz, and 48 kHz.
■ I2S
SPI Interface
■ SPI
EZ-USB FX3 supports an SPI Master interface on the Serial
Peripherals port.The maximum frequency of operation is
33 MHz.
The SPI, UART and I2S interfaces are multiplexed on the Serial
Peripheral port.
The SPI controller supports four modes of SPI communication
with Start-Stop clock. The SPI controller is a single master
controller with a single automated SSN control. It supports
transaction sizes from 4-bit to 32 bits long.
The Pin List on page 32 shows details of how these interfaces
are multiplexed.
UART Interface
The UART interface of EZ-USB FX3 supports full duplex
communication. It includes the signals noted in Table 1.
Boot Options
EZ-USB FX3 can load boot images from various sources,
selected by the configuration of the PMODE pins. The boot
options for EZ-USB FX3 are listed as follows:
Table 1. UART Interface Signals
Signal
TX
Description
Output signal
Input signal
Flow control
Flow control
■ Boot from USB
■ Boot from I2C
RX
CTS
RTS
■ Boot from SPI (SPI devices supported are M25P16 (16 Mbit),
M25P80 (8 Mbit), and M25P40 (4 Mbit)) or their equivalents
■ Boot from GPIF II ASync ADMUX mode
■ Boot from GPIF II Sync ADMUX mode
■ Boot from GPIF II ASync SRAM mode
The UART is capable of generating a range of baud rates from
300 bps to 4608 Kbps selectable by the firmware.
2
I C Interface
EZ-USB FX3 has an I2C interface compatible with the I2C Bus
Specification Revision 3. EZ-USB FX3’s I2C interface is capable
of operating as I2C Master only, hence may be used to
communicate with other I2C slave devices. For example,
EZ-USB FX3 may boot from an EEPROM connected to the I2C
interface, as a selectable boot option.
EZ-USB FX3’s I2C Master Controller also supports Multi-master
mode functionality.
The power supply for the I2C interface is VIO5, which is a
separate power domain from the other serial peripherals. This is
to allow the I2C interface the flexibility to operate at a different
voltage than the other serial interfaces.
Table 2. Booting Options for EZ-USB FX3
PMODE[2:0][2]
Boot From
Sync ADMUX (16-bit)
F00
F01
F11
F0F
F1F
1FF
0F1
Async ADMUX (16-bit)
USB boot
Async SRAM (16-bit)
I2C, On Failure, USB Boot is Enabled
I2C only
SPI, On Failure, USB Boot is Enabled
The bus frequencies supported by the I2C controller are 100 kHz,
400 kHz, and 1 MHz. When VIO5 is 1.2V, the maximum
operating frequency supported is 100 kHz. When VIO5 is 1.8 V,
2.5 V or 3.3 V, the operating frequencies supported are 400 kHz
and 1 MHz.
Note
2. F indicates Floating.
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Reset
Clocking
EZ-USB FX3 allows either a crystal to be connected between the
XTALIN and XTALOUT pins or an external clock to be connected
at the CLKIN pin.
Hard Reset
A hard reset is initiated by asserting the Reset# pin on EZ-USB
FX3. The specific reset sequence and timing requirements are
detailed in Figure 17 and Table 15.
Crystal frequency supported is 19.2 MHz, while the external
clock frequencies supported are 19.2, 26, 38.4, and 52 MHz.
Soft Reset
EZ-USB FX3 has an on-chip oscillator circuit that uses an
external 19.2 MHz (±100 ppm) crystal (when the crystal option is
used). The FSLC[2:0] pins must be configured appropriately to
select the crystal option/clock frequency option. The configu-
ration options are shown in Table 3.
Soft Reset involves the processor setting the appropriate bits in
the PP_INIT control register. There are two types of Soft Reset:
■ CPU Reset - The CPU Program Counter is reset. Firmware
does not need to be reloaded following a CPU Reset.
Clock inputs to EZ-USB FX3 must meet the phase noise and
jitter requirements specified in Table 4.
■ Whole Device Reset - This reset is identical to Hard Reset. The
firmware must be reloaded following a Whole Device Reset.
The input clock frequency is independent of the clock/data rate
of EZ-USB FX3 core or any of the device interfaces (including
P-Port and S-Port). The internal PLL applies the appropriate
clock multiply option depending on the input frequency.
Table 3. Crystal/Clock Frequency Selection
FSLC[2]
FSLC[1]
FSLC[0]
Crystal/ Clock Frequency
19.2 MHz crystal
0
1
1
1
1
0
0
0
1
1
0
0
1
0
1
19.2 MHz input CLK
26 MHz input CLK
38.4 MHz input CLK
52 MHz input CLK
Table 4. Input Clock Specifications for EZ-USB FX3
Parameter Description
Phase noise
Specification
Units
Min
–
Max
–75
–104
–120
–128
–130
150
70
100 Hz Offset
1 kHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
dB
dB
dB
dB
dB
ppm
%
–
–
–
–
Maximum frequency deviation
Duty cycle
–
30
–
Overshoot
3
%
Undershoot
–
–3
%
Rise time/fall time
–
3
ns
Requirements for the optional 32 kHZ clock input are listed in
Table 5.
32-kHz Watchdog Timer Clock Input
EZ-USB FX3 includes a watchdog timer. The watchdog timer can
be used to interrupt the ARM926EJ-S core, auto wakeup
EZ-USB FX3 in Standby mode and reset the ARM926EJ-S core.
The watch dog timer runs off a 32 kHz clock. This 32 kHz clock
may optionally be supplied from an external source on a
dedicated pin of EZ-USB FX3.
Table 5. 32 kHz Clock Input Requirements
Parameter
Duty cycle
Min
40
–
Max
60
Units
%
Frequency deviation
Rise time/fall time
±200
3
ppm
ns
The watchdog timer can be disabled by firmware.
–
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CYUSB3014
VBATT/VBUS: This is the 3.2V to 6V battery power supply for
the USB I/O, and analog circuits. This supply powers the USB
transceiver through EZ-USB FX3's internal voltage regulator.
VBATT is internally regulated to 3.3V.
Power
EZ-USB FX3 has the following power supply domains.
IO_VDDQ: This refers to a group of independent supply domains
for digital I/Os. The voltage level on these supplies is 1.8V to
3.3V. EZ-USB FX3 provides six independent supply domains for
digital I/Os listed as follows. Refer to Table 16 for details on the
signals assigned to each power domain.
Power Modes
EZ-USB FX3 supports different power modes as follows:
■ Normal mode: This is the full functional operating mode. In this
■ VIO1 - GPIF II I/O power supply domain
■ VIO2 - IO2 power supply domain
mode the internal CPU clock and the internal PLLs are enabled.
Normal operating power consumption does not exceed the sum
of ICC_CORE max and ICC_USB max (please refer to Table 7
for current consumption specifications).
■ VIO3 - IO3 power supply domain
■ VIO4 - UART/SPI/I2S power supply domain
The I/O power supplies (VIO1,VIO2,VIO3,VIO4, VIO5) may be
turned off when the corresponding interface is not in use.
■ VIO5 - I2C and JTAG power supply domain (1.2V to 3.3V is
EZ-USB FX3 supports four low power modes:
■ Suspend mode with USB 3.0 PHY enabled (L1)
■ Suspend mode with USB 3.0 PHY disabled (L2)
■ Standby mode (L3)
supported)
■ CVDDQ - Clock power supply domain
■ VDD: This is the supply voltage for the logic core. The nominal
supply voltage level is 1.2 V. This supplies the core logic
circuits. The same supply must also be used for the following:
■ Core power down mode (L4)
❐ AVDD: This is the 1.2 V supply for the PLL, crystal oscillator
and other core analog circuits
❐ U3TXVDDQ/U3RXVDDQ: These are the 1.2 V supply volt-
ages for the USB 3.0 interface.
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The different low power modes are described in Table 6..
Table 6. Entry and Exit Methods for Low Power Modes
Low Power Mode Characteristics
Suspend Mode with ■ Thepowerconsumptioninthis ■ Firmware executing on
Methods of Entry
Methods of Exit
■ D+ transitioning to low or high
■ D- transitioning to low or high
■ Impedance change on OTG_ID pin
■ Resume condition on SSRX +/-
■ Detection of VBUS
USB 3.0 PHY
Enabled (L1)
mode does not exceed ISB1
ARM926EJ-ScorecanputEZ-USB
FX3 into suspend mode. For
example, on USB suspend
condition, firmware may decide to
put EZ-USB FX3 into suspend
mode
■ USB 3.0 PHY is enabled and
is in U3 mode (one of the
suspend modes defined by
the USB3.0 specification).
This one block alone is opera-
tional with its internal clock
while all other clocks are shut
down
■ External Processor, through the
use of mailbox registers can put
EZ-USB FX3 into suspend mode
■ Level detect on UART_CTS
(programmable polarity)
■ GPIF II interface assertion of
CTL[0]
■ AllI/Osmaintaintheirprevious
state
■ Assertion of RESET#
■ Power supply for the wakeup
source and core power must
be retained. All other power
domains can be turned on/off
individually
■ Thestatesoftheconfiguration
registers, buffer memory and
all internal RAM are
maintained
■ All transactions must be
completed before EZ-USB
FX3 enters Suspend mode
(state of outstanding transac-
tions are not preserved)
■ The firmware resumes
operation from where it was
suspended (except when
woken up by RESET#
assertion) because the
program counter does not
reset
Document Number 001-52136 Rev. *H
Page 10 of 38
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CYUSB3014
Table 6. Entry and Exit Methods for Low Power Modes (continued)
Low Power Mode
Characteristics
Methods of Entry
Methods of Exit
Suspend Mode with ■ Thepowerconsumptioninthis ■ Firmware executing on
■ D+ transitioning to low or high
■ D- transitioning to low or high
■ Impedance change on OTG_ID pin
■ Resume condition on SSRX +/-
■ Detection of VBUS
USB 3.0 PHY
Disabled (L2)
mode does not exceed ISB2
ARM926EJ-ScorecanputEZ-USB
FX3 into suspend mode. For
example, on USB suspend
condition, firmware may decide to
put EZ-USB FX3 into suspend
mode
■ USB 3.0 PHY is disabled and
the USB interface is in
suspend mode
■ The clocks are shut off. The
PLLs are disabled
■ External Processor, through the
use of mailbox registers can put
EZ-USB FX3 into suspend mode
■ Level detect on UART_CTS
(programmable polarity)
■ AllI/Osmaintaintheirprevious
state
■ GPIF II interface assertion of
CTL[0]
■ USB interface maintains the
previous state
■ Assertion of RESET#
■ Power supply for the wakeup
source and core power must
be retained. All other power
domains can be turned on/off
individually
■ Thestatesoftheconfiguration
registers, buffer memory and
all internal RAM are
maintained
■ All transactions must be
completed before EZ-USB
FX3 enters Suspend mode
(state of outstanding transac-
tions are not preserved)
■ The firmware resumes
operation from where it was
suspended (except when
woken up by RESET#
assertion) because the
program counter does not
reset
Document Number 001-52136 Rev. *H
Page 11 of 38
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CYUSB3014
Table 6. Entry and Exit Methods for Low Power Modes (continued)
Low Power Mode
Characteristics
Methods of Entry
Methods of Exit
■ Detection of VBUS
Standby Mode (L3) ■ Thepowerconsumptioninthis ■ Firmware executing on
mode does not exceed ISB3
ARM926EJ-S core or external
processor configures the appro-
priate register
■ Level detect on UART_CTS
(Programmable Polarity)
■ All configuration register
settings and program/data
RAM contents are preserved.
However, datainthebuffersor
other parts of the data path, if
any, is not guaranteed.
■ GPIF II interface assertion of
CTL[0]
■ Assertion of RESET#
Therefore, the external
processor should take care
that needed data is read
before putting EZ-USB FX3
into this Standby Mode
■ The program counter is reset
on waking up from Standby
mode
■ GPIO pins maintain their
configuration
■ Crystal oscillator is turned off
■ Internal PLL is turned off
■ USB transceiver is turned off
■ ARM926EJ-Scoreispowered
down. Upon wakeup, the core
re-startsandrunstheprogram
stored in the program/data
RAM
■ Power supply for the wakeup
source and core power must
be retained. All other power
domains can be turned on/off
individually
Core Power Down
Mode (L4)
■ Thepowerconsumptioninthis ■ Turn off VDD
mode does not exceed ISB4
■ Reapply VDD
■ Assertion of RESET#
■ Core power is turned off
■ All buffer memory, configu-
ration registers and the
program RAM do not maintain
state. It is necessary to reload
the firmware on exiting from
this mode
■ In this mode, all other power
domains can be turned on/off
individually
Document Number 001-52136 Rev. *H
Page 12 of 38
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PRELIMINARY
CYUSB3014
Configuration Options
EMI
EZ-USB FX3 meets EMI requirements outlined by FCC 15B
(USA) and EN55022 (Europe) for consumer electronics.
EZ-USB FX3 can tolerate reasonable EMI conducted by
aggressor outlined by these specifications and continue to
function as expected.
Configuration options are available for specific usage models.
Contact Cypress Applications/Marketing for details.
Digital I/Os
EZ-USB FX3 provides firmware controlled pull up or pull down
resistors internally on all digital I/O pins. The pins can be pulled
high through an internal 50 kΩ resistor or can be pulled low
through an internal 10 kΩ resistor to prevent the pins from
floating. The I/O pins may have the following states:
System Level ESD
EZ-USB FX3 has built-in ESD protection on the D+, D-, GND
pins on the USB interface. The ESD protection levels provided
on these ports are:
■ Tristated (High-Z)
■ ± 2.2 KV Human Body Model (HBM) based on JESD22-A114
Specification
■ Weak Pull up (via internal 50 kΩ)
■ Pull down (via internal 10 kΩ)
■ ± 6 KV Contact Discharge and ± 8 KV Air Gap Discharge based
on IEC61000-4-2 level 3A
■ Hold (I/O hold its value) when in low power modes
■ ± 8 KV Contact Discharge and ± 15 KV Air Gap Discharge
based on IEC61000-4-2 level 4C.
■ The JTAG signals TDI, TMC, TRST# signals have fixed 50 kΩ
internal pull-ups & the TCK signal has a fixed 10 kΩ pull down
resistor.
This protection ensures the device will continue to function after
ESD events up to the levels stated.
GPIOs
The SSRX+, SSRX-, SSTX+, SSTX- pins only have up to +/-
2.2KV Human Body Model (HBM) internal ESD protection.
EZ-USB allows for a flexible pin configuration both on the GPIF
II and the serial peripheral interfaces. Any unused control pins
on the GPIF II interface may be used as GPIOs. Similarly, any
unused pins on the serial peripheral interfaces may be
configured as GPIOs. Please refer to the Pin List for pin config-
uration options.
All GPIF II and GPIO pins support an external load of up to 16pF
per pin.
Document Number 001-52136 Rev. *H
Page 13 of 38
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PRELIMINARY
CYUSB3014
Contact discharge, ± 8 KV air gap discharge based on
IEC61000-4-2 level 3A and ± 8 KV contact discharge, ± 15 KV
air gap discharge based on IEC61000-4-2 level 4C
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device.
Latch up current...........................................................> 200 mA
Maximum output short circuit current
Storage temperature..................................... –65 °C to +150 °C
Ambient temperature with
power supplied (Industrial).................... ......... –40 °C to +85 °C
for all I/O configurations. (Vout = 0V)[1].................... .. –100 mA
Operating Conditions
Supply voltage to ground potential
VDD, AVDDQ .......................................................................TBD
TA (ambient temperature under bias)
VIO1,VIO2, VIO3, VIO4, VIO5.............................................TBD
U3TXVDDQ, U3RXVDDQ...................................................TBD
DC input voltage to any input pin.........................................TBD
Industrial......................................................... –40 °C to +85 °C
VDD, AVDDQ, U3TXVDDQ, U3RXVDDQ
Supply voltage...................................................1.15 V to 1.25 V
VBATT supply voltage.......................... ....................3.2 V to 6 V
VIO1, VIO2, VIO3, VIO4, CVDDQ
DC voltage applied to
outputs in high Z state.................... ..................................... TBD
Static discharge voltage
ESD protection levels............................................................
Supply voltage.......................................................1.7 V to 3.6 V
VIO5 supply voltage...................... .................... 1.15 V to 3.6 V
± 2.2 KV human body model (HBM) based on JESD22-A114
Additional ESD protection levels on D+, D-,
GND pins and serial Peripherals pins................. ........... ± 6 KV
Table 7. DC Specifications
Parameter
VDD
Description
Core voltage supply
Min
1.15
1.15
1.7
Max
1.25
1.25
3.6
Units
V
Notes
1.2 V typical
1.2 V typical
AVDD
Analog voltage supply
V
VIO1
GPIF II I/O power supply domain
IO2 power supply domain
IO3 power supply domain
UART/SPI/I2S power supply domain
USB voltage supply
V
1.8, 2.5 and 3.3 V typical
1.8, 2.5 and 3.3 V typical
1.8, 2.5 and 3.3 V typical
1.8, 2.5 and 3.3 V typical
3.7 V typical
VIO2
1.7
3.6
V
VIO3
1.7
3.6
V
VIO4
1.7
3.6
V
VBATT
VBUS
3.2
6
V
USB voltage supply
4.1
6
V
5 V typical
U3TXVDDQ
U3RXVDDQ
CVDDQ
VIO5
USB3.0 1.2-V supply
1.15
1.15
1.7
1.25
1.25
3.6
V
1.2 V typical
USB3.0 1.2-V supply
V
1.2 V typical
Clock voltage supply
I2C and JTAG voltage supply
V
1.8,3.3 V typical
1.15
0.625 × VCC
3.6
V
1.2,1.8, 2.5 and 3.3 V typical
VIH1
Input HIGH voltage 1
VCC + 0.3
V
For 2.0V ≤ VCC ≤ 3.6 V
(except USB port)
VIH2
Input HIGH voltage 2
VCC – 0.4
VCC + 0.3
V
For 1.7 V ≤ VCC ≤ 2.0 V
(except USB port)
VIL
Input LOW voltage
Output HIGH voltage
Output LOW voltage
Input leakage current
–0.3
0.25 × VCC
V
V
VOH
VOL
IIX
0.9 × VCC
–
0.1 × VCC
1
IOH (max)= –100 µA
IOL(min) = +100 µA
–
V
–1
µA
All I/O signals held at VDDQ
(For I/Os that have a
pull-up/down resistor
connected, the leakage
current increases by
VDDQ/Rpu or VDDQ/RPD
IOZ
Output High-Z leakage current
–1
1
µA
All I/O signals held at VDDQ
Document Number 001-52136 Rev. *H
Page 14 of 38
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CYUSB3014
Table 7. DC Specifications (continued)
Parameter
Description
Core and analog voltage operating
current
Min
Max
Units
Notes
ICC Core
–
200
mA
Total current through AVDD,
VDD
ICC USB
ISB1
USB voltage supply operating current
–
–
60
–
mA
mA
Total suspend current during suspend
mode with USB 3.0 PHY enabled (L1)
Core Current: 1.5 mA
IO Current: 20 uA
USB Current: 2 mA
for Typical PVT (Typical
silicon, all power supplies at
their respective nominal levels
at 25°C.)
ISB2
ISB3
ISB4
Total suspend current during suspend
mode with USB 3.0 PHY disabled (L2)
–
–
–
–
–
–
mA
µA
µA
Core Current: 250 uA
IO Current: 20 uA
USB Current: 1.2 mA
for Typical PVT (Typical
silicon, all power supplies at
their respective nominal levels
at 25°C.)
Total standby current during standby
mode (L3)
Core Current: 60 uA
IO Current: 20 uA
USB Current: 40 uA
for Typical PVT (Typical
silicon, all power supplies at
their respective nominal levels
at 25°C.)
Total standby current during core
power-down mode (L4)
Core Current: 0 uA
IO Current: 20 uA
USB Current: 40 uA
for Typical PVT (Typical
silicon, all power supplies at
their respective nominal levels
at 25°C.)
VRAMP
VN
Voltage ramp rate on core and I/O
supplies
0.2
–
50
100
20
V/ms Voltage ramp must be
monotonic
Noise level permitted on VDD and I/O
supplies
mV
Max p-p noise level permitted
on all supplies except AVDD
VN_AVDD
Noise level permitted on AVDD supply
–
mV
Max p-p noise level permitted
on AVDD
Document Number 001-52136 Rev. *H
Page 15 of 38
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PRELIMINARY
CYUSB3014
AC Timing Parameters
GPIF II Timing
Figure 7. GPIF II Timing in Synchronous Mode
tCLKH tCLKL
CLK
tCLK
tCO
tHZ
tDOH
tCOE
tDS tDH
tDOH
tLZ
tLZ
Data1
( OUT)
Data2
( OUT)
DQ- [31:0]
Data(IN)
tS tH
CTL(IN)
tCTLO
tCOH
CTL( OUT)
Table 8. GPIF II Timing Parameters in Synchronous Mode[3]
Parameter Description
Frequency
Min
–
Max
100
–
Unit
MHz
ns
Interface clock frequency
Interface clock period
Clock high time
tCLK
tCLKH
tCLKL
tS
10
4
–
ns
Clock low time
4
–
ns
CTL input to clock setup time
(Sync speed =1)
2
–
ns
tH
CTL input to clock hold time
(Sync speed =1)
0.5
2
–
–
–
8
9
ns
ns
ns
ns
tDS
tDH
tCO
tCOE
Data in to clock setup time
(Sync speed =1)
Data in to clock hold time
(Sync speed =1)
0.5
–
Clock to data out propagation delay when DQ bus is already in
output direction(Sync speed =1)
Clock to data out propagation delay when DQ lines change to
output from tristate and valid data is available on the DQ bus
(Sync speed =1)
-
tCTLO
tDOH
tCOH
tHZ
Clock to CTL out propagation delay (Sync speed =1)
Clock to data out hold
–
2
8
–
ns
ns
ns
ns
ns
ns
ns
ns
Clock to CTL out hold
0
–
Clock to High-Z
–
8
tLZ
Clock to Low-Z (Sync speed =1)
0
–
tS_ss0
tH_ss0
tCO_ss0
CTL input/data input to clock setup time (Sync speed = 0)
CTL input/data input to clock hold time (Sync speed = 0)
5
–
2.5
–
–
Clock to data out / CTL out
15
propagation delay (sync speed = 0)
tLZ_ss0
Clock to low-Z (sync speed = 0)
2
–
ns
Note
3. All parameters guaranteed by design and validated through characterization.
Document Number 001-52136 Rev. *H
Page 16 of 38
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CYUSB3014
Figure 8. GPIF II Timing in Asynchronous Mode
tAH
tDH/
tDS/ tAS
DATA/ ADDR
DATA IN
tCHZ
tCTLassert_DQlatch
tCTLdeassert_DQlatch
CTL#
(I/P, ALE/DLE)
tAA/tDO
tCHZ/tOEHZ
tCLZ/ tOELZ
DATA OUT
DATA OUT
CTL#
(I/P, non ALE/ DLE
tCTLdeassert
tCTLassert
tCTLalpha
ALPHA
O/P
tCTLbeta
BETA
O/P
1
tCTLassert + n * tGRANULARITY1
tCTLdeassert + n * tGRANULARITY
tCTL#
(O/P)
1. n is an integer >= 0
tDST
tDHT
DATA/
ADDR
tCTLdeassert_DQassert
tCTLassert_DQassert
CTL#
I/P (non DLE/ALE)
Figure 9. GPIF II Timing in Asynchronous DDR Mode
tDS
tCTLdeassert_DqlatchDDR
tCTLassert_DQlatchDDR
CTL#
(I/P)
tDS
tDH
tDH
DATA IN
Document Number 001-52136 Rev. *H
Page 17 of 38
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PRELIMINARY
CYUSB3014
[4]
Table 9. GPIF II Timing in Asynchronous Mode
Note The following parameters assume one state transition
Parameter Description
Min
Max Units
Notes
tDS
tDH
Data In to DLE setup time. Valid in DDR async
also.
2.3
–
ns
Data In to DLE hold time. Valid in DDR async
mode.
2
–
ns
tAS
tAH
Address In to ALE setup time
Address In to ALE hold time
2.3
2
–
–
–
ns
ns
ns
tCTLassert
CTL I/O asserted width for CTRL inputs without
DQ input association and for outputs.
7
tCTLdeassert
CTL I/O deasserted width for CTRL inputs
without DQ input association and for outputs.
7
–
–
ns
ns
tCTLassert_DQassert
CTL asserted pulse width for CTL inputs that
signify DQ inputs valid at the asserting edge but
do not employ in-built latches (ALE/DLE) for
those DQ inputs.
20
tCTLdeassert_DQassert
tCTLassert_DQdeassert
tCTLdeassert_DQdeassert
tCTLassert_DQlatch
CTL deasserted pulse width for CTL inputs that
signify DQ input valid at the asserting edge but
do not employ in-built latches (ALE/DLE) for
those DQ inputs.
7
7
–
–
–
–
–
ns
ns
ns
ns
ns
CTL asserted pulse width for CTL inputs that
signify DQ inputs valid at the de-asserting edge
but do not employ in-built latches (ALE/DLE) for
those DQ inputs.
CTL deasserted pulse width for CTL inputs that
signify DQ inputs valid at the deasserting edge
but do not employ in-built latches (ALE/DLE) for
those DQ inputs.
20
7
CTL asserted pulse width for CTL inputs that
employ in-built latches (ALE/DLE) to latch the
DQ inputs. In this non_DDR case, in-built
latches always close at the de-asserting edge.
tCTLdeassert_DQlatch
CTL deasserted pulse width for CTL inputs that
employ in-built latches (ALE/DLE) to latch the
DQ inputs. In this non-DDR case, in-built
latches always close at the de-asserting edge.
10
tCTLassert_DQlatchDDR
tCTLdeassert_DQlatchDDR
CTL asserted pulse width for CTL inputs that
employ in-built latches (DLE) to latch the DQ
inputs in DDR mode.
10
10
–
–
ns
ns
CTL deasserted pulse width for CTL inputs that
employ in-built latches (DLE) to latch the DQ
inputs in DDR mode.
tGRANULARITY
tAA
Granularity of tCTLassert/tCTLdeassert for all
outputs
5
–
–
ns
ns
At 200 MHz internal
clock
DQ/CTL input to DQ output time when DQ
change or CTL change needs to be detected
and affects internal updates of input and output
DQ lines.
30
tDO
CTL to data out when the CTL change merely
enables the output flop update whose data was
already established.
–
25
ns
Note
4. All parameters guaranteed by design and validated through characterization.
Document Number 001-52136 Rev. *H
Page 18 of 38
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CYUSB3014
[4]
Table 9. GPIF II Timing in Asynchronous Mode (continued)
Note The following parameters assume one state transition
Parameter Description
Min
Max Units
Notes
tOELZ
CTL designated as OE to low-Z. Time when
external devices should stop driving data.
0
–
ns
tOEHZ
tCLZ
CTL designated as OE to High-Z
8
0
8
–
ns
ns
CTL (non OE) to Low-Z. Time when external
devices should stop driving data.
tCHZ
CTL (non OE) to High-Z
30
–
30
25
30
–
ns
ns
ns
ns
ns
tCTLalpha
tCTLbeta
tDST
CTL to alpha change at output
CTL to Beta change at output
–
Addr/data setup when DLE/ALE not used
Addr/data hold when DLE/ALE not used
2
tDHT
20
–
Slave FIFO Interface
Synchronous Slave FIFO Timing
Figure 10. Synchronous Slave FIFO Read Mode
Synchronous Read Cycle Timing
tCYC
PCLK
tCH tCL
3 cycle latency
from addr to data
SLCS
t
AS tAH
FIFO ADDR
An
Am
tRDH
tRDS
SLRD
SLOE
FLAGA
(Dedicated thread Flag for An)
(1 = Not Empty 0= Empty)
FLAGB
(Dedicated thread Flag for Am)
(1 = Not Empty 0= Empty)
tCDH
tOEZ
tOELZ
tOEZ
tCO
tOELZ
High-Z
Data
driven:DN(An)
DN+2(Am)
DN+1(An)
DN(Am)
Data Out
DN+1(Am)
SLWR (HIGH)
Document Number 001-52136 Rev. *H
Page 19 of 38
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PRELIMINARY
CYUSB3014
The same sequence of events is shown for a burst read.
Synchronous Slave FIFO sequence description:
1. FIFO address is stable and SLCS is asserted
Note For burst mode, the SLRD# and SLOE# are left asserted
during the entire duration of the read. When SLOE# is asserted,
the data bus is driven (with data from the previously addressed
FIFO). For each subsequent rising edge of PCLK, while the
SLRD# is asserted, the FIFO pointer is incremented and the next
data value is placed on the data bus.
2. SLOE is asserted. SLOE is an output enable only, whose sole
function is to drive the data bus.
3. SLRD is asserted
4. The FIFO pointer is updated on the rising edge of the PCLK,
whilethe SLRD is asserted. This starts thepropagation ofdata
from the newly addressed location to the data bus. After a
propagation delay of tco (measured from the rising edge of
PCLK) the new data value is present. N is the first data value
read from the FIFO. To have data on the FIFO data bus, SLOE
must also be asserted.
Document Number 001-52136 Rev. *H
Page 20 of 38
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PRELIMINARY
CYUSB3014
Figure 11. Synchronous Slave FIFO Write Mode
Synchronous Write Cycle Timing
tCYC
PCLK
tCH tCL
SLCS
tAH
tAS
Am
An
FIFO ADDR
SLWR
tWRS
tWRH
tCFLG
FLAGA
dedicated thread FLAG for An
(1 = Not Full 0= Full)
tCFLG
FLAGB
current thread FLAG for Am
(1 = Not Full 0= Full)
tDS tDH
tDS tDH
tDH
DN(Am)
DN+1(Am) DN+2(Am)
DN(An)
Data IN
High-Z
t
PES tPEH
PKTEND
SLOE
(HIGH)
Synchronous ZLP Write Cycle Timing
tCYC
PCLK
tCH tCL
SLCS
tAH
tAS
An
FIFO ADDR
SLWR
(HIGH)
t
PES tPEH
PKTEND
tCFLG
FLAGA
dedicated thread FLAG for An
(1 = Not Full 0= Full)
FLAGB
current thread FLAG for Am
(1 = Not Full 0= Full)
Data IN
High-Z
SLOE
(HIGH)
Document Number 001-52136 Rev. *H
Page 21 of 38
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PRELIMINARY
CYUSB3014
the FIFO data bus is written to the FIFO on every rising edge of
PCLK. The FIFO pointer is updated on each rising edge of PCLK.
Synchronous Slave FIFO Write Sequence Description
■ FIFO address is stable and the signal SLCS# is asserted
■ External master/peripheral outputs the data onto the data bus
■ SLWR# is asserted
Short Packet: A short packet can be committed to the USB host
by using the PKTEND#. The external device/processor should
be designed to assert the PKTEND# along with the last word of
data and SLWR# pulse corresponding to the last word. The
FIFOADDR lines have to be held constant during the PKTEND#
assertion.
■ While the SLWR# is asserted, data is written to the FIFO and
on the rising edge of gthe PCLK, the FIFO pointer is incre-
mented
Zero Length Packet: The external device/processor can signal a
Zero Length Packet (ZLP) to EZ-USB FX3, simply by asserting
PKTEND#, without asserting SLWR#. SLCS# and address must
be driven as shown in the above timing diagram.
■ The FIFO flog is updated after a delay of t
from the rising
WFLG
edge of the clock
The same sequence of events is also shown for burst write
FLAG Usage: The FLAG signals are monitored by the external
processor for flow control. FLAG signals are outputs from
EZ-USB FX3 that may be configured to show empty/full/partial
status for a dedicated thread or the current thread being
addressed.
Note: Forthe burst mode, SLWR# and SLCS# are left asserted
for the entire duration of writing all the required data values. In
this burst write mode, after the SLWR# is asserted, the data on
[5]
Table 10. Synchronous Slave FIFO Parameters
Parameter
Description
Min
–
Max
100
–
Units
MHz
ns
FREQ
tCYC
tCH
Interface clock frequency
Clock period
10
4
Clock high time
–
ns
tCL
Clock low time
4
–
ns
tRDS
tRDH
tWRS
tWRH
tCO
SLRD# to CLK setup time
SLRD# to CLK hold time
SLWR# to CLK setup time
SLWR# to CLK hold time
Clock to valid data
2
–
ns
0.5
2
–
ns
–
ns
0.5
–
–
ns
8
ns
tDS
Data input setup time
CLK to data input hold
Address to CLK setup time
CLK to address hold time
SLOE# to data low-Z
2
–
ns
tDH
0.5
2
–
ns
tAS
–
ns
tAH
0.5
0
–
ns
tOELZ
tCFLG
tOEZ
tPES
tPEH
tCDH
–
ns
CLK to flag output propagation delay
SLOE# deassert to Data Hi Z
PKTEND# to CLK setup
CLK to PKTEND# hold
CLK to data output hold
–
8
ns
–
8
ns
2
–
ns
0.5
2
–
–
ns
Note Three-cycle latency from ADDR to DATA/FLAGS
.
Note
5. All parameters guaranteed by design and validated through characterization.
Document Number 001-52136 Rev. *H
Page 22 of 38
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PRELIMINARY
CYUSB3014
Asynchronous Slave FIFO Timing
Figure 12. Asynchronous Slave FIFO Read Mode
SLCS
tAS
tAH
An
Am
FIFO ADDR
tRDl tRDh
SLRD
SLOE
tFLG
tRFLG
FLAGA
dedicated thread Flag for An
(1=Not empty 0 = Empty)
FLAGB
dedicated thread Flag for Am
(1=Not empty 0 = Empty)
tRDO
tRDO
tOH
tOE
tLZ
tOE
tRDO
tOH
DN(An)
DN(An)
DN(Am)
DN+1(Am)
DN+2(Am)
Data Out
High-Z
SLWR
(HIGH)
In the above diagram , data N is the first valid data read from the
FIFO. For data to appear on the data bus during the read cycle
SLOE# must be in an asserted state. SLRD# and SLOE# can
also be tied together.
Asynchronous Slave FIFO Read Sequence
Description
■ FIFO address is stable and the SLCS# signal is asserted.
■ SLOE# is asserted. This results in the data bus being driven.
■ SLRD # is asserted.
The same sequence of events is also shown for a burst read.
Note: In burst read mode, during SLOE# assertion, the data bus
is in a driven state (data driven is from previously addressed
FIFO). On assertion of SLRD# data from the FIFO is driven on
the data bus (SLOE# must also be asserted) and the FIFO
pointer is incremented on de-assertion of SLRD#.
■ Data from the FIFO is driven on assertion of SLRD#. This data
is valid after a propagation delay of tRDO from the falling edge
of SLRD#.
■ FIFO pointer is incremented on de-assertion of SLRD#
Document Number 001-52136 Rev. *H
Page 23 of 38
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PRELIMINARY
CYUSB3014
Figure 13. Asynchronous Slave FIFO Write Mode
SLCS
tAS
tAH
An
Am
FIFO ADDR
tWRl
tWRh
SLWR
tFLG
tWFLG
FLAGA
dedicated thread Flag for An
(1=Not Full 0 = Full)
tWFLG
FLAGB
dedicated thread Flag for Am
(1=Not Full 0 = Full)
tWR
tWR
tWRH
tWRH
S
S
High-Z
DN(An)
DN(Am)
DN+1(Am)
DN+2(Am)
DATA In
tWRPE
tPEh
PKTEND
SLOE
(HIGH)
Change tWRPE definition to SLWR# de-assert to PKTEND de-assert = 0ns min (This means that PKTEND should not be be deasserted before SLWR#)
Note: PKTEND must be asserted at the same time as SLWR#.
Asynchronous ZLP Write Cycle Timing
SLCS
tAS
tAH
An
FIFO ADDR
SLWR
(HIGH)
tPEl
tPEh
PKTEND
tWFLG
FLAGA
dedicated thread Flag for An
(1=Not Full 0 = Full)
FLAGB
dedicated thread Flag for Am
(1=Not Full 0 = Full)
High-Z
DATA In
SLOE
(HIGH)
Document Number 001-52136 Rev. *H
Page 24 of 38
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PRELIMINARY
CYUSB3014
Short Packet: A short packet can be committed to the USB host
by using the PKTEND#. The external device/processor should
be designed to assert the PKTEND# along with the last word of
data and SLWR# pulse corresponding to the last word. The
FIFOADDR lines have to be held constant during the PKTEND#
assertion.
Asynchronous Slave FIFO Write Sequence
Description
■ FIFO address is driven and SLCS# is asserted
■ SLWR# is asserted. SLCS# must be asserted with SLWR# or
before SLWR# is asserted
Zero Length Packet: The external device/processor can signal a
Zero Length Packet (ZLP) to EZ-USB FX3, simply by asserting
PKTEND#, without asserting SLWR#. SLCS# and address must
be driven as shown in the above timing diagram.
■ Data must be present on the bus tWRS before the deasserting
edge of SLWR#
■ De-assertion of SLWR# causes the data to be written from the
data bus to the FIFO and then FIFO pointer is incremented
FLAG Usage: The FLAG signals are monitored by the external
processor for flow control. FLAG signals are outputs from
EZ-USB FX3 that may be configured to show empty/full/partial
status for a dedicated address or the current address.
■ TheFIFOflagisupdatedafterthetWFLGfromthede-asserting
edge of SLWR.
The same sequence of events is shown for a burst write.
Note that in the burst write mode, on SLWR# de-assertion, the
data is written to the FIFO and then the FIFO pointer is incre-
mented.
[6]
Table 11. Asynchronous Slave FIFO Parameters
Parameter
Description
Min
20
10
7
Max
–
Units
ns
tRDI
SLRD# low
tRDh
tAS
SLRD# high
–
ns
Address to SLRD#/SLWR# setup time
SLRD#/SLWR#/PKTEND to address hold time
SLRD# to FLAGS output propagation delay
ADDR to FLAGS output propagation delay
SLRD# to data valid
–
ns
tAH
2
–
ns
tRFLG
tFLG
tRDO
tOE
–
35
22.5
25
25
–
ns
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OE# low to data valid
tLZ
OE# low to data low-Z
0
tOH
SLOE# deassert data output hhold
SLWR# low
–
22.5
–
tWRI
tWRh
tWRS
tWRH
tWFLG
tPEI
20
10
7
SLWR# high
–
Data to SLWR# setup time
SLWR# to Data Hold time
SLWR#/PKTEND to Flags output propagation delay
PKTEND low
–
2
–
–
35
–
7.5
7.5
0
tPEh
tWRPE
PKTEND high
–
SLWR# deassert to PKTEND deassert
–
Note
6. All parameters guaranteed by design and validated through characterization.
Document Number 001-52136 Rev. *H
Page 25 of 38
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CYUSB3014
Serial Peripherals Timing
I2C Timing
Figure 14. I2C Timing Definition
Document Number 001-52136 Rev. *H
Page 26 of 38
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PRELIMINARY
CYUSB3014
[7]
Table 12. I2C Timing Parameters
Parameter
I2C Standard Mode Parameters
Description
Min
Max
Units
Notes
fSCL
SCL clock frequency
0
4
100
–
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
tHD:STA
tLOW
Hold time START condition
LOW period of the SCL
HIGH period of the SCL
4.7
4
–
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
–
Setup time for a repeated START condition
Data hold time
4.7
0
–
–
Data setup time
250
–
–
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
Bus free time between a STOP and START condition
Data valid time
1000
300
–
tf
–
tSU:STO
tBUF
4
4.7
–
–
tVD:DAT
tVD:ACK
tSP
3.45
3.45
n/a
Data valid ACK
–
Pulse width of spikes that must be suppressed by input filter
n/a
I2C Fast Mode Parameters
fSCL
SCL clock frequency
0
0.6
1.3
0.6
0.6
0
400
–
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
ns
tHD:STA
tLOW
Hold time START condition
LOW period of the SCL
–
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
HIGH period of the SCL
–
Setup time for a repeated START condition
Data hold time
–
–
Data setup time
100
–
–
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
Bus free time between a STOP and START condition
Data valid time
300
300
–
tf
–
tSU:STO
tBUF
0.6
1.3
–
–
tVD:DAT
tVD:ACK
tSP
0.9
0.9
50
Data valid ACK
–
Pulse width of spikes that must be suppressed by input filter
0
I2C Fast Mode Plus Parameters (Not supported at I2C_VDDQ=1.2V)
fSCL
SCL clock frequency
0
0.26
0.5
0.26
0.26
0
1000
–
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
ns
tHD:STA
tLOW
Hold time START condition
LOW period of the SCL
–
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
HIGH period of the SCL
–
Setup time for a repeated START condition
Data hold time
–
–
Data setup time
50
–
–
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
Bus free time between a STOP and START condition
Data valid time
120
120
–
tf
–
tSU:STO
tBUF
0.26
0.5
–
–
tVD:DAT
tVD:ACK
tSP
0.45
0.45
50
Data valid ACK
–
Pulse width of spikes that must be suppressed by input filter
0
Note
7. All parameters guaranteed by design and validated through characterization.
Document Number 001-52136 Rev. *H
Page 27 of 38
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PRELIMINARY
CYUSB3014
I2S Timing Diagram
Figure 15. I2S Transmit Cycle
[8]
Table 13. I2S Timing Parameters
Parameter
Description
Min
Max
Units
ns
2
tT
I S transmitter clock cycle
Ttr
–
2
tTL
tTH
tTR
tTF
tThd
tTd
I S transmitter cycle LOW period
0.35 Ttr
–
–
ns
2
I S transmitter cycle HIGH period
0.35 Ttr
ns
2
I S transmitter rise time
–
–
0
–
0.15 Ttr
0.15 Ttr
–
ns
2
I S transmitter fall time
ns
2
I S transmitter data hold time
ns
2
I S transmitter delay time
0.3tT
ns
Note tT is selectable through clock gears. Max Ttr is designed for 96 kHz codec at 32 bits to be 326 ns (3.072 MHz).
Note
8. All parameters guaranteed by design and validated through characterization.
Document Number 001-52136 Rev. *H
Page 28 of 38
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PRELIMINARY
CYUSB3014
SPI Timing Specification
Figure 16. SPI Timing
SSN
(output)
tssnh
tsck
tlag
tlead
SCK
(CPOL=0,
Output)
trf
twsck
twsck
SCK
(CPOL=1,
Output)
tdis
tsdi
thoi
LSB
MISO
(input)
MSB
MSB
td
tsdd
tdi
v
MOSI
(output)
LSB
SPI Master Timing for CPHA = 0
SSN
(output)
tssnh
tsck
tlag
tlead
trf
SCK
(CPOL=0,
Output)
twsck
twsck
SCK
(CPOL=1,
Output)
tdis
thoi
LSB
tsdi
MISO
(input)
MSB
MSB
tdi
tdv
MOSI
(output)
LSB
SPI Master Timing for CPHA = 1
Document Number 001-52136 Rev. *H
Page 29 of 38
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PRELIMINARY
CYUSB3014
[9]
Table 14. SPI Timing Parameters
Parameter
Description
Min
0
Max
33
–
Units
MHz
ns
fop
Operating frequency
Cycle time
tsck
twsck
tlead
tlag
trf
30
Clock high/low time
SSN-SCK lead time
Enable lag time
Rise/fall time
13.5
–
ns
[10]
[10]
1/2 tsck -5
1.5tsck + 5
ns
[10]
0.5
–
1.5 tsck +5
ns
8
5
5
–
–
–
–
–
ns
tsdd
tdv
Output SSN to valid data delay time
Output data valid time
–
ns
–
ns
tdi
Output data invalid
0
ns
tssnh
tsdi
thoi
tdis
Minimum SSN high time
Data setup time input
10
8
ns
ns
Data hold time input
0
ns
Disable data output on SSN high
0
ns
Reset Sequence
The hard reset sequence requirements for EZ-USB FX3 are specified here.
Table 15. Reset and Standby Timing Parameters
Parameter
Definition
Conditions
Min (ms)
Max (ms)
tRPW
Minimum RESET# pulse width
Clock Input
1
5
5
1
–
–
–
–
Crystal Input
tRH
tRR
Minimum high on RESET#
–
–
Reset recovery time (after which Boot loader begins
firmware download)
tSBY
tWU
Time to enter standby/suspend (from the time
MAIN_CLOCK_EN/ MAIN_POWER_EN bit is set)
–
–
1
Time to wakeup from standby
Clock Input
Crystal Input
–
1
5
5
–
–
–
tWH
Minimum time before Standby/Suspend source may
be reasserted
Notes
9. All parameters guaranteed by design and validated through characterization.
10. Depends on LAG and LEAD setting in SPI_CONFIG register.
Document Number 001-52136 Rev. *H
Page 30 of 38
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PRELIMINARY
CYUSB3014
Figure 17. Reset Sequence
VDD
( core )
xVDDQ
XTALIN/
CLKIN
XTALIN/ CLKIN must be stable
before exiting Standby/Suspend
tRh
tRR
Mandatory
Reset Pulse
Hard Reset
RESET #
tWH
tWU
tRPW
tSBY
Standby/
Suspend
Source
Standby/Suspend source Is asserted
(MAIN_POWER_EN/ MAIN_CLK_EN bit
is set)
Standby/Suspend
source Is deasserted
Ball Map
Figure 18. Ball Map for EZ-USB FX3 (Top View)
1
2
3
4
5
6
7
8
9
10
11
NC
U3VSSQ
VIO4
U3RXVDDQ
FSLC[0]
GPIO[55]
GPIO[51]
VSS
SSRXM
R_USB3
VDD
SSRXP
FSLC[1]
GPIO[57]
GPIO[53]
GPIO[49]
GPIO[41]
GPIO[30]
GPIO[31]
GPIO[34]
VSS
SSTXP
SSTXM
CVDDQ
XTALIN
CLKIN_32
FSLC[2]
TCK
VSS
DP
DM
VDD
TDO
AVDD
AVSS
XTALOUT
CLKIN
A
B
C
D
E
F
G
H
J
U3TXVDDQ
RESET#
GPIO[56]
GPIO[48]
GPIO[46]
GPIO[25]
GPIO[29]
GPIO[28]
GPIO[27]
VDD
VSS
TRST#
VIO5
O[60]
VSS
R_USB2
VSS
GPIO[54]
GPIO[50]
GPIO[47]
VIO2
OTG_ID
GPIO[52]
VIO3
I2C_GPIO[58] I2C_GPIO[59]
TDI
TMS
VDD
GPIO[1]
GPIO[4]
GPIO[7]
GPIO[9]
GPIO[13]
VIO1
VBATT
GPIO[0]
GPIO[3]
GPIO[6]
GPIO[8]
GPIO[12]
GPIO[11]
VBUS
VDD
GPIO[45]
GPIO[42]
GPIO[39]
GPIO[36]
GPIO[33]
VSS
GPIO[44]
GPIO[43]
GPIO[40]
GPIO[37]
VSS
GPIO[2]
GPIO[21]
GPIO[20]
GPIO[19]
GPIO[18]
VDD
GPIO[5]
GPIO[15]
GPIO[24]
GPIO[14]
GPIO[17]
INT#
VSS
GPIO[22]
GPIO[26]
GPIO[16]
GPIO[23]
VSS
VSS
VDD
VIO1
GPIO[38]
GPIO[35]
VSS
VDD
GPIO[10]
VSS
K
L
VSS
GPIO[32]
Document Number 001-52136 Rev. *H
Page 31 of 38
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CYUSB3014
Pin Description
Table 16. Pin List
Pin
I/O
Name
Description
GPIFII (VIO1 Power Domain)
GPIF™II Interface
DQ[0]
Slave FIFO Interface
F10
F9
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
CVDDQ
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[7]
GPIO[8]
GPIO[9]
GPIO[10]
GPIO[11]
GPIO[12]
GPIO[13]
GPIO[14]
GPIO[15]
GPIO[16]
GPIO[17]
GPIO[18]
GPIO[19]
GPIO[20]
GPIO[21]
GPIO[22]
GPIO[23]
GPIO[24]
GPIO[25]
GPIO[26]
GPIO[27]
GPIO[28]
GPIO[29]
GPIO[30]
GPIO[31]
GPIO[32]
INT#
DQ[0]
DQ[1]
DQ[1]
F7
DQ[2]
DQ[2]
G10
G9
F8
DQ[3]
DQ[3]
DQ[4]
DQ[4]
DQ[5]
DQ[5]
H10
H9
J10
J9
DQ[6]
DQ[6]
DQ[7]
DQ[7]
DQ[8]
DQ[8]
DQ[9]
DQ[9]
K11
L10
K10
K9
J8
DQ[10]
DQ[11]
DQ[12]
DQ[13]
DQ[14]
DQ[15]
PCLK
DQ[10]
DQ[11]
DQ[12]
DQ[13]
DQ[14]
DQ[15]
CLK
G8
J6
K8
K7
J7
CTL[0]
SLCS#
SLWR#
SLOE#
SLRD#
FLAGA
FLAGB
GPIO
CTL[1]
CTL[2]
H7
G7
G6
K6
H8
G5
H6
K5
J5
CTL[3]
CTL[4]
CTL[5]
CTL[6]
CTL[7]
PKTEND#
GPIO
CTL[8]
CTL[9]
GPIO
CTL[10]
CTL[11]
CTL[12]
PMODE[0]
PMODE[1]
PMODE[2]
INT#/CTL[15]
RESET#
GPIO
A1
H5
G4
H4
L4
A0
PMODE[0]
PMODE[1]
PMODE[2]
CTL[15]
RESET#
L8
C5
RESET#
IO2 (VIO2 Power Domain)
GPIF II (32-bit data mode)
K2
J4
K1
J2
J3
VIO2
VIO2
VIO2
VIO2
VIO2
I/O
I/O
I/O
I/O
I/O
GPIO[33]
GPIO[34]
GPIO[35]
GPIO[36]
GPIO[37]
DQ[16]
DQ[17]
DQ[18]
DQ[19]
DQ[20]
GPIO
GPIO
GPIO
GPIO
GPIO
Document Number 001-52136 Rev. *H
Page 32 of 38
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Table 16. Pin List (continued)
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Name
Description
J1
H2
H3
F4
G2
G3
F3
F2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
GPIO[38]
GPIO[39]
GPIO[40]
GPIO[41]
GPIO[42]
GPIO[43]
GPIO[44]
GPIO[45]
DQ[21]
DQ[22]
DQ[23]
DQ[24]
DQ[25]
DQ[26]
DQ[27]
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
IO3 (VIO3 Power Domain)
GPIF II - 32
(FX3)+UART+I2S
GPIO+I2S
UART+SPI+
I2S
F5
E1
E5
E4
D1
D2
D3
VIO3
VIO3
VIO3
VIO3
VIO3
VIO3
VIO3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO[46]
GPIO[47]
GPIO[48]
GPIO[49]
GPIO[50]
GPIO[51]
GPIO[52]
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
DQ[28]
DQ[29]
DQ[30]
DQ[31]
I2S_CLK
I2S_SD
I2S_WS
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
UART_RTS
UART_CTS
UART_TX
UART_RX
I2S_CLK
I2S_SD
I2S_WS
IO4 (VIO4) Power Domain
D4
C1
C2
D5
C4
VIO4
VIO4
VIO4
VIO4
VIO4
I/O
I/O
I/O
I/O
I/O
GPIO[53]
GPIO[54]
GPIO[55]
GPIO[56]
GPIO[57]
SPI_SCK
SPI_SSN
SPI_MISO
SPI_MOSI
GPIO
UART_RTS
UART_CTS
UART_TX
UART_RX
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
UART_RTS
UART_CTS
UART_TX
UART_RX
I2S_MCLK
GPIO
I2S_CLK
I2S_SD
SPI_SCK
SPI_SSN
SPI_MISO
SPI_MOSI
I2S_MCLK
I2S_WS
I2S_MCLK
USB Port (VBATT/VBUS Power Domain)
C9
VBUS/
VBATT
I
OTG_ID
OTG_ID
USB Port (U3TXVDDQ/U3RXVDDQ Power Domain)
A3
A4
A6
A5
U3RXVDDQ
U3RXVDDQ
U3TXVDDQ
U3TXVDDQ
I
I
SSRXM
SSRXP
SSTXM
SSTXP
SSRX-
SSRX+
O
O
SSTX-
SSTX+
USB Port (VBATT/VBUS Power Domain)
A9
VBUS/VBATT
VBUS/VBATT
I/O
I/O
DP
DM
NC
D+
A10
A11
D-
No connect
Crystal/Clocks (CVDDQ Power Domain)
B2
C6
C7
B4
E6
D7
D6
CVDDQ
AVDD
I
FSLC[0]
XTALIN
FSLC[0]
I/O
XTALIN
AVDD
I/O
XTALOUT
FSLC[1]
FSLC[2]
CLKIN
XTALOUT
CVDDQ
CVDDQ
CVDDQ
CVDDQ
I
I
I
I
FSLC[1]
FSLC[2]
CLKIN
CLKIN_32
CLKIN_32
I2C and JTAG (VIO5 Power Domain)
2
D9
VIO5
VIO5
I/O
I/O
I2C_GPIO[58]
I2C_GPIO[59]
I C_SCL
2
D10
I C_SDA
Document Number 001-52136 Rev. *H
Page 33 of 38
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Table 16. Pin List (continued)
Pin
I/O
Name
TDI
Description
E7
C10
B11
E8
VIO5
VIO5
VIO5
VIO5
VIO5
VIO5
I
O
I
TDI
TDO
TDO
TRST#
TRST#
TMS
I
TMS
F6
I
TCK
TCK
D11
I/O
O[60]
Charger detect output
Power
E10
B10
A1
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VBATT
VDD
U3VSSQ
VBUS
VSS
E11
D8
H11
E2
VIO1
VSS
L9
VIO1
VSS
G1
F1
VIO2
VSS
G11
E3
PWR
VIO3
L1
B1
L6
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VSS
VIO4
VSS
B6
B5
A2
C11
L11
A7
B7
C3
B8
E9
B9
F11
H1
L7
CVDDQ
U3TXVDDQ
U3RXVDDQ
VIO5
VSS
AVDD
AVSS
VDD
VSS
VDD
VSS
VDD
VDD
VDD
J11
L5
VDD
VDD
K4
L3
VSS
VSS
K3
L2
VSS
VSS
A8
VSS
Precision Resistors
C8
B3
VBUS/VBATT
U3TXVDDQ
I/O
I/O
R_usb2
R_usb3
Precision resistor for USB2.0 (Connect a 6.04 kΩ+/-1% resistor between this pin and GND)
Precision resistor for USB3.0 (Connect a 200 Ω+/-1% resistor between this pin and GND)
Document Number 001-52136 Rev. *H
Page 34 of 38
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PRELIMINARY
CYUSB3014
Package Diagram
Figure 19. 121-Ball FBGA 10x10x1.2 Diagram
001-54471 *B
Ordering Information
Table 17. Ordering Information
Ordering Code
Package Type
CYUSB3014-BZXI
121-ball BGA
Ordering Code Definition
3
CY USB
XXX BZX I
:
Temperature range
Industrial
Package type: BGA
Marketing Part Number
Base part number for USB 3.0
Marketing Code: USB = USB Controller
Company ID: CY = Cypress
Document Number 001-52136 Rev. *H
Page 35 of 38
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PRELIMINARY
CYUSB3014
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
DMA
HNP
MMC
MTP
PLL
Description
direct memory access
Unit of Measure
host negotiation protocol
multimedia card
°C
degree Celsius
µA
µs
microamperes
microseconds
milliamperes
media transfer protocol
phase locked loop
mA
Mbps
MHz
ms
ns
SD
secure digital
Megabytes per second
mega hertz
milliseconds
nanoseconds
ohms
SD
secure digital
SDIO
SLC
secure digital input / output
single-level cell
SPI
serial peripheral interface
session request protocol
universal serial bus
wafer level chip scale package
Ω
SRP
pF
pico Farad
volts
USB
V
WLCSP
Document Number 001-52136 Rev. *H
Page 36 of 38
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PRELIMINARY
CYUSB3014
Document History Page
Document Title: CYUSB3014 EZ-USB® FX3 SuperSpeed USB Controller
Document Number: 001-52136
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
2669761
2758370
VSO/PYRS
VSO
03/06/09
09/01/09
New Datasheet
*A
Updated the part# from CYX01XXBB to CYUSB3011-BZXI
Changed the title from “ADVANCE” to “ADVANCE INFORMATION”
In page 1, the second bullet (Flexible Host Interface), add “32-bit, 100 MHz”
to first sub bullet.
In page 1, changed the second bullet “Flexible Host Interface” to General
Programmable Interface”.
In page 1, the second bullet (Flexible Host Interface), removed "DMA Slave
Support” and "MMC Slave support with Pass through Boot" sub bullets.
In page 1, third bullet, changed "50 μA with Core Power" to "60 μA with
Core Power"
In page 1, fifth bullet, added "at 1 MHz"
In page 1, seventh bullet, added "up to 4MHz" to UART
In page 1, Applications Section, move “Digital Still Cameras” to second line.
In page 1, Applications Section, added “Machine Vision” and Industrial
Cameras”
Added ™ to GPIF and FX3.
In page 1, updated Logic Block Diagram.
In page 2, section of “Functional Overview”, updated the whole section.
In page 2, removed the section of “Product Interface”
In page 2, removed the section of “Processor Interface (P-Port)”
In page 2, removed the section of “USB Interface (U-Port)”
In page 2, removed the section of “Other Interfaces”
In page 2, added a section of "GPIF II"
In page 2, added a section of "CPU"
In page 2, added a section of "JTAG Interface"
In page 2, added a section of "Boot Options"
In page 2, added a section of "ReNumeration"
In page 2, added a section of "Power"
In the section of “Package”, replaced “West Bridge USB 3.0 Platform” by
FX3.
In the section of “Package”, added 0.8 mm pitch in front of BGA.
Added Pin List (Table 1)
*B
2779196
VSO/PYRS
09/29/09
12/08/09
Features:
Added the thrid bullet “Fully accessible 32-bit ARM9 core with 512kB of
embedded SRAM”
Added the thrid line “EZ USB™ Software and DVK for easy code devel-
opment”
Table 1: Pin 74, corrected to NC - No Connect.
Changed title to EZ-USB™ FX3: SuperSpeed USB Controller
*C
*D
2823531
3080927
OSG
OSG
Added data sheet to the USB3.0 EROS spec 001-51884. No technical
updates.
11/08/2010 Changed status from Advance to Preliminary
Changed part number from CYUSB3011 to CYUSB3014
Added the following sections: Power, Configuration Options, Digital I/Os,
System Level ESD, Absolute Maximum Ratings, AC Timing Parameters,
Reset Sequence, Package Diagram
Added DC Specifications table
Updated feature list
Updated Pin List
Added support for selectable clock input frequencies.
Updated block diagram
Updated part number
Updated package diagram
Document Number 001-52136 Rev. *H
Page 37 of 38
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PRELIMINARY
CYUSB3014
Document Title: CYUSB3014 EZ-USB® FX3 SuperSpeed USB Controller
Document Number: 001-52136
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
*E
3204393
OSG
03/24/2011 Updated Slave FIFO protocol and added ZLP signaling protocol
Changed GPIFII asynchronous tDO parameter
Changed Async Slave FIFO tOE parameter
Changed Async Slave FIFO tRDO parameter
Added tCOE parameter to GPIFII Sync mode timing parameters
Renamed GPIFII Sync mode tDO to tCO and tDO_ss0 to tCO_ss0
Modified description of GPIFII Sync tCO (previously tDO) parameter
Changed tAH(address hold time) parameter in Async Slave FIFO modes
to be with respect to rising edge of SLWR#/SLRD# instead of falling edge.
Correspondingly, changed the tAH number.
Removed 24 bit data bus support for GPIFII.
*F
*G
*H
3218493
3235250
3217917
OSG
GSZ
OSG
04/07/2011 Minor ECN - Release to web. No content changes.
04/20/2011 Minor updates in Features.
04/06/2011 Updated GPIFII Synchronous Timing diagram. Added SPI Boot option.
Corrected values of R_USB2 and R_USB3. Corrected TCK and TRST#
pull-up/pull-down configuration. Minor updates to block diagrams.
Corrected Synchronous Slave FIFO tDH parameter.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
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cypress.com/go/interface
cypress.com/go/powerpsoc
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psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
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Interface
Lighting & Power Control
Memory
cypress.com/go/memory
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USB Controllers
Wireless/RF
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© Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number 001-52136 Rev. *H
Revised May 17, 2011
Page 38 of 38
®
EZ-USB™ is a trademark and West Bridge is a registered trademark of Cypress Semiconductor Corp. All products and company names mentioned in this document may be the trademarks of their
respective holders.
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