CYW4343W [CYPRESS]
Single-Chip 802.11 b/g/n MAC/Baseband/Radiowith Bluetooth 4.1;型号: | CYW4343W |
厂家: | CYPRESS |
描述: | Single-Chip 802.11 b/g/n MAC/Baseband/Radiowith Bluetooth 4.1 |
文件: | 总103页 (文件大小:1224K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CYW4343W
Single-Chip 802.11 b/g/n MAC/Baseband/Radio
with Bluetooth 4.1
The Cypress CYW4343W is a highly integrated single-chip solution and offers the lowest RBOM in the industry for wearables, Internet
of Things (IoT) gateways, home automation, and a wide range of other portable devices. The chip includes a 2.4 GHz WLAN IEEE
802.11 b/g/n MAC/baseband/radio and Bluetooth 4.1 support. In addition, it integrates a power amplifier (PA) that meets the output
power requirements of most handheld systems, a low-noise amplifier (LNA) for best-in-class receiver sensitivity, and an internal
transmit/receive (iTR) RF switch, further reducing the overall solution cost and printed circuit board area.
The WLAN host interface supports SDIO v2.0 mode, providing a raw data transfer rate up to 200 Mbps when operating in 4-bit mode
at a 50 MHz bus frequency. An independent, high-speed UART is provided for the Bluetooth host interface.Using advanced design
techniques and process technology to reduce active and idle power, the CYW4343W is designed to address the needs of highly mobile
devices that require minimal power consumption and compact size. It includes a power management unit that simplifies the system
power topology and allows for operation directly from a rechargeable mobile platform battery while maximizing battery life.
The CYW4343W implements the world’s most advanced Enhanced Collaborative Coexistence algorithms and hardware mechanisms,
allowing for an extremely collaborative WLAN and Bluetooth coexistence.
Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Broadcom Part Number
Cypress Part Number
BCM4343W
CYW4343W
BCM4343WKUBG
CYW4343WKUBG
■ OneDriver™ software architecture for easy migration from
existing embedded WLAN and Bluetooth devices as well as to
future devices.
Features
IEEE 802.11x Key Features
Bluetooth Features
■ Single-band 2.4 GHz IEEE 802.11b/g/n.
■ Complies with Bluetooth Core Specification Version 4.1 with
provisions for supporting future specifications.
■ Support for 2.4 GHz Cypress TurboQAM® data rates (256-
QAM) and 20 MHz channel bandwidth.
■ Bluetooth Class 1 or Class 2 transmitter operation.
■ Integrated iTR switch supports a single 2.4 GHz antenna
shared between WLAN and Bluetooth.
■ Supports extended Synchronous Connections (eSCO), for
enhanced voice quality by allowing for retransmission of
dropped packets.
■ Supports explicit IEEE 802.11n transmit beamforming
■ Tx and Rx Low-density Parity Check (LDPC) support for
improved range and power efficiency.
■ Adaptive Frequency Hopping (AFH) for reducing radio
frequency interference.
■ Supports standard SDIO v2.0 host interface.
■ Interface support — Host Controller Interface (HCI) using a
high-speed UART interface and PCM for audio data.
■ Supports Space-Time Block Coding (STBC) in the receiver.
■ IntegratedARM Cortex-M3 processor and on-chip memory for
complete WLAN subsystem functionality, minimizing the need
to wake up the applications processor for standard WLAN
functions. This allows for further minimization of power
consumption, while maintaining the ability to field-upgrade with
future features. On-chip memory includes 512 KB SRAM and
640 KB ROM.
■ Low-power consumption improves battery life of handheld
devices.
■ Supports multiple simultaneous Advanced Audio Distribution
Profiles (A2DP) for stereo sound.
■ Automatic frequency detection for standard crystal and TCXO
values.
Cypress Semiconductor Corporation
Document Number: 002-14797 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 28, 2017
CYW4343W
General Features
■ 153-bump WLCSP package (115 μm bump diameter, 180 μm
bump pitch).
■ Supports a battery voltage range from 3.0V to 4.8V with an
internal switching regulator.
■ Security:
❐ WPA and WPA2 (Personal) support for powerful encryption
and authentication.
■ Programmable dynamic power management.
■ 4 Kbit One-Time Programmable (OTP) memory for storing
board parameters.
❐ AES in WLAN hardware for faster data encryption and IEEE
802.11i compatibility.
❐ Reference WLAN subsystem provides Cisco Compatible Ex-
tensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, CCX 5.0).
■ Can be routed on low-cost 1 x 1 PCB stack-ups.
❐ Reference WLAN subsystem provides Wi–Fi Protected Set-
up (WPS).
■ 74-ball[4343W+43CS4343W1]74-ball 63-ball WLBGA
package (4.87 mm × 2.87 mm, 0.4 mm pitch).
■ Worldwide regulatory support: Global products supported with
worldwide homologated design.
Figure 1. CYW4343W System Block Diagram
VDDIO VBAT
WL_REG_ON
WLAN
Host I/F
WL_IRQ
SDIO
2.4 GHz WLAN +
Bluetooth TX/RX
CLK_REQ
BT_REG_ON
PCM
BPF
CYW4343W
Bluetooth
Host I/F
BT_DEV_WAKE
BT_HOST_WAKE
UART
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CYW4343W
Contents
7.2.8 Local Oscillator Generation ....................25
7.2.9 Calibration ..............................................25
1. Overview............................................................ 5
1.1 Overview ............................................................. 5
1.2 Features .............................................................. 6
1.3 Standards Compliance ........................................ 7
8. Bluetooth Baseband Core.............................. 26
8.1 Bluetooth 4.1 Features .......................................26
8.2 Link Control Layer ..............................................26
8.3 Test Mode Support .............................................27
2. Power Supplies and Power Management....... 8
2.1 Power Supply Topology ...................................... 8
2.2 CYW4343W PMU Features ................................ 8
2.3 WLAN Power Management ............................... 11
2.4 PMU Sequencing .............................................. 11
2.5 Power-Off Shutdown ......................................... 12
2.6 Power-Up/Power-Down/Reset Circuits ............. 12
8.4 Bluetooth Power Management Unit ...................27
8.4.1 RF Power Management ..........................27
8.4.2 Host Controller Power Management ......27
8.5 BBC Power Management ...................................29
8.5.1 Wideband Speech ..................................29
8.6 Packet Loss Concealment .................................29
8.6.1 Codec Encoding .....................................30
8.6.2 Multiple Simultaneous A2DP Audio
3. Frequency References ................................... 13
3.1 Crystal Interface and Clock Generation ............ 13
3.2 TCXO ................................................................ 13
3.3 External 32.768 kHz Low-Power Oscillator ....... 15
Streams ..................................................30
8.7 Adaptive Frequency Hopping .............................30
8.8 Advanced Bluetooth/WLAN Coexistence ...........30
8.9 Fast Connection (Interlaced Page and Inquiry
Scans) ................................................................30
4. WLAN System Interfaces ............................... 16
4.1 SDIO v2.0 .......................................................... 16
4.1.1 SDIO Pin Descriptions ........................... 16
9. Microprocessor and Memory Unit for Bluetooth
31
5. Wireless LAN MAC and PHY.......................... 17
9.1 RAM, ROM, and Patch Memory .........................31
9.2 Reset ..................................................................31
5.1 MAC Features ................................................... 17
5.1.1 MAC Description .................................... 17
Figure 9..PSM ...................................................... 18
Figure 9..WEP ...................................................... 18
Figure 9..TXE ....................................................... 18
Figure 9..RXE ...................................................... 18
Figure 9..IFS ........................................................ 19
Figure 9..TSF ....................................................... 19
Figure 9..NAV ...................................................... 19
Figure 9..MAC-PHY Interface .............................. 19
10.Bluetooth Peripheral Transport Unit............. 32
10.1 PCM Interface ....................................................32
10.1.1 Slot Mapping ...........................................32
10.1.2 Frame Synchronization ...........................32
10.1.3 Data Formatting ......................................32
10.1.4 Wideband Speech Support .....................32
10.1.5 PCM Interface Timing .............................33
10.1.5.Short Frame Sync, Master Mode ...............33
Table 7..Short Frame Sync, Slave Mode ..............34
Table 8..Long Frame Sync, Master Mode .............35
Table 9..Long Frame Sync, Slave Mode ...............36
5.2 PHY Description ................................................ 19
5.2.1 PHY Features ........................................ 20
6. WLAN Radio Subsystem................................ 21
6.1 Receive Path ..................................................... 22
6.2 Transmit Path .................................................... 22
6.3 Calibration ......................................................... 22
10.2 UART Interface ..................................................37
10.3 I2S Interface .......................................................38
10.3.1 I2S Timing ...............................................39
11.CPU and Global Functions ............................ 41
11.1 WLAN CPU and Memory Subsystem ................41
11.2 One-Time Programmable Memory .....................41
11.3 GPIO Interface ...................................................41
7. Bluetooth Subsystem Overview.................... 23
7.1 Features ............................................................ 23
7.2 Bluetooth Radio ................................................. 24
7.2.1 Transmit ................................................. 24
7.2.2 Digital Modulator .................................... 24
7.2.3 Digital Demodulator and Bit
11.4 External Coexistence Interface ..........................41
11.4.1 2-Wire Coexistence ................................42
11.4.2 3-Wire and 4-Wire Coexistence
Synchronizer .......................................... 24
7.2.4 Power Amplifier ..................................... 24
7.2.5 Receiver ................................................ 25
7.2.6 Digital Demodulator and Bit Synchronizer 25
7.2.7 Receiver Signal Strength Indicator ........ 25
Interfaces ................................................42
11.5 JTAG Interface ..................................................43
11.6 UART Interface .................................................43
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CYW4343W
12.WLAN Software Architecture......................... 44
12.1 Host Software Architecture ............................... 44
12.2 Device Software Architecture ............................ 44
12.3 Remote Downloader ......................................... 44
12.4 Wireless Configuration Utility ............................ 44
16.Bluetooth RF Specifications.......................... 78
17.Internal Regulator Electrical Specifications. 84
17.1 Core Buck Switching Regulator .........................84
17.2 3.3V LDO (LDO3P3) ..........................................85
17.3 CLDO .................................................................86
17.4 LNLDO ...............................................................87
13.Pinout and Signal Descriptions..................... 45
13.1 Ball Map ............................................................ 45
13.2 WLBGA Ball List in Ball Number Order with X-Y
Coordinates ....................................................... 47
18.System Power Consumption......................... 88
18.1 WLAN Current Consumption ..............................88
18.1.1 2.4 GHz Mode ........................................88
13.3 WLCSP Bump List in Bump Order with X-Y
Coordinates ....................................................... 49
18.2 Bluetooth Current Consumption .........................89
19.Interface Timing and AC Characteristics ..... 90
19.1 SDIO Default Mode Timing ................................90
19.2 SDIO High-Speed Mode Timing .........................91
19.3 JTAG Timing ......................................................92
13.4 WLBGA Ball List Ordered By Ball Name ........... 54
13.5 WLCSP Bump List Ordered By Name .............. 55
13.6 Signal Descriptions ........................................... 57
13.7 WLAN GPIO Signals and Strapping Options .... 65
13.8 Chip Debug Options .......................................... 65
13.9 I/O States .......................................................... 66
20.Power-Up Sequence and Timing................... 93
20.1 Sequencing of Reset and Regulator Control
Signals ...............................................................93
20.1.1 Description of Control Signals ................93
20.1.2 Control Signal Timing Diagrams .............94
14.DC Characteristics.......................................... 68
14.1 Absolute Maximum Ratings .............................. 68
14.2 Environmental Ratings ...................................... 68
14.3 Electrostatic Discharge Specifications .............. 69
21.Package Information ...................................... 96
21.1 Package Thermal Characteristics ......................96
21.1.1 Junction Temperature Estimation and
PSI Versus Thetajc ..................................96
14.4 Recommended Operating Conditions and DC
Characteristics .................................................. 69
15.WLAN RF Specifications................................ 71
15.1 2.4 GHz Band General RF Specifications ......... 71
15.2 WLAN 2.4 GHz Receiver Performance
22.Mechanical Information.................................. 97
23.Ordering Information.................................... 101
24.Additional Information ................................. 101
24.1 Acronyms and Abbreviations ...........................101
24.2 IoT Resources ..................................................101
Document History Page............................................... 102
Sales, Solutions, and Legal Information .................... 103
Specifications .................................................... 72
15.3 WLAN 2.4 GHz Transmitter Performance
Specifications .................................................... 75
15.4 General Spurious Emissions Specifications ...... 77
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CYW4343W
1. Overview
1.1 Overview
The Cypress CYW4343W provides the highest level of integration for a mobile or handheld wireless system, with integrated IEEE 802.11 b/g/n. It provides a small form-factor
solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and function. The CYW4343W is
designed to address the needs of highly mobile devices that require minimal power consumption and reliable operation.
Figure 2 shows the interconnection of all the major physical blocks in the CYW4343W and their associated external interfaces, which are described in greater detail in
subsequent sections.
Figure 2. CYW4343W Block Diagram
C o rte x
D e b u g
M 3
A H B
A H B to A P B
B r id g e
R A M
R O M
A P B
P a tc h
In te rC tr l
D M A
W D T im e r
S W T im e r
B P L
B u ffe r
A P U
M o d e m
R F
B u s A rb
A R M IP
G P IO
C tr l
D ig ita l
D e m o d .
&
B it
S y n c
JT A G su p p o r te d o v e r S D IO o r B T P C M
S D IO
B T C lo c k /
H o p p e r
P A
B lu e R F
In te r fa c e
S W R E G
L D O x 2
L P O
X T A L O S C .
P O R
P o w e r
S u p p ly
S le e p C L K
X T A L
U A R T
D ig ita l
M o d .
P M U
C o n tro l
L C U
S D IO
W L _ R E G _ O N
D e b u g
U A R T
R X / T X
B u ffe r
A R M
C M 3
W D T
O T P
D ig ita l
I/ O
I2 S /P C M
G P IO
U A R T
JT A G *
G P IO
U A R T
R A M
R O M
S u p p o rte d o v e r S D IO o r B T P C M
B T P H Y
G P IO
IF
P L L
B T ‐W L A N
E C I
W a k e /
B T C lo c k C o n tr o l
C lo c k
2 .4 G H z
P A
Sle e pC trl
S le e p ‐
tim e
K e e p in g
P M U
C tr l
P M U
M a n a g e m e n t
S h a re d L N A
B P F
W iM a x
C o e x .
X O
B u ffe r
L P O
P O R
W L A N
P T U
*
V ia G P IO c o n fig u ra tio n , JT A G is s u p p o rte d o v e r S D IO o r B T P C M
Document No. 002-14797 Rev. *I
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CYW4343W
1.2 Features
The CYW4343W supports the following WLAN and Bluetooth features:
■ IEEE 802.11b/g/n single-band radio with an internal power amplifier, LNA, and T/R switch
■ Bluetooth v4.1 with integrated Class 1 PA
■ Concurrent Bluetooth, and WLAN operation
■ On-chip WLAN driver execution capable of supporting IEEE 802.11 functionality
■ Simultaneous BT/WLAN reception with a single antenna
■ WLAN host interface options:
❐ SDIO v2.0, including default and high-speed timing.
■ BT UART (up to 4 Mbps) host digital interface that can be used concurrently with the above WLAN host interfaces.
■ ECI—enhanced coexistence support, which coordinates BT SCO transmissions around WLAN receptions.
■ I2S/PCM for BT audio
■ HCI high-speed UART (H4 and H5) transport support
■ Wideband speech support (16 bits, 16 kHz sampling PCM, through I2S and PCM interfaces)
■ Bluetooth SmartAudio® technology improves voice and music quality to headsets.
■ Bluetooth low power inquiry and page scan
■ Bluetooth Low Energy (BLE) support
■ Bluetooth Packet Loss Concealment (PLC)
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CYW4343W
1.3 Standards Compliance
The CYW4343W supports the following standards:
■ Bluetooth 2.1 + EDR
■ Bluetooth 3.0
■ Bluetooth 4.1 (Bluetooth Low Energy)
■ IEEE 802.11n—Handheld Device Class (Section 11)
■ IEEE 802.11b
■ IEEE 802.11g
■ IEEE 802.11d
■ IEEE 802.11h
■ IEEE 802.11i
The CYW4343W will support the following future drafts/standards:
■ IEEE 802.11r — Fast Roaming (between APs)
■ IEEE 802.11k — Resource Management
■ IEEE 802.11w — Secure Management Frames
■ IEEE 802.11 Extensions:
■ IEEE 802.11e QoS Enhancements (as per the WMM® specification is already supported)
■ IEEE 802.11i MAC Enhancements
■ IEEE 802.11r Fast Roaming Support
■ IEEE 802.11k Radio Resource Measurement
The CYW4343W supports the following security features and proprietary protocols:
■ Security:
❐ WEP
❐ WPA™ Personal
❐ WPA2™ Personal
❐ WMM
❐ WMM-PS (U-APSD)
❐ WMM-SA
❐ WAPI
❐ AES (Hardware Accelerator)
❐ TKIP (host-computed)
❐ CKIP (SW Support)
■ Proprietary Protocols:
❐ CCXv2
❐ CCXv3
❐ CCXv4
❐ CCXv5
■ IEEE 802.15.2 Coexistence Compliance — on silicon solution compliant with IEEE 3-wire requirements.
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CYW4343W
2. Power Supplies and Power Management
2.1 Power Supply Topology
One Buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW4343W. All regulators
are programmable via the PMU. These blocks simplify power supply design for Bluetooth and WLAN functions in embedded designs.
A single VBAT (3.0V to 4.8V DC maximum) and VDDIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided
by the regulators in the CYW4343W.
Two control signals, BT_REG_ON and WL_REG_ON, are used to power up the regulators and take the respective circuit blocks out
of reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down
only when both BT_REG_ON and WL_REG_ON are deasserted. The CLDO and LNLDO can be turned on and off based on the
dynamic demands of the digital baseband.
The CYW4343W allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNLDO
regulators. When in this state, LPLDO1 provides the CYW4343W with all required voltage, further reducing leakage currents.
Note: VBAT should be connected to the LDO_VDDBAT5V and SR_VDDBAT5V pins of the device.
Note: VDDIO should be connected to the SYS_VDDIO and WCC_VDDIO pins of the device.
2.2 CYW4343W PMU Features
The PMU supports the following:
■ VBAT to 1.35Vout (170 mA nominal, 370 mA maximum) Core-Buck (CBUCK) switching regulator
■ VBAT to 3.3Vout (250 mA nominal, 450 mA maximum 800 mA peak maximum) LDO3P3
■ 1.35V to 1.2Vout (100 mA nominal, 150 mA maximum) LNLDO
■ 1.35V to 1.2Vout (80 mA nominal, 200 mA maximum) CLDO with bypass mode for deep sleep
■ Additional internal LDOs (not externally accessible)
■ PMU internal timer auto-calibration by the crystal clock for precise wake-up timing from extremely low power-consumption mode.
■ PMU input supplies automatic sensing and fast switching to support A4WP operations.
Figure 3 and Figure 4 show the typical power topology of the CYW4343W.
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CYW4343W
Figure 3. Typical Power Topology (1 of 2)
SR_VDDBAT5V
W L RF— TX M ixer and PA
VBAT
(not all versions)
CYW4343W
M ini PM U
Internal VCOLDO
1.2V
1.2V
1.2V
1.2V
W L RF— LOGEN
W L RF— RX LNA
W L RF— ADC REF
W L RF— TX
80 m A (NM OS)
Internal RXLDO
10 m A (NM OS)
VBAT:
Operational:
Perform ance:
3.0— 4.8V
3.0— 4.8V
VDD1P35
Internal ADCLDO
10 m A (NM OS)
Absolute M axim um : 5.5V
VDDIO
Operational:
Internal TXLDO
80 m A (PM OS)
1.2V
1.2V
1.8— 3.3V
1.35V
Internal AFELDO
80 m A (NM OS)
W L RF— AFE and TIA
Core Buck
Regulator
10 m A average,
> 10 m A at start‐up
W L RF— RFPLL PFD and M M D
SR_VLX
M ini PM U is placed
in W L radio
Int_SR_VBAT
Peak: 370 m A
W LRF_XTAL_
VDD1P2
Avg: 170 m A
2.2 uH
(320 m A)
SW 1
600 @
0603
100 M Hz
W L RF— XTAL
1.2V
LDO_VDD_1P5
LNLDO
SR_VBAT5V
(100 m A)
VBAT
G ND
4.7 uF
0402
VOUT_LNLDO
0.1 uF
0201
SR_PVSS
2.2 uF
0402
PM U_VSS
W CC_VDDIO
SYS_VDDIO
W CC_VDDIO
LPLDO1
(5 m A)
1.1V
(40 m A)
VSEL1
W LAN/BT/CLB/Top, Alw ays On
W L OTP
SYS_VDDIO
W PT_1P8
VDDC1
VDDC2
(40 m A)
(40 m A)
W PT_1P8
1.3V, 1.2V,
or 0.95V
(AVS)
CL LDO
Peak: 200 m A
Avg: 80 m A
(Bypass in deep‐
sleep)
o_w pt_resetb
W PTLDO
(40 m A)
1.3V
2.2 uF
0402
VOUT_CLDO
W L Digital and PHY
W L_REG_ON
BT_REG_ON
o_w l_resetb
o_bt_resetb
W L VDDM (SROM s & AOS)
Power switch
No power switch
Supply ball
Ground ball
Supply bum p/pad
Ground bum p/pad
External to chip
BT VDDM
BT Digital
No dedicated power switch, but internal power‐
down m odes and block‐specific power switches
BT/W LAN reset
balls
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CYW4343W
Figure 4. Typical Power Topology (2 of 2)
CYW4343W
6.4 mA
1.8V, 2.5V, and 3.3V
WL BBPLL/DFLL
WL OTP 3.3V
LDO3P3 with
Back‐Power
VOUT_3P3
WLRF_PA_VDD
480 to 800 mA
6.4 mA
VBAT
Protection
WL RF—PA (2.4 GHz)
LDO_
VDDBAT5V
1 uF
0201
4.7 uF
0402
(Peak 450‐800 mA
200 mA Average) 3.3V
2.5V Cap‐less
LNLDO
WL RF—ADC, AFE, LOGEN,
LNA, NMOS Mini‐PMU LDOs
22
ohm
(10 mA)
SW2
Peak: 92 mA
Average: 75 mA
Resistance: 1 ohm
Placed inside WL Radio
WPT_3P3
Peak: 70 mA
BT_PAVDD
Average: 15 mA
BT Class 1 PA
1 uF
0201
Power switch
No power switch
External to chip
Supply ball
No dedicated power switch, but internal power‐
down modes and block‐specific power switches
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CYW4343W
2.3 WLAN Power Management
The CYW4343W has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the
chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current
and supply voltages. Additionally, the CYW4343W integrated RAM is a high volatile memory with dynamic clock control. The dominant
supply current consumed by the RAM is leakage current only. Additionally, the CYW4343W includes an advanced WLAN power
management unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the CYW4343W into various
power management states appropriate to the operating environment and the activities that are being performed. The power
management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required
resources and a table that describes the relationship between resources and the time needed to enable and disable them. Power-up
sequences are fully programmable. Configurable, free-running counters (running at the 32.768 kHz LPO clock) in the PMU sequencer
are used to turn on/turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for
the current mode. Slower clock speeds are used wherever possible.
The CYW4343W WLAN power states are described as follows:
■ Active mode— All WLAN blocks in the CYW4343W are powered up and fully functional with active carrier sensing and frame
transmission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock
speeds are dynamically adjusted by the PMU sequencer.
■ Doze mode—The radio, analog domains, and most of the linear regulators are powered down. The rest of the CYW4343W remains
powered up in an IDLE state. All main clocks (PLL, crystal oscillator) are shut down to reduce active power to the minimum. The
32.768 kHz LPO clock is available only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to wake
up the chip and transition to Active mode. In Doze mode, the primary power consumed is due to leakage current.
■ Deep-sleep mode—Most of the chip, including analog and digital domains, and most of the regulators are powered off. Logic states
in the digital core are saved and preserved to retention memory in the always-on domain before the digital core is powered off. To
avoid lengthy hardware reinitialization, the logic states in the digital core are restored to their pre-deep-sleep settings when a wake-
up event is triggered by an external interrupt, a host resume through the SDIO bus, or by the PMU timers.
■ Power-down mode—The CYW4343W is effectively powered off by shutting down all internal regulators. The chip is brought out of
this mode by external logic re-enabling the internal regulators.
2.4 PMU Sequencing
The PMU sequencer is used to minimize system power consumption. It enables and disables various system resources based on a
computation of required resources and a table that describes the relationship between resources and the time required to enable and
disable them.
Resource requests can derive from several sources: clock requests from cores, the minimum resources defined in the ResourceMin
register, and the resources requested by any active resource request timers. The PMU sequencer maps clock requests into a set of
resources required to produce the requested clocks.
Each resource is in one of the following four states:
■ enabled
■ disabled
■ transition_on
■ transition_off
The timer value is 0 when the resource is enabled or disabled and nonzero during state transition. The timer is loaded with the time_on
or time_off value of the resource when the PMU determines that the resource must be enabled or disabled. That timer decrements
on each 32.768 kHz PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If
the time_on value is 0, the resource can transition immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that
the resource can transition immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either
the immediate transition or the timer load-decrement sequence.
During each clock cycle, the PMU sequencer performs the following actions:
■ Computes the required resource set based on requests and the resource dependency table.
■ Decrements all timers whose values are nonzero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource
and inverts the ResourceState bit.
■ Compares the request with the current resource status and determines which resources must be enabled or disabled.
■ Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered-up dependents.
■ Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled.
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2.5 Power-Off Shutdown
The CYW4343W provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices
in the system, remain operational. When the CYW4343W is not needed in the system, VDDIO_RF and VDDC are shut down while
VDDIO remains powered. This allows the CYW4343W to be effectively off while keeping the I/O pins powered so that they do not
draw extra current from any other devices connected to the I/O.
During a low-power shutdown state, provided VDDIO remains applied to the CYW4343W, all outputs are tristated, and most input
signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths
or create loading on any digital signals in the system, and enables the CYW4343W to be fully integrated in an embedded device and
to take full advantage of the lowest power-savings modes.
When the CYW4343W is powered on from this state, it is the same as a normal power-up, and the device does not retain any
information about its state from before it was powered down.
2.6 Power-Up/Power-Down/Reset Circuits
The CYW4343W has two signals (see Table 2) that enable or disable the Bluetooth and WLAN circuits and the internal regulator
blocks, allowing the host to control power consumption. For timing diagrams of these signals and the required power-up sequences,
see Section 20.: “Power-Up Sequence and Timing” .
Table 2. Power-Up/Power-Down/Reset Control Signals
Signal
Description
This signal is used by the PMU (with BT_REG_ON) to power-up the WLAN section. It is also OR-gated with the
BT_REG_ON input to control the internal CYW4343W regulators. When this pin is high, the regulators are enabled
and the WLAN section is out of reset. When this pin is low, the WLAN section is in reset. If BT_REG_ON and
WL_REG_ON are both low, the regulators are disabled. This pin has an internal 200 k pull-down resistor that is
enabled by default. It can be disabled through programming.
WL_REG_ON
This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down the internal
CYW4343W regulators. If BT_REG_ON and WL_REG_ON are low, the regulators will be disabled. This pin has
an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming.
BT_REG_ON
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3. Frequency References
An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency
reference driven by a temperature-compensated crystal oscillator (TCXO) signal may be used. No software settings are required to
differentiate between the two. In addition, a low-power oscillator (LPO) is provided for lower power mode timing.
3.1 Crystal Interface and Clock Generation
The CYW4343W can use an external crystal to provide a frequency reference. The recommended configuration for the crystal
oscillator, including all external components, is shown in Figure 5. Consult the reference schematics for the latest configuration.
Figure 5. Recommended Oscillator Configuration
C
WLRF_XTAL_XOP
12 – 27 pF
C
WLRF_XTAL_XON
R
12 – 27 pF
Note: Resistor value determined by crystal drive level.
See reference schematics for details.
The CYW4343W uses a fractional-N synthesizer to generate the radio frequencies, clocks, and data/packet timing so that it can
operate using numerous frequency references. The frequency reference can be an external source such as a TCXO or a crystal
interfaced directly to the CYW4343W.
The default frequency reference setting is a 37.4 MHz crystal or TCXO. The signal requirements and characteristics for the crystal
interface are shown in Table 3.
Note: Although the fractional-N synthesizer can support many reference frequencies, frequencies other than the default require
support to be added in the driver, plus additional extensive system testing. Contact Broadcom for further details.
3.2 TCXO
As an alternative to a crystal, an external precision TCXO can be used as the frequency reference, provided that it meets the phase
noise requirements listed in Table 3.
If the TCXO is dedicated to driving the CYW4343W, it should be connected to the WLRF_XTAL_XOP pin through an external capacitor
with value ranges from 200 pF to 1000 pF as shown in Figure 6.
Figure 6. Recommended Circuit to Use with an External Dedicated TCXO
200 pF – 1000 pF
TCXO
WLRF_XTAL_XOP
WLRF_XTAL_XON
NC
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Table 3. Crystal Oscillator and External Clock Requirements and Performance
Crystal
Min. Typ.
External Frequency
Reference
Parameter
Frequency
Conditions/Notes
Max.
Min. Typ. Max.
Units
MHz
pF
–
–
–
–
–
–
37.4a
–
–
–
–
–
–
Crystal load capacitance
ESR
12
–
–
–
–
–
–
60
Ω
External crystal must be able to tolerate
this drive level.
Drive level
200
–
–
–
–
–
μW
Resistive
–
–
–
–
–
–
10k
–
100k
–
–
7
Ω
Input Impedance (WLRF_X-
TAL_XOP)
Capacitive
pF
WLRF_XTAL_XOP input
voltage
AC-coupled analog signal
DC-coupled digital signal
DC-coupled digital signal
–
–
–
–
–
–
–
400b
–
–
–
–
1260
0.2
mVp-p
V
WLRF_XTAL_XOP input low
level
–
–
0
WLRF_XTAL_XOPinputhigh
level
–
–
1.0
–20
1.26
20
V
Frequency tolerance
Initial + over temperature
–20
20
ppm
Duty cycle
37.4 MHz clock
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
40
–
50
–
60
%
Phase Noisec, d, e
(IEEE 802.11 b/g)
37.4 MHz clock at 10 kHz offset
37.4 MHz clock at 100 kHz offset
37.4 MHz clock at 10 kHz offset
37.4 MHz clock at 100 kHz offset
37.4 MHz clock at 10 kHz offset
37.4 MHz clock at 100 kHz offset
–129
–136
–134
–141
–140
–147
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
–
–
Phase Noisec, d, e
(IEEE 802.11n, 2.4 GHz)
–
–
–
–
Phase Noisec, d, e
(256-QAM)
–
–
–
–
a. The frequency step size is approximately 80 Hz. The CYW4343W does not auto-detect the reference clock frequency; the frequency is
specified in the software and/or NVRAM file.
b. To use 256-QAM, a 800 mV minimum voltage is required.
c. For a clock reference other than 37.4 MHz, 20 × log10(f/37.4) dB should be added to the limits, where f = the reference clock frequency in
MHz.
d. Phase noise is assumed flat above 100 kHz.
e. The CYW4343W supports a 26 MHz reference clock sharing option. See the phase noise requirement in the table.
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3.3 External 32.768 kHz Low-Power Oscillator
The CYW4343W uses a secondary low-frequency sleep clock for low-power mode timing. Either the internal low-precision LPO or an
external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process,
voltage, and temperature, which is adequate for some applications. However, one trade-off caused by this wide LPO tolerance is a
small current consumption increase during power save mode that is incurred by the need to wake up earlier to avoid missing beacons.
Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock that meets the requirements listed in Table
4.
Note: The CYW4343W will auto-detect the LPO clock. If it senses a clock on the EXT_SLEEP_CLK pin, it will use that clock. If it
doesn't sense a clock, it will use its own internal LPO.
■ To use the internal LPO: Tie EXT_SLEEP_CLK to ground. Do not leave this pin floating.
■ To use an external LPO: Connect the external 32.768 kHz clock to EXT_SLEEP_CLK.
Table 4. External 32.768 kHz Sleep-Clock Specifications
Parameter
LPO Clock
Units
Nominal input frequency
Frequency accuracy
Duty cycle
32.768
±200
kHz
ppm
%
30–70
Input signal amplitude
Signal type
200–3300
mV, p-p
–
Square wave or sine wave
>100
<5
kΩ
Input impedancea
Clock jitter
pF
<10,000
ppm
a. When power is applied or switched off.
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4. WLAN System Interfaces
4.1 SDIO v2.0
The CYW4343W WLAN section supports SDIO version 2.0. for both 1-bit (25 Mbps) and 4-bit modes (100 Mbps), as well as high
speed 4-bit mode (50 MHz clocks—200 Mbps). It has the ability to map the interrupt signal on a GPIO pin. This out-of-band interrupt
signal notifies the host when the WLAN device wants to turn on the SDIO interface. The ability to force control of the gated clocks
from within the WLAN chip is also provided.
SDIO mode is enabled using the strapping option pins. See Table 20 for details.
Three functions are supported:
■ Function 0 standard SDIO function. The maximum block size is 32 bytes.
■ Function 1 backplane function to access the internal System-on-a-Chip (SoC) address space. The maximum block size is 64 bytes.
■ Function 2 WLAN function for efficient WLAN packet transfer through DMA. The maximum block size is 512 bytes.
4.1.1 SDIO Pin Descriptions
Table 5. SDIO Pin Descriptions
SD 4-Bit Mode
Data line 0
SD 1-Bit Mode
Data line
DATA0
DATA1
DATA2
DATA3
CLK
DATA
IRQ
NC
Data line 1 or Interrupt
Data line 2
Interrupt
Not used
Not used
Clock
Data line 3
NC
Clock
CLK
CMD
CMD
Command line
Command line
Figure 7. Signal Connections to SDIO Host (SD 4-Bit Mode)
CLK
CMD
CYW4343W
SD Host
DAT[3:0]
Figure 8. Signal Connections to SDIO Host (SD 1-Bit Mode)
CLK
CMD
CYW4343W
SD Host
DATA
IRQ
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5. Wireless LAN MAC and PHY
5.1 MAC Features
The CYW4343W WLAN MAC supports features specified in the IEEE 802.11 base standard, and amended by IEEE 802.11n. The
salient features are listed below:
■ Transmission and reception of aggregated MPDUs (A-MPDU).
■ Support for power management schemes, including WMM power-save, power-save multipoll (PSMP) and multiphase PSMP
operation.
■ Support for immediate ACK and Block-ACK policies.
■ Interframe space timing support, including RIFS.
■ Support for RTS/CTS and CTS-to-self frame sequences for protecting frame exchanges.
■ Back-off counters in hardware for supporting multiple priorities as specified in the WMM specification.
■ Timing synchronization function (TSF), network allocation vector (NAV) maintenance, and target beacon transmission time (TBTT)
generation in hardware.
■ Hardware off-load for AES-CCMP, legacy WPA TKIP, legacy WEP ciphers, WAPI, and support for key management.
■ Support for coexistence with Bluetooth and other external radios.
■ Programmable independent basic service set (IBSS) or infrastructure basic service set functionality
■ Statistics counters for MIB support.
5.1.1 MAC Description
The CYW4343W WLAN MAC is designed to support high throughput operation with low-power consumption. It does so without
compromising on Bluetooth coexistence policies, thereby enabling optimal performance over both networks. In addition, several
power-saving modes that have been implemented allow the MAC to consume very little power while maintaining network-wide timing
synchronization. The architecture diagram of the MAC is shown in Figure 9.
Figure 9. WLAN MAC Architecture
Embedded CPU Interface
Host Registers, DMA Engines
TX‐FIFO
32 KB
RX‐FIFO
10 KB
PSM
PMQ
PSM
UCODE
Memory
IFS
Backoff, BTCX
WEP
WEP, TKIP, AES
TSF
SHM
BUS
IHR
NAV
BUS
Shared Memory
6 KB
RXE
RX A‐MPDU
TXE
TX A‐MPDU
EXT‐ IHR
MAC
‐
PHY Interface
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The following sections provide an overview of the important modules in the MAC.
PSM
The programmable state machine (PSM) is a microcoded engine that provides most of the low-level control to the hardware to
implement the IEEE 802.11 specification. It is a microcontroller that is highly optimized for flow-control operations, which are predom-
inant in implementations of communication protocols. The instruction set and fundamental operations are simple and general, which
allows algorithms to be optimized until very late in the design process. It also allows for changes to the algorithms to track evolving
IEEE 802.11 specifications.
The PSM fetches instructions from the microcode memory. It uses the shared memory to obtain operands for instructions, as a data
store, and to exchange data between both the host and the MAC data pipeline (via the SHM bus). The PSM also uses a scratch-pad
memory (similar to a register bank) to store frequently accessed and temporary variables.
The PSM exercises fine-grained control over the hardware engines by programming internal hardware registers (IHR). These IHRs
are collocated with the hardware functions they control and are accessed by the PSM via the IHR bus.
The PSM fetches instructions from the microcode memory using an address determined by the program counter, an instruction literal,
or a program stack. For ALU operations, the operands are obtained from shared memory, scratch-pad memory, IHRs, or instruction
literals, and the results are written into the shared memory, scratch-pad memory, or IHRs.
There are two basic branch instructions: conditional branches and ALU-based branches. To better support the many decision points
in the IEEE 802.11 algorithms, branches can depend on either readily available signals from the hardware modules (branch condition
signals are available to the PSM without polling the IHRs) or on the results of ALU operations.
WEP
The wired equivalent privacy (WEP) engine encapsulates all the hardware accelerators to perform the encryption and decryption, as
well as the MIC computation and verification. The accelerators implement the following cipher algorithms: legacy WEP, WPA TKIP,
and WPA2 AES-CCMP.
Based on the frame type and association information, the PSM determines the appropriate cipher algorithm to be used. It supplies
the keys to the hardware engines from an on-chip key table. The WEP interfaces with the transmit engine (TXE) to encrypt and
compute the MIC on transmit frames and the receive engine (RXE) to decrypt and verify the MIC on receive frames. WAPI is also
supported.
TXE
The transmit engine (TXE) constitutes the transmit data path of the MAC. It coordinates the DMA engines to store the transmit frames
in the TXFIFO. It interfaces with WEP module to encrypt frames and transfers the frames across the MAC-PHY interface at the
appropriate time determined by the channel access mechanisms.
The data received from the DMA engines are stored in transmit FIFOs. The MAC supports multiple logical queues to support traffic
streams that have different QoS priority requirements. The PSM uses the channel access information from the IFS module to schedule
a queue from which the next frame is transmitted. Once the frame is scheduled, the TXE hardware transmits the frame based on a
precise timing trigger received from the IFS module.
The TXE module also contains the hardware that allows the rapid assembly of MPDUs into anA-MPDU for transmission. The hardware
module aggregates the encrypted MPDUs by adding appropriate headers and pad delimiters as needed.
RXE
The receive engine (RXE) constitutes the receive data path of the MAC. It interfaces with the DMAengine to drain the received frames
from the RX FIFO. It transfers bytes across the MAC-PHY interface and interfaces with the WEP module to decrypt frames. The
decrypted data is stored in the RX FIFO.
The RXE module contains programmable filters that are programmed by the PSM to accept or filter frames based on several criteria
such as receiver address, BSSID, and certain frame types.
The RXE module also contains the hardware required to detect A-MPDUs, parse the headers of the containers, and disaggregate
them into component MPDUS.
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IFS
The IFS module contains the timers required to determine interframe space timing including RIFS timing. It also contains multiple
back-off engines required to support prioritized access to the medium as specified by WMM.
The interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the PHY. These timers
provide precise timing to the TXE to begin frame transmission. The TXE uses this information to send response frames or perform
transmit frame-bursting (RIFS or SIFS separated, as within a TXOP).
The back-off engines (for each access category) monitor channel activity, in each slot duration, to determine whether to continue or
pause the back-off counters. When the back-off counters reach 0, the TXE gets notified so that it may commence frame transmission.
In the event of multiple back-off counters decrementing to 0 at the same time, the hardware resolves the conflict based on policies
provided by the PSM.
The IFS module also incorporates hardware that allows the MAC to enter a low-power state when operating under the IEEE power-
saving mode. In this mode, the MAC is in a suspended state with its clock turned off. A sleep timer, whose count value is initialized
by the PSM, runs on a slow clock and determines the duration over which the MAC remains in this suspended state. Once the timer
expires, the MAC is restored to its functional state. The PSM updates the TSF timer based on the sleep duration, ensuring that the
TSF is synchronized to the network.
The IFS module also contains the PTA hardware that assists the PSM in Bluetooth coexistence functions.
TSF
The timing synchronization function (TSF) module maintains the TSF timer of the MAC. It also maintains the target beacon trans-
mission time (TBTT). The TSF timer hardware, under the control of the PSM, is capable of adopting timestamps received from beacon
and probe response frames in order to maintain synchronization with the network.
The TSF module also generates trigger signals for events that are specified as offsets from the TSF timer, such as uplink and downlink
transmission times used in PSMP.
NAV
The network allocation vector (NAV) timer module is responsible for maintaining the NAV information conveyed through the duration
field of MAC frames. This ensures that the MAC complies with the protection mechanisms specified in the standard.
The hardware, under the control of the PSM, maintains the NAV timer and updates the timer appropriately based on received frames.
This timing information is provided to the IFS module, which uses it as a virtual carrier-sense indication.
MAC-PHY Interface
The MAC-PHY interface consists of a data path interface to exchange RX/TX data from/to the PHY. In addition, there is a programming
interface, which can be controlled either by the host or the PSM to configure and control the PHY.
5.2 PHY Description
The CYW4343W WLAN digital PHY is designed to comply with IEEE 802.11b/g/n single stream to provide wireless LAN connectivity
supporting data rates from 1 Mbps to 96 Mbps for low-power, high-performance handheld applications.
The PHY has been designed to meet specification requirements in the presence of interference, radio nonlinearity, and impairments.
It incorporates efficient implementations of the filters, FFT, and Viterbi decoder algorithms. Efficient algorithms have been designed
to achieve maximum throughput and reliability, including algorithms for carrier sense/rejection, frequency/phase/timing acquisition
and tracking, and channel estimation and tracking. The PHY receiver also contains a robust IEEE 802.11b demodulator. The PHY
carrier sense has been tuned to provide high throughput for IEEE 802.11g/IEEE 802.11b hybrid networks with Bluetooth coexistence.
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5.2.1 PHY Features
■ Supports the IEEE 802.11b/g/n single-stream standards.
■ Explicit IEEE 802.11n transmit beamforming.
■ Supports optional Greenfield mode in TX and RX.
■ Tx and Rx LDPC for improved range and power efficiency.
■ Supports IEEE 802.11h/d for worldwide operation.
■ Algorithms achieving low power, enhanced sensitivity, range, and reliability.
■ Algorithms to maximize throughput performance in the presence of Bluetooth signals.
■ Automatic gain control scheme for blocking and nonblocking application scenarios for cellular applications.
■ Closed-loop transmit power control.
■ Designed to meet FCC and other regulatory requirements.
■ Support for 2.4 GHz Broadcom TurboQAM data rates and 20 MHz channel bandwidth.
Figure 10. WLAN PHY Block Diagram
CCK/DSSS
Demodulate
Filters
and
Radio
Comp
Frequency
and Timing
Synch
Descramble
and
Deframe
OFDM
Demodulate
Viterbi
Decoder
Carrier Sense,
AGC, and Rx
FSM
Buffers
Radio
Control
Block
MAC
Interface
FFT/IFFT
AFE
and
Radio
Modulation
and Coding
Tx FSM
Frame and
Scramble
Filters and
Radio Comp
Modulate/
Spread
PA Comp
COEX
The PHY is capable of fully calibrating the RF front-end to extract the highest performance. On power-up, the PHY performs a full
calibration suite to correct for IQ mismatch and local oscillator leakage. The PHY also performs periodic calibration to compensate
for any temperature related drift, thus maintaining high-performance over time. A closed-loop transmit control algorithm maintains the
output power at its required level and can control TX power on a per-packet basis.
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6. WLAN Radio Subsystem
The CYW4343W includes an integrated WLAN RF transceiver that has been optimized for use in 2.4 GHz Wireless LAN systems. It
is designed to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 GHz
unlicensed ISM band. The transmit and receive sections include all on-chip filtering, mixing, and gain control functions. Improvements
to the radio design include shared TX/RX baseband filters and high immunity to supply noise.
Figure 11 shows the radio functional block diagram.
Figure 11. Radio Functional Block Diagram
WL DAC
WL TXLPF
WL DAC
WL PA
WL PGA
WL TX G‐Mixer WL TXLPF
Voltage
Regulators
WLAN BB
WLRF_2G_RF
WLRF_2G_eLG
4 ~ 6 nH
Recommend
Q = 40
WL ADC
WL ADC
10 pF
WL RXLPF
SLNA
WL G‐LNA12
WL RXLPF
WL RX G‐Mixer
WL ATX
WL ARX
WL GTX
WL GRX
Gm
BT LNA GM
CLB
WL LOGEN
WL PLL
BT PLL
Shared XO
BT RX
BT TX
BT LOGEN
LPO/Ext LPO/RCAL
BT ADC
BT ADC
BT RXLPF
BT LNA Load
BT PA
BT RX Mixer
BT RXLPF
BT BB
BT
BT DAC
BT DAC
BT TX Mixer
BT TXLPF
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6.1 Receive Path
The CYW4343W has a wide dynamic range, direct conversion receiver. It employs high-order on-chip channel filtering to ensure
reliable operation in the noisy 2.4 GHz ISM band.
6.2 Transmit Path
Baseband data is modulated and upconverted to the 2.4 GHz ISM band. A linear on-chip power amplifier is included, which is capable
of delivering high output powers while meeting IEEE 802.11b/g/n specifications without the need for an external PA. This PAis supplied
by an internal LDO that is directly supplied by VBAT, thereby eliminating the need for a separate PALDO. Closed-loop output power
control is integrated.
6.3 Calibration
The CYW4343W features dynamic on-chip calibration, eliminating process variation across components. This enables the
CYW4343W to be used in high-volume applications because calibration routines are not required during manufacturing testing. These
calibration routines are performed periodically during normal radio operation. Automatic calibration examples include baseband filter
calibration for optimum transmit and receive performance and LOFT calibration for leakage reduction. In addition, I/Q calibration, R
calibration, and VCO calibration are performed on-chip.
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7. Bluetooth Subsystem Overview
The Cypress CYW4343W is a Bluetooth 4.1-compliant, baseband processor and 2.4 GHz transceiver. It features the highest level of
integration and eliminates all critical external components, thus minimizing the footprint, power consumption, and system cost of a
Bluetooth.
The CYW4343W is the optimal solution for any Bluetooth voice and/or data application. The Bluetooth subsystem presents a standard
Host Controller Interface (HCI) via a high speed UART and PCM interface for audio. The CYW4343W incorporates all Bluetooth 4.1
features including secure simple pairing, sniff subrating, and encryption pause and resume.
The CYW4343W Bluetooth radio transceiver provides enhanced radio performance to meet the most stringent mobile phone
temperature applications and the tightest integration into mobile handsets and portable devices. It is fully compatible with any of the
standard TCXO frequencies and provides full radio compatibility to operate simultaneously with GPS, WLAN, NFC, and cellular radios.
The Bluetooth transmitter also features a Class 1 power amplifier with Class 2 capability.
7.1 Features
Major Bluetooth features of the CYW4343W include:
■ Supports key features of upcoming Bluetooth standards
■ Fully supports Bluetooth Core Specification version 4.1 plus enhanced data rate (EDR) features:
❐ Adaptive Frequency Hopping (AFH)
❐ Quality of Service (QoS)
❐ Extended Synchronous Connections (eSCO)—voice connections
❐ Fast connect (interlaced page and inquiry scans)
❐ Secure Simple Pairing (SSP)
❐ Sniff Subrating (SSR)
❐ Encryption Pause Resume (EPR)
❐ Extended Inquiry Response (EIR)
❐ Link Supervision Timeout (LST)
■ UART baud rates up to 4 Mbps
■ Supports all Bluetooth 4.1 packet types
■ Supports maximum Bluetooth data rates over HCI UART
■ Multipoint operation with up to seven active slaves
❐ Maximum of seven simultaneous active ACL links
❐ Maximum of three simultaneous active SCO and eSCO connections with scatternet support
■ Trigger Beacon fast connect (TBFC)
■ Narrowband and wideband packet loss concealment
■ Scatternet operation with up to four active piconets with background scan and support for scatter mode
■ High-speed HCI UART transport support with low-power out-of-band BT_DEV_WAKE and BT_HOST_WAKE signaling (see “Host
Controller Power Management” )
■ Channel-quality driven data rate and packet type selection
■ Standard Bluetooth test modes
■ Extended radio and production test mode features
■ Full support for power savings modes
❐ Bluetooth clock request
❐ Bluetooth standard sniff
❐ Deep-sleep modes and software regulator shutdown
■ TCXO input and auto-detection of all standard handset clock frequencies. Also supports a low-power crystal, which can be used
during power save mode for better timing accuracy.
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7.2 Bluetooth Radio
The CYW4343W has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has
been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4 GHz
unlicensed ISM band. It is fully compliant with the Bluetooth Radio Specification and EDR specification and meets or exceeds the
requirements to provide the highest communication link quality of service.
7.2.1 Transmit
The CYW4343W features a fully integrated zero-IF transmitter. The baseband transmit data is GFSK-modulated in the modem block
and upconverted to the 2.4 GHz ISM band in the transmitter path. The transmitter path has signal filters, an I/Q upconverter, an output
power amplifier, and RF filters. The transmitter path also incorporates /4–DQPSK for 2 Mbps and 8–DPSK for 3 Mbps to support
EDR. The transmitter section is compatible with the Bluetooth Low Energy specification. The transmitter PA bias can also be adjusted
to provide Bluetooth Class 1 or Class 2 operation.
7.2.2 Digital Modulator
The digital modulator performs the data modulation and filtering required for the GFSK, /4–DQPSK, and 8–DPSK signal. The fully
digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal and is much
more stable than direct VCO modulation schemes.
7.2.3 Digital Demodulator and Bit Synchronizer
The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit-
synchronization algorithm.
7.2.4 Power Amplifier
The fully integrated PA supports Class 1 or Class 2 output using a highly linearized, temperature-compensated design. This provides
greater flexibility in front-end matching and filtering. Due to the linear nature of the PAcombined with some integrated filtering, external
filtering is required to meet the Bluetooth and regulatory harmonic and spurious requirements. For integrated mobile handset appli-
cations in which Bluetooth is integrated next to the cellular radio, external filtering can be applied to achieve near-thermal noise levels
for spurious and radiated noise emissions. The transmitter features a sophisticated on-chip transmit signal strength indicator (TSSI)
block to keep the absolute output power variation within a tight range across process, voltage, and temperature.
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7.2.5 Receiver
The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit
synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order on-chip channel
filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology with built-in out-of-band attenuation
enables the CYW4343W to be used in most applications with minimal off-chip filtering. For integrated handset operation, in which the
Bluetooth function is integrated close to the cellular transmitter, external filtering is required to eliminate the desensitization of the
receiver by the cellular transmit signal.
7.2.6 Digital Demodulator and Bit Synchronizer
The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit
synchronization algorithm.
7.2.7 Receiver Signal Strength Indicator
The radio portion of the CYW4343W provides a Receiver Signal Strength Indicator (RSSI) signal to the baseband so that the controller
can take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the
transmitter should increase or decrease its output power.
7.2.8 Local Oscillator Generation
Local Oscillator (LO) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels.
The LO generation subblock employs an architecture for high immunity to LO pulling during PA operation. The CYW4343W uses an
internal RF and IF loop filter.
7.2.9 Calibration
The CYW4343W radio transceiver features an automated calibration scheme that is self contained in the radio. No user interaction
is required during normal operation or during manufacturing to optimize performance. Calibration optimizes the performance of all the
major blocks within the radio to within 2% of optimal conditions, including filter gain and phase characteristics, matching between key
components, and key gain blocks. This takes into account process variation and temperature variation. Calibration occurs transpar-
ently during normal operation during the settling time of the hops and calibrates for temperature variations as the device cools and
heats during normal operation in its environment.
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8. Bluetooth Baseband Core
The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high-performance Bluetooth operation.
The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it,
handles data flow control, schedules SCO/ACLTX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages
data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these
functions, it independently handles HCI event types and HCI command types.
The following transmit and receive functions are also implemented in the BBC hardware to increase the reliability and security of data
before sending and receiving it over the air:
■ Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC),
data decryption, and data dewhitening in the receiver.
■ Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in the
transmitter.
8.1 Bluetooth 4.1 Features
The BBC supports all Bluetooth 4.1 features, with the following benefits:
■ Dual-mode classic Bluetooth and classic Low Energy (BT and BLE) operation.
■ Low energy physical layer
■ Low energy link layer
■ Enhancements to HCI for low energy
■ Low energy direct test mode
■ 128 AES-CCM secure connection for both BT and BLE
Note: The CYW4343W is compatible with the Bluetooth Low Energy operating mode, which provides a dramatic reduction in the
power consumption of the Bluetooth radio and baseband. The primary application for this mode is to provide support for low data rate
devices, such as sensors and remote controls.
8.2 Link Control Layer
The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU).
This layer contains the command controller that takes commands from the software, and other controllers that are activated or
configured by the command controller, to perform the link control tasks. Each task performs a different state in the Bluetooth link
controller.
■ Major states:
❐ Standby
❐ Connection
■ Substates:
❐ Page
❐ Page Scan
❐ Inquiry
❐ Inquiry Scan
❐ Sniff
❐ BLE Adv
❐ BLE Scan/Initiation
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8.3 Test Mode Support
The CYW4343W fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth System Version 3.0.
This includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence.
In addition to the standard Bluetooth Test Mode, the CYW4343W also supports enhanced testing features to simplify RF debugging
and qualification as well as type-approval testing. These features include:
■ Fixed frequency carrier-wave (unmodulated) transmission
❐ Simplifies some type-approval measurements (Japan)
❐ Aids in transmitter performance analysis
■ Fixed frequency constant receiver mode
❐ Receiver output directed to an I/O pin
❐ Allows for direct BER measurements using standard RF test equipment
❐ Facilitates spurious emissions testing for receive mode
■ Fixed frequency constant transmission
❐ Eight-bit fixed pattern or PRBS-9
❐ Enables modulated signal measurements with standard RF test equipment
8.4 Bluetooth Power Management Unit
The Bluetooth Power Management Unit (PMU) provides power management features that can be invoked by either software through
power management registers or packet handling in the baseband core. The power management functions provided by the
CYW4343W are:
■ RF Power Management
■ Host Controller Power Management
■ BBC Power Management
8.4.1 RF Power Management
The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz trans-
ceiver. The transceiver then processes the power-down functions accordingly.
8.4.2 Host Controller Power Management
When running in UART mode, the CYW4343W can be configured so that dedicated signals are used for power management
handshaking between the CYW4343W and the host. The basic power saving functions supported by those handshaking signals
include the standard Bluetooth defined power savings modes and standby modes of operation.
Table 6 describes the power-control handshake signals used with the UART interface.
Table 6. Power Control Pin Description
Signal
Type
Description
Bluetooth device wake-up signal: Signal from the host to the CYW4343W indicating that the host
requires attention.
BT_DEV_WAKE
I
■ Asserted: The Bluetooth device must wake up or remain awake.
■ Deasserted: The Bluetooth device may sleep when sleep criteria are met.
The polarity of this signal is software configurable and can be asserted high or low.
Host wake-up signal. Signal from the CYW4343W to the host indicating that the CYW4343W requires
attention.
BT_HOST_WAKE
CLK_REQ
O
O
■ Asserted: Host device must wake up or remain awake.
■ Deasserted: Host device may sleep when sleep criteria are met.
The polarity of this signal is software configurable and can be asserted high or low.
The CYW4343W asserts CLK_REQ when Bluetooth or WLAN directs the host to turn on the
reference clock. The CLK_REQ polarity is active-high. Add an external 100 kΩ pull-down resistor to
ensure the signal is deasserted when the CYW4343W powers up or resets when VDDIO is present.
Note: Pad function Control Register is set to 0 for these pins.
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Figure 12. Startup Signaling Sequence
LPO
Host IOs unconfigured
Host IOs configured
VDDIO
T1
HostResetX
BT_GPIO_0
(BT_DEV_WAKE)
T2
BTH IOs unconfiguredBTH IOs configured
BT_REG_ON
BT_GPIO_1
(BT_HOST_WAKE)
T3
Host side drives
this line low
BT_UART_CTS_N
BT_UART_RTS_N
BTH device drives this
line low indicating
transport is ready
T4
CLK_REQ_OUT
Notes :
T5
Driven
Pulled
T1 is the time for host to settle it’s IOs after a reset.
T2 is the time for host to drive BT_REG_ON high after the Host IOs are configured.
T3 is the time for BTH (Bluetooth) device to settle its IOs after a reset and reference clock settling time has
elapsed.
T4 is the time for BTH device to drive BT_UART_RTS_N low after the host drives BT_UART_CTS_N low. This
assumes the BTH device has already completed initialization.
T5 is the time for BTH device to drive CLK_REQ_OUT high after BT_REG_ON goes high. Note this pin is used for
designs that use an external reference clock source from the Host. This pin is irrelevant for Crystal reference
clock based designs where the BTH device generates it’s own reference clock from an external crystal connected
to it’s oscillator circuit.
Timing diagram assumes VBAT is present.
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8.5 BBC Power Management
The following are low-power operations for the BBC:
■ Physical layer packet-handling turns the RF on and off dynamically within transmit/receive packets.
■ Bluetooth-specified low-power connection modes: sniff and hold. While in these modes, the CYW4343W runs on the low-power
oscillator and wakes up after a predefined time period.
■ Alow-powershutdownfeatureallowsthedevicetobeturnedoffwhilethehostandanyotherdevicesinthesystemremainoperational.
When the CYW4343W is not needed in the system, the RF and core supplies are shut down while the I/O remains powered. This
allows the CYW4343W to effectively be off while keeping the I/O pins powered, so they do not draw extra current from any other I/
O-connected devices.
During the low-power shut-down state, provided VDDIO remains applied to the CYW4343W, all outputs are tristated, and most input
signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths
or create loading on digital signals in the system and enables the CYW4343W to be fully integrated in an embedded device to take
full advantage of the lowest power-saving modes.
Two CYW4343W input signals are designed to be high-impedance inputs that do not load the driving signal even if the chip does not
have VDDIO power supplied to it: the frequency reference input (WRF_TCXO_IN) and the 32.768 kHz input (LPO). When the
CYW4343W is powered on from this state, it is the same as a normal power-up, and the device does not contain any information
about its state from the time before it was powered down.
8.5.1 Wideband Speech
The CYW4343W provides support for wideband speech (WBS) technology. The CYW4343W can perform subband-codec (SBC), as
well as mSBC, encoding and decoding of linear 16 bits at 16 kHz (256 kbps rate) transferred over the PCM bus.
8.6 Packet Loss Concealment
Packet Loss Concealment (PLC) improves the apparent audio quality for systems with marginal link performance. Bluetooth messages
are sent in packets. When a packet is lost, it creates a gap in the received audio bit-stream. Packet loss can be mitigated in several
ways:
■ Fill in zeros.
■ Ramp down the output audio signal toward zero (this is the method used in current Bluetooth headsets).
■ Repeat the last frame (or packet) of the received bit-stream and decode it as usual (frame repeat).
These techniques cause distortion and popping in the audio stream. The CYW4343W uses a proprietary waveform extension
algorithm to provide dramatic improvement in the audio quality. Figure 13 and Figure 14 show audio waveforms with and without
Packet Loss Concealment. Cypress PLC/BEC algorithms also support wideband speech.
Figure 13. CVSD Decoder Output Waveform Without PLC
Packet losses causes ramp-down
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Figure 14. CVSD Decoder Output Waveform After Applying PLC
8.6.1 Codec Encoding
The CYW4343W can support SBC and mSBC encoding and decoding for wideband speech.
8.6.2 Multiple Simultaneous A2DP Audio Streams
The CYW4343W has the ability to take a single audio stream and output it to multiple Bluetooth devices simultaneously. This allows
a user to share his or her music (or any audio stream) with a friend.
8.7 Adaptive Frequency Hopping
The CYW4343W gathers link quality statistics on a channel by channel basis to facilitate channel assessment and channel map
selection. The link quality is determined using both RF and baseband signal processing to provide a more accurate frequency-hop
map.
8.8 Advanced Bluetooth/WLAN Coexistence
The CYW4343W includes advanced coexistence technologies that are only possible with a Bluetooth/WLAN integrated die solution.
These coexistence technologies are targeted at small form-factor platforms, such as cell phones and media players, including appli-
cations such as VoWLAN + SCO and Video-over-WLAN + High Fidelity BT Stereo.
Support is provided for platforms that share a single antenna between Bluetooth and WLAN. Dual-antenna applications are also
supported. The CYW4343W radio architecture allows for lossless simultaneous Bluetooth and WLAN reception for shared antenna
applications. This is possible only via an integrated solution (shared LNAand joint AGC algorithm). It has superior performance versus
implementations that need to arbitrate between Bluetooth and WLAN reception.
The CYW4343W integrated solution enables MAC-layer signaling (firmware) and a greater degree of sharing via an enhanced
coexistence interface. Information is exchanged between the Bluetooth and WLAN cores without host processor involvement.
The CYW4343W also supports Transmit Power Control (TPC) on the STA together with standard Bluetooth TPC to limit mutual
interference and receiver desensitization. Preemption mechanisms are utilized to prevent AP transmissions from colliding with
Bluetooth frames. Improved channel classification techniques have been implemented in Bluetooth for faster and more accurate
detection and elimination of interferers (including non-WLAN 2.4 GHz interference).
The Bluetooth AFH classification is also enhanced by the WLAN core’s channel information.
8.9 Fast Connection (Interlaced Page and Inquiry Scans)
The CYW4343W supports page scan and inquiry scan modes that significantly reduce the average inquiry response and connection
times. These scanning modes are compatible with the Bluetooth version 2.1 page and inquiry procedures.
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9. Microprocessor and Memory Unit for Bluetooth
The Bluetooth microprocessor core is based on the ARM Cortex-M3 32-bit RISC processor with embedded ICE-RT debug and JTAG
interface units. It runs software from the link control (LC) layer up to the host controller interface (HCI).
The ARM core is paired with a memory unit that contains 576 KB of ROM for program storage and boot ROM, and 160 KB of RAM
for data scratch-pad and patch RAM code. The internal ROM allows for flexibility during power-on reset (POR) to enable the same
device to be used in various configurations. At power-up, the lower-layer protocol stack is executed from the internal ROM memory.
External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes or feature additions. These patches
may be downloaded from the host to the CYW4343W through the UART transports.
9.1 RAM, ROM, and Patch Memory
The CYW4343W Bluetooth core has 160 KB of internal RAM which is mapped between general purpose scratch-pad memory and
patch memory, and 576 KB of ROM used for the lower-layer protocol stack, test mode software, and boot ROM. The patch memory
is used for bug fixes and feature additions to ROM memory code.
9.2 Reset
The CYW4343W has an integrated power-on reset circuit that resets all circuits to a known power-on state. The BT POR circuit is out
of reset after BT_REG_ON goes high. If BT_REG_ON is low, then the POR circuit is held in reset.
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10. Bluetooth Peripheral Transport Unit
10.1 PCM Interface
The CYW4343W supports two independent PCM interfaces that share pins with the I2S interfaces. The PCM interface on the
CYW4343W can connect to linear PCM codec devices in master or slave mode. In master mode, the CYW4343W generates the
PCM_CLK and PCM_SYNC signals, and in slave mode, these signals are provided by another master on the PCM interface and are
inputs to the CYW4343W. The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific HCI
commands.
10.1.1 Slot Mapping
The CYW4343W supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three
channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample
interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate of 128 kHz, 512 kHz, or
1024 kHz. The corresponding number of slots for these interface rates is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM
data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow
other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM
clock during the last bit of the slot.
10.1.2 Frame Synchronization
The CYW4343W supports both short- and long-frame synchronization in both master and slave modes. In short-frame synchronization
mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is
synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the
first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization
signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident
with the first bit of the first slot.
10.1.3 Data Formatting
The CYW4343W may be configured to generate and accept several different data formats. For conventional narrowband speech
mode, the CYW4343W uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support
various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0’s, 1’s, a sign
bit, or a programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first.
10.1.4 Wideband Speech Support
When the host encodes Wideband Speech (WBS) packets in transparent mode, the encoded packets are transferred over the PCM
bus for an eSCO voice connection. In this mode, the PCM bus is typically configured in master mode for a 4 kHz sync rate with 16-
bit samples, resulting in a 64 kbps bit rate. The CYW4343W also supports slave transparent mode using a proprietary rate-matching
scheme. In SBC-code mode, linear 16-bit data at 16 kHz (256 kbps rate) is transferred over the PCM bus.
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10.1.5 PCM Interface Timing
Short Frame Sync, Master Mode
Figure 15. PCM Timing Diagram (Short Frame Sync, Master Mode)
1
2
3
PCM_BCLK
4
PCM_SYNC
PCM_OUT
8
High Impedance
7
5
6
PCM_IN
Table 7. PCM Interface Timing Specifications (Short Frame Sync, Master Mode)
Ref No. Characteristics
Minimum
Typical
Maximum
Unit
MHz
ns
1
PCM bit clock frequency
PCM bit clock low
PCM bit clock high
PCM_SYNC delay
PCM_OUT delay
PCM_IN setup
–
41
41
0
–
–
–
–
–
–
–
12
–
2
3
4
5
6
7
–
ns
25
25
–
ns
0
ns
8
ns
PCM_IN hold
8
–
ns
Delay from rising edge of PCM_BCLK during last bit period to
PCM_OUT becoming high impedance
8
0
–
25
ns
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Short Frame Sync, Slave Mode
Figure 16. PCM Timing Diagram (Short Frame Sync, Slave Mode)
1
2
3
PCM_BCLK
4
5
PCM_SYNC
PCM_OUT
9
High Impedance
8
6
7
PCM_IN
Table 8. PCM Interface Timing Specifications (Short Frame Sync, Slave Mode)
Ref No. Characteristics
Minimum Typical Maximum
Unit
MHz
ns
1
PCM bit clock frequency
PCM bit clock low
PCM bit clock high
PCM_SYNC setup
PCM_SYNC hold
PCM_OUT delay
PCM_IN setup
–
41
41
8
–
–
–
–
–
–
–
–
12
–
2
3
4
5
6
7
8
–
ns
–
ns
8
–
ns
0
25
–
ns
8
ns
PCM_IN hold
8
–
ns
Delay from rising edge of PCM_BCLK during last bit period to
PCM_OUT becoming high impedance
9
0
–
25
ns
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Long Frame Sync, Master Mode
Figure 17. PCM Timing Diagram (Long Frame Sync, Master Mode)
1
2
3
PCM_BCLK
4
PCM_SYNC
PCM_OUT
8
High Impedance
7
Bit 0
Bit 0
Bit 1
Bit 1
5
6
PCM_IN
Table 9. PCM Interface Timing Specifications (Long Frame Sync, Master Mode)
Ref No. Characteristics
Minimum
Typical
Maximum
Unit
MHz
ns
1
PCM bit clock frequency
PCM bit clock low
PCM bit clock high
PCM_SYNC delay
PCM_OUT delay
PCM_IN setup
–
41
41
0
–
–
–
–
–
–
–
12
–
2
3
4
5
6
7
–
ns
25
25
–
ns
0
ns
8
ns
PCM_IN hold
8
–
ns
Delay from rising edge of PCM_BCLK during last bit period to
PCM_OUT becoming high impedance
8
0
–
25
ns
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Long Frame Sync, Slave Mode
Figure 18. PCM Timing Diagram (Long Frame Sync, Slave Mode)
1
2
3
PCM_BCLK
4
5
PCM_SYNC
9
PCM_OUT
PCM_IN
Bit 0
Bit 0
HIGH IMPEDANCE
8
Bit 1
6
7
Bit 1
Table 10. PCM Interface Timing Specifications (Long Frame Sync, Slave Mode)
Ref No. Characteristics
Minimum
Typical
Maximum
Unit
MHz
ns
1
PCM bit clock frequency
PCM bit clock low
PCM bit clock high
PCM_SYNC setup
PCM_SYNC hold
PCM_OUT delay
PCM_IN setup
–
41
41
8
–
–
–
–
–
–
–
–
12
–
2
3
4
5
6
7
8
–
ns
–
ns
8
–
ns
0
25
–
ns
8
ns
PCM_IN hold
8
–
ns
Delay from rising edge of PCM_BCLK during last bit period to
PCM_OUT becoming high impedance
9
0
–
25
ns
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10.2 UART Interface
The CYW4343W uses UART for Bluetooth HCI. The UART is a standard 4-wire interface (RX, TX, RTS, and CTS) with adjustable
baud rates from 9600 bps to 4.0 Mbps. The interface features an automatic baud rate detection capability that returns a baud rate
selection. Alternatively, the baud rate may be selected through a vendor-specific UART HCI command.
The UART has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support EDR. Access to the FIFOs is conducted through
the Advanced High Performance Bus (AHB) interface through either DMA or the CPU. The UART supports the Bluetooth 4.1 UART
HCI specification: H4 and H5. The default baud rate is 115.2 Kbaud.
The UART supports the 3-wire H5 UART transport as described in the Bluetooth specification (Three-wire UART Transport Layer).
Compared to H4, the H5 UART transport reduces the number of signal lines required by eliminating the CTS and RTS signals.
The CYW4343W UART can perform XON/XOFF flow control and includes hardware support for the Serial Line Input Protocol (SLIP).
It can also perform a wake-on activity function. For example, activity on the RX or CTS inputs can wake the chip from a sleep state.
Normally, the UART baud rate is set by a configuration record downloaded after device reset or by automatic baud rate detection, and
the host does not need to adjust the baud rate. Support for changing the baud rate during normal HCI UART operation is included
through a vendor-specific command that allows the host to adjust the contents of the baud rate registers. The CYW4343W UARTs
operate correctly with the host UART as long as the combined baud rate error of the two devices is within ±2% (see Table 11).
Table 11. Example of Common Baud Rates
Desired Rate
4000000
3692000
3000000
2000000
1500000
1444444
921600
460800
230400
115200
57600
Actual Rate
4000000
3692308
3000000
2000000
1500000
1454544
923077
461538
230796
115385
57692
Error (%)
0.00
0.01
0.00
0.00
0.00
0.70
0.16
0.16
0.17
0.16
0.16
0.00
0.16
0.00
0.16
0.00
38400
38400
28800
28846
19200
19200
14400
14423
9600
9600
UART timing is defined in Figure 19 and Table 12.
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Figure 19. UART Timing
UART_CTS_N
UART_TXD
1
2
Midpoint of STOP bit
Midpoint of STOP bit
UART_RXD
3
UART_RTS_N
Table 12. UART Timing Specifications
Ref No. Characteristics
Minimum
Typical
Maximum
Unit
1
Delay time, UART_CTS_N low to UART_TXD valid
–
–
–
–
1.5
Bit periods
Setup time, UART_CTS_N high before midpoint
of stop bit
2
3
–
–
0.5
0.5
Bit periods
Bit periods
Delay time, midpoint of stop bit to UART_RTS_N high
2
10.3 I S Interface
The CYW4343W supports an independent I2S digital audio port for high-fidelity Bluetooth audio. The I2S interface supports both
master and slave modes. The I2S signals are:
■ I2S Clock: I2S SCK
■ I2S Word Select: I2S WS
■ I2S Data Out: I2S SDO
■ I2S Data In: I2S SDI
I2S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S SDO is always an output. The channel
word length is 16 bits and the data is justified so that the MSB of the left-channel data is aligned with the MSB of the I2S bus, per the
I2S specification. The MSB of each data word is transmitted one bit-clock cycle after the I2S WS transition, synchronous with the falling
edge of the bit clock. Left-channel data is transmitted when I2S WS is low, and right-channel data is transmitted when I2S WS is high.
Data bits sent by the CYW4343W are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on the
rising edge of I2S_SSCK.
The clock rate in master mode is either of the following:
48 kHz x 32 bits per frame = 1.536 MHz
48 kHz x 50 bits per frame = 2.400 MHz
The master clock is generated from the input reference clock using an N/M clock divider.
In slave mode, clock rates up to 3.072 MHz are supported.
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10.3.1 I2S Timing
Note: Timing values specified in Table 13 are relative to high and low threshold levels
Table 13. Timing for I2S Transmitters and Receivers
Transmitter
Receiver
Lower Limit Upper Limit
Min. Max.
Lower LImit
Min. Max.
Upper Limit
Min. Max.
Notes
Min.
Max.
T
–
–
–
T
–
–
–
1
Clock period T
tr
r
Master mode: Clock generated by transmitter or receiver.
0.35T
0.35T
–
–
–
–
–
–
0.35T
0.35T
–
–
–
–
–
–
2
2
High tHC
Low tLC
tr
tr
tr
tr
Slave mode: Clock accepted by transmitter or receiver.
–
–
–
0.35T
0.35T
–
–
–
–
–
–
–
–
–
0.35T
0.35T
–
–
–
–
–
–
–
3
3
4
High tHC
tr
tr
tr
Low tLC
tr
0.15T
Rise time tRC
tr
Transmitter
Delay tdtr
–
0
–
–
–
–
0.8T
–
–
–
–
–
–
–
–
5
4
Hold time thtr
–
Receiver
–
–
–
–
–
–
–
–
–
–
0.2T
–
–
–
–
6
6
Setup time tsr
Hold time thr
r
0
Note:
■ The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be able to handle the
data transfer rate.
■ At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason,
tHC and tLC are specified with respect to T.
■ In slave mode, the transmitter and receiver need a clock signal with minimum high and low periods so that they can detect the signal.
As long as the minimum periods are greater than 0.35Tr, any clock that meets the requirements can be used.
■ Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock
edge can result in tdtr not exceeding tRC, which means thtr becomes zero or negative. Therefore, the transmitter has to guarantee
that thtr is greater than or equal to zero, as long as the clock rise-time, tRC, does not exceed tRCmax, where tRCmax is not less than
0.15Ttr.
■ To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T,
always giving the receiver sufficient setup time.
The data setup and hold time must not be less than the specified receiver setup and hold time.
Note: The time periods specified in Figure 20 and Figure 21 are defined by the transmitter speed. The receiver specifications must
match transmitter performance.
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Figure 20. I2S Transmitter Timing
T
tRC*
tLC > 0.35T
tHC > 0.35T
VH = 2.0V
VL = 0.8V
SCK
thtr > 0
tdtr < 0.8T
SD and WS
T = Clock period
Ttr = Minimum allowed clock period for transmitter
T = Ttr
* tRC is only relevant for transmitters in slave mode.
Figure 21. I2S Receiver Timing
T
tLC > 0.35T
tHC > 0.35
VH = 2.0V
VL = 0.8V
SCK
tsr > 0.2T
thr > 0
SD and WS
T = Clock period
Tr = Minimum allowed clock period for transmitter
T > Tr
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11. CPU and Global Functions
11.1 WLAN CPU and Memory Subsystem
The CYW4343W includes an integrated ARM Cortex-M3 processor with internal RAM and ROM. The ARM Cortex-M3 processor is
a low-power processor that features low gate count, low interrupt latency, and low-cost debugging. It is intended for deeply embedded
applications that require fast interrupt response features. The processor implements the ARM architecture v7-M with support for the
Thumb-2 instruction set. ARM Cortex-M3 provides a 30% performance gain over ARM7TDMI.
At 0.19 µW/MHz, the Cortex-M3 is the most power efficient general purpose microprocessor available, outperforming 8- and 16-bit
devices on MIPS/µW. It supports integrated sleep modes.
ARM Cortex-M3 uses multiple technologies to reduce cost through improved memory utilization, reduced pin overhead, and reduced
silicon area. ARM Cortex-M3 supports independent buses for code and data access (ICode/DCode and system buses). ARM Cortex-
M3 supports extensive debug features including real-time tracing of program execution.
On-chip memory for the CPU includes 512 KB SRAM and 640 KB ROM.
11.2 One-Time Programmable Memory
Various hardware configuration parameters may be stored in an internal 4096-bit One-Time Programmable (OTP) memory, which is
read by system software after a device reset. In addition, customer-specific parameters, including the system vendor ID and the MAC
address, can be stored, depending on the specific board design.
The initial state of all bits in an unprogrammed OTP device is 0. After any bit is programmed to a 1, it cannot be reprogrammed to 0.
The entire OTP array can be programmed in a single write cycle using a utility provided with the Broadcom WLAN manufacturing test
tools. Alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0 state
can be altered during each programming cycle.
Prior to OTP memory programming, all values should be verified using the appropriate editable nvram.txt file, which is provided with
the reference board design package. Documentation on the OTP development process is available on the Broadcom customer
support portal (http://www.broadcom.com/support).
11.3 GPIO Interface
Five general purpose I/O (GPIO) pins are available on the CYW4343W that can be used to connect to various external devices.
GPIOs are tristated by default. Subsequently, they can be programmed to be either input or output pins via the GPIO control register.
They can also be programmed to have internal pull-up or pull-down resistors.
GPIO_0 is normally used as a WL_HOST_WAKE signal.
The CYW4343W supports 2-wire, 3-wire, and 4-wire coexistence configurations using GPIO_1 through GPIO_4. The signal functions
of GPIO_1 through GPIO_4 are programmable to support the three coexistence configurations.
11.4 External Coexistence Interface
The CYW4343W supports 2-wire, 3-wire, and 4-wire coexistence interfaces to enable signaling between the device and an external
colocated wireless device in order to manage wireless medium sharing for optimal performance. The external colocated device can
be any of the following ICs: GPS, WiMAX, LTE, or UWB. An LTE IC is used in this section for illustration.
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11.4.1 2-Wire Coexistence
Figure 22 shows a 2-wire LTE coexistence example. The following definitions apply to the GPIOs in the figure:
■ GPIO_1: WLAN_SECI_TX output to an LTE IC.
■ GPIO_2: WLAN_SECI_RX input from an LTE IC.
Figure 22. 2-Wire Coexistence Interface to an LTE IC
GPIO_1
GPIO_2
WLAN_SECI_TX
WLAN_SECI_RX
UART_IN
WLAN
UART_OUT
Coexistence
Interface
BT
CYW4343W
LTE/IC
Notes:
OR’ing to generate ISM_RX_PRIORITY for ERCX_TXCONF or BT_RX_PRIORITY is achieved by
setting the GPIO mask registers appropriately.
WLAN_SECI_OUT and WLAN_SECI_IN are multiplexed on the GPIOs.
See Figure 19 and Table 12: “UART Timing Specifications” for UART timing.
11.4.2 3-Wire and 4-Wire Coexistence Interfaces
Figure 23 and Figure 24 show 3-wire and 4-wire LTE coexistence examples, respectively. The following definitions apply to the GPIOs
in the figures:
■ For the 3-wire coexistence interface:
■ GPIO_2: WLAN priority output to an LTE IC.
■ GPIO_3: LTE_RX input from an LTE IC.
■ GPIO_4: LTE_TX input from an LTE IC.
For the 4-wire coexistence interface:
■ GPIO_1: WLAN priority output to an LTE IC.
■ GPIO_2: LTE frame sync input from an LTE IC. This GPIO applies only to the 4-wire coexistence interface.
■ GPIO_3: LTE_RX input from an LTE IC.
■ GPIO_4: LTE_TX input from an LTE IC.
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Figure 23. 3-Wire Coexistence Interface to an LTE IC
GPIO_2
W LAN
W LAN Priority
GPIO_3
Coexistence
Interface
LTE_RX
LTE_TX
GPIO_4
BT
CYW4343W
LTE/IC
Note: OR’ing to generate W CN_PRIORITY for ERCX_TXCONF or BT_RX_PRIORITY is achieved by
setting the GPIO mask registers appropriately.
Figure 24. 4-Wire Coexistence Interface to an LTE IC
GPIO_1
WLAN Priority
WLAN
GPIO_2
LTE_Frame_Sync
Coexistence
GPIO_3
Interface
LTE_RX
LTE_TX
GPIO_4
BT
CYW4343W
LTE/IC
Note: OR’ing to generate WCN_PRIORITY for ERCX_TXCONF or BT_RX_PRIORITY is achieved by
setting the GPIO mask registers appropriately.
11.5 JTAG Interface
The CYW4343W supports the IEEE 1149.1 JTAG boundary scan standard over SDIO for performing device package and PCB
assembly testing during manufacturing. In addition, the JTAG interface allows Cypress to assist customers by using proprietary debug
and characterization test tools during board bring-up. Therefore, it is highly recommended to provide access to the JTAG pins by
means of test points or a header on all PCB designs.
11.6 UART Interface
One UART interface can be enabled by software as an alternate function on the JTAG pins. UART_RX is available on the JTAG_TDI
pin, and UART_TX is available on the JTAG_TDO pin.
The UART is primarily for debugging during development. By adding an external RS-232 transceiver, this UART enables the
CYW4343W to operate as RS-232 data termination equipment (DTE) for exchanging and managing data with other serial devices. It
is compatible with the industry standard 16550 UART, and it provides a FIFO size of 64 × 8 in each direction.
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12. WLAN Software Architecture
12.1 Host Software Architecture
The host driver (DHD) provides a transparent connection between the host operating system and the CYW4343W media (for example,
WLAN) by presenting a network driver interface to the host operating system and communicating with the CYW4343W over a SDIO
interface-specific bus to:
■ Forward transmit and receive frames between the host network stack and the CYW4343W device.
■ Pass control requests from the host to the CYW4343W device, returning the CYW4343W device responses.
The driver communicates with the CYW4343W over the bus using a control channel and a data channel to pass control messages
and data messages. The actual message format is based on the BDC protocol.
12.2 Device Software Architecture
The wireless device, protocol, and bus drivers are run on the embedded ARM processor using a Cypress defined operating system
called HNDRTE, which transfers data over a propriety Cypress format over the SDIO interface between the host and device (BDC/
LMAC). The data portion of the format consists of IEEE 802.11 frames wrapped in a Cypress encapsulation. The host architecture
provides all missing functionality between a network device and the Cypress device interface. The host can also be customized to
provide functionality between the Cypress device interface and a full network device interface.
This transfer requires a message-oriented (framed) interconnect between the host and device. The SDIO bus is an addressed bus—
each host-initiated bus operation contains an explicit device target address—and does not natively support a higher-level data frame
concept. Broadcom has implemented a hardware/software message encapsulation scheme that ignores the bus operation code
address and prefixes each frame with a 4-byte length tag for framing. The device presents a packet-level interface over which data,
control, and asynchronous event (from the device) packets are supported.
The data and control packets received from the bus are initially processed by the bus driver and then passed on to the protocol driver.
If the packets are data packets, they are transferred to the wireless device driver (and out through its medium), and a data packet
received from the device medium follows the same path in the reverse direction. If the packets are control packets, the protocol header
is decoded by the protocol driver. If the packets are wireless IOCTL packets, the IOCTLAPI of the wireless driver is called to configure
the wireless device. The microcode running in the D11 core processes all time-critical tasks.
12.3 Remote Downloader
When the CYW4343W powers up, the DHD initializes and downloads the firmware to run in the device.
Figure 25. WLAN Software Architecture
DHD Host Driver
SPI
BDC/LMAC Protocol
Wireless Device Driver
D11 Core
12.4 Wireless Configuration Utility
The device driver that supports the Cypress IEEE 802.11 family of wireless solutions provides an input/output control (IOCTL) interface
for making advanced configuration settings. The IOCTL interface makes it possible to make settings that are normally not possible
when using just the native operating system-specific IEEE 802.11 configuration mechanisms. The utility uses IOCTLs to query or set
a number of different driver/chip operating properties.
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13. Pinout and Signal Descriptions
13.1 Ball Map
Figure 26 shows the 74-ball WLBGA ball map. Figure 27 shows the 153-bump WLCSP.
Figure 26. 74-Ball WLBGA Ball Map (Bottom View)
A
B
C
D
E
F
G
H
J
K
L
M
BT_UART_ BT_DEV_ BT_HOST_
BT_VCO_V
DD
WLRF_2G_ WLRF_2G_
WLRF_PA_
VDD
FM_RF_IN
BT_IF_VDD BT_PAVDD
1
2
3
4
5
6
7
1
2
3
4
5
6
7
RXD
WAKE
WAKE
eLG
RF
WLRF_GE
NERAL_GN
D
WLRF_VD
D_
1P35
BT_UART_ BT_UART_
FM_RF_VD BTFM_PLL BTFM_PLL
WLRF_LNA
_GND
WLRF_PA_
GND
FM_OUT1 FM_OUT2
BT_IF_VSS
TXD
CTS_N
D
_VDD
_VSS
WLRF_XTA
L_
VDD1P2
BT_I2S_
WS
BT_UART_
VDDC
FM_RF_VS
S
BT_VCO_V WLRF_GPI
WLRF_VC
O_GND
BT_I2S_DO
RTS_N
SS
O
BT_I2S_CL BT_PCM_O BT_PCM_I
UT
WLRF_AFE
_GND
WLRF_XTA WLRF_XTA
VSSC
BT_GPIO_3
VDDC
GPIO_3
GPIO_4
K
N
L_GND
L_XOP
BT_PCM_C BT_PCM_S SYS_VDDI
WLRF_XTA
L_XON
WPT_1P8 WPT_3P3
LPO_IN BT_GPIO_4 BT_GPIO_5
VSSC
GPIO_2
LK
YNC
O
PMU_AVS VOUT_CLD VOUT_LNL BT_REG_O WCC_VDDI WL_REG_
SDIO_DAT
A_0
SR_VLX
GPIO_1
GPIO_0
SDIO_CMD CLK_REQ
S
O
DO
N
O
ON
SR_VDDB LDO_VDD1
LDO_VDD
BAT5V
SDIO_DAT SDIO_DAT
SDIO_DAT
SDIO_CLK
A_2
SR_PVSS
VOUT_3P3
AT5V
P5
A_1
A_3
A
B
C
D
E
F
G
H
J
K
L
M
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Figure 27. 153-Bump WLCSP (Top View)
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13.2 WLBGA Ball List in Ball Number Order with X-Y Coordinates
Table 14 provides ball numbers and names in ball number order. The table includes the X and Y coordinates for a top view with a (0,0)
center.
Table 14. CYW4343W WLBGA Ball List — Ordered By Ball Number
Ball Number
A1
Ball Name
BT_UART_RXD
X Coordinate
–1200.006
–799.992
–399.996
0
Y Coordinate
2199.996
2199.996
2199.996
2199.996
2199.996
2199.978
2199.978
1800
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
B6
B7
C1
C2
C3
C4
C5
C6
C7
D2
D3
D4
D5
D6
E1
E2
E3
E5
E6
E7
F1
F2
F4
F5
BT_UART_TXD
BT_I2S_WS or BT_PCM_SYNC
BT_I2S_CLK or BT_PCM_CLK
BT_PCM_CLK or BT_I2S_CLK
SR_VLX
399.996
799.992
1199.988
–1200.006
–799.992
–399.996
0
SR_PVSS
BT_DEV_WAKE
BT_UART_CTS_N
BT_I2S_DO or BT_PCM_OUT
BT_PCM_OUT or BT_I2S_DO
BT_PCM_SYNC or BT_I2S_WS
PMU_AVSS
1800
1800
1800
399.996
799.992
1199.988
–1200.006
–799.992
–399.996
0
1800
1799.982
1799.982
1399.995
1399.986
1399.995
1399.995
1399.986
1399.986
1399.986
999.99
SR_VBAT5V
BT_HOST_WAKE
FM_OUT1
BT_UART_RTS_N
BT_PCM_IN or BT_I2S_DI
SYS_VDDIO
399.996
799.992
1199.988
–799.992
–399.996
0
VOUT_CLDO
LDO_VDD15V
FM_OUT2
VDDC
999.999
999.999
999.99
VSSC
WPT_1P8
399.996
799.992
–1199.988
–799.992
–399.996
399.996
799.992
1199.988
–1199.988
–799.992
0
VOUT_LNLDO
FM_RF_IN
999.99
599.994
599.994
599.994
599.994
599.994
599.994
199.998
199.998
199.998
199.998
FM_RF_VDD
FM_RF_VSS
WPT_3P3
BT_REG_ON
VOUT_3P3
BT_VCO_VDD
BTFM_PLL_VDD
BT_GPIO_3
LPO_IN
399.996
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CYW4343W
Table 14. CYW4343W WLBGA Ball List — Ordered By Ball Number (Cont.)
Ball Number
F6
Ball Name
X Coordinate
800.001
1199.988
–1199.988
–799.992
0
Y Coordinate
WCC_VDDIO
LDO_VBAT5V
BT_IF_VDD
199.998
199.998
F7
G1
G2
G4
G5
G6
H1
H2
H3
H4
H5
H6
H7
J1
–199.998
–199.998
–199.998
–199.998
–199.998
–599.994
–599.994
–599.994
–599.994
–599.994
–599.994
–599.994
–999.99
BTFM_PLL_VSS
VDDC
BT_GPIO_4
399.996
800.001
–1199.988
–799.992
–399.996
0
WL_REG_ON
BT_PAVDD
BT_IF_VSS
BT_VCO_VSS
WLRF_AFE_GND
BT_GPIO_5
399.996
800.001
1200.006
–1199.988
–799.992
–399.996
399.996
800.001
1200.006
–1199.988
–799.992
0
GPIO_1
SDIO_DATA_1
WLRF_2G_eLG
WLRF_LNA_GND
WLRF_GPIO
VSSC
J2
–999.99
J3
–999.99
J5
–999.999
–999.999
–999.999
–1399.986
–1399.986
–1399.995
–1399.995
–1399.995
–1799.982
–1799.982
–1799.982
–1799.991
–1799.991
–1799.991
–2199.978
–2199.978
–2199.978
–2199.978
–2199.978
–2199.996
J6
GPIO_0
J7
SDIO_DATA_3
WLRF_2G_RF
WLRF_GENERAL_GND
GPIO_3
K1
K2
K4
K5
K6
L2
GPIO_4
399.996
800.001
–799.992
–399.996
0
SDIO_DATA_0
WLRF_PA_GND
WLRF_VCO_GND
WLRF_XTAL_GND
GPIO_2
L3
L4
L5
399.996
800.001
1200.006
–1199.988
–799.992
–399.996
0
L6
SDIO_CMD
L7
SDIO_DATA_2
WLRF_PA_VDD
WLRF_VDD_1P35
WLRF_XTAL_VDD1P2
WLRF_XTAL_XOP
WLRF_XTAL_XON
CLK_REQ
M1
M2
M3
M4
M5
M6
M7
399.996
800.001
SDIO_CLK
1200.006
–2199.996
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CYW4343W
13.3 WLCSP Bump List in Bump Order with X-Y Coordinates
Table 15. CYW4343W WLCSP Bump List — Ordered By Bump Number
Bump View
(0,0 Center of Die)
Top View
(0,0 Center of Die)
Bump
Bump Name
BT_UART_RXD
Number
X Coordinate
Y Coordinate
2133.594
2195.919
2275.020
2275.020
2133.594
2133.594
1992.168
1992.168
1992.168
1992.168
1850.742
1850.742
1850.742
1850.742
1850.742
1717.578
1709.316
1709.316
1709.316
1567.890
1567.890
1567.890
1426.464
1426.464
1285.038
1189.863
860.760
X Coordinate
Y Coordinate
2133.594
2195.919
2275.020
2275.020
2133.594
2133.594
1992.168
1992.168
1992.168
1992.168
1850.742
1850.742
1850.742
1850.742
1850.742
1717.578
1709.316
1709.316
1709.316
1567.890
1567.890
1567.890
1426.464
1426.464
1285.038
1189.863
860.760
1
1228.248
944.082
238.266
–327.438
662.544
379.692
1086.822
521.118
–44.586
–327.438
1228.248
945.396
662.544
379.692
–186.012
516.501
1086.822
238.266
–327.438
662.544
96.840
–1228.248
–944.082
–238.266
327.438
2
BT_VDDC_ISO_2
BT_PCM_CLK or BT_I2S_CLK
BT_TM1
3
4
5
BT_GPIO_3
–662.544
–379.692
–1086.822
–521.118
44.586
6
BT_DEV_WAKE
BT_UART_RTS_N
BT_GPIO_4
7
8
9
BT_VDDC_ISO_1
BT_GPIO_5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
327.438
BT_HOST_WAKE
BT_UART_TXD
BT_GPIO_2
–1228.248
–945.396
–662.544
–379.692
186.012
BT_VDDC
BT_I2S_CLK or BT_PCM_CLK
BT_VDDC
–516.501
–1086.822
–238.266
327.438
BT_PCM_SYNC or BT_I2S_WS
BT_I2S_WS or BT_PCM_SYNC
BT_PCM_OUT or BT_I2S_DO
BT_PCM_IN or BT_I2S_DI
VSSC
–662.544
–96.840
BT_UART_CTS_N
BT_I2S_DI or BT_PCM_IN
BT_I2S_DO or BT_PCM_OUT
VSSC
–186.012
238.266
–327.438
96.840
186.012
–238.266
327.438
–96.840
BT_VDDC
518.391
238.266
–44.586
110.286
–327.438
521.118
238.266
–44.586
229.986
1185.471
–875.142
–518.391
–238.266
44.586
VSSC
BT_VDDC
719.334
719.334
VSSC
561.303
–110.286
327.438
561.303
VSSC
436.482
436.482
BT_VDDC
436.473
–521.118
–238.266
44.586
436.473
VSSC
153.630
153.630
VSSC
153.630
153.630
BT_VDDC
–185.976
–455.270
–836.352
–229.986
–1185.471
875.142
–185.976
–455.270
–836.352
BT_PAVSS
VSSC
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CYW4343W
Table 15. CYW4343W WLCSP Bump List — Ordered By Bump Number (Cont.)
Bump View
Top View
(0,0 Center of Die)
Bump
(0,0 Center of Die)
Bump Name
Number
X Coordinate
Y Coordinate
1443.096
1443.096
1275.098
1243.098
1243.098
1043.100
960.593
X Coordinate
Y Coordinate
1443.096
1443.096
1275.098
1243.098
1243.098
1043.100
960.593
37
FM_DAC_VOUT1
1243.031
1043.033
820.485
1243.031
1043.033
1252.220
820.485
1120.383
1274.787
1172.988
972.990
772.304
1276.551
686.628
886.626
1185.471
1185.462
781.893
781.893
429.885
1185.471
786.393
429.885
583.250
1262.642
1082.642
1206.990
628.713
986.531
451.188
799.992
612.878
986.531
1249.686
1069.686
274.613
75.519
–1243.031
–1043.033
–820.485
–1243.031
–1043.033
–1252.220
–820.485
–1120.383
–1274.787
–1172.988
–972.990
–772.304
–1276.551
–686.628
–886.626
–1185.471
–1185.462
–781.893
–781.893
–429.885
–1185.471
–786.393
–429.885
–583.250
–1262.642
–1082.642
–1206.990
–628.713
–986.531
–451.188
–799.992
–612.878
–986.531
–1249.686
–1069.686
–274.613
–75.519
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
FM_DAC_AVSS
FM_PLLAVSS
FM_DAC_VOUT2
FM_DAC_AVDD
FM_VCOVSS
FM_PLLDVDD1P2
FM_VCOVDD1P2
FM_RFVDD1P2
FM_RFVSS
892.373
892.373
764.213
764.213
563.990
563.990
FM_IFVSS
563.990
563.990
FM_IFDVDD1P2
FM_RFINMAIN
BT_DVSS
563.990
563.990
383.225
383.225
160.911
160.911
BT_IFVDD1P2
148.775
148.775
BT_AGPIO
–55.274
–55.274
BT_PAVDD2P5
BT_LNAVDD1P2
BT_LNAVSS
–255.272
–263.768
–463.766
–499.995
–655.268
–663.764
–699.993
–999.990
–1006.290
–1006.290
–1458.198
–1590.210
–1649.615
–1682.370
–1729.224
–1800.135
–1829.615
–2016.945
–2016.945
–2086.677
–2106.621
–2298.978
–255.272
–263.768
–463.766
–499.995
–655.268
–663.764
–699.993
–999.990
–1006.290
–1006.290
–1458.198
–1590.210
–1649.615
–1682.370
–1729.224
–1800.135
–1829.615
–2016.945
–2016.945
–2086.677
–2106.621
–2298.978
BT_PLLVSS
BT_VCOVDD1P2
BT_VCOVSS
BT_PLLVDD1P2
WRF_AFE_GND
WRF_RFIN_ELG_2G
WRF_RX2G_GND
WRF_RFIO_2G
WRF_GENERAL_GND
WRF_PA_GND3P3
WRF_VCO_GND
WRF_GPAIO_OUT
WRF_PMU_VDD1P35
WRF_PA_GND3P3
WRF_PA_VDD3P3
WRF_PA_VDD3P3
WRF_XTAL_GND1P2
WRF_XTAL_VDD1P2
WRF_XTAL_XOP
311.126
–311.126
Document No. 002-14797 Rev. *I
Page 50 of 103
CYW4343W
Table 15. CYW4343W WLCSP Bump List — Ordered By Bump Number (Cont.)
Bump View
Top View
(0,0 Center of Die)
Bump
(0,0 Center of Die)
Bump Name
Number
X Coordinate
Y Coordinate
–2298.978
2133.594
2133.594
1850.742
1002.186
436.482
X Coordinate
Y Coordinate
–2298.978
2133.594
2133.594
1850.742
1002.186
436.482
75
WRF_XTAL_XON
131.126
96.840
–131.126
–96.840
186.012
–96.813
44.586
76
LPO_IN
77
WCC_VDDIO
VSSC
–186.012
96.813
78
79
WCC_VDDIO
GPIO_12
GPIO_11
GPIO_9
–44.586
80
–1299.420
–1157.994
–1016.568
–1299.420
–1157.994
–186.012
–468.864
–1299.420
–610.290
–1157.994
–44.586
1299.420
1157.994
1016.568
1299.420
1157.994
186.012
468.864
1299.420
610.290
1157.994
44.586
81
295.056
295.056
82
153.630
153.630
83
GPIO_10
GPIO_8
153.630
153.630
84
12.204
12.204
85
VSSC
–129.222
–129.222
–129.222
–270.648
–270.648
–412.074
–412.074
–553.500
–553.500
–553.500
–694.926
–694.926
–694.926
–836.352
–977.778
–977.778
–1119.204
–1120.266
–1260.630
–1260.630
–1268.568
–1402.056
–1543.482
–1543.482
–1551.420
–1551.420
–1682.775
–1684.908
–129.222
–129.222
–129.222
–270.648
–270.648
–412.074
–412.074
–553.500
–553.500
–553.500
–694.926
–694.926
–694.926
–836.352
–977.778
–977.778
–1119.204
–1120.266
–1260.630
–1260.630
–1268.568
–1402.056
–1543.482
–1543.482
–1551.420
–1551.420
–1682.775
–1684.908
86
VDDC
87
GPIO_7
88
VSSC
89
GPIO_6
90
VSSC
91
GPIO_4
–1299.420
96.840
1299.420
–96.840
186.012
1157.994
44.586
92
VSSC
93
VDDC
–186.012
–1157.994
–44.586
94
GPIO_5
95
VDDC
96
WL_VDDP_ISO
GPIO_2
–733.716
–1299.420
–1157.994
–1016.568
–1299.420
–1157.994
–720.954
–1016.568
–1299.420
–137.700
–841.113
–1016.568
–1299.420
109.152
733.716
1299.420
1157.994
1016.568
1299.420
1157.994
720.954
1016.568
1299.420
137.700
841.113
1016.568
1299.420
–109.152
173.700
843.237
1157.994
97
98
GPIO_3
99
WCC_VDDIO
GPIO_0
100
101
102
103
104
105
106
107
108
109
110
111
112
GPIO_1
VSSC
WCC_VDDIO
SDIO_CMD
GPIO_14
VSSC
VDDC
SDIO_CLK
GPIO_15
PACKAGEOPTION_0
VSSC
–173.700
–843.237
–1157.994
SDIO_DATA_0
Document No. 002-14797 Rev. *I
Page 51 of 103
CYW4343W
Table 15. CYW4343W WLCSP Bump List — Ordered By Bump Number (Cont.)
Bump View
Top View
(0,0 Center of Die)
Bump
(0,0 Center of Die)
Bump Name
Number
X Coordinate
Y Coordinate
–1692.846
–1826.334
–1826.334
–1834.272
–1834.272
–1967.760
–2056.131
–2109.186
–2109.186
–2250.612
2274.984
2274.984
2133.563
2133.563
2133.563
1992.141
1992.141
1992.141
1850.720
1850.720
1709.298
1567.877
1567.877
1426.455
1285.034
1285.034
1285.034
1143.612
1143.612
1002.191
1002.191
1002.191
860.769
X Coordinate
Y Coordinate
–1692.846
–1826.334
–1826.334
–1834.272
–1834.272
–1967.760
–2056.131
–2109.186
–2109.186
–2250.612
2274.984
2274.984
2133.563
2133.563
2133.563
1992.141
1992.141
1992.141
1850.720
1850.720
1709.298
1567.877
1567.877
1426.455
1285.034
1285.034
1285.034
1143.612
1143.612
1002.191
1002.191
1002.191
860.769
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
PACKAGEOPTION_1
–32.274
–1016.568
–1299.420
109.152
32.274
1016.568
1299.420
–109.152
173.700
1157.994
232.227
1016.568
1299.420
1157.994
739.130
1021.973
597.708
880.551
1163.394
739.130
1021.973
1304.816
597.708
880.551
1021.973
880.551
1163.394
739.130
597.708
880.551
1163.394
739.130
1304.816
597.708
880.551
1163.394
739.130
1021.973
1304.816
597.708
880.551
875.142
VDDC
SDIO_DATA_1
PACKAGEOPTION_2
JTAG_SEL
–173.700
–1157.994
–232.227
–1016.568
–1299.420
–1157.994
–739.130
–1021.973
–597.708
–880.551
–1163.394
–739.130
–1021.973
–1304.816
–597.708
–880.551
–1021.973
–880.551
–1163.394
–739.130
–597.708
–880.551
–1163.394
–739.130
–1304.816
–597.708
–880.551
–1163.394
–739.130
–1021.973
–1304.816
–597.708
–880.551
–875.142
SDIO_DATA_2
GPIO_13
WCC_VDDIO
VSSC
SDIO_DATA_3
SR_PVSS
SR_PVSS
VSSC
SR_VLX
SR_VLX
SR_VLX
SR_VDDBAT5V
SR_VDDBAT5V
PMU_AVSS
SR_VDDBAT5V
LDO_VDD1P5
VOUT_CLDO
LDO_VDD1P5
VOUT_CLDO
WCC_VDDIO
VOUT_LNLDO
VOUT_3P3
SYS_VDDIO
LDO_VDDBAT5V
VSSC
VOUT_3P3_SENSE
VOUT_3P3
WPT_1P8
WPT_3P3
860.769
860.769
LDO_VDDBAT5V
WL_REG_ON
BT_REG_ON
WL_VDDM_ISO
860.769
860.769
719.348
719.348
719.348
719.348
12.204
12.204
Document No. 002-14797 Rev. *I
Page 52 of 103
CYW4343W
Table 15. CYW4343W WLCSP Bump List — Ordered By Bump Number (Cont.)
Bump View
Top View
(0,0 Center of Die)
Bump
(0,0 Center of Die)
Bump Name
Number
X Coordinate
Y Coordinate
–985.716
X Coordinate
Y Coordinate
-985.716
151
152
153
PLL_VSSC
PLL_VDDC
CLK_REQ
–116.586
29.286
116.586
–29.286
–238.266
–1130.076
1992.168
–1130.076
1992.168
238.266
Document No. 002-14797 Rev. *I
Page 53 of 103
CYW4343W
13.4 WLBGA Ball List Ordered By Ball Name
Table 16 provides the ball numbers and names in ball name order.
Table 16. CYW4343W WLBGA Ball List — Ordered By Ball Name
Ball Name
Ball Number
Ball Name
BT_DEV_WAKE
Ball Number
LPO_IN
F5
B1
F4
G5
H5
C1
A4
B3
A3
G1
H2
H1
A5
C4
B4
B5
E6
B2
C3
A1
A2
F1
H3
F2
G2
M6
C2
D2
E1
E2
E3
J6
PMU_AVSS
SDIO_CLK
SDIO_CMD
B6
M7
L6
BT_GPIO_3
BT_GPIO_4
BT_GPIO_5
SDIO_DATA_0
SDIO_DATA_1
SDIO_DATA_2
SDIO_DATA_3
SR_PVSS
K6
H7
L7
BT_HOST_WAKE
BT_I2S_CLK or BT_PCM_CLK
BT_I2S_DO or BT_PCM_OUT
BT_I2S_WS or BT_PCM_SYNC
BT_IF_VDD
J7
A7
B7
A6
C5
D3
G4
E7
C6
D6
D4
J5
SR_VDDBAT5V
SR_VLX
BT_IF_VSS
BT_PAVDD
SYS_VDDIO
BT_PCM_CLK or BT_I2S_CLK
BT_PCM_IN or BT_I2S_DI
BT_PCM_OUT or BT_I2S_DO
BT_PCM_SYNC or BT_I2S_WS
BT_REG_ON
VDDC
VDDC
VOUT_3P3
VOUT_CLDO
VOUT_LNLDO
VSSC
BT_UART_CTS_N
BT_UART_RTS_N
BT_UART_RXD
BT_UART_TXD
BT_VCO_VDD
VSSC
WCC_VDDIO
WL_REG_ON
WLRF_2G_eLG
WLRF_2G_RF
WLRF_AFE_GND
WLRF_GENERAL_GND
WLRF_GPIO
WLRF_LNA_GND
WLRF_PA_GND
WLRF_PA_VDD
WLRF_VCO_GND
WLRF_VDD_1P35
WLRF_XTAL_GND
WLRF_XTAL_VDD1P2
WLRF_XTAL_XON
WLRF_XTAL_XOP
WPT_1P8
F6
G6
J1
BT_VCO_VSS
K1
H4
K2
J3
BTFM_PLL_VDD
BTFM_PLL_VSS
CLK_REQ
FM_OUT1
J2
FM_OUT2
L2
FM_RF_IN
M1
L3
FM_RF_VDD
FM_RF_VSS
M2
L4
GPIO_0
GPIO_1
H6
L5
M3
M5
M4
D5
E5
GPIO_2
GPIO_3
K4
K5
C7
F7
GPIO_4
LDO_VDD1P5
WPT_3P3
LDO_VDDBAT5V
Document No. 002-14797 Rev. *I
Page 54 of 103
CYW4343W
13.5 WLCSP Bump List Ordered By Name
Table 17 provides the bump numbers and names in bump name order.
Table 17. CYW4343W WLCSP Bump List — Ordered By Bump Name
Bump Name
FM_IFDVDD1P2
Bump Number(s)
Bump Name
Bump Number(s)
52
48
BT_AGPIO
FM_IFVSS
47
BT_DEV_WAKE
BT_DVSS
6
FM_PLLAVSS
FM_PLLDVDD1P2
FM_RFINMAIN
FM_RFVDD1P2
FM_RFVSS
FM_VCOVDD1P2
FM_VCOVSS
GPIO_0
39
50
43
BT_GPIO_2
13
49
BT_GPIO_3
5
45
BT_GPIO_4
8
46
BT_GPIO_5
10
44
BT_HOST_WAKE
BT_I2S_CLK or BT_PCM_CLK
BT_I2S_DI or BT_PCM_IN
BT_I2S_DO or BT_PCM_OUT
BT_I2S_WS or BT_PCM_SYNC
BT_IFVDD1P2
11
42
15
100
101
97
23
GPIO_1
24
GPIO_2
18
GPIO_3
98
51
GPIO_4
91
BT_LNAVDD1P2
BT_LNAVSS
54
GPIO_5
94
55
GPIO_6
89
BT_PAVDD2P5
53
GPIO_7
87
BT_PAVSS
35
GPIO_8
84
BT_PCM_CLK or BT_I2S_CLK
BT_PCM_IN or BT_I2S_DI
BT_PCM_OUT or BT_I2S_DO
BT_PCM_SYNC or BT_I2S_WS
BT_PLLVDD1P2
BT_PLLVSS
3
GPIO_9
82
20
GPIO_10
83
19
GPIO_11
81
17
GPIO_12
80
59
GPIO_13
119
105
109
117
133, 135
141, 147
76
56
GPIO_14
BT_REG_ON
149
GPIO_15
BT_TM1
4
JTAG_SEL
LDO_VDD1P5
LDO_VDDBAT5V
LPO_IN
BT_UART_CTS_N
BT_UART_RTS_N
BT_UART_RXD
22
7
1
BT_UART_TXD
12
PACKAGEOPTION_0
PACKAGEOPTION_1
PACKAGEOPTION_2
PLL_VDDC
PLL_VSSC
PMU_AVSS
SDIO_CLK
SDIO_CMD
SDIO_DATA_0
SDIO_DATA_1
110
113
116
152
151
131
108
104
112
115
BT_VCOVDD1P2
BT_VCOVSS
57
58
BT_VDDC
14, 16, 26, 28, 31, 34
BT_VDDC_ISO_1
BT_VDDC_ISO_2
CLK_REQ
9
2
153
41
38
37
40
FM_DAC_AVDD
FM_DAC_AVSS
FM_DAC_VOUT1
FM_DAC_VOUT2
Document No. 002-14797 Rev. *I
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CYW4343W
Bump Name
SDIO_DATA_2
Bump Number(s)
118
SDIO_DATA_3
SR_PVSS
122
123, 124
129, 130, 132
126, 127, 128
140
SR_VDDBAT5V
SR_VLX
SYS_VDDIO
VDDC
86, 93, 95, 107, 114
139, 144
143
VOUT_3P3
VOUT_3P3_SENSE
VOUT_CLDO
VOUT_LNLDO
134, 136
138
21, 25, 27, 29, 30, 32,
33, 36, 78, 85, 88, 90,
92, 102, 106, 111, 121,
125, 142
VSSC
77, 79, 99, 103, 120,
137
WCC_VDDIO
WL_REG_ON
148
WL_VDDM_ISO
WL_VDDP_ISO
150
96
WPT_1P8
145
WPT_3P3
146
WRF_AFE_GND
WRF_GENERAL_GND
WRF_GPAIO_OUT
WRF_PA_GND3P3
WRF_PMU_VDD1P35
WRF_RFIN_ELG_2G
WRF_RFIO_2G
60
64
67
65, 69, 70, 71
68
61
63
62
66
72
73
75
74
WRF_RX2G_GND
WRF_VCO_GND
WRF_XTAL_GND1P2
WRF_XTAL_VDD1P2
WRF_XTAL_XON
WRF_XTAL_XOP
Document No. 002-14797 Rev. *I
Page 56 of 103
CYW4343W
13.6 Signal Descriptions
Table 18 provides the WLBGA package signal descriptions.
Table 18. WLBGA Signal Descriptions
Signal Name
WLBGA Ball Type
Description
RF Signal Interface
WLRF_2G_RF
K1
O
2.4 GHz BT and WLAN RF output port
SDIO Bus Interface
SDIO clock input
SDIO_CLK
M7
L6
K6
H7
L7
J7
I
SDIO_CMD
I/O
I/O
I/O
I/O
I/O
SDIO command line
SDIO data line 0
SDIO_DATA_0
SDIO_DATA_1
SDIO_DATA_2
SDIO_DATA_3
SDIO data line 1.
SDIO data line 2. Also used as a strapping option (see Table 22).
SDIO data line 3
Note: Per Section 6 of the SDIO specification, 10 to 100 kΩ pull-ups are required on the four DATA lines and the CMD line. This
requirement must be met during all operating states by using external pull-up resistors or properly programming internal SDIO host
pull-ups.
WLAN GPIO Interface
WLRF_GPIO
J3
I/O
Test pin. Not connected in normal operation.
Clocks
WLRF_XTAL_XON
WLRF_XTAL_XOP
M5
M4
O
I
XTAL oscillator output
XTAL oscillator input
External system clock request—Used when the system clock is not provided
by a dedicated crystal (for example, when a shared TCXO is used). Asserted
to indicate to the host that the clock is required. Shared by BT, and WLAN.
CLK_REQ
LPO_IN
M6
F5
O
I
External sleep clock input (32.768 kHz). If an external 32.768 kHz clock
cannot be provided, pull this pin low. However, BLE will be always on and
cannot go to deep sleep.
FM Receiver
FM_OUT1
FM_OUT2
FM_RF_IN
FM_RF_VDD
C2
D2
E1
E2
O
O
I
FM analog output 1
FM analog output 2
FM radio antenna port
FM power supply
Bluetooth PCM
I
BT_PCM_CLK or
BT_I2S_CLK
2
A5
C4
B4
I/O
I
PCM or I S clock; can be master (output) or slave (input)
2
BT_PCM_IN or BT_I2S_DI
PCM or I S data input sensing
BT_PCM_OUT or
BT_I2S_DO
2
O
PCM or I S data output
BT_PCM_SYNC or
BT_I2S_WS
B5
I/O
PCM SYNC or I2S_WS; can be master (output) or slave (input)
Bluetooth GPIO
BT_GPIO_3
BT_GPIO_4
BT_GPIO_5
F4
G5
H5
I/O
I/O
I/O
WPT_INTb to wireless charging PMU.
BSC_SDA to/from wireless charging PMU.
BSC_SCL from wireless charging PMU.
Document No. 002-14797 Rev. *I
Page 57 of 103
CYW4343W
Table 18. WLBGA Signal Descriptions (Cont.)
Signal Name
WLBGA Ball Type
Bluetooth UART and Wake
Description
UART clear-to-send. Active-low clear-to-send signal for the HCI UART
interface.
BT_UART_CTS_N
BT_UART_RTS_N
B2
C3
I
UART request-to-send. Active-low request-to-send signal for the HCI UART
interface.
O
BT_UART_RXD
BT_UART_TXD
BT_DEV_WAKE
BT_HOST_WAKE
A1
A2
B1
C1
I
UART serial input. Serial data input for the HCI UART interface.
UART serial output. Serial data output for the HCI UART interface.
DEV_WAKE or general-purpose I/O signal.
O
I/O
I/O
HOST_WAKE or general-purpose I/O signal.
Note: By default, the Bluetooth BT WAKE signals provide GPIO/WAKE functionality, and the UART pins provide UART functionality.
Through software configuration, the PCM interface can also be routed over the BT_WAKE/UART signals as follows:
■ PCM_CLK on the UART_RTS_N pin
■ PCM_OUT on the UART_CTS_N pin
■ PCM_SYNC on the BT_HOST_WAKE pin
■ PCM_IN on the BT_DEV_WAKE pin
In this case, the BT HCI transport included sleep signaling will operate using UART_RXD and UART_TXD; that is, using a 3-Wire
UART Transport.
Bluetooth/FM I2S
BT_I2S_CLK or BT_PC-
M_CLK
2
A4
B3
A3
I/O
I/O
I/O
I S or PCM clock; can be master (output) or slave (input)
BT_I2S_DO or BT_PC-
M_OUT
2
I S or PCM data output
BT_I2S_WS or BT_PC-
M_SYNC
2
I S WS or PCM sync; can be master (output) or slave (input)
Miscellaneous
Used by PMU to power up or power down the internal regulators used by the
WLAN section. Also, when deasserted, this pin holds the WLAN section in
reset. This pin has an internal 200 k pull-down resistor that is enabled by
default. It can be disabled through programming.
WL_REG_ON
BT_REG_ON
G6
E6
I
I
Used by PMU to power up or power down the internal regulators used by the
Bluetooth/FM section. Also, when deasserted, this pin holds the Bluetooth/
FM section in reset. This pin has an internal 200 k pull-down resistor that
is enabled by default. It can be disabled through programming.
WPT_3P3
WPT_1P8
E5
D5
N/A
N/A
Not used. Do not connect to this pin.
Not used. Do not connect to this pin.
Programmable GPIO pins. This pin becomes an output pin when it is used
as WLAN_HOST_WAKE/out-of-band signal.
GPIO_0
J6
I/O
GPIO_1
H6
L5
K4
K5
J1
I/O
I/O
I/O
I/O
I
Programmable GPIO pins
GPIO_2
Programmable GPIO pins
GPIO_3
Programmable GPIO pins
GPIO_4
Programmable GPIO pins
WLRF_2G_eLG
Connect to an external inductor. See the reference schematic for details.
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Table 18. WLBGA Signal Descriptions (Cont.)
Signal Name WLBGA Ball Type
Integrated Voltage Regulators
SR VBAT input power supply
Description
SR_VDDBAT5V
B7
A6
I
CBUCK switching regulator output. See Table 37 for details of the inductor
and capacitor required on this output.
SR_VLX
O
LDO_VDDBAT5V
LDO_VDD1P5
VOUT_LNLDO
VOUT_CLDO
F7
C7
D6
C6
I
LDO VBAT
I
LNLDO input
O
O
Output of low-noise LNLDO
Output of core LDO
Bluetooth Power Supplies
Bluetooth PA power supply
Bluetooth IF block power supply
Bluetooth RF PLL power supply
Bluetooth RF power supply
Power Supplies
BT_PAVDD
H1
G1
F2
F1
I
I
I
I
BT_IF_VDD
BTFM_PLL_VDD
BT_VCO_VDD
WLRF_XTAL_VDD1P2
WLRF_PA_VDD
WCC_VDDIO
SYS_VDDIO
M3
I
XTAL oscillator supply
M1
I
Power amplifier supply
F6
I
VDDIO input supply. Connect to VDDIO.
VDDIO input supply. Connect to VDDIO.
LNLDO input supply
C5
I
WLRF_VDD_1P35
VDDC
M2
I
D3, G4
E7
I
Core supply for WLAN and BT.
3.3V output supply. See the reference schematic for details.
Ground
VOUT_3P3
O
BT_IF_VSS
H2
G2
H3
E3
B6
A7
D4, J5
H4
J2
I
I
I
I
I
I
I
I
I
I
I
I
I
1.2V Bluetooth IF block ground
Bluetooth/FM RF PLL ground
1.2V Bluetooth RF ground
FM RF ground
BTFM_PLL_VSS
BT_VCO_VSS
FM_RF_VSS
PMU_AVSS
Quiet ground
SR_PVSS
Switcher-power ground
Core ground for WLAN and BT
AFE ground
VSSC
WLRF_AFE_GND
WLRF_LNA_GND
WLRF_GENERAL_GND
WLRF_PA_GND
WLRF_VCO_GND
WLRF_XTAL_GND
2.4 GHz internal LNA ground
Miscellaneous RF ground
2.4 GHz PA ground
K2
L2
L3
VCO/LO generator ground
XTAL ground
L4
Table 19 provides the WLCSP package signal descriptions.
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Table 19. WLCSP Signal Descriptions
Signal Name
WLCSP Bump
Type
Description or Instruction
RF Signal Interface
Connect to an external inductor. See the
reference schematic for details.
WRF_RFIN_ELG_2G
WRF_RFIO_2G
61
63
I
I/O
2.4 GHz BT and WLAN RF input/output port
SDIO Bus Interface
SDIO_CLK
108
104
112
115
I
SDIO clock input
SDIO_CMD
I/O
I/O
I/O
SDIO command line
SDIO data line 0
SDIO data line 1.
SDIO_DATA_0
SDIO_DATA_1
SDIO data line 2. Also used as a strapping option (see
Table 22).
SDIO_DATA_2
SDIO_DATA_3
118
122
I/O
I/O
SDIO data line 3
Note: Per Section 6 of the SDIO specification, 10 to 100 kΩ pull-ups are required on the four DATA lines and the CMD line. This
requirement must be met during all operating states by using external pull-up resistors or properly programming internal SDIO host
pull-ups.
WLAN GPIO Interface
WRF_GPAIO_OUT
67
O
Test pin. Not connected in normal operation.
Clocks
WRF_XTAL_XON
WRF_XTAL_XOP
75
74
O
I
XTAL oscillator output
XTAL oscillator input
External system clock request—Used when the system
clock is not provided by a dedicated crystal (for example,
when a shared TCXO is used). Asserted to indicate to the
host that the clock is required. Shared by BT, and WLAN.
CLK_REQ
LPO_IN
153
76
O
I
External sleep clock input (32.768 kHz). If an external
32.768 kHz clock cannot be provided, pull this pin low.
However, BLE will be always on and cannot go to deep
sleep.
FM
FM_DAC_VOUT1
FM_DAC_VOUT2
FM_RFINMAIN
37
40
49
O
FM DAC output 1
FM DAC output 2
FM RF input
O
I
Bluetooth PCM
2
BT_PCM_CLK or BT_I2S_CLK
BT_PCM_IN or BT_I2S_DI
BT_PCM_OUT or BT_I2S_DO
3
I/O
I
PCM or I S clock; can be master (output) or slave (input)
2
20
19
PCM or I S data input sensing
2
O
PCM or I S data output
PCM SYNC or I2S WS; can be master (output) or slave
(input)
BT_PCMM_SYNC or BT_I2S_WS
17
I/O
Bluetooth GPIO
BT_AGPIO
BT_GPIO_2
BT_GPIO_3
BT_GPIO_4
52
13
5
I/O
I/O
I/O
I/O
Bluetooth analog GPIO
Bluetooth general purpose I/O
WPT_INTb to wireless charging PMU.
BSC_SDA to/from wireless charging PMU.
8
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Table 19. WLCSP Signal Descriptions (Cont.)
Signal Name WLCSP Bump
Type
I/O
I/O
Description or Instruction
BT_GPIO_5
BT_TM1
10
4
BSC_SCL from wireless charging PMU
ARM JTAG mode
Bluetooth UART and Wake
UART clear-to-send. Active-low clear-to-send signal for
the HCI UART interface.
BT_UART_CTS_N
BT_UART_RTS_N
BT_UART_RXD
BT_UART_TXD
22
7
I
UARTrequest-to-send.Active-lowrequest-to-sendsignal
for the HCI UART interface.
O
I
UART serial input. Serial data input for the HCI UART
interface.
1
UART serial output. Serial data output for the HCI UART
interface.
12
O
DEV_WAKE or general-purpose
I/O signal
BT_DEV_WAKE
BT_HOST_WAKE
6
I/O
I/O
11
HOST_WAKE or general-purpose I/O signal
Note: By default, the Bluetooth BT WAKE signals provide GPIO/WAKE functionality, and the UART pins provide UART functionality.
Through software configuration, the PCM interface can also be routed over the
BT_WAKE/UART signals as follows:
■ PCM_CLK on the UART_RTS_N pin
■ PCM_OUT on the UART_CTS_N pin
■ PCM_SYNC on the BT_HOST_WAKE pin
■ PCM_IN on the BT_DEV_WAKE pin
In this case, the BT HCI transport included sleep signaling will operate using UART_RXD and UART_TXD; that is, using a 3-Wire
UART Transport.
Bluetooth/FM I2S
2
BT_I2S_CLK or BT_PCM_CLK
BT_I2S_DI or BT_PCM_IN
BT_I2S_DO or BT_PCM_OUT
15
23
24
I/O
I
I S or PCM clock; can be master (output) or slave (input)
2
I S or PCM data input
2
O
I S or PCM data output
2
I S WS or PCM SYNC; can be master (output) or slave
(input)
BT_I2S_WS or BT_PCM_SYNC
18
I/O
Miscellaneous
Used by PMU to power up or power down the internal
regulators used by the WLAN section. Also, when
deasserted, this pin holds the WLAN section in reset. This
pin has an internal 200 k pull-down resistor that is
enabled by default. It can be disabled through
programming.
WL_REG_ON
148
I
I
Used by PMU to power up or power down the internal
regulators used by the Bluetooth/FM section. Also, when
deasserted, this pin holds the Bluetooth/FM section in
reset. This pin has an internal 200 k pull-down resistor
that is enabled by default. It can be disabled through
programming.
BT_REG_ON
149
WPT_3P3
WPT_1P8
146
145
N/A
N/A
Not used. Do not connect to this pin.
Not used. Do not connect to this pin.
Programmable GPIO pin. This pin becomes an output pin
when it is used as WLAN_HOST_WAKE/out-of-band
signal.
GPIO_0
100
I/O
GPIO_1
GPIO_2
101
97
I/O
I/O
Programmable GPIO pin
Programmable GPIO pin
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Table 19. WLCSP Signal Descriptions (Cont.)
Signal Name WLCSP Bump
Type
I/O
Description or Instruction
Programmable GPIO pin
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
98
91
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Programmable GPIO pin
Programmable GPIO pin
Programmable GPIO pin
Programmable GPIO pin
Programmable GPIO pin
Programmable GPIO pin
Programmable GPIO pin
Programmable GPIO pin
Programmable GPIO pin
Programmable GPIO pin
Programmable GPIO pin
Programmable GPIO pin
VDDIO
94
89
87
84
82
83
81
80
119
105
109
110
113
116
117
PACKAGEOPTION_0
PACKAGEOPTION_1
PACKAGEOPTION_2
JTAG_SEL
I
Ground
I
Ground
I
JTAG select. Connect to ground.
Integrated Voltage Regulators
SR_VDDBAT5V
SR_VLX
129, 130, 132
I
SR VBAT input power supply
CBUCK switching regulator output. See Table 37 for
details of the inductor and capacitor required on this
output.
126, 127, 128
O
LDO_VDDBAT5V
LDO_VDD1P5
VOUT_LNLDO
VOUT_CLDO
141, 147
133, 135
138
I
LDO VBAT
I
LNLDO input
O
O
Output of low-noise LDO (LNLDO)
Output of core LDO
134, 136
Bluetooth Power Supplies
BT_IFVDD1P2
51
54
53
59
57
PWR
PWR
PWR
PWR
PWR
Bluetooth IF-block power supply
BT_LNAVDD1P2
BT_PAVDD2P5
BT_PLLVDD1P2
BT_VCOVDD1P2
Bluetooth RF LNA power supply
Bluetooth RF PA power supply
Bluetooth RF PLL power supply
Bluetooth RF power supply
14, 16, 26, 28, 31,
34
BT_VDDC
PWR
Bluetooth core power supply
BT_VDDC_ISO_1
BT_VDDC_ISO_2
9
2
PWR
PWR
Bluetooth core power supply
Bluetooth core power supply
Power Supplies
PWR
FM_DAC_AVDD
FM_IFDVDD1P2
FM_PLLDVDD1P2
FM_RFVDD1P2
FM_VCOVDD1P2
41
48
43
45
44
FM DAC power supply
FM IF power supply
FM PLL power supply
FM RF power supply
FM VCO power supply
PWR
PWR
PWR
PWR
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Table 19. WLCSP Signal Descriptions (Cont.)
Signal Name WLCSP Bump
Type
PWR
I
Description or Instruction
Core PLL power supply
PLL_VDDC
152
140
SYS_VDDIO
VDDIO input supply. Connect to VDDIO.
86, 93, 95, 107,
114
VDDC
I
Core supply for WLAN and BT
3.3V output supply. See the reference schematic for
details.
VOUT_3P3
139, 144
143
O
O
I
VOUT_3P3_SENSE
WCC_VDDIO
Voltage sense pin for LDO 3.3V output
77, 79, 99, 103,
120, 137
VDDIO input supply. Connect to VDDIO.
WL_VDDM_ISO
150
96
–
–
I
Test pin. Not connected in normal operation.
Test pin. Not connected in normal operation.
XTAL oscillator supply
WL_VDDP_ISO
WRF_XTAL_VDD1P2
WRF_PA_VDD3P3
WRF_PMU_VDD1P35
73
70, 71
68
I
Power amplifier supply
I
LNLDO input supply
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Table 19. WLCSP Signal Descriptions (Cont.)
Signal Name WLCSP Bump
Type
Ground
Description or Instruction
BT_DVSS
50
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
I
Bluetooth digital ground
BT_LNAVSS
BT_PAVSS
BT_PLLVSS
BT_VCOVSS
55
Bluetooth LNA ground
Bluetooth PA ground
Bluetooth PLL ground
Bluetooth VCO ground
FM DAC analog ground
FM IF-block ground
FM PLL analog ground
FM RF ground
35
56
58
FM_DAC_AVSS
FM_IFVSS
38
47
FM_PLLAVSS
FM_RFVSS
FM_VCOVSS
PLL_VSSC
39
46
42
FM VCO ground
151
131
123, 124
PLL core ground
PMU_AVSS
SR_PVSS
Quiet ground
I
Switcher-power ground
21, 25, 27, 29, 30,
32, 33, 36, 78, 85,
88, 90, 92, 102,
106, 111, 121,
125, 142
VSSC
I
Core ground for WLAN and BT
WRF_AFE_GND
60
I
I
I
I
I
I
AFE ground
WRF_RX2G_GND
WRF_GENERAL_GND
WRF_PA_GND3P3
WRF_VCO_GND
62
2.4 GHz internal LNA ground
Miscellaneous RF ground
2.4 GHz PA ground
VCO/LO generator ground
XTAL ground
64
65, 69
66
WRF_XTAL_GND1P2
72
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13.7 WLAN GPIO Signals and Strapping Options
The pins listed in Table 20 are sampled at power-on reset (POR) to determine the various operating modes. Sampling occurs a few
milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative
function specified in the signal descriptions table. Each strapping option pin has an internal pull-up (PU) or pull-down (PD) resistor
that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to ground using
a 10 kΩ resistor or less.
Note: Refer to the reference board schematics for more information.
Table 20. GPIO Functions and Strapping Options
Pin Name
WLBGA Pin # Default
L7
Function
Description
WLAN host interface
select
This pin selects the WLAN host interface mode. The
default is SDIO.
SDIO_DATA_2
1
13.8 Chip Debug Options
The chip can be accessed for debugging via the JTAG interface, multiplexed on the SDIO_DATA_0 through SDIO_DATA_3 (and
SDIO_CLK) I/O or the Bluetooth PCM I/O depending on the bootstrap state of GPIO_1 and GPIO_2.
Table 21 shows the debug options of the device.
Table 21. Chip Debug Options
JTAG_SEL GPIO_2
BT PCM I/O Pad
Function
GPIO_1
Function
Normal mode
SDIO I/O Pad Function
0
0
0
0
0
0
1
1
0
1
0
1
SDIO
JTAG
SDIO
BT PCM
JTAG over SDIO
BT PCM
JTAG
JTAG over BT PCM
SWD over GPIO_1/GPIO_2 SDIO
BT PCM
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13.9 I/O States
The following notations are used in Table 22:
■ I: Input signal
■ O: Output signal
■ I/O: Input/Output signal
■ PU = Pulled up
■ PD = Pulled down
■ NoPull = Neither pulled up nor pulled down
Table 22. I/O Statesa
Out-of-Reset;
Out-of-Reset;
(WL_REG_ON = 1 (WL_REG_ON = 0
BT_REG_ON = 0) BT_REG_ON = 1)
Power-Downc
LowPowerState/Sleep WL_REG_ON = 0
(WL_REG_ON = 1;
BT_REG_ON =
Do Not Care)
Keeper
b
Name
I/O
Active Mode
(All Power Present)
BT_REG_ON = 0
VDDIOs Present
VDDIOs Present
Power Rail
WL_REG_ON
I
N
N
Y
Input; PD (pull-down
can be disabled)
Input; PD (pull-down
can be disabled)
Input; PD (of 200K)
Input; PD (200k)
Input; PD (200k)
–
–
BT_REG_ON
CLK_REQ
I
Input; PD (pull down
can be disabled)
Input; PD (pull down
can be disabled)
Input; PD (of 200K)
Input; PD (200k)
Input; PD (200k)
Input; PD (200k)
–
I/O
Open drain or push-pull Open drain or push-pull PD
(programmable). Active (programmable). Active
Open drain,
active high.
Open drain,
active high.
Open drain,
active high.
WCC_VDDIO
high.
high
BT_HOST_
WAKE
I/O
Y
Y
I/O; PU, PD, NoPull
(programmable)
I/O; PU, PD, NoPull
(programmable)
High-Z, NoPull
High-Z, NoPull
–
–
Input, PD
Input, PD
Output, Drive low
Input, PD
WCC_VDDIO
WCC_VDDIO
BT_DEV_WAK I/O
E
I/O; PU, PD, NoPull
(programmable)
Input; PU, PD, NoPull
(programmable)
BT_UART_CTS
BT_UART_RTS
I
O
I
Y
Y
Y
Input; NoPull
Output; NoPull
Input; PU
Input; NoPull
Output; NoPull
Input; NoPull
High-Z, NoPull
High-Z, NoPull
High-Z, NoPull
–
–
–
Input; PU
Input; PU
Input; PU
Input, NoPull
Output, NoPull
Input, NoPull
WCC_VDDIO
WCC_VDDIO
WCC_VDDIO
BT_UART_RX
D
BT_UART_TXD
O
Y
N
Output; NoPull
Output; NoPull
High-Z, NoPull
–
Input; PU
Output, NoPull
Input; PU
WCC_VDDIO
WCC_VDDIO
SDIO_DATA_0 I/O
SDIO_DATA_1 I/O
SDIO_DATA_2 I/O
SDIO_DATA_3 I/O
SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE ->
NoPull
SDIO MODE -> PU
SDIO MODE ->
NoPull
N
N
N
SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE ->
NoPull
SDIO MODE -> PU
SDIO MODE -> PU
SDIO MODE -> PU
SDIO MODE ->
NoPull
Input; PU
Input; PU
Input; PU
WCC_VDDIO
WCC_VDDIO
WCC_VDDIO
SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE ->
NoPull
SDIO MODE ->
NoPull
SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE ->
NoPull
SDIO MODE ->
NoPull
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Table 22. I/O Statesa (Cont.)
Out-of-Reset;
Out-of-Reset;
(WL_REG_ON = 1 (WL_REG_ON = 0
BT_REG_ON = 0) BT_REG_ON = 1)
Power-Downc
LowPowerState/Sleep WL_REG_ON = 0
(WL_REG_ON = 1;
BT_REG_ON =
Do Not Care)
Keeper
b
Name
I/O
Active Mode
(All Power Present)
BT_REG_ON = 0
VDDIOs Present
VDDIOs Present
Power Rail
SDIO_CMD
I/O
N
N
SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE ->
NoPull
SDIO MODE -> PU
SDIO MODE ->
NoPull
Input; PU
WCC_VDDIO
SDIO_CLK
I
SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE ->
NoPull
SDIO MODE ->
NoPull
SDIO MODE ->
NoPull
Input
WCC_VDDIO
Input; NoPulld
Input; NoPulld
Input; NoPulld
Input; NoPulld
Input; NoPulld
Input; NoPulld
Input; NoPulld
Input; NoPulld
BT_PCM_CLK I/O
BT_PCM_IN I/O
Y
Y
Y
Y
High-Z, NoPull
–
–
–
–
Input, PD
Input, PD
Input, PD
Input, PD
Input, PD
Input, PD
Input, PD
Input, PD
WCC_VDDIO
WCC_VDDIO
WCC_VDDIO
WCC_VDDIO
High-Z, NoPull
High-Z, NoPull
High-Z, NoPull
BT_PCM_OUT I/O
BT_PCM_SYN I/O
C
Input; NoPulle
Input; NoPulle
Input; NoPulle
Input; NoPulle
BT_I2S_WS
BT_I2S_CLK
BT_I2S_DO
I/O
I/O
I/O
Y
Y
Y
High-Z, NoPull
High-Z, NoPull
High-Z, NoPull
High-Z, NoPull
High-Z, NoPullf
–
Input, PD
Input, PD
Input, PD
PD
Input, PD
WCC_VDDIO
WCC_VDDIO
WCC_VDDIO
–
Output, Drive low
Input, PD
Input; NoPulle
Input; NoPulle
PD
–
JTAG_SEL
GPIO_0
I
Y
Y
PD
Input, PD
Input, PD
WCC_VDDIO
WCC_VDDIO
I/O
TBD
Active mode
Input, SDIO OOB Int, Active mode
NoPull
Input, NoPull
High-Z, NoPullf
High-Z, NoPullf
GPIO_1
GPIO_2
I/O
I/O
Y
Y
TBD
TBD
Active mode
Active mode
Input, PD
Active mode
Active mode
Input, Strap, PD
WCC_VDDIO
Input, GCI GPIO[7],
NoPull
Input, Strap, NoPull WCC_VDDIO
High-Z, NoPullf
High-Z, NoPullf
High-Z, NoPullf
High-Z, NoPullf
High-Z, NoPullf
High-Z, NoPullf
High-Z, NoPullf
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Y
Y
N
Y
Y
Y
Y
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Active mode
Active mode
Active mode
Active mode
Active mode
Active mode
Active mode
Input, GCI GPIO[0],
PU
Active mode
Active mode
Active mode
Active mode
Input, PU
Input, PU
Input, PU
Input, NoPull
WCC_VDDIO
WCC_VDDIO
WCC_VDDIO
WCC_VDDIO
WCC_VDDIO
WCC_VDDIO
WCC_VDDIO
Input, GCI GPIO[1],
PU
Input, GCI GPIO[2],
PU
Input, GCI GPIO[3],
NoPull
Output, WLAN UART Active mode
RTS#, NoPull
Output, NoPull,
Low
Input, WLAN UART
CTS#, NoPull
Active mode
Input, NoPull
Input, WLAN UART
RX, NoPull
Active mode
Input, NoPull
Document No. 002-14797 Rev. *I
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CYW4343W
Table 22. I/O Statesa (Cont.)
Out-of-Reset;
Out-of-Reset;
(WL_REG_ON = 1 (WL_REG_ON = 0
BT_REG_ON = 0) BT_REG_ON = 1)
Power-Downc
LowPowerState/Sleep WL_REG_ON = 0
(WL_REG_ON = 1;
BT_REG_ON =
Do Not Care)
Keeper
b
Name
I/O
Active Mode
(All Power Present)
BT_REG_ON = 0
VDDIOs Present
VDDIOs Present
Power Rail
High-Z, NoPullf
GPIO_10
I/O
Y
TBD
Active mode
Output, WLAN UART Active mode
TX, NoPull
Output, NoPull,
Low
WCC_VDDIO
High-Z, NoPullf
High-Z, NoPullf
GPIO_11
GPIO_12
I/O
I/O
Y
Y
TBD
TBD
Active mode
Active mode
Input, Low, NoPull
Active mode
Active mode
Input, NoPull
Input, NoPull
WCC_VDDIO
WCC_VDDIO
Input, GCI GPIO[6],
NoPull
High-Z, NoPullf
GPIO_13
I/O
Y
TBD
Active mode
Input, GCI GPIO[7],
NoPull
Active mode
Input, NoPull
WCC_VDDIO
High-Z, NoPullf
High-Z, NoPullf
GPIO_14
GPIO_15
I/O
I/O
Y
Y
TBD
TBD
Active mode
Active mode
Input, PD
Input, PD
Active mode
Active mode
Input, PD
Input, PD
WCC_VDDIO
WCC_VDDIO
a. PU = pulled up, PD = pulled down.
b. N = pad has no keeper. Y = pad has a keeper. Keeper is always active except in the power-down state. If there is no keeper, and it is an input and there is NoPull, then the pad should be
driven to prevent leakage due to floating pad, for example, SDIO_CLK.
c. In the Power-down state (xx_REG_ON = 0): High-Z; NoPull => The pad is disabled because power is not supplied.
d. Depending on whether the PCM interface is enabled and the configuration is master or slave mode, it can be either an output or input.
e. Depending on whether the I2S interface is enabled and the configuration is master or slave mode, it can be either an output or input.
f. The GPIO pull states for the active and low-power states are hardware defaults. They can all be subsequently programmed as a pull-up or pull-down.
Document No. 002-14797 Rev. *I
Page 68 of 103
CYW4343W
14. DC Characteristics
Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization.
14.1 Absolute Maximum Ratings
Caution! The absolute maximum ratings in Table 23 indicate levels where permanent damage to the device can occur, even if these
limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Excluding VBAT,
operation at the absolute maximum conditions for extended periods can adversely affect long-term reliability of the device.
Table 23. Absolute Maximum Ratings
Rating
DC supply for VBAT and PA driver supply
DC supply voltage for digital I/O
Symbol
Value
a
Unit
VBAT
–0.5 to +6.0
–0.5 to 3.9
–0.5 to 3.9
V
V
V
V
V
V
V
V
VDDIO
DC supply voltage for RF switch I/Os
DC input supply voltage for CLDO and LNLDO
DC supply voltage for RF analog
DC supply voltage for core
VDDIO_RF
–
–0.5 to 1.575
–0.5 to 1.32
–0.5 to 1.32
–0.5
VDDRF
VDDC
b
Maximum undershoot voltage for I/O
V
undershoot
overshoot
b
Maximum overshoot voltage for I/O
V
VDDIO + 0.5
125
Maximum junction temperature
T
°C
j
a. Continuous operation at 6.0V is supported.
b. Duration not to exceed 25% of the duty cycle.
14.2 Environmental Ratings
The environmental ratings are shown in Table 24.
Table 24. Environmental Ratings
Characteristic
Value
Units
Conditions/Comments
a
Ambient temperature (T )
–30 to +70°C
C
C
%
Operation
A
Storage temperature
–40 to +125°C
Less than 60
Less than 85
–
Storage
Relative humidity
%
Operation
a. Functionality is guaranteed, but specifications require derating at extreme temperatures (see the specification tables for details).
Document No. 002-14797 Rev. *I
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CYW4343W
14.3 Electrostatic Discharge Specifications
Extreme caution must be exercised to prevent electrostatic discharge (ESD) damage. Proper use of wrist and heel grounding straps
to discharge static electricity is required when handling these devices. Always store unused material in its antistatic packaging.
Table 25. ESD Specifications
Pin Type
Symbol
Condition
ESD Rating
1000
Unit
ESD, Handling Reference:
NQY00083, Section 3.4, Group ESD_HAND_HBM
D9, Table B
Human Body Model Contact Discharge per
JEDEC EID/JESD22-A114
V
Machine Model (MM)
ESD_HAND_MM
Machine Model Contact
30
V
V
Charged Device Model Contact Discharge
per JEDEC EIA/JESD22-C101
CDM
ESD_HAND_CDM
300
14.4 Recommended Operating Conditions and DC Characteristics
Functional operation is not guaranteed outside the limits shown in Table 26, and operation outside these limits for extended periods
can adversely affect long-term reliability of the device.
Table 26. Recommended Operating Conditions and DC Characteristics
Value
Element
Symbol
Unit
Minimum
Typical
–
Maximum
a
b
DC supply voltage for VBAT
VBAT
3.0
4.8
V
V
V
DC supply voltage for core
VDD
1.14
1.14
1.2
1.26
1.26
DC supply voltage for RF blocks in chip
VDDRF
1.2
VDDIO,
VDDIO_SD
DC supply voltage for digital I/O
1.71
–
3.63
V
DC supply voltage for RF switch I/Os
External TSSI input
VDDIO_RF
TSSI
3.13
0.15
0.4
3.3
–
3.46
0.95
0.7
V
V
V
Internal POR threshold
Vth_POR
–
SDIO Interface I/O Pins
For VDDIO_SD = 1.8V:
Input high voltage
VIH
VIL
1.27
–
–
–
–
–
–
V
V
V
V
Input low voltage
0.58
–
Output high voltage @ 2 mA
Output low voltage @ 2 mA
For VDDIO_SD = 3.3V:
Input high voltage
VOH
VOL
1.40
–
0.45
VIH
0.625 × VDDIO
–
–
–
–
–
V
V
V
V
0.25 ×
VDDIO
Input low voltage
VIL
–
Output high voltage @ 2 mA
Output low voltage @ 2 mA
VOH
VOL
0.75 × VDDIO
–
–
0.125 ×
VDDIO
Other Digital I/O Pins
For VDDIO = 1.8V:
Input high voltage
VIH
VIL
0.65 × VDDIO
–
–
–
–
V
V
0.35 ×
VDDIO
Input low voltage
Output high voltage @ 2 mA
Output low voltage @ 2 mA
VOH
VOL
VDDIO – 0.45
–
–
–
–
V
V
0.45
Document No. 002-14797 Rev. *I
Page 70 of 103
CYW4343W
Table 26. Recommended Operating Conditions and DC Characteristics (Cont.)
Element Symbol
Value
Unit
Minimum
Typical
Maximum
For VDDIO = 3.3V:
Input high voltage
Input low voltage
VIH
2.00
–
–
–
–
–
V
V
V
V
VIL
–
0.80
–
Output high voltage @ 2 mA
Output low Voltage @ 2 mA
VOH
VOL
VDDIO – 0.4
–
0.40
RF Switch Control Output Pinsc
For VDDIO_RF = 3.3V:
Output high voltage @ 2 mA
Output low voltage @ 2 mA
Input capacitance
VOH
VOL
VDDIO – 0.4
–
–
–
–
0.40
5
V
V
–
–
C
pF
IN
a. The CYW4343W is functional across this range of voltages. However, optimal RF performance specified in the data sheet is guaranteed only
for 3.2V < VBAT < 4.8V.
b. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration over the lifetime of the device are
allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration over the lifetime of the device are allowed.
c. Programmable 2 mA to 16 mA drive strength. Default is 10 mA.
Document No. 002-14797 Rev. *I
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CYW4343W
15. WLAN RF Specifications
The CYW4343W includes an integrated direct conversion radio that supports the 2.4 GHz band. This section describes the RF
characteristics of the 2.4 GHz radio.
Note: Values in this data sheet are design goals and may change based on device characterization results.
Unless otherwise stated, the specifications in this section apply when the operating conditions are within the limits specified in
Table 24: “Environmental Ratings” and Table 26: “Recommended Operating Conditions and DC Characteristics” . Functional
operation outside these limits is not guaranteed.
Typical values apply for the following conditions:
■ VBAT = 3.6V.
■ Ambient temperature +25°C.
Figure 28. RF Port Location
Chip
Port
C2
TX
RX
Filter
Antenna
Port
10 pF
CYW4343W
C1
L1
4.7 nH
10 pF
Note: All specifications apply at the chip port unless otherwise specified.
15.1 2.4 GHz Band General RF Specifications
Table 27. 2.4 GHz Band General RF Specifications
Item
Condition
Including TX ramp down
Including TX ramp up
Minimum
Typical
Maximum
Unit
µs
TX/RX switch time
RX/TX switch time
–
–
–
–
5
2
µs
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CYW4343W
15.2 WLAN 2.4 GHz Receiver Performance Specifications
Note: Unless otherwise specified, the specifications in Table 28 are measured at the chip port (for the location of the chip port, see
Figure 28).
Table 28. WLAN 2.4 GHz Receiver Performance Specifications
Parameter
Frequency range
Condition/Notes
Minimum
2400
Typical
–
Maximum Unit
–
2500
–
MHz
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
1 Mbps DSSS
2 Mbps DSSS
5.5 Mbps DSSS
11 Mbps DSSS
6 Mbps OFDM
9 Mbps OFDM
12 Mbps OFDM
18 Mbps OFDM
24 Mbps OFDM
36 Mbps OFDM
48 Mbps OFDM
54 Mbps OFDM
–97.5
–93.5
–91.5
–88.5
–91.5
–90.5
–87.5
–85.5
–82.5
–80.5
–76.5
–75.5
–99.5
–95.5
–93.5
–90.5
–93.5
–92.5
–89.5
–87.5
–84.5
–82.5
–78.5
–77.5
–
RX sensitivity (8% PER for 1024
a
octet PSDU)
–
–
–
–
–
–
RX sensitivity (10% PER for 1000
octet PSDU) at WLAN RF port
a
–
–
–
–
20 MHz channel spacing for all MCS rates (Mixed mode)
256-QAM, R = 5/6
256-QAM, R = 3/4
MCS7
–67.5
–69.5
–71.5
–73.5
–74.5
–79.5
–82.5
–84.5
–86.5
–90.5
–69.5
–71.5
–73.5
–75.5
–76.5
–81.5
–84.5
–86.5
–88.5
–92.5
–
–
–
–
–
–
–
–
–
–
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
RX sensitivity
MCS6
(10% PER for 4096 octet PSDU).
Defined for default parameters:
Mixed mode, 800 ns GI.
MCS5
MCS4
MCS3
MCS2
MCS1
MCS0
Document No. 002-14797 Rev. *I
Page 73 of 103
CYW4343W
Table 28. WLAN 2.4 GHz Receiver Performance Specifications (Cont.)
Parameter
Condition/Notes
Minimum
Typical
–13
Maximum Unit
704–716 MHz
LTE
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
777–787 MHz
776–794 MHz
815–830 MHz
816–824 MHz
816–849 MHz
824–849 MHz
824–849 MHz
824–849 MHz
824–849 MHz
830–845 MHz
832–862 MHz
880–915 MHz
880–915 MHz
880–915 MHz
1710–1755 MHz
1710–1755 MHz
1710–1755 MHz
1710–1785 MHz
1710–1785 MHz
1710–1785 MHz
1850–1910 MHz
1850–1910 MHz
1850–1910 MHz
1850–1910 MHz
1850–1915 MHz
1920–1980 MHz
1920–1980 MHz
1920–1980 MHz
2300–2400 MHz
2500–2570 MHz
2570–2620 MHz
5G
LTE
–13
CDMA2000
LTE
–
–13.5
–12.5
–13.5
–11.5
–11.5
–12.5
–11.5
–8
–
CDMA2000
LTE
–
–
WCDMA
CDMA2000
LTE
–
–
–
GSM850
LTE
–
–
–11.5
–11.5
–10
LTE
–
WCDMA
LTE
–
–
–12
E-GSM
WCDMA
LTE
–
–9
–
–13
Blocking level for 3 dB RX sensitivity
degradation (without external
filtering).
–
–14.5
–14.5
–13
b
CDMA2000
WCDMA
LTE
–
–
–
–14.5
–12.5
–11.5
–16
GSM1800
GSM1900
CDMA2000
WCDMA
LTE
–
–
–
–
–13.5
–16
–
LTE
–
–17
WCDMA
CDMA2000
LTE
–
–17.5
–19.5
–19.5
–44
–
–
LTE
–
LTE
–
–43
LTE
–
–34
WLAN
–
>–4
@ 1, 2 Mbps (8% PER, 1024 octets)
@ 5.5, 11 Mbps (8% PER, 1024 octets)
@ 6–54 Mbps (10% PER, 1000 octets)
–6
–12
–15.5
–
Maximum receive level
@ 2.4 GHz
–
–
Document No. 002-14797 Rev. *I
Page 74 of 103
CYW4343W
Table 28. WLAN 2.4 GHz Receiver Performance Specifications (Cont.)
Parameter
Condition/Notes
Minimum
Typical
Maximum Unit
Adjacent channel rejection-DSSS.
(Difference between interfering and
desired signal [25 MHz apart] at 8%
PER for 1024 octet PSDU with
desired signal level as specified in
Condition/Notes.)
11 Mbps DSSS
–70 dBm
35
–
–
dB
6 Mbps OFDM
9 Mbps OFDM
12 Mbps OFDM
–79 dBm
–78 dBm
–76 dBm
–74 dBm
–71 dBm
–67 dBm
–63 dBm
–62 dBm
–61 dBm
16
15
13
11
8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3
5
–
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Adjacent channel rejection-OFDM.
(Difference between interfering and 18 Mbps OFDM
desired signal (25 MHz apart) at 10%
24 Mbps OFDM
36 Mbps OFDM
48 Mbps OFDM
54 Mbps OFDM
65 Mbps OFDM
c
PER for 1000 octet PSDU with
desired signal level as specified in
Condition/Notes.)
4
0
–1
–2
–3
–5
10
Range –98 dBm to –75 dBm
Range above –75 dBm
d
RCPI accuracy
Return loss
Zo = 50Ω across the dynamic range.
a. Optimal RF performance, as specified in this data sheet, is guaranteed only for temperatures between –10°C and 55°C.
b. The cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that band for the purpose
of this test. It is not intended to indicate any specific usage of each band in any specific country.
c. For 65 Mbps, the size is 4096.
d. The minimum and maximum values shown have a 95% confidence level.
Document No. 002-14797 Rev. *I
Page 75 of 103
CYW4343W
15.3 WLAN 2.4 GHz Transmitter Performance Specifications
Note: Unless otherwise specified, the specifications in Table 28 are measured at the chip port (for the location of the chip port, see
Figure 28).
Table 29. WLAN 2.4 GHz Transmitter Performance Specifications
Parameter
Condition/Notes
Minimum Typical Maximum
Unit
Frequency range
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MHz
776–794 MHz
CDMA2000
–167.5
–163.5
–154.5
–152.5
–149.5
–145.5
–143.5
–140.5
–138.5
–139
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
–
869–960 MHz
CDMAOne, GSM850
DAB
1450–1495 MHz
1570–1580 MHz
1592–1610 MHz
1710–1800 MHz
1805–1880 MHz
1850–1910 MHz
1910–1930 MHz
1930–1990 MHz
2010–2075 MHz
2110–2170 MHz
2305–2370 MHz
2370–2400 MHz
2496–2530 MHz
2530–2560 MHz
2570–2690 MHz
5000–5900 MHz
GPS
GLONASS
DSC-1800-Uplink
GSM1800
GSM1900
Transmitted power in cellular
and WLAN 5G bands (at 21
dBm, 90% duty cycle,
TDSCDMA, LTE
GSM1900, CDMAOne, WCDMA
TDSCDMA
a
1 Mbps CCK).
–127.5
–124.5
–104.5
–81.5
WCDMA
LTE Band 40
LTE Band 40
LTE Band 41
LTE Band 41
LTE Band 41
WLAN 5G
–94.5
–120.5
–121.5
–109.5
dBm/
MHz
4.8–5.0 GHz
2nd harmonic
3rd harmonic
–
–
–
–26.5
–23.5
–32.5
–
–
–
Harmonic level (at 21 dBm
dBm/
MHz
with 90% duty cycle, 1 Mbps 7.2–7.5 GHz
CCK)
dBm/
MHz
9.6–10 GHz
4th harmonic
EVM Does Not Exceed
–9 dB
–
IEEE 802.11b
(DSSS/CCK)
21
–
–
dBm
OFDM, BPSK
–8 dB
20.5
20.5
20.5
–
–
–
–
–
–
dBm
dBm
dBm
TX power at the chip port for
OFDM, QPSK
–13 dB
–19 dB
the highest power level
setting at 25°C, VBA = 3.6V,
OFDM, 16-QAM
and spectral mask and EVM
OFDM, 64-QAM
b, c
compliance
(R = 3/4)
–25 dB
–27 dB
–32 dB
18
17.5
15
–
–
–
–
–
–
–
–
dBm
dBm
dBm
dB
OFDM, 64-QAM
(R = 5/6)
OFDM, 256-QAM
(R = 5/6)
TX power control
–
9
dynamic range
Document No. 002-14797 Rev. *I
Page 76 of 103
CYW4343W
Table 29. WLAN 2.4 GHz Transmitter Performance Specifications (Cont.)
Parameter
Condition/Notes
Minimum Typical Maximum
Unit
Closed loop TX power
variation at highest power
level setting
Across full temperature and voltage range. Applies
across 5 to 21 dBm output power range.
–
–
±1.5
dB
Carrier suppression
Gain control step
Return loss
–
15
–
–
0.25
6
–
–
–
–
–
–
–
–
–
dBc
dB
–
Zo = 50
4
dB
EVM degradation
–
3.5
±2
15
4
dB
VSWR = 2:1.
VSWR = 3:1.
Output power variation
ACPR-compliant power level
EVM degradation
–
dB
Load pull variation for output
power, EVM, and Adjacent
Channel Power Ratio
(ACPR)
–
dBm
dB
–
Output power variation
ACPR-compliant power level
–
±3
15
dB
–
dBm
a. The cellular standards listed indicate only typical usages of that band in some countries. Other standards may also be used within those
bands.
b. TX power for channel 1 and channel 11 is specified separately by nonvolatile memory parameters to ensure band-edge compliance.
c. Optimal RF performance, as specified in this data sheet, is guaranteed only for temperatures between –10°C and 55°C.
15.4 General Spurious Emissions Specifications
Table 30. General Spurious Emissions Specifications
Parameter
Condition/Notes
Minimum
2400
General Spurious Emissions
Typical
Maximum
2500
Unit
Frequency range
–
–
MHz
30 MHz < f < 1 GHz
RBW = 100 kHz
RBW = 1 MHz
RBW = 1 MHz
RBW = 1 MHz
RBW = 100 kHz
RBW = 1 MHz
RBW = 1 MHz
RBW = 1 MHz
–
–
–
–
–
–
–
–
–99
–44
–68
–88
–99
–54
–88
–88
–96
–41
–65
–85
–96
–51
–85
–85
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
1 GHz < f < 12.75 GHz
1.8 GHz < f < 1.9 GHz
5.15 GHz < f < 5.3 GHz
30 MHz < f < 1 GHz
TX emissions
1 GHz < f < 12.75 GHz
1.8 GHz < f < 1.9 GHz
5.15 GHz < f < 5.3 GHz
RX/standby
emissions
Note: The specifications in this table apply at the chip port.
Document No. 002-14797 Rev. *I
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CYW4343W
16. Bluetooth RF Specifications
Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization.
Unless otherwise stated, limit values apply for the conditions specified in Table 24: “Environmental Ratings” and
Table 26: “Recommended Operating Conditions and DC Characteristics” . Typical values apply for the following conditions:
■ VBAT = 3.6V.
■ Ambient temperature +25°C.
Note: All Bluetooth specifications apply at the chip port. For the location of the chip port, see Figure 28: “RF Port Location,” on page
71.
Table 31. Bluetooth Receiver RF Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Unit
Note: The specifications in this table are measured at the chip output port unless otherwise specified.
General
Frequency range
RX sensitivity
–
2402
–
–
2480
–
MHz
dBm
GFSK, 0.1% BER, 1 Mbps
–94
/4–DQPSK, 0.01% BER,
2 Mbps
–
–96
–
dBm
8–DPSK, 0.01% BER, 3 Mbps
–
–16
–
–90
–
–
–
dBm
dBm
dBm
Input IP3
–
–
Maximum input at antenna
–
–20
Interference Performancea
C/I co-channel
GFSK, 0.1% BER
GFSK, 0.1% BER
GFSK, 0.1% BER
GFSK, 0.1% BER
GFSK, 0.1% BER
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
11
0.0
–30
–40
–9
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
C/I 1 MHz adjacent channel
C/I 2 MHz adjacent channel
C/I 3 MHz adjacent channel
C/I image channel
C/I 1 MHz adjacent to image channel GFSK, 0.1% BER
–20
13
C/I co-channel
/4–DQPSK, 0.1% BER
C/I 1 MHz adjacent channel
C/I 2 MHz adjacent channel
C/I 3 MHz adjacent channel
C/I image channel
/4–DQPSK, 0.1% BER
/4–DQPSK, 0.1% BER
/4–DQPSK, 0.1% BER
/4–DQPSK, 0.1% BER
0.0
–30
–40
–7
C/I 1 MHz adjacent to image channel /4–DQPSK, 0.1% BER
–20
21
C/I co-channel
8–DPSK, 0.1% BER
8–DPSK, 0.1% BER
8–DPSK, 0.1% BER
8–DPSK, 0.1% BER
8–DPSK, 0.1% BER
C/I 1 MHz adjacent channel
C/I 2 MHz adjacent channel
C/I 3 MHz adjacent channel
C/I Image channel
5.0
–25
–33
0.0
–13
C/I 1 MHz adjacent to image channel 8–DPSK, 0.1% BER
Out-of-Band Blocking Performance (CW)
30–2000 MHz
0.1% BER
–
–
–
–10.0
–27
–
–
–
dBm
dBm
dBm
2000–2399 MHz
2498–3000 MHz
0.1% BER
0.1% BER
–27
Document No. 002-14797 Rev. *I
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CYW4343W
Table 31. Bluetooth Receiver RF Specifications (Cont.)
Parameter
Conditions
0.1% BER
Minimum
Typical
Maximum
Unit
3000 MHz–12.75 GHz
–
–10.0
–
dBm
Out-of-Band Blocking Performance, Modulated Interferer (LTE)
GFSK (1 Mbps)
2310 MHz
2330 MHz
2350 MHz
2370 MHz
2510 MHz
2530 MHz
2550 MHz
2570 MHz
LTE band40 TDD 20M BW
LTE band40 TDD 20M BW
LTE band40 TDD 20M BW
LTE band40 TDD 20M BW
LTE band7 FDD 20M BW
LTE band7 FDD 20M BW
LTE band7 FDD 20M BW
LTE band7 FDD 20M BW
–
–
–
–
–
–
–
–
–20
–19
–20
–24
–24
–21
–21
–20
–
–
–
–
–
–
–
–
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
/4 DPSK (2 Mbps)
2310 MHz
2330 MHz
2350 MHz
2370 MHz
2510 MHz
2530 MHz
2550 MHz
2570 MHz
LTE band40 TDD 20M BW
LTE band40 TDD 20M BW
LTE band40 TDD 20M BW
LTE band40 TDD 20M BW
LTE band7 FDD 20M BW
LTE band7 FDD 20M BW
LTE band7 FDD 20M BW
LTE band7 FDD 20M BW
–
–
–
–
–
–
–
–
–20
–19
–20
–24
–24
–20
–20
–20
–
–
–
–
–
–
–
–
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
8DPSK (3 Mbps)
2310 MHz
2330 MHz
2350 MHz
2370 MHz
2510 MHz
2530 MHz
2550 MHz
2570 MHz
LTE band40 TDD 20M BW
LTE band40 TDD 20M BW
LTE band40 TDD 20M BW
LTE band40 TDD 20M BW
LTE band7 FDD 20M BW
LTE band7 FDD 20M BW
LTE band7 FDD 20M BW
LTE band7 FDD 20M BW
–
–
–
–
–
–
–
–
–20
–19
–20
–24
–24
–21
–20
–20
–
–
–
–
–
–
–
–
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
Out-of-Band Blocking Performance, Modulated Interferer (Non-LTE)
a
GFSK (1 Mbps)
698–716 MHz
776–849 MHz
824–849 MHz
824–849 MHz
880–915 MHz
880–915 MHz
1710–1785 MHz
WCDMA
WCDMA
GSM850
WCDMA
E-GSM
–
–
–
–
–
–
–
–12
–12
–12
–
–
–
–
–
–
–
dBm
dBm
dBm
dBm
dBm
dBm
dBm
–11
WCDMA
GSM1800
Document No. 002-14797 Rev. *I
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CYW4343W
Table 31. Bluetooth Receiver RF Specifications (Cont.)
Parameter Conditions
1710–1785 MHz
Minimum
Typical
Maximum
Unit
dBm
dBm
dBm
dBm
dBm
dBm
dBm
WCDMA
GSM1900
WCDMA
–
–
–
–
–
–
–
–
–
–
–
–
–
1850–1910 MHz
1850–1910 MHz
1880–1920 MHz
1920–1980 MHz
2010–2025 MHz
2500–2570 MHz
–17
–18
–18
–18
–21
TD-SCDMA
WCDMA
TD–SCDMA
WCDMA
–
a
/4 DPSK (2 Mbps)
698–716 MHz
WCDMA
WCDMA
GSM850
WCDMA
E-GSM
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–8
–8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
776–794 MHz
824–849 MHz
–9
824–849 MHz
–9
880–915 MHz
–8
880–915 MHz
WCDMA
GSM1800
WCDMA
GSM1900
WCDMA
TD-SCDMA
WCDMA
TD-SCDMA
WCDMA
–8
1710–1785 MHz
1710–1785 MHz
1850–1910 MHz
1850–1910 MHz
1880–1920 MHz
1920–1980 MHz
2010–2025 MHz
2500–2570 MHz
–14
–14
–15
–14
–16
–15
–17
–21
a
8DPSK (3 Mbps)
698–716 MHz
WCDMA
WCDMA
GSM850
WCDMA
E-GSM
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–11
–11
–11
–12
–11
–11
–16
–15
–17
–17
–17
–17
–18
–21
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
776–794 MHz
824–849 MHz
824–849 MHz
880–915 MHz
880–915 MHz
WCDMA
GSM1800
WCDMA
GSM1900
WCDMA
TD-SCDMA
WCDMA
TD-SCDMA
WCDMA
1710–1785 MHz
1710–1785 MHz
1850–1910 MHz
1850–1910 MHz
1880–1920 MHz
1920–1980 MHz
2010–2025 MHz
2500–2570 MHz
RX LO Leakage
2.4 GHz band
–
–
–90.0
–80.0
dBm
Document No. 002-14797 Rev. *I
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CYW4343W
Table 31. Bluetooth Receiver RF Specifications (Cont.)
Parameter Conditions
Spurious Emissions
Minimum
Typical
Maximum
Unit
30 MHz–1 GHz
–
–
–
–
–
–
–
–95
–70
–62
–47
–
dBm
1–12.75 GHz
dBm
869–894 MHz
925–960 MHz
1805–1880 MHz
1930–1990 MHz
2110–2170 MHz
–147
–147
–147
–147
–147
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
–
–
–
–
a. The Bluetooth reference level for the required signal at the Bluetooth chip port is 3 dB higher than the typical sensitivity level.
Table 32. LTE Specifications for Spurious Emissions
Parameter
Conditions
Typical
–147
Unit
2500–2570 MHz
2300–2400 MHz
2570–2620 MHz
2545–2575 MHz
Band 7
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
Band 40
Band 38
XGP Band
–147
–147
–147
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CYW4343W
Table 33. Bluetooth Transmitter RF Specificationsa
Parameter Conditions
General
Minimum
Typical
Maximum
Unit
Frequency range
2402
–
12.0
8.0
8.0
4
2480
MHz
dBm
dBm
dBm
dB
Basic rate (GFSK) TX power at Bluetooth
QPSK TX power at Bluetooth
–
–
–
2
–
–
–
8
8PSK TX power at Bluetooth
Power control step
–20 dBc BW
–
–
GFSK In-Band Spurious Emissions
EDR In-Band Spurious Emissions
–
0.93
1
MHz
1.0 MHz < |M – N| < 1.5 MHz
1.5 MHz < |M – N| < 2.5 MHz
M – N = the frequency range for which
the spurious emission is measured
relative to the transmit center
frequency.
–
–
–
–38
–31
–43
–26.0
–20.0
–40.0
dBc
dBm
dBm
b
|M – N| 2.5 MHz
Out-of-Band Spurious Emissions
c,d
30 MHz to 1 GHz
–
–
–
–
–
–
–
–
–
–36.0
–30.0
dBm
dBm
dBm
dBm
d,e,f
1 GHz to 12.75 GHz
1.8 GHz to 1.9 GHz
5.15 GHz to 5.3 GHz
–
–
–47.0
–
–47.0
–
GPS Band Spurious Emissions
Spurious emissions
–
–
–103
dBm
Out-of-Band Noise Floorg
65–108 MHz
FM RX
–
–
–
–
–
–
–
–
–147
–146
–146
–146
–146
–144
–143
–137
–
–
–
–
–
–
–
–
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
776–794 MHz
869–960 MHz
925–960 MHz
1570–1580 MHz
1805–1880 MHz
1930–1990 MHz
2110–2170 MHz
CDMA2000
cdmaOne, GSM850
E-GSM
GPS
GSM1800
GSM1900, cdmaOne, WCDMA
WCDMA
a. Unless otherwise specified, the specifications in this table apply at the chip output port, and output power specifications are with the temperature
correction algorithm and TSSI enabled.
b. Typically measured at an offset of ±3 MHz.
c. The maximum value represents the value required for Bluetooth qualification as defined in the v4.1 specification.
d. The spurious emissions during Idle mode are the same as specified in Table 33.
e. Specified at the Bluetooth antenna port.
f. Meets this specification using a front-end band-pass filter.
g. Transmitted power in cellular and FM bands at the Bluetooth antenna port. See Figure 28 for location of the port.
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CYW4343W
Table 34. LTE Specifications for Out-of-Band Noise Floor
Parameter
Conditions
Typical
–130
Unit
2500–2570 MHz
2300–2400 MHz
2570–2620 MHz
2545–2575 MHz
Band 7
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
Band 40
Band 38
XGP Band
–130
–130
–130
Table 35. Local Oscillator Performance
Parameter
Minimum
Typical
Maximum
Unit
LO Performance
Lock time
–
–
72
–
s
Initial carrier frequency tolerance
±25
±75
kHz
Frequency Drift
DH1 packet
DH3 packet
DH5 packet
Drift rate
–
–
–
–
±8
±8
±8
5
±25
±40
±40
20
kHz
kHz
kHz
kHz/50 µs
Frequency Deviation
a
00001111 sequence in payload
140
115
–
155
140
1
175
–
kHz
kHz
MHz
b
10101010 sequence in payload
Channel spacing
–
a. This pattern represents an average deviation in payload.
b. Pattern represents the maximum deviation in payload for 99.9% of all frequency deviations.
Table 36. BLE RF Specifications
Parameter
Frequency range
Conditions
Minimum
Typical
–
Maximum
Unit
MHz
dBm
dBm
kHz
%
–
2402
–
2480
a
RX sense
GFSK, 0.1% BER, 1 Mbps
–97
8.5
–
–
b
TX power
–
–
–
–
–
Mod Char: delta f1 average
225
99.9
0.8
255
–
275
–
c
Mod Char: delta f2 max
Mod Char: ratio
0.95
–
%
a. The Bluetooth tester is set so that Dirty TX is on.
b. BLE TX power can be increased to compensate for front-end losses such as BPF, diplexer, switch, etc.). The output is capped at 12 dBm.
The BLE TX power at the antenna port cannot exceed the 10 dBm specification limit.
c. At least 99.9% of all delta F2 max. frequency values recorded over 10 packets must be greater than 185 kHz.
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CYW4343W
17. Internal Regulator Electrical Specifications
Note: Values in this data sheet are design goals and are subject to change based on device characterization results.
Functional operation is not guaranteed outside of the specification limits provided in this section.
17.1 Core Buck Switching Regulator
Table 37. Core Buck Switching Regulator (CBUCK) Specifications
Specification
Notes
Min.
Typ.
Max.
Units
a
Input supply voltage (DC)
DC voltage range inclusive of disturbances.
2.4
3.6
4.8
V
PWM mode switching
frequency
CCM, load > 100 mA VBAT = 3.6V.
–
4
–
MHz
PWM output current
Output current limit
–
–
–
–
–
370
–
mA
mA
1400
Programmable, 30 mV steps.
Default = 1.35V.
Output voltage range
1.2
–4
1.35
–
1.5
4
V
PWM output voltage
DC accuracy
Includes load and line regulation.
Forced PWM mode.
%
Measure with 20 MHz bandwidth limit.
Static load, max. ripple based on VBAT = 3.6V,
Vout = 1.35V,
PWM ripple voltage, static
–
7
20
mVpp
Fsw = 4 MHz, 2.2 μH inductor L > 1.05 μH, Cap + Board
total-ESR < 20 mΩ,
C
> 1.9 μF, ESL<200 pH
out
Peak efficiency at 200 mAload, inductor DCR = 200 mΩ,
VBAT = 3.6V, VOUT = 1.35V
PWM mode peak efficiency
PFM mode efficiency
–
–
–
–
85
77
–
–
%
%
10 mA load current, inductor DCR = 200 mΩ, VBAT =
3.6V, VOUT = 1.35V
Start-up time from
power down
VDDIO already ON and steady.
Time from REG_ON rising edge to CLDO reaching 1.2V
400
2.2
4.7
500
–
µs
µH
µF
0603 size, 2.2 μH ±20%,
DCR = 0.2Ω ± 25%
External inductor
Ceramic, X5R, 0402,
ESR <30 mΩ at 4 MHz, 4.7 μF ±20%, 10V
b
c
External output capacitor
2.0
10
For SR_VDDBATP5V pin,
ceramic, X5R, 0603,
ESR < 30 mΩ at 4 MHz, ±4.7 μF ±20%, 10V
b
External input capacitor
0.67
40
4.7
–
–
–
µF
µs
Input supply voltage ramp-up time 0 to 4.3V
a. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are
allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed.
b. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and
aging.
c. Total capacitance includes those connected at the far end of the active load.
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CYW4343W
17.2 3.3V LDO (LDO3P3)
Table 38. LDO3P3 Specifications
Specification
Notes
Min.
Typ.
Max.
Units
Min. = V + 0.2V = 3.5V dropout voltage requirement
must be met under maximum load for performance
specifications.
o
a
Input supply voltage, V
Output current
3.1
3.6
4.8
V
in
–
0.001
–
3.3
–
450
–
mA
V
Nominal output voltage, V
Dropout voltage
Default = 3.3V.
At max. load.
–
–
o
200
+5
mV
Output voltage DC accuracy
Quiescent current
Line regulation
Includes line/load regulation.
No load
–5
–
–
%
66
–
85
µA
V
from (V + 0.2V) to 4.8V, max. load
–
3.5
0.3
mV/V
mV/mA
in
o
Load regulation
load from 1 mA to 450 mA
–
–
V
≥ V + 0.2V,
in
o
PSRR
V = 3.3V, C = 4.7 µF,
20
–
–
–
dB
o
o
Max. load, 100 Hz to 100 kHz
LDO turn-on time
Chip already powered up.
160
4.7
250
µs
µF
Ceramic, X5R, 0402,
(ESR: 5 mΩ–240 mΩ), ± 10%, 10V
b
External output capacitor, C
1.0
5.64
o
For SR_VDDBATA5V pin (shared with band gap)
Ceramic, X5R, 0402,
(ESR: 30m-200 mΩ), ± 10%, 10V.
Not needed if sharing VBAT capacitor 4.7 µF with
SR_VDDBATP5V.
External input capacitor
–
4.7
–
µF
a. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are
allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed.
b. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and
aging.
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CYW4343W
17.3 CLDO
Table 39. CLDO Specifications
Specification
Notes
Min. Typ. Max.
Units
V
Min. = 1.2 + 0.15V = 1.35V dropout voltage requirement
must be met under maximum load.
Input supply voltage, V
Output current
1.3
0.2
1.35
–
1.5
200
1.26
in
–
mA
V
Programmable in 10 mV steps.
Default = 1.2.V
Output voltage, V
Dropout voltage
0.95
1.2
o
At max. load
–
–4
–
–
–
150
+4
–
mV
%
Output voltage DC accuracy
Includes line/load regulation
No load
13
1.24
µA
mA
Quiescent current
200 mA load
–
–
V
from (V + 0.15V) to 1.5V,
o
in
Line regulation
Load regulation
–
–
5
mV/V
maximum load
Load from 1 mA to 300 mA
Power down
–
–
0.02 0.05
mV/mA
µA
5
1
–
20
3
Leakage current
PSRR
Bypass mode
–
µA
@1 kHz, Vin ≥ 1.35V, C = 4.7 µF
20
–
dB
o
VDDIO up and steady. Time from the REG_ON rising edge
to the CLDO
reaching 1.2V.
Start-up time of PMU
LDO turn-on time
–
–
–
700
µs
LDO turn-on time when rest of the
chip is up.
140
2.2
180
–
µs
µF
a
External output capacitor, C
Total ESR: 5 mΩ–240 mΩ
1.1
o
Only use an external input capacitor
at the VDD_LDO pin if it is not supplied
from CBUCK output.
External input capacitor
–
1
2.2
µF
a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and
aging.
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CYW4343W
17.4 LNLDO
Table 40. LNLDO Specifications
Specification
Notes
Min. V = V + 0.15V = 1.35V
Min.
Typ.
Max.
Units
IN
O
Input supply voltage, Vin
Output current
(where V = 1.2V) dropout voltage requirement must be
met under maximum load.
1.3
1.35
1.5
V
O
–
0.1
1.1
–
150
mA
V
Programmable in 25 mV steps.
Default = 1.2V
Output voltage, V
1.2
1.275
o
Dropout voltage
At maximum load
Includes line/load regulation
No load
–
–4
–
–
–
150
+4
mV
%
Output voltage DC accuracy
Quiescent current
10
970
12
µA
µA
Max. load
–
990
V
from (V + 0.15V) to 1.5V,
o
in
Line regulation
–
–
5
mV/V
200 mA load
Load from 1 mA to 200 mA:
Load regulation
Leakage current
Output noise
–
–
–
0.025
0.045
20
mV/mA
µA
V
≥ (V + 0.12V)
in
o
Power-down, junction temp. = 85°C
@30 kHz, 60–150 mA load C = 2.2 µF
@100 kHz, 60–150 mA load C = 2.2 µF
5
–
60
35
o
nV/ Hz
–
o
PSRR
@1 kHz, V ≥ (V + 0.15V), C = 4.7 µF
20
–
–
–
dB
µs
in
o
o
LDO turn-on time
LDO turn-on time when rest of chip is up
140
180
Total ESR (trace/capacitor):
5 mΩ–240 mΩ
a
External output capacitor, C
0.5
2.2
4.7
µF
o
Only use an external input capacitor at the VDD_LDO pin
if it is not supplied from CBUCK output.
External input capacitor
–
1
2.2
µF
Total ESR (trace/capacitor): 30 mΩ–200 mΩ
a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and
aging.
Document No. 002-14797 Rev. *I
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CYW4343W
18. System Power Consumption
Note: The values in this data sheet are design goals and are subject to change based on device characterization.Unless otherwise
stated, these values apply for the conditions specified in Table 26: “Recommended Operating Conditions and DC Characteristics” .
18.1 WLAN Current Consumption
Table 41 shows typical currents consumed by the CYW4343W’s WLAN section. All values shown are with the Bluetooth core in Reset
mode with Bluetooth off.
18.1.1 2.4 GHz Mode
Table 41. 2.4 GHz Mode WLAN Power Consumption
VBAT = 3.6V, VDDIO = 1.8V, TA 25°C
Mode
Rate
VBAT (mA)
Vio (µA)
Sleep Modes
Leakage (OFF)
N/A
N/A
0.0035
0.08
80
a
Sleep (idle, unassociated)
0.0058
0.0058
1.05
b
Sleep (idle, associated, inter-beacons)
Rate 1
Rate 1
Rate 1
Rate 1
Rate 1
80
c
IEEE Power Save PM1 DTIM1 (Avg.)
IEEE Power Save PM1 DTIM3 (Avg.)
IEEE Power Save PM2 DTIM1 (Avg.)
IEEE Power Save PM2 DTIM3 (Avg.)
74
d
c
d
0.35
86
1.05
74
0.35
86
Active Modes
e
Rx Listen Mode
N/A
37
12
12
12
12
12
15
15
15
15
Rate 1
39
Rate 11
40
f
Rx Active (at –50dBm RSSI)
Rate 54
40
Rate MCS7
41
Rate 1 @ 20 dBm
Rate 11 @ 18 dBm
Rate 54 @ 15 dBm
Rate MCS7 @ 15 dBm
320
290
260
260
f
Tx
a. Device is initialized in Sleep mode, but not associated.
b. Device is associated, and then enters Power Save mode (idle between beacons).
c. Beacon interval = 100 ms; beacon duration = 1 ms @ 1 Mbps (Integrated Sleep + wakeup + beacon).
d. Beacon interval = 300 ms; beacon duration = 1 ms @ 1 Mbps (Integrated Sleep + wakeup + beacon).
e. Carrier sense (CCA) when no carrier present.
f. Tx output power is measured on the chip-out side; duty cycle =100%. Tx Active mode is measured in Packet Engine mode (pseudo-random
data)
Document No. 002-14797 Rev. *I
Page 88 of 103
CYW4343W
18.2 Bluetooth Current Consumption
The Bluetooth current consumption measurements are shown in Table 42.
Note:
■ The WLAN core is in reset (WLAN_REG_ON = low) for all measurements provided in Table 42.
■ The BT current consumption numbers are measured based on GFSK TX output power = 10 dBm.
Table 42. Bluetooth BLE Current Consumption
VBAT (VBAT = 3.6V)
Typical
VDDIO (VDDIO = 1.8V)
Operating Mode
Units
Typical
150
162
172
–
Sleep
6
µA
µA
Standard 1.28s Inquiry Scan
500 ms Sniff Master
DM1/DH1 Master
193
305
23.3
28.4
29.1
25.1
11.8
187
93
µA
mA
mA
mA
mA
mA
µA
DM3/DH3 Master
–
DM5/DH5 Master
–
3DH5/3DH5 Master
SCO HV3 Master
–
–
a
BLE Scan
164
163
163
BLE Adv. – Unconnectable 1.00 sec
BLE Connected 1 sec
µA
71
µA
a. No devices present. A 1.28 second interval with a scan window of 11.25 ms.
Document No. 002-14797 Rev. *I
Page 89 of 103
CYW4343W
19. Interface Timing and AC Characteristics
Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization.
Unless otherwise stated, the specifications in this section apply when the operating conditions are within the limits specified in Table
24 and Table 26. Functional operation outside of these limits is not guaranteed.
19.1 SDIO Default Mode Timing
SDIO default mode timing is shown by the combination of Figure 29 and Table 43.
Figure 29. SDIO Bus Timing (Default Mode)
fPP
tW L
tW H
SDIO_CLK
tTHL
tTLH
tIH
tISU
Input
Output
tODLY
tODLY
(max)
(m in)
Table 43. SDIO Bus Timing a Parameters (Default Mode)
Parameter
Symbol
Minimum
Typical
Maximum
Unit
SDIO CLK (All values are referred to minimum VIH and maximum VILb)
Frequency—Data Transfer mode
Frequency—Identification mode
Clock low time
fPP
fOD
0
0
–
–
–
–
–
–
25
400
–
MHz
kHz
ns
tWL
tWH
tTLH
tTHL
10
10
–
Clock high time
–
ns
Clock rise time
10
10
ns
Clock fall time
–
ns
Inputs: CMD, DAT (referenced to CLK)
Input setup time
Input hold time
tISU
tIH
5
5
–
–
–
–
ns
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time—Data Transfer mode
Output delay time—Identification mode
tODLY
tODLY
0
0
–
–
14
50
ns
ns
a. Timing is based on CL 40 pF load on command and data.
b. min(Vih) = 0.7 × VDDIO and max(Vil) = 0.2 × VDDIO.
Document No. 002-14797 Rev. *I
Page 90 of 103
CYW4343W
19.2 SDIO High-Speed Mode Timing
SDIO high-speed mode timing is shown by the combination of Figure 30 and Table 44.
Figure 30. SDIO Bus Timing (High-Speed Mode)
fPP
tWL
tWH
50% VDD
SDIO_CLK
tTHL
tTLH
tIH
tISU
Input
Output
tODLY
tOH
Table 44. SDIO Bus Timing a Parameters (High-Speed Mode)
Parameter Symbol
SDIO CLK (all values are referred to minimum VIH and maximum VILb)
Minimum
Typical
Maximum
Unit
Frequency – Data Transfer Mode
Frequency – Identification Mode
Clock low time
fPP
fOD
0
0
7
7
–
–
–
–
–
–
–
–
50
400
–
MHz
kHz
ns
tWL
Clock high time
tWH
tTLH
tTHL
–
ns
Clock rise time
3
ns
Clock fall time
3
ns
Inputs: CMD, DAT (referenced to CLK)
Input setup time
Input hold time
tISU
tIH
6
2
–
–
–
–
ns
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer Mode
Output hold time
tODLY
tOH
–
2.5
–
–
–
–
14
–
ns
ns
pF
Total system capacitance (each line)
CL
40
a. Timing is based on CL 40 pF load on command and data.
b. min(Vih) = 0.7 × VDDIO and max(Vil) = 0.2 × VDDIO.
Document No. 002-14797 Rev. *I
Page 91 of 103
CYW4343W
19.3 JTAG Timing
Table 45. JTAG Timing Characteristics
Signal Name
Output
Maximum
Output
Minimum
Period
Setup
Hold
TCK
125 ns
–
–
–
–
20 ns
20 ns
–
–
0 ns
0 ns
–
TDI
–
–
TMS
–
–
–
100 ns
–
–
TDO
0 ns
–
JTAG_TRST
250 ns
–
–
Document No. 002-14797 Rev. *I
Page 92 of 103
CYW4343W
20. Power-Up Sequence and Timing
20.1 Sequencing of Reset and Regulator Control Signals
The CYW4343W has two signals that allow the host to control power consumption by enabling or disabling the Bluetooth, WLAN, and
internal regulator blocks. These signals are described below. Additionally, diagrams are provided to indicate proper sequencing of the
signals for various operational states (see Figure 31 through Figure 34). The timing values indicated are minimum required values;
longer delays are also acceptable.
Note:
■ The WL_REG_ON and BT_REG_ON signals are OR’ed in the CYW4343W. The diagrams show both signals going high at the
same time (as would be the case if both REG signals were controlled by a single host GPIO). If two independent host GPIOs are
used (one for WL_REG_ON and one for BT_REG_ON), then only one of the two signals needs to be high to enable the CYW4343W
regulators.
■ The CYW4343W has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 110 ms after VDDC
and VDDIO have both passed the POR threshold (see Table 26: “Recommended Operating Conditions and DC Characteristics” ).
Wait at least 150 ms after VDDC and VDDIO are available before initiating SDIO accesses.
■ VBAT and VDDIO should not rise faster than 40 µs. VBAT should be up before or at the same time as VDDIO. VDDIO should not
be present first or be held high before VBAT is high.
20.1.1 Description of Control Signals
■ WL_REG_ON: Used by the PMU to power up the WLAN section. It is also OR-gated with the BT_REG_ON input to control the
internal CYW4343W regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this
pin is low the WLAN section is in reset. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled.
■ BT_REG_ON: Used by the PMU (OR-gated with WL_REG_ON) to power up the internal CYW4343W regulators. If both the
BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. When this pin is low and WL_REG_ON is high, the BT
section is in reset.
Note: For both the WL_REG_ON and BT_REG_ON pins, there should be at least a 10 ms time delay between consecutive toggles
(where both signals have been driven low). This is to allow time for the CBUCK regulator to discharge. If this delay is not followed,
then there may be a VDDIO in-rush current on the order of 36 mA during the next PMU cold start.
Document No. 002-14797 Rev. *I
Page 93 of 103
CYW4343W
20.1.2 Control Signal Timing Diagrams
Figure 31. WLAN = ON, Bluetooth = ON
32.678 kHz
Sleep Clock
VBAT
90% of VH
VDDIO
~ 2 Sleep cycles
WL_REG_ON
BT_REG_ON
Figure 32. WLAN = OFF, Bluetooth = OFF
32.678 kHz
Sleep Clock
VBAT
VDDIO
WL_REG_ON
BT_REG_ON
Document No. 002-14797 Rev. *I
Page 94 of 103
CYW4343W
Figure 33. WLAN = ON, Bluetooth = OFF
32.678 kHz
Sleep Clock
VBAT
90% of VH
VDDIO
~ 2 Sleep cycles
WL_REG_ON
BT_REG_ON
Figure 34. WLAN = OFF, Bluetooth = ON
32.678 kHz
Sleep Clock
VBAT
90% of VH
VDDIO
~ 2 Sleep cycles
WL_REG_ON
BT_REG_ON
Document No. 002-14797 Rev. *I
Page 95 of 103
CYW4343W
21. Package Information
21.1 Package Thermal Characteristics
Table 46. Package Thermal Characteristicsa
Characteristic
Value in Still Air
JA (°C/W)
JB (°C/W)
JC (°C/W)
53.11
13.14
6.36
0.04
14.21
125
(°C/W)
JT
(°C/W)
JB
b
Maximum Junction Temperature T (°C)
j
Maximum Power Dissipation (W)
1.2
a. No heat sink, TA = 70°C. This is an estimate based on a 4-layer PCB that conforms to EIA/JESD51–7
(101.6 mm x 114.3 mm x 1.6 mm) and P = 1.2W continuous dissipation.
b. Absolute junction temperature limits maintained through active thermal monitoring and dynamic TX duty cycle limiting.
21.1.1 Junction Temperature Estimation and PSI Versus Thetajc
Package thermal characterization parameter PSI-JT ( ) yields a better estimation of actual junction temperature (T ) versus using
JT
J
the junction-to-case thermal resistance parameter Theta-J (JC). The reason for this is JC assumes that all the power is dissipated
C
through the top surface of the package case. In actual applications, some of the power is dissipated through the bottom and sides of
the package. takes into account power dissipated through the top, bottom, and sides of the package. The equation for calculating
JT
the device junction temperature is as follows:
T = T + P
J
T
JT
Where:
■
T = junction temperature at steady-state condition, °C
J
■
T = package case top center temperature at steady-state condition, °C
T
■
■
P = device power dissipation, Watts
= package thermal characteristics (no airflow), °C/W
JT
Document No. 002-14797 Rev. *I
Page 96 of 103
CYW4343W
22. Mechanical Information
Figure 35 shows the mechanical drawing for the CYW4343W WLBGA package.
Figure 35. 74-Ball WLBGA Mechanical Information
Figure 36 shows the mechanical drawing for the CYW4343W WLCSP package. Figure 37 shows the WLCSP keep-out areas.
Document No. 002-14797 Rev. *I
Page 97 of 103
CYW4343W
Figure 36. 153-Bump WLCSP Mechanical Information
Note: No top-layer metal is allowed in the keep-out areas
Note: A DXF file containing WLBGA keep-outs can be imported into a layout program. Contact your Cypress FAE for more
information.
Document No. 002-14797 Rev. *I
Page 98 of 103
CYW4343W
Figure 37. WLCSP Package Keep-Out Areas—Top View with the Bumps Facing Down
Document No. 002-14797 Rev. *I
Page 99 of 103
CYW4343W
Figure 38. WLBGA Package Keep-Out Areas—Top View with the Bumps Facing Down
Document No. 002-14797 Rev. *I
Page 100 of 103
CYW4343W
23. Ordering Information
Table 47. Part Ordering Information
Part Number a
Operating Ambient
Temperature
Package
Description
74-ball WLBGA halogen-free package
(4.87 mm x 2.87 mm, 0.40 pitch)
2.4 GHz single-band WLAN
IEEE 802.11n + BT 4.1
CYW4343WKUBG
CYW4343WKWBG
–30°C to +70°C
–30°C to +70°C
2.4 GHz single-band WLAN
IEEE 802.11n + BT 4.1
153-bump WLCSP
a. Add “T” to the end of the part number to specify “Tape and Reel.”
24. Additional Information
24.1 Acronyms and Abbreviations
In most cases, acronyms and abbreviations are defined upon first use. For a more complete list of acronyms and other terms used in
Cypress documents, go to: http://www.cypress.com/glossary.
diagrams, product bill of materials, PCB layout information, and
software updates. Customers can acquire technical documen-
tation and software from the Cypress Support Community
website
24.2 IoT Resources
Cypress provides a wealth of data at http://www.cypress.com/
internet-things-iot to help you to select the right IoT device for
your design, and quickly and effectively integrate the device into
your design. Cypress provides customer access to a wide range
of information, including technical documentation, schematic
(http://community.cypress.com/).
Document No. 002-14797 Rev. *I
Page 101 of 103
CYW4343W
Document History Page
Document Title: CYW4343W Single-Chip 802.11 b/g/n MAC/Baseband/Radio with Bluetooth 4.1
Document Number: 002-14797
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
-
-
-
-
-
-
-
-
03/10/2014 4343W-DS100-R
Initial release
*A
*B
*C
*D
*E
*F
-
-
-
-
-
-
04/18/2014 4343W-DS101-R
Refer to the earlier release for detailed revision history.
06/09/2014 4343W-DS102-R
Refer to the earlier release for detailed revision history
09/05/2014 4343W-DS103-R
Refer to the earlier release for detailed revision history
10/03/2014 4343W-DS104-R
Refer to the earlier release for detailed revision history
01/12/2015 4343W-DS105-R
Refer to the earlier release for detailed revision history
07/01/2015 4343W-DS106-R
Updated:
Table 22, “I/O States”.
Table 25, “ESD Specifications”.
Table 28, “WLAN 2.4 GHz Receiver Performance Specifications”.
Table 29, “WLAN 2.4 GHz Transmitter Performance Specifications”.
Table 41, “2.4 GHz Mode WLAN Power Consumption”.
Table 47, “Part Ordering Information”
*G
-
-
08/24/15
4343W-DS107-R
Updated:
Figure3: “Typical Power Topology (1 of 2), and
Figure4: “Typical Power Topology (2 of 2),.
Table 2:“Crystal Oscillator and External Clock Requirements and Performance”.
Table23:“I/O States”.
*H
*I
5445248
5600195
UTSV
SGUP
10/19/2016 Migrated to Cypress template format
Added Cypress part numbering scheme
01/12/2017 Removed FM Receiver and wireless Charging from the topic.
Removed FM from Figure 1, Figure 2, Figure 3, Figure 4.
Removed “8.4 Generic SPI mode” and “SPI Protocol”.
Removed FM from Section 7: “Bluetooth Subsystem Overview” on page 23.
Removed “8.5.1.FM power Management” and “8.6.3 FM over Bluetooth”.
Updated Figure 25 (removed SPI).
Removed Section 18: FM Receiver Specifications”.
Removed FMRX from the Ordering Information.
Document Number: 002-14797 Rev. *I
Page 102 of 103
CYW4343W
Sales, Solutions, and Legal Information
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closest to you, visit us at Cypress Locations.
®
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®
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cypress.com/arm
cypress.com/automotive
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PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
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Forums | WICED IoT Forums | Projects | Video | Blogs |
Training | Components
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Technical Support
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USB Controllers
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cypress.com/wireless
103
© Cypress Semiconductor Corporation, 2014-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 002-14797 Rev. *I
Revised March 28, 2017
Page 103 of 103
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