MB39C011AEVB-01 [CYPRESS]
2ch DC/DC Converter IC with Synchronous Rectification Datasheet;
| 型号： | MB39C011AEVB-01 |
| 厂家： | 
CYPRESS |
| 描述： | 2ch DC/DC Converter IC with Synchronous Rectification Datasheet |
| 文件： | 总53页 (文件大小：1523K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MB39C011A
2ch DC/DC Converter IC with
Synchronous Rectification Datasheet
The MB39C011A is a two-channel DC/DC converter IC suitable for down-conversion that utilizes synchronous rectification and pulse
width modulation (PWM). The MB39C011A can operate over a wide range of power supply voltages (4.5 V to 17 V), making it optimal
as a built-in power supply in digital audio visual equipment and various other electronic devices.
Features
■ Wide range of power supply voltages: 4.5 V to 17 V
■ Supports high frequency operation: 2.0 MHz (Max)
■ Supports synchronous rectification method (CH1, CH2)
■ An arbitrary output voltage can be configured using an external resistance.
■ Built-in standby function: 0 μA (Typ)
■ Low current consumption: 2.2 mA (Typ, At quiescence)
■ Built-in soft-start circuit that can control each channel separately independent of the load
■ Built-in timer latch type short-circuit protection circuit (shares the soft-start capacitor)
■ Built-in totem pole type output stage for external P-ch/N-ch MOS FET devices
■ Package : TSSOP-16-pin
Applications
Digital TV
Photocopiers
Surveillance cameras
Set-top boxes (STB)
DVD players, DVD recorders
Projectors
IP phones
Vending machines
Consoles and other non-portable devices
Cypress Semiconductor Corporation
Document Number: 002-08369 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 24, 2017
MB39C011A
Contents
1.
2.
3.
4.
5.
6.
7.
8.
Pin Assignment............................................................. 3
23. Ordering Information.................................................. 46
24. EV Board Ordering Information................................. 46
Pin Description ............................................................ 4
Block Diagram............................................................... 5
Absolute Maximum Ratings......................................... 6
Recommended Operating Conditions ........................ 7
Electrical Characteristics............................................. 8
Typical Characteristics............................................... 10
Functional Description............................................... 12
25. RoHS Compliance Information Of Lead (Pb) Free
Version......................................................................... 47
26. Marking Format (Lead-free version) ........................ 47
27. Labeling Sample (Lead-free version) ....................... 48
28. MB39C011APFT-❏❏❏E1 Recommended Mounting
Conditions................................................................... 49
28.1 Recommended Mounting Conditions............................ 49
28.2 Parameters for Each Mounting Method........................ 50
8.1 DC/DC Converter Block................................................ 12
8.2 Protection Function....................................................... 13
29. Package Dimensions.................................................. 51
9.
Switching Scheme Selection..................................... 20
10. Setting The Output Voltage........................................ 21
11. Setting The Triangular Oscillation Frequency ......... 22
11.1 Power Dissipation and Thermal Design........................ 22
12. Setting The Soft-start And Short-circuit Detection
Times............................................................................ 24
13. VB Pin And VH Pin Connections In Condition
Of Vcc Voltage............................................................. 24
14. Design Of Phase Compensation Circuit................... 26
14.1 Phase compensation circuit when low ESR capacitor is
used as output capacitor............................................... 26
14.2 Notes on Phase Compensation Circuit Constants........ 27
15. Handling the Unused Channel Pins when using
a Single Channel......................................................... 29
16. I/O Equivalent Circuit ................................................. 31
17. Example Application Circuit ...................................... 33
18. Parts List ..................................................................... 34
19. Part Selection.............................................................. 35
19.1 Coil selection ................................................................ 35
19.2 SW FET selection......................................................... 36
19.3 Fly-back Diode Selection.............................................. 38
19.4 Output capacitor selection ............................................ 39
19.5 Input capacitor selection............................................... 39
19.6 VB pin capacitor............................................................ 40
19.7 VH pin capacitor ........................................................... 40
20. PCB Layout ................................................................ 41
21. Reference Data............................................................ 43
22. Usage Precaution ....................................................... 45
22.1 Do not configure the IC over the maximum ratings ...... 45
22.2 Use the device within the recommended operating
conditions...................................................................... 45
22.3 Printed circuit board ground lines should be set up with
consideration for common Impedance.......................... 45
22.4 Take appropriate measures against static electricity.... 45
22.5 Do not apply negative voltages..................................... 45
Document Number: 002-08369 Rev. *B
Page 2 of 53
MB39C011A
1. Pin Assignment
(TOP VIEW)
16
15
14
13
12
11
10
9
VCC
OUT1-1
OUT1-2
VB
1
2
3
4
5
6
7
8
VH
OUT2-1
OUT2-2
CTL
RT
GND
FB1
FB2
-INE1
CSCP1
-INE2
CSCP2
(FPT-16P-M07)
Document Number: 002-08369 Rev. *B
Page 3 of 53
MB39C011A
2. Pin Description
Pin No.
Pin Name
I/O
-
O
O
I/O
-
Description
1
2
VCC
Power supply pin for the reference voltage circuit and control circuit.
OUT1-1
OUT1-2
VB
Output pin for P-ch drive (drives the gate of the external High side FET).
Output pin for N-ch drive (drives the gate of the external Low side FET).
Power supply pin for the N-ch FET drive circuit (VB = 5 V).
Triangular-wave oscillation frequency setting resistor connection pin.
Error amplifier (Error Amp1) output pin.
3
4
5
RT
6
FB1
O
7
-INE1
CSCP1
CSCP2
-INE2
FB2
I
Error amplifier (Error Amp1) inverted input pin.
8
-
-
Timer-latch short-circuit protection circuit 1 capacitor connection pin.
Timer-latch short-circuit protection circuit 2 capacitor connection pin.
Error amplifier (Error Amp2) inverted input pin.
9
10
11
12
13
14
15
16
I
O
-
Error amplifier (Error Amp2) output pin.
GND
Ground pin for the reference voltage circuit, control circuit, and output circuit.
Power supply control pin. IC becomes a stand-by mode by setting CTL pin “L” level.
Output pin for N-ch drive (drives the gate of the external Low side FET).
Output pin for P-ch drive (drives the gate of the external High side FET).
Power supply pin for the N-ch FET drive circuit (VH = VCC − 5 V).
CTL
I
OUT2-2
OUT2-1
VH
O
O
O
Document Number: 002-08369 Rev. *B
Page 4 of 53
MB39C011A
3. Block Diagram
-INE1
step-down
Vo1
A
7
VB
VB
VB
VB
<< CH1 >>
Vcc
(1.8 V)
A
Error
Amp1
PWM
Comp.1
(2.3u) (1.0u)
(2.3u) (1.0u)
Drive1-1
P-ch
OUT1-1
OUT1-2
2
3
(1.0 V)
FB1
Drive1-2
N-ch
6
step-down
B
Vo2
(3.3 V)
-INE2
<< CH2 >>
B
10
Error
Amp2
PWM
Comp.2
Drive2-1
P-ch
OUT2-1
OUT2-2
15
14
V
IN
(6 V to 17 V)
(1.0 V)
FB2
11
Drive2-2
N-ch
2.5 V
SCP
Comp.2
(1.7 V)
(0.7 V)
(1.7 V)
CSCP2
(1.9 V)
VB
9
4
(0.7 V)
2.5 V
SCP
(2.0 V)
Comp.1
VH
(Vcc-5 V)
16
VH
(1.9 V)
Bias
Voltage
CSCP1
8
SR Latch
Reset
(2.0 V)
UVLO
VCC
CTL
1
VB
(5 V)
ErrorAmp Ref.
(1.0 V)
OSC
Power
ON/OFF
CTL
Bias
Voltage
bias
13
H:ON (Power ON)
L:OFF(Standbymode)
VTH=1.4 V
VR1
CT
12
5
GND
RT
Document Number: 002-08369 Rev. *B
Page 5 of 53
MB39C011A
4. Absolute Maximum Ratings
Rating
Parameter
Symbol
Condition
Unit
Min
Max
18
Power supply voltage
V
VCC pin
-
V
V
CC
V
VB pin (When VCC pin connected to VB pin)
-
− 0.3
-
-
-
7
B
Input voltage
V
-INE1, -INE2 pins
V
V
INE
B
V
CTL pin
18
60
V
CTL
Output current
I
OUT1-1, OUT1-2, OUT2-1, OUT2-2 pins
mA
mA
O
Peak output current
Power dissipation
Storage temperature
I
Duty ≤ 5% (t = 1/fosc × Duty)
700
OP
[1]
P
Ta ≤ + 25˚C
-
− 55
1060
+ 125
mW
D
T
-
˚C
STG
[1] : When mounted on a 10 cm square double-sided epoxy circuit board.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in
excess of absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-08369 Rev. *B
Page 6 of 53
MB39C011A
5. Recommended Operating Conditions
Value
Typ
12
Parameter
Symbol
Condition
Unit
Min
4.5
0
Max
Power supply voltage
V
I
VCC pin
VH pin
VB pin
17
V
CC
VH pin output current
VB pin output current
-
-
40
0
mA
mA
VH
I
− 40
VB
VB pin(When VCC pin connected to
VB pin)
VB pin input voltage
V
4.5
5
6
V
B
Input voltage
V
V
-INE1, -INE2 pins
CTL pin
0
0
-
-
V
− 0.9
B
V
V
INE
CTL pin input voltage
17
CTL
OUT1-1, OUT1-2, OUT2-1, OUT2-2
pins
Output current
I
f
− 45
-
+ 45
mA
OUT
Oscillation frequency
Timing resistor
Tj ≤ + 85˚C
RT pin
100
3.6
-
500
16
2000
100
4.7
kHz
kΩ
μF
OSC
R
T
VH pin capacitor
VB pin capacitor
C
VH pin
1.0
1.0
VH
VB
C
VB pin
-
4.7
μF
CSCP1,
CSCP2
CSCP1, CSCP2 pin capacitor
CSCP1, CSCP2 pins
-
0.047
1.0
μF
˚C
Operating ambient
temperature
Ta
-
− 30
+ 25
+ 85
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor
device. All of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their representatives beforehand.
Document Number: 002-08369 Rev. *B
Page 7 of 53
MB39C011A
6. Electrical Characteristics
(Ta = +25˚C, VCC = 12 V)
Value
Typ
4.0
Parameter
Symbol Pin No.
Condition
Unit
Max
Min
3.8
3.6
-
1.9
− 3.2
3.6
Under Voltage
V
V
4
4
VB
4.2
4.0
-
V
V
TLH
THL
Threshold voltage
Lockout Protection
Circuit Block
[UVLO]
VB
3.8
[1]
Hysteresis width
Threshold voltage
Input source current
Reset voltage
V
4
-
-
0.2
V
H
V
8, 9
8, 9
4
2.0
− 2.3
3.8
2.1
− 1.4
4.0
V
TH
Short-circuitprotection
circuit Block
I
RT = 16 kΩ
μA
V
CSCP
[SCP]
V
VB =
RST
Triangular Wave Oscil- Oscillation
fosc
2, 15
8, 9
RT = 16 kΩ
450
500
− 3.3
1.00
0
550
kHz
μA
V
lator Block [OSC]
frequency
CSCP1, 2 = 0 V,
RT = 16 kΩ
Soft-Start Block [CS]
Charge current
I
− 4.6
0.99
− 2.0
1.01
CS
FB1 = 1 V,
FB2 = 1 V
Threshold voltage
V
6, 11
TH
-INE1 = 0 V,
-INE2 = 0 V
Input bias current
Voltage gain
I
7, 10
6, 11
6, 11
− 100
+ 100
nA
dB
B
[1]
A
DC
-
-
80
-
-
V
Frequency band-
width
1]
Error Amp Block
[Error Amp1,
Error Amp2]
BW
A
= 0 dB
5.0[
MHz
V
V
6, 11
6, 11
-
-
V
− 0.3
V − 0.1
B
-
200
V
OH
B
Output voltage
V
-
-
40
mV
OL
Output source
current
FB1 = 1 V,
FB2 = 1 V
I
6, 11
6, 11
-400
8.0
− 300
μA
SOURCE
FB1 = 1 V,
FB2 = 1 V
Output sink current
I
4.0
-
mA
SINK
PWM Comparator
Block [PWM Comp.1, Threshold voltage
PWM Comp.2]
V
6, 11
6, 11
Duty cycle = 0 %
0.6
0.7
1.7
-
V
V
T0
V
Duty cycle = 100 %
-
1.8
T100
VH Bias Voltage Block
Output voltage
[VH]
VCC = 6 V to 17 V
VH = 0 to 40 mA
V
16
4
V
− 5.5
V
− 5.0
V − 4.5
CC
V
H
CC
CC
VB Bias Voltage Block
Output voltage
[VB]
VCC = 6 V to 17 V
VB = 0 to − 40 mA
V
4.5
5.0
5.5
V
B
(Continued)
Document Number: 002-08369 Rev. *B
Page 8 of 53
MB39C011A
(Continued)
(Ta = +25˚C, VCC = 12 V)
Value
Typ
Parameter
Symbol Pin No.
Condition
Unit
Max
Min
OUT1-1 = 7 V
OUT2-1 = 7 V
Duty ≤ 5%
2, 15
Output source
current
[1]
I
-
− 500
-
mA
SOURCE
VB = VCC = 5 V
OUT1-2 = 0 V
OUT2-2 = 0 V
Duty ≤ 5%
3, 14
2, 15
VCC = 5 V,
At connect VH-GND
OUT1-1 = 5 V
OUT2-1 = 5 V
Duty ≤ 5%
[1]
Output sink current
I
-
-
500
-
mA
SINK
OUT1-2 = 5 V
OUT2-2 = 5 V
Duty ≤ 5%
3, 14
2, 3,
OutputBlock[Drive1to
2]
OUT1-1, OUT1-2,
OUT2-1, OUT2-2 = − 45
mA
R
4.0
6.0
Ω
OH
14, 15
Output on resistor
OUT1-1, OUT2-1 = 45
2, 15
-
-
4.0
2.6
6.0
3.9
Ω
Ω
mA
R
OL
OUT1-2, OUT2-2 = 45
3, 14
mA
OUT1-1, OUT2-1 : H→L
OUT1-2, OUT2-2 : H→L
2, 3,
14, 15
Dead time
td
20
40
80
ns
OUT1-1, OUT2-1 : L →H
OUT1-2, OUT2-2: L →H
V
13
13
13
13
1
IC active mode
IC standby mode
CTL = 5 V
2
0
-
-
-
-
-
17
0.8
100
1
V
IH
CTL input voltage
V
V
IL
CTLH
Control Block
General
I
50
μA
μA
μA
Input current
I
CTL = 0 V
-
0
CTLL
Standby current
I
CTL = 0 V
10
CCS
Power supply
current
I
1
CTL = 5 V
-
2.2
3.3
mA
CC
[1] : Standard design value
Document Number: 002-08369 Rev. *B
Page 9 of 53
MB39C011A
7. Typical Characteristics
Power supply current vs.Power supply voltage
VB bias voltage vs.Power supply voltage
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
Ta = + 25˚C
Ta = + 25˚C
VB = 0 A
4
6
8
10
12
14
16
18
4
6
8
10 12 14 16 18
Power supply voltage VCC (V)
Power supply voltage VCC (V)
VB bias voltage vs.Operating ambient
temperature
VB bias voltage vs.VB bias output current
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
Ta = + 25˚C
VCC = 12 V
VCC = 12 V
VB = 0 A
-40 -20
0
+20 +40 +60 +80 +100
-100
-80
-60
-40
-20
0
VB bias output current IVB (mA)
Operating ambient temperature Ta (˚C)
Voltage between VCC and VH vs.Power supply
voltage
Voltage between VCC and VH vs.VH bias output
current
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
Ta = + 25˚C
VH = 0 A
Ta = + 25˚C
VCC = 12 V
4.7
4.6
4.5
4.7
4.6
4.5
4
6
8
10
12
14
16
18
0
20
40
60
80
100
Power supply voltage VCC (V)
VH bias output current IVH (mA)
(Continued)
Document Number: 002-08369 Rev. *B
Page 10 of 53
MB39C011A
(Continued)
Voltage between VCC and VH vs.
Operating ambient temperature
Triangular-wave generator frequency vs.
Timing resistance
5.5
10000
1000
100
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
Ta = + 25˚C
VCC = VB =
5 V
VCC = 12 V
VH = 0 A
1
10
100
-40 -20
0
+20 +40 +60 +80 +100
Operating ambient temperature Ta (˚C)
Timing resistance RT (kΩ)
Triangular-wave generator frequency vs.
Power supply voltage
Triangular-wave generator frequency vs.
Operating ambient temperature
650
600
550
500
450
400
350
650
600
550
500
450
400
350
Ta = + 25˚C
VCC = VB
fosc = 500 kHz
VCC = VB = 5 V
fosc = 500 kHz
-40 -20
0
+20 +40 +60 +80 +100
4.5
5.0
5.0
6.0
6.5
7.0
Power supply voltage VCC (V)
Operating ambient temperature Ta (˚C)
Error Amp threshold voltage vs.
Operating ambient temperature
Power dissipation vs.
Operating ambient temperature
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
1200
1060
1000
800
600
400
200
0
VCC = VB = 5 V
-50 -25
0
+25 +50 +75 +100 +125
-40 -20
0
+20 +40 +60 +80 +100
Operating ambient temperature Ta (˚C)
Operating ambient temperature Ta (˚C)
Document Number: 002-08369 Rev. *B
Page 11 of 53
MB39C011A
8. Functional Description
8.1 DC/DC Converter Block
8.1.1 Triangular Wave Oscillator Block (OSC)
The triangular wave oscillator block has a built-in capacitor for setting the oscillator frequency. The triangular wave is
generated by connecting a resistor for selecting the frequency of the triangular wave to the RT pin (pin 5).The triangular
wave is input internally to the PWM comparator in the IC.
8.1.2 Error Amplifier Block (Error Amp1, Error Amp2)
The error amplifiers (Error Amp1, Error Amp2) detect the DC/DC converter output voltages and output the PWM control
signals. The output voltages can be set to an arbitrary level by externally connecting output voltage setting resistors to the
error amplifier inverted input pins.
In addition, an arbitrary loop gain can be set by connecting a feedback resistor and capacitor from the error amplifier output
(FB1 pin (pin 6), FB2 pin (pin 11)) to inverted input terminal (-INE1 pin (pin 7), -INE2 pin (pin 10)), enabling stable phase
compensation of the system.Connecting a soft-start capacitor to the CSCP1 and CSCP2 pins (pins 8 and 9) prevents rush
currents when the IC is turned on. Using an error amplifier for soft-start detection makes the soft-start time constant,
independent of the output load of DC/DC converter.
8.1.3 PWM Comparator Block (PWM Comp.)
The PWM comparator circuit is a voltage-pulse width converter for controlling the output duty of the error amplifiers (Error
Amp1, Error Amp2) depending on their output voltage.
The PWM comparator circuit compares the triangular wave generated by the triangular wave oscillator to the error amplifier
output voltage and turns on the external output transistor during the interval in which the triangular wave voltage is lower
than the error amplifier output voltage.
8.1.4 Output Block (Drive1-1, 1-2, Drive 2-1, 2-2)
The output circuit consists of CMOS drivers on both the high side and the low side, and is capable of driving an external
P-ch MOS FET on the high side and an external N-ch MOS FET on the low side.
8.1.5 Power Supply Control Block (CTL)
The DC/DC converter can be put into standby mode by setting the CTL pin (pin 13) to the “L” level (the maximum power
supply current in standby mode is 10 μA), and put into operating mode by setting the CTL pin (pin 13) to the “H” level.
Control Function Table
CTL
L
IC
OFF (Standby)
ON (Operating)
H
Document Number: 002-08369 Rev. *B
Page 12 of 53
MB39C011A
8.2
Protection Function
8.2.1 Soft-start Circuit
To prevent rush currents when the IC is turned on, soft-start can be performed by connecting soft-start capacitors (CSCP1
and CSCP2) to the CSCP1 and CSCP2 pins (pins 8 and 9). When CTL pin (pin 13) is driven to the “H” level and the IC
begins operation (VCC ≥ UVLO threshold voltage), the external soft-start capacitors (CSCP1 and CSCP2) connected to the
CSCP1 and CSCP2 pins (pins 8 and 9) are charged by the charging current obtained from the following formula.
ICS ≅ 5.4 × 10−5 / RT
ICS :Charge current [A]
RT :Timing resistance [kΩ]
The error amplifier output (FB1 pin (pin 6), FB2 pin (pin 11)) is determined by comparing the voltages of the two non-inverted
input pins (whichever of the internal 1.0 V reference voltage and the CSCP1 and CSCP2 pins (pin 8 and pin 9) has the lowest
voltage) against the inverted input pin voltages (-INE1 pin (pin 7) voltage, -INE2 pin (pin 10) voltage). During the soft-start
period, FB1 and FB2 are determined by comparing the internal 1.0 V reference voltage against the voltages of the CSCP1
and CSCP2 pins (pins 8 and 9), and the DC/DC converter output voltages rise in proportion to voltages of the CSCP1 and
CSCP2 pins (pins 8 and 9) as the soft-start capacitors (CSCP1 and CSCP2) connected to the CSCP1 and CSCP2 pins (pins
8 and 9) are charged.
The soft-start time can be found from the following formula.
ts ≅ 0.019 × CSCP × RT
ts
:Soft-start time (time to output voltage 100%) [s]
CSCP :Capacitance of CSCP pin [μF]
RT
:Timing resistance [kΩ]
CSCP pin voltage
≅ 1.3 V
≅ reference voltage 1.0 V
≅ 0 V
Error Amp block -INE1 (-INE2) voltage
t
Soft start time, ts
Document Number: 002-08369 Rev. *B
Page 13 of 53
MB39C011A
Soft-start circuit
VB
Ic1[A] ≅ 3.7×10−5/RT [kΩ]
Ic2[A] ≅ 1.7×10−5/RT [kΩ]
Vo
Ic1
Ic2
RT : Timing resistor
(-INE2)
-INE1
R1
R2
10
7
Ics
L priority
Error Amp
CSCP1
8
9
(1.0 V)
(CSCP2)
CSCP
FB1
6
(FB2)
UVLO
11
8.2.2
Timer-Latch Short-Circuit Protection Circuit
Each channel has a short-circuit detection comparator (SCP Comp1 and Comp2) that constantly compares the output level of the
error amplifier against the reference voltage. While the DC/DC converter load conditions remain stable, the error amplifier output
does not change and the short-circuit protection comparator remains in an equilibrium state. At this time, the CSCP1 and CSCP2
pins (pins 8 and 9) maintain the voltage from when the soft-start finished (about 1.3 V). If the output voltage of the DC/DC converter
falls drastically due to a short-circuit or other load conditions, the output voltage of the error amplifier rises 1.9 V or more, and the
external CSCP1 and CSCP2 capacitors are further charged. When the CSCP1 or CSCP2 capacitors are charged to about 2.0 V,
a latch is set that turns off the external P-ch/N-ch MOSFETs (dead time is set to 100%). At this time, the latch input is closed and
the CSCP1 and CSCP2 pins (pins 8 and 9) are held at the “L” level. Once the protection circuit has been activated, it can be reset
by allowing the VB pin (pin 4) voltage to 3.8 V (minimum) or loss by turning the power off and on again.
tCSCP ≅ 0.019 × CSCP × RT
tCSCP :Short-circuit detection time [s]
CSCP :Capacitance of CSCP pin [μF]
RT
:Timing resistance [kΩ]
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MB39C011A
Timer-latch short-circuit protection circuit
(FB2)
FB1
11
6
Vo
R1
R2
Error
Amp1
-INE1
7
(-INE2)
10
(1.0 V)
2.5 V
Ic1
Ic2
SCP
Comp.
(1.9 V)
Ics
to Drive
CSCP1
8
9
(CSCP2)
(2.0 V)
VB
S
Latch
R
UVLO
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MB39C011A
Soft-start and short-circuit protection timing chart
CSCP voltage
Soft-start time
Short-circuit detection time
ts
tcscp
2.0 V
1.3 V
1.0 V
Output short
Output short
t
(1)
(2) (3)
(4)
(5)
(6)
(7)
1. When the CTL pin (pin 13) is set to the “H” level and the IC becomes active, the voltages of the CSCP1 and CSCP2 pins (pins
8 and 9) rise due to the capacitors attached externally to the CSCP1 and CSCP2 pins (pins 8 and 9) being charged. During
this time, Error Amp1 and Error Amp2 are controlled by the CSCP1 and CSCP2 pins (pins 8 and 9) and the -INE1 and -INE2
pins (pins 7 and 10) inputs, thus performing a soft-start.
2. When the CSCP1 and CSCP2 pins (pins 8 and 9) reach 1 V or more, Error Amp1 and Error Amp2 become controlled by the
internal reference voltage (1 V) and the -INE1 and -INE2 pin (pins 7 and 10) inputs, and the output voltage is held at a constant
level.
3. The CSCP1 and CSCP2 pins (pins 8 and 9) are clamped to about 1.3 V.
4. When there is a short circuit in the load and the error amplifier output becomes 1.9 V or more, the short-circuit protection
comparator (SCP Comp.) is activated and the CSCP1 and CSCP2 capacitors are charged further.
5. If the short-circuit in the load is cleared within the short-circuit detection time tCSCP, the CSCP1 and CSCP2 pins (pins 8 and
9) return to the clamping voltage of about 1.3 V.
6. When there is a short-circuit in the load and the error amplifier output becomes 1.9 V or more, the short-circuit protection
comparator (SCP Comp.) is activated and the CSCP1 and CSCP2 capacitors are charged further.
7. The latch is set when the load short-circuit is not released even if short-circuit detection time tCSCP passes, external MOS FET
P-ch/N-ch are turned off, and the CSCP1,CSCP2 pins (pins 8 and 9) are hold at “L” level.
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MB39C011A
Notes :
■ The output is stopped by the short-circuit protection (SCP) function when the DC/DC output is short-circuited to GND etc.
However, care needs to be taken because the short-circuit protection (SCP) function will not stop the output when a half
short-circuit occurs. Measures such as placing a fuse in the input can be used for this situation. [ Half short-circuit refers to a
short-circuit condition where an overcurrent flows, but it is not sufficient to reduce the output voltage.]
■ In the event that an output short current flows that exceeds the capacity of the input power supply, the power supply voltage
may drop. If the power supply voltage at this time drops below 3.8 V, the output is stopped by the under voltage lockout
protection circuit (UVLO). However, once the input power supply voltage recovers after the output has been stopped, the
output will begin again. Care needs to be taken because this situation may result in a repeating cycle of “short-circuit →
power-supply voltage drop → output stop → power-supply voltage recovery → output start → short-circuit”. There are putting
a fuse in the input etc. as measures.
■ Notestheshort-circuitprotection(SCP)functionwhentheDC/DCconverterisstarted/stopped. Theoutputmayalsobestopped
by the short-circuit protection (SCP) function under the following conditions.
❐ Operations that act on the input power supply and the CTL pin (for example, shorting the input power supply to the CTL pin).
❐ During the transition period when the input power supply voltage (VIN) is changing (such as when the input power supply is
turned on or turned off), the condition is met that input power supply voltage (VIN) < output setting voltage (VO).
Although this is normal IC operation, as an example of startup of the IC, the output may be stopped due to the following
process.
(1) DC/DC converter output begins when VIN ( = VB) > UVLO threshold voltage.
(2) A period of time occurs where the input power supply voltage (VIN) < the output voltage setting (VO), and the duty cycle
becomes 100% on. The error amplifier output rises above 1.9 V due to the feedback control.
(3) The output is stopped after the short-circuit detection time has elapsed.
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MB39C011A
Example where the output stops when the DC/DC converter is activated by the input power supply (example of output
stopped by SCP during startup)
Voltage [V]
Input power supply voltage VIN ( = CTL)
Output voltage setting
Output voltage (VO)
Time [s]
(1) (2) (3)
In this case, the output can be prevented from being stopped by the SCP function during startup by
controlling the CTL pin independently.
Example of the DC/DC converter being started by the CTL pin
Voltage [V]
Input power supply voltage VIN
CTL
Output voltage setting
Output voltage (VO)
Time [s]
Furthermore, when turning off the input power supply, set the CTL pin to “L” before turning off the input power supply.
8.2.3 Under Voltage Lockout Protection Circuit (UVLO)
A drop in the power supply voltage may cause the IC to malfunction, resulting in breakdown or degradation of the system.
To prevent such malfunctions, the under voltage lockout protection circuit detects decreases in VB voltage due to the power
supply voltage, and locks, the OUT1-1 pin (pin 2) and OUT2-1 pin (pin 15) at the “H” level and the OUT1-2 pin (pin 3) and
OUT2-2 pin (pin 14) at the “L” level. The system is restored if the VB voltage rises above the threshold voltage of the under
voltage lockout protection circuit.
Function Table When the Protection Circuit (UVLO) is Operating
When the UVLO circuit is operating (the VB voltage is below the UVLO threshold voltage), the following pins are fixed at the
following logic levels.
OUT1-1
OUT1-2
OUT2-1
OUT2-2
CSCP1
CSCP2
H
L
H
L
L
L
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MB39C011A
8.2.4 Operation When CTL is Turned On and Off
When CTL is turned on, the internal reference voltages VR1 and VB begin to rise. When VB exceeds the threshold voltage
(VTH) of UVLO (under voltage lockout protection circuit), UVLO is released, and the output drive circuits of each channel
are allowed to operate.When CTL is off, the output drive circuit of each channel is locked in the full off state and the CSCP1
and CSCP2 pins (pins 8 and 9) are fixed at the “L” level, even if the UVLO circuit is in the clear state. When the internal
reference voltages VR1 and VB begin to fall and when VB falls below the threshold voltage of the UVLO (under voltage
lockout protection circuit), the UVLO circuit is activated.
8.2.5 Independent Control Of Each Channel
The on/off state of each output voltage can be controlled independently by externally connecting the CSCP1 and CSCP2
pins (pins 8 and 9) to the drain pin of an NMOS transistor or to an NMOS open drain pin of a microcontroller, etc. When the
CSCP1 or CSCP2 pins (pins 8 and 9) is set to the “L” level by turning on the external NMOS transistor, the output voltage
turns off. Furthermore, when the external NMOS transistor is turned off, the soft-start function begins and the output voltage
turns on. Note that the internal operation of the IC continues when the output voltages are turned off using the CSCP1 and
CSCP2 pins (pins 8 and 9). Set the CTL pin (pin 13) to the “L” level to enter standby mode (the maximum power supply
current in standby mode is 10 μA).
V
Vo1
MB39C011A
CSCP1
Vo2
CTL1
CS
CS
CSCP2
CTL
CTL1
CTL2
CTL
CTL2
CTL
t
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MB39C011A
9. Switching Scheme Selection
This device can operate even by a synchronous rectification and an asynchronous rectification. There is superiority or
inferiority respectively. Select the switching type considering the features as a guide.
Switching type
Parts
Feature
■ Superior cost advantages
Asynchronous rectification P-ch FET + Fly-back diode
P-ch FET + N-ch FET
■ Underlargeloadcurrentsandlowoutputvoltages,itisinefficient because
generation of heat of the Fly-back diode (SBD) is large.
■ Offers a balance between cost and efficiency.
■ Supports large load currents and low output voltages
■ Emphasis on efficiency (particularly effective at high oscillator
Synchronous rectification
P-ch FET + N-ch FET + Fly-back
diode
frequencies)
■ Supports large load currents and low output voltages
■ Because of the increased number of parts, the cost is a disadvantage.
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MB39C011A
10. Setting The Output Voltage
The output voltage can be set to an arbitrary value by the ratio of the feedback resistance to -INE1 (-INE2).
■ Set the output voltage to a value higher than the reference voltage (1 V) of the Error Amp.
■ Under usage conditions where the duty cycle is 30% or less, set VO1 < VO2 as much as possible.
VO
D =
×100
VIN
D
:Duty cycle [%]
VIN
VO
:Power supply voltage of switching system [V]
:Output setting voltage [V]
R1, R2 :Output voltage setting resistors [Ω]
Vo1,2
(-INE2)
R1
Error
Amp
10
1.0
R2
7
Vo =
(R1+R2)
-INE1
R2
1.0 V
(CSCP2)
CSCP1
9
8
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MB39C011A
11. Setting The Triangular Oscillation Frequency
The triangular oscillation frequency is determined by the timing resistor (RT) connected to the RT pin (pin 5).
0.001
fosc ≅
122.4 × 10 − 12 × RT ×103 + 96 × 10 − 9
fosc : Triangular oscillation frequency [kHz]
RT
: Timing resistance [kΩ]
The upper limit on the oscillation frequency that can be set depends on the junction temperature and duty cycle. It is recommended
that the device is used within the range shown in the following graph.
Oscillation frequency vs. Junction temperature
2100
1900
1700
1500
1300
1100
900
700
500
300
100
-30
0
+30
+60
+90
+120
Junction temperature Tj (˚C)
Note : Refer to “ Power Dissipation and Thermal Design” for details on calculating the junction temperature.
11.1 Power Dissipation and Thermal Design
It is necessary to examine it for the use at a high power-supply voltage, a high oscillation frequency, and the high temperature.
Also use within the range of “Oscillation frequency vs. Junction temperature”.
The junction temperature can be investigated from the internal power dissipation of the IC.
The internal power dissipation of the IC (PIC) is given by the following formula.
PIC = VCC × (ICC + Qg × fosc)
PIC
: Internal IC power dissipation [W]
VCC : Power supply voltage (VIN : [V])
ICC
Qg
: Power supply current (3.3 mA Max)
: Total electric charge (Vgs = 5 V) of all SW FET for 2ch [C]
fosc : Oscillation frequency [Hz]
The junction temperature is given by the following formula.
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MB39C011A
Tj = Ta + θja × PIC
Tj
:Junction temperature ( + 125˚C Max)
:Ambient temperature [˚C]
Ta
θja :TSSOP-16 package thermal resistance (94˚C/W)
PIC :Internal IC power dissipation [W]
Synchronous rectification,
Synchronous rectification,
at 4.5 V ≤ VIN ≤ 6 V (VCC = VB)
at VIN > 6 V(VB = 5 V)
Duty cycle vs. Oscillation frequency
Duty cycle vs. Oscillation frequency
100
100
80
60
40
20
0
80
60
Applicability
Applicability
40
20
0
0
500
1000
1500
2000
0
500
1000
1500
2000
Oscillation frequency fosc(kHz)
Oscillation frequency fosc(kHz)
Asynchronous rectification,
Asynchronous rectification,
at 4.5 V ≤ VIN ≤ 6 V(VCC = VB)
at VIN > 6 V(VB = 5 V)
Duty cycle vs. Oscillation frequency
Duty cycle vs. Oscillation frequency
100
80
60
40
20
0
100
80
60
40
20
0
Applicability
Applicability
0
500
1000
1500
2000
0
500
1000
1500
2000
Oscillation frequency fosc(kHz)
Oscillation frequency fosc(kHz)
Notes :
Refer to “ Setting The Output Voltage” for details on calculating the duty cycle.
When using the IC outside of the ranges shown in the above graphs, check for jitter and other adverse effects on
the output voltage before use.
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MB39C011A
12. Setting The Soft-start And Short-circuit Detection Times
Set the soft-start time and the short-circuit detection time using the CSCP pins. Both become the same time.
ts = tCSCP ≅ 0.019 × CSCP × RT
ts
:Soft-start time (time to output voltage 100%) [s]
tCSCP :Short-circuit detection time [s]
CSCP :CSCP pin capacitor [μF]
RT
:Timing resistance [kΩ]
13. VB Pin And VH Pin Connections In Condition Of Vcc Voltage
In the range of 4.5 V ≤ VCC ≤ 6.0 V, there is a chance that the VB voltage[1] and VH voltage[2] may drop due to the internal IC
regulator saturating. As a result, there are drive voltage shortage and a bird clapper of SW FET. It is therefore recommended that
the VB pin (pin 4) and VH pin (pin 16) are connected as shown in the “VB pin and VH pin connection table”.
[1]: Voltage between VB pin (pin 4) and GND pin (pin 12) : 5 V
[2] : Voltage between VCC pin (pin 1) and VH pin (pin 16) : 5 V
VB pin and VH pin connection table
VCC condition
VB pin
VH pin
4.5 ≤ VCC ≤ 6 V
6 V ≤ VCC ≤ 17 V
Connected to VCC
VB capacitor connection
Connected to GND
VH capacitor connection
[4]
[4]
[4]
[4]
[3]
Used with VCC crossing 6 V (ex. 5 V ≤
VCC ≤ 7 V)
VB capacitor connection
VH capacitor connection
[3]: Check that the switching operation is functioning normally.
[4]: Refer to the connection of the VB pin (pin 4) and the VH pin (pin 16) in the “Block Diagram”.
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MB39C011A
Transition diagram of the VB voltage and VH voltage (VB pin: VB capacitor connection, VH pin: VH capacitor connection)
VCC
Voltage
VH voltage
VH pin voltage
VB pin voltage
5 V
VB voltage
Power supply voltage VCC
VCC ≅ 6 V
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MB39C011A
14. Design Of Phase Compensation Circuit
14.1 Phase compensation circuit when low ESR capacitor is used as output
capacitor
When a low-ESR capacitor such as a ceramic capacitor is used as the output capacitor, it becomes easy to vibrate for a phase
delay of the 180° to be generated due to the resonant frequency of the LC. In this case, it is common to use a phase compensation
circuit that can advance the phase, such as a 2-pole/2-zero circuit.
2-pole/2-zero phase compensation circuit
VO1,VO2
R3
Rc
Cc
R1
C1
-
To PWM
Comp.1,2
-INE1,-INE2
R2
FB1,FB2
+
Error
Amp1,Amp2
Vref
Set the R3, Rc, C1, and Cc constants in the phase compensation circuit by using the following formula as a guide. As for frequency
(fCO) of crossover, in which the band width of the control loop of DC/DC is shown, height is excellent in the rapid response. However,
vibration may be generated due to an insufficient phase margin. Although the
crossover frequency (fCO) can be set to any value, the maximum value must be 1/2 of the oscillation frequency (fOSC), or 1/5 of
the oscillation frequency (fOSC) as preferable. Furthermore, the crossover frequency (fCO) should be set such that the phase margin
is a minimum of 30°, or more than 45° as preferable.
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MB39C011A
fLC × R1
R3, Rc : [Ω]
R3 ≅
2 × fESR − fLC
C1, Cc : [F]
fLC
: Resonant frequency [Hz] of the coil L [H] and output
capacitor C [F]
1
fLC
fESR
=
2 × π√L × C
1
: Resonant frequency [Hz] of the output capacitor C [F] and ESR
C1 ≅
[Ω]
π × fLC (R1 + R3)
1
fESR
=
2 × π × ESR × C
(R1//R3) × fESR × fCO
Rc ≅
Cc ≅
2
VIN × fLC
fCO
: Crossover frequency (arbitrary setting) [Hz]
1
R1//R3 : Resistance of R1 and R3 connected in parallel [Ω]
VIN : Switching system power supply voltage [V]
2 × π × RC × fLC
14.2 Notes on Phase Compensation Circuit Constants
Select the constants of the following three points and select the constant for the design of the phase compensation circuit when
the large load sudden change, or the capacitor is connected to DC/DC converter operating.
In particular, if a capacitance much larger than the output capacitance of the DC/DC converter is connected by hard-switching
while the DC/DC converter is operating, the output voltage may begin vibrating or the protection function may be activated, due
to the sudden response. Note the following points.
14.2.1 Error Amp output (FB1 and FB2 pins) current capacity
The resistance constants of the phase compensation circuit need to be designed by considering the current capacities of the Error
Amp outputs (FB1 and FB2 pins (pins 6 and 11)). Take the output source current
( − 300 μA Max) of the Error Amp and the threshold voltage VT100 (1.7 V Typ) of the PWM Comp into consideration, select the
resistance values such that the following formula is satisfied.
1.7 [V]
R1//R2//R3 = Resistance of R1, R2 and R3 connected in parallel [Ω]
RC : [Ω]
300 [μA] >
R1//R2//R3 + RC
Although low resistance values may be desired to improve the noise immunity, the above formula may not be satisfied as a result.
While it is ideal for each of the resistance values to satisfy the above formula, in this situation the values may be used after
confirming that there are no problems when used under the rapidly varying load conditions.
14.2.2 Phase Margin at the Output Load changes
Select phase compensation constants that ensure the phase margin when the output load (resistive load, capacitative load,
inductive load) is connected.
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MB39C011A
14.2.3 Phase Margin at the rEverse Current Flow from the Output Pin
Under usage conditions where current from the DC/DC converter output (VO) pin flows by the load sudden change,
select phase compensation constants that ensure the phase margin even when reverse current flow occurs.
Example of measuring the phase margin during reverse current flow
R
VIN
VO
DC/DC
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MB39C011A
15. Handling the Unused Channel Pins when using a Single Channel
Although this device is a 2-channel DC/DC converter control IC, it is also able to be used as a 1-channel DC/DC converter by
handling the pins of the unused channel as shown in the following diagram.
1. Connection when CH 1 is not used
“Open”
2
3
OUT1-1
OUT1-2
“Open”
“Open”
6
FB1
-INE1
7
8
CSCP1
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MB39C011A
2. Connection when CH 2 is not used
“Open”
“Open”
“Open”
OUT2-1
OUT2-2
FB2
15
14
11
-INE2
10
9
CSCP2
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MB39C011A
16. I/O Equivalent Circuit
<VB bias voltage block>
<CTL block>
VCC
VCC
CTL
13
VB
4
GND
GND
<PWM comparator block>
<Triangular wave oscillator block>
VB
VB
FBx
RT
5
GND
GND
x : Each channel No.
(Continued)
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MB39C011A
(Continued)
<Soft-start block, Error Amp block>
VB
-INEx
CSCPx
GND
<Output block(OUTx-1)>
<VH bias voltage block>
VCC
VCC
1
VH
16
OUTx-1
VH
GND
GND
<Output block (OUTx-2)>
VB
OUTx-2
GND
GND
12
x : Each channel No.
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MB39C011A
17. Example Application Circuit
VIN
GND
CTL
MB39C011A
VCC
1
C7
13
7
CTL
16
VH
VB
C9
C3
C5
R3
R4
4
2
-INE1
C8
Q1
R7
C4
OUT1-1
L1
R6
V
o1
1.8 V
GND1
6
FB1
C10
C11
C13
3
OUT1-2
R9
Q2
10
11
-INE2
FB2
R10
R12
R13
C6
15
14
OUT2-1
OUT2-2
L2
Q3
Q4
V
3.3 V
o2
C12
8
9
5
GND2
CSCP1
CSCP2
RT
C1
C2
12
GND
R1
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MB39C011A
18. Parts List
Component
Item
Specification
Component
Item
Specification
VDS = − 30 V,
ID = − 4 A (Max)
Q1
Q2
Q3
Q4
P-ch FET
C1
Ceramic condenser
0.015 μF (50 V)
VDS = 30 V,
ID = 5 A (Max)
N-ch FET
P-ch FET
N-ch FET
C2
C3
C4
Ceramic condenser
Ceramic condenser
Ceramic condenser
0.015 μF (50 V)
100 pF (50 V)
470 pF (50 V)
VDS = − 30 V,
ID = − 4 A (Max)
VDS = 30 V,
ID = 5 A (Max)
R1
R3
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
16 kΩ
C5
C6
Ceramic condenser
Ceramic condenser
Ceramic condenser
Ceramic condenser
Ceramic condenser
Ceramic condenser
Ceramic condenser
Ceramic condenser
Ceramic condenser
220 pF (50 V)
2200 pF (50 V)
0.1 μF (50 V)
1 μF (16 V)
2 kΩ
R4
5.1 kΩ + 75 kΩ
100 kΩ
10 kΩ
C7
R6
C8
R7
C9
1 μF (16 V)
R9
1 kΩ
C10
C11
C12
C13
22 μF (25 V)
33 μF (6.3 V)
22 μF (25 V)
33 μF (6.3 V)
R10
R12
R13
1.5 kΩ + 33 kΩ
15 kΩ
5.6 kΩ
3.3 μH
(IDC = 6.7 A)
L1
L2
Inductor
Inductor
-
-
-
-
-
-
4.7 μH (IDC = 6 A)
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MB39C011A
19. Part Selection
19.1 Coil selection
As a rough guide, choose the inductance of the coil such that the peak-to-peak ripple current of the coil is less than 50% of the
maximum load current. The inductance in this case is given by the following formula.
VIN − VO
LOR × IOMAX
VO
L ≥
×
VIN × fosc
L
: Coil inductance [H]
IOMAX : Maximum load current [A]
LOR
VIN
: 0.5
: Switching system power-supply voltage [V]
: Output voltage setting [V]
: Oscillation frequency [Hz]
VO
fosc
When the IC is used with asynchronous rectification, it is recommended that the IC be used in the load current range where the
coil current is continuous in order to ensure responsiveness to the load. For asynchronous rectification it is therefore recommended
that the minimum value of the load current is used as the basis for setting the inductance value.
VIN − VO
2 × IOMIN
VO
L ≥
×
VIN × fosc
L
: Coil inductance [H]
IOMIN
: Minimum load current [A]
: Switching system power-supply voltage [V]
: Output voltage setting [V]
: Oscillation frequency [Hz]
VIN
VO
fosc
The maximum value of the current flowing through the coil needs to be found in order to determine whether the current flowing
through the coil is within the rated value. The maximum current flowing through the coil is given by the following formula.
ΔIL
2
ILMAX = IOMAX
+
VIN − VO
VO
ΔIL ≥
×
L
VIN × fosc
Coil current
ILMAX
IOMAX
The coil current changes
according to the load current.
ΔIL
IOMIN
Time
0
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MB39C011A
ILMAX
IOMAX
ΔIL
: Maximum coil current [A]
: Maximum load current [A]
: Coil ripple current peak to peak value [A]
: Coil inductance [H]
L
VIN
: Switching system power-supply voltage [V]
: Output setting voltage [V]
VO
fosc
: Oscillation frequency [Hz]
19.2 SW FET selection
The maximum value of the current flowing through the SW FET needs to be found in order to determine whether the current flowing
through the SW FET is within the rated value. The maximum current flowing through the
SW FET is given by the following formula.
ΔIL
2
IDMAX ≥ IOMAX
+
IDMAX
IOMAX
ΔIL
: Maximum SW FET drain current [A]
: Maximum load current [A]
: Coil ripple current peak to peak value [A]
Furthermore, the power dissipation of the SW FET needs to be found in order to determine whether the power dissipation of the
SW FET is within the rated value. The power dissipation of the SW FET is given by the following formula.
High side FET (P-ch MOS FET) power dissipation PHiSideFET = PRon + PSW
VO
2
PRon : High side FET (P-ch MOS FET) conduction loss
PRon = IOMAX
×
×Ron
VIN
IOMAX : Maximum load current [A]
VIN
VO
: Switching system power supply voltage [V]
: Output voltage [V]
Ron
: High side FET ON resistance [Ω]
VIN × fOSC (Ibtm × tr × Itop × tf)
PSW : High side FET (P-ch MOS FET) switching loss
PSW =
2
VIN
: Switching system power supply voltage [V]
: Oscillation frequency [Hz]
fosc
Ibtm
: Bottom value of ripple current of coil [A]
ΔIL
2
Ibtm = IOMAX
−
Itop
:Top value of ripple current of coil [A]
ΔIL
2
Itop = IOMAX
+
Document Number: 002-08369 Rev. *B
Page 36 of 53
MB39C011A
ΔIL
tr
: Coil ripple current peak to peak value [A]
: Turn-on time of High side FET [s]
: Turn-off time of High side FET [s]
tf
tr and tf are simply obtained by the following formula.
Qgd × 4
5 − Vgs (on)
Qgd × 4
Vgs (on)
tr =
tf =
Qgd
: Quantity of charge between the gate and drain of High side FET [C]
: Absolute value of voltage difference between the gate and source of the High side FET at Qgd
[V]
Vgs(on)
VO
Low side FET(N-ch MOS FET)
conduction loss
PLoSideFET = PRon = IOMAX2× (1 −
) × Ron
VIN
PRon
IOMAX
VIN
: Low side FET conduction loss [W]
: Maximum load current [A]
: Switching system power supply voltage [V]
: Output voltage [V]
VO
Ron
: Low side FET ON resistance [Ω]
To select SW FETs that offer good conversion efficiency, the High side FET in particular should select such that the switching loss
is small (the power dissipated when the SW FET changes between ON and OFF). However, because there is generally a trade-off
between switching loss and conduction loss, this balance needs to be considered when making the selection.
As a guide, select FETs such that the total Qg of the SW FETs is as follows.
0.04
fosc
0.04
fosc
QgHiSideFET<
QgLoSideFET<
QgHiSideFET
: Sum total electric charge of the CH1 and CH2 High side FETs [C]
QgLoSideFET : Sum total electric charge of the CH1 and CH2 Low side FETs [C]
fosc : Oscillation frequency [Hz]
The SW FETs used with this device typically have a drive voltage of 4 V. Although there are FETs that support a drive voltage of
less than 4 V, low drive voltage FETs generally have a larger Qg even at equal value of Ron, the efficiency lowers. If a FET with
a low drive voltage is used, check that the low side FET does not self turn-on and that the dead-time is secured under the usage
conditions.
Document Number: 002-08369 Rev. *B
Page 37 of 53
MB39C011A
19.3 Fly-back Diode Selection
Select a Schottky barrier diode (SBD) that has a small forward voltage drop.
The peak current flowing through the Fly-back diode needs to be found in order to determine whether the current flowing through
the Fly-back diode is within the rated value. When the DC/DC converter IC is used with asynchronous rectification, the maximum
current through the Fly-back diode is given by the following formula.
ΔIL
2
If ≥ IOMAX
If
: Forward current [A]
IOMAX
ΔIL
: Maximum load current [A]
: Coil ripple current peak to peak value [A]
Furthermore, the power dissipation of the Fly-back diode needs to be found in order to determine whether the power dissipation
of the Fly-back diode is within the rated value. The power dissipation of the Fly-back diode is given by the following formula.
VO
PSBD = IOMAX × (1 −
) × Vf
VIN
PSBD : Fly-back diode power dissipation [W]
IOMAX : Maximum load current [A]
VIN
VO
Vf
: Switching system power supply voltage [V]
: Output voltage [V]
:Forward voltage [V]
When the DC/DC converter is used with synchronous rectification, the length of time that the current flows through the Fly-back
diode is limited to the synchronous rectification period (dead time). For example, at an oscillating frequency of 500 kHz, the
proportion of time that current flows is less than 5%. Therefore, select that Fly-back diode current does not exceed the peak forward
surge current (IFSM) rated value. The peak forward surge current value of the SBD is given by the following formula.
ΔIL
2
IFSM ≥ IOMAX
+
IFSM
IOMAX : Maximum load current [A]
ΔIL : Coil ripple current peak to peak value [A]
: Peak forward surge current value of Fly-back diode [A]
Document Number: 002-08369 Rev. *B
Page 38 of 53
MB39C011A
19.4 Output capacitor selection
Because the ripple voltage increases if the ESR is large, a low ESR capacitor needs to be used in order to reduce the ripple voltage.
However, using a capacitor with a low ESR has a large effect on the phase characteristics of the loop, and care needs to be taken
to prevent the system from losing stability. Furthermore, the capacitor that is used should have sufficient tolerance for the ripple
current.
If taking into account the switching ripple voltage, the minimum necessary capacitance is given by the following formula.
1
CO
≥
2π × fosc× (ΔVO/ΔIL − ESR)
ESR : Series resistance element of output capacitance [Ω]
ΔVO : Switching ripple voltage [V]
ΔIL
: Coil ripple current peak to peak value [A]
CO
: Output capacitance [F]
fosc : Oscillation frequency [Hz]
When a capacitive load is connected, it is recommended that the DC/DC converter output capacitor have the same capacitance
as the load capacitance.
The allowable ripple current of the output capacitor is given by the following formula.
ΔIL
Irms ≥
2√3
Irms : Allowable ripple current (Root-mean-square value) [A]
ΔIL
: Coil ripple current peak to peak value [A]
19.5 Input capacitor selection
Select an input capacitor that has as small an ESR as possible. Ceramic capacitors are ideal. If a large capacitance is required
that cannot be provided by a ceramic capacitor, use a polymer capacitor or a tantalum capacitor with a low ESR. Furthermore, the
capacitor that is used should have sufficient tolerance for the ripple current.
The allowable ripple current is given by the following formula.
√VO (VIN − VO)
Irms ≥ IOMAX
VIN
Irms
: Allowable ripple current (Root-mean-square value) [A]
IOMAX : Maximum load current [A]
VIN
VO
: Switching system power supply voltage [V]
: Output voltage [V]
Document Number: 002-08369 Rev. *B
Page 39 of 53
MB39C011A
19.6 VB pin capacitor
Although the VB pin capacitor typically has a capacitance of 1 μF, this needs to be adjusted if theSW FETbeing used has a large Qg.
The following formula provides a guide to the lower limit of the VB pin capacitor. If this lower limit exceeds 1 μF, use the formula
as a guide to set the capacitance.
CVBmin ≥ 0.1 × QgLoSideFET
CVBmin
: Lower limit of VB pin capacitor [μF]
QgLoSideFET
: Sum total electric charge of CH1 and CH2 Low side FETs [nC]
19.7 VH pin capacitor
The VH pin capacitor typically has a capacitance of 1 μF (when the VB pin capacitor ≤ 1 μF). However, this needs to be adjusted,
if the VB pin capacitor exceeds 1 μF or if the SW FET being used has a large Qg.
The following formula provides a guide to the lower limit of the VH pin capacitor. If this lower limit exceeds 1 μF, use the formula
as a guide to set the capacitance.
Large one either of
CVHmin ≥ 0.01×QgHiSideFET or CVHmin ≥ CVB
CVHmin
QgHiSideFET
CVB
: Lower limit of VH pin capacitor [μF]
: Sum total electric charge of CH1 and CH2 high side FETs [nC]
: Capacitance of VB pin capacitor [μF]
Document Number: 002-08369 Rev. *B
Page 40 of 53
MB39C011A
20. PCB Layout
Consider the following points when designing the PCB layout :
Make the input capacitor (Cin), SW FET, Fly-back diode (SBD), coil (L), and output capacitor (Cout) connections on the surface
as much as possible, and avoid making the connections with the through-holes.
Take the most care with the loop consisting of the input capacitor (Cin), SW FET, and Fly-back diode (SBD), and make the
current loop as small as possible.
Create through-hole directly next to the GND pins of the input capacitor (Cin), SW FET, Fly-back diode (SBD), and output
capacitor (Cout), and connect these to the SW system GND inner layer.
Large currents flow momentarily through the wiring of the OUTx-x pins that are connected to the SW FET gates. Use a wiring
width of about 0.8 mm as a guide, and make the wiring as short as possible.
Arrange the bypass capacitors that are connected to the VCC, VB, and VH pins (pins 1, 4, and 16) near the pins as possible.
Furthermore, connect the GND pin of the VCC and VB by-pass capacitor with a nearest GND pin of the IC. (Create a
through-hole directly next to the GND pin of the IC (pin 12) and the GND pins of the bypass capacitors to reinforce the
connection to the inner ground layer).
The wiring for the -INE1, -INE2, FB1, FB2, and RT pins (pins 7, 10, 6, 11, and 5) is sensitive to noise and should be made as
short as possible. Furthermore, the feedback line from the output (VO) should be kept as far away from SW system components
as possible.
Create as much ground plane on the side where the IC is mounted as possible. To prevent creating a large current path to the
control system GND, connect this to the PGND (SW system GND) at a single point.
Document Number: 002-08369 Rev. *B
Page 41 of 53
MB39C011A
Example of arranging
SW system parts
GND wiring example
SWFET
VIN
Cin
SW system GND
SW system
GND
SWFET
SBD
Cout
L
VH
VCC
VO
SW system GND
VB
Feedback line
To -INE
Control system
GND
RT
Control system GND
Control system GND and SW
system GND are connected
by one point.
Through-hole
Surface
GND layer
(Layer1)
(Layer2)
Document Number: 002-08369 Rev. *B
Page 42 of 53
MB39C011A
21. Reference Data
CH1
CH2
Conversion Efficiency vs. Load Current
Conversion Efficiency vs. Load Current
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
Ta = + 25˚C
VIN = 12 V
VO1 = 1.8 V
fosc = 500 kHz
Ta = + 25˚C
VIN = 12 V
VO2 = 3.3 V
fosc = 500 kHz
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Load Current IO1 (A)
Load Current IO2 (A)
Output Voltage vs. Load Current
Output Voltage vs. Load Current
1.84
1.83
1.82
1.81
1.80
1.79
1.78
1.77
1.76
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
Ta = + 25˚C
Ta = + 25˚C
VIN = 12 V
VO2 = 3.3 V setting
fosc = 500 kHz
VIN = 12 V
VO1=1.8 V setting
fosc = 500 kHz
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Load Current IO1 (A)
Load Current IO2 (A)
(Continued)
Document Number: 002-08369 Rev. *B
Page 43 of 53
MB39C011A
(Continued)
CH2 Switching Wave Form
CH1 Switching Wave Form
OUT-1
OUT-2
OUT-1
OUT-2
Ta = + 25˚C
Ta = + 25˚C
V
= 12 V
V
V
= 12 V
= 1.8 V
IN
IN
V
= 3.3 V
O2
O1
fosc = 500 kHz
fosc = 500 kHz
5 V/div, 80 ns/div
5 V/div, 200 ns/div
CH2 Sudden Load Variation Waveform
CH1 Sudden Load Variation Waveform
IO1 2 A/div
I
O2 2 A/div
VO1 500 mV/div
VO2 500 mV/div
Ta = + 25˚C
Ta = + 25˚C
V
V
I
= 12 V
= 3.3 V
= 0 ⇔ 3 A
IN
V
V
I
= 12 V
= 1.8 V
= 0 ⇔ 3 A
IN
O2
O1
O2
O1
fosc = 500 kHz
fosc = 500 kHz
40 μs/div
40 μs/div
CTL Startup Waveform
CTL 5 V/div
V
O
O
2 1 V/div
V
1 1 V/div
Ta = + 25˚C
V
= 12 V,
IN
V 1=1.8 V, I = 3 A,
O
O1
V 2 = 3.3 V, I = 3 A,
O
O2
fosc = 500 kHz
Soft start setting time = 4.5 ms
1 ms/div
Document Number: 002-08369 Rev. *B
Page 44 of 53
MB39C011A
22. Usage Precaution
22.1 Do not configure the IC over the maximum ratings
If the IC is used over the maximum ratings, the LSI may be permanently damaged.
It is preferable for the device to normally operate within the recommended usage conditions. Usage outside of these conditions
can have a bad effect on the reliability of the LSI.
22.2 Use the device within the recommended operating conditions
The recommended operating conditions are under which the LSI is guaranteed to operate. The electrical ratings are guaranteed
when the device is used within the recommended operating conditions and under the conditions stated for each item.
22.3 Printed circuit board ground lines should be set up with consideration for
common Impedance
22.4 Take appropriate measures against static electricity
Containers for semiconductor materials should have anti-static protection or be made of conductive material.
After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
Work platforms, tools, and instruments should be properly grounded.
Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground.
22.5 Do not apply negative voltages
The use of negative voltages below − 0.3 V may create parasitic transistors on LSI lines, which can cause malfunctions.
Document Number: 002-08369 Rev. *B
Page 45 of 53
MB39C011A
23. Ordering Information
Part number
Package
Remarks
16-pin plastic TSSOP
(FPT-16P-M07)
MB39C011APFT-❏❏❏E1
Lead-free version
24. EV Board Ordering Information
Part number
EV board version No.
Remarks
MB39C011AEVB-01
Board rev.1.0
TSSOP-16-pin
Document Number: 002-08369 Rev. *B
Page 46 of 53
MB39C011A
25. RoHS Compliance Information Of Lead (Pb) Free Version
The LSI products with “E1” are compliant with RoHS Directive, and has observed the standard of lead, cadmium, mercury,
Hexavalent chromium, polybrominated biphenyls (PBB), and polybrominated diphenyl ethers (PBDE). Products that are complied
with this standard have “E1” appended to the part number.
26. Marking Format (Lead-free version)
Lead-free
version
INDEX
Document Number: 002-08369 Rev. *B
Page 47 of 53
MB39C011A
27. Labeling Sample (Lead-free version)
Lead-free mark
JEITA logo JEDEC logo
MB123456P - 789 - GE1
(3N) 1MB123456P-789-GE1 1000
G
Pb
(3N)2 1561190005 107210
QC PASS
PCS
1,000
MB123456P - 789 - GE1
ASSEMBLED IN JAPAN
2006/03/01
MB123456P - 789 - GE1
1/1
1561190005
0605 - Z01A 1000
The part number of a lead-free product has
the trailing characters "E1".
Document Number: 002-08369 Rev. *B
Page 48 of 53
MB39C011A
28. MB39C011APFT-❏❏❏E1 Recommended Mounting Conditions
28.1 Recommended Mounting Conditions
Item
Condition
IR (infrared reflow), Manual soldering (partial heating method)
2 times
Mounting Method
Mounting times
Please use it within two years after
Before opening
Manufacture.
From opening to the 2nd
reflow
Storage period
Less than 8 days
When the storage period after
opening was exceeded
Please processes within 8 days
after baking (125˚C, 24H)
Storage conditions
5˚C to 30˚C, 70%RH or less (the lowest possible humidity)
Document Number: 002-08369 Rev. *B
Page 49 of 53
MB39C011A
28.2 Parameters for Each Mounting Method
28.2.1
IR (infrared reflow)
H rank : 260˚C Max
260 °C
255 °C
170 °C
to
190 °C
(b)
(c)
(d)
(e)
RT
(a)
(d')
(a) Temperature Increase gradient
(b) Preliminary heating
(c) Temperature Increase gradient
(d) Actual heating
: Average 1˚C/s to 4˚C/s
: Temperature 170˚C to 190˚C, 60s to 180s
: Average 1˚C/s to 4˚C/s
: Temperature 260˚C Max; 255˚C or more, 10s or less
(d’)
: Temperature 230˚C or more, 40s or less or
Temperature 225˚C or more, 60s or less or
Temperature 220˚C or more, 80s or less
(e) Cooling
: Natural cooling or forced cooling
Note : Temperature : the top of the package body
28.2.2
Manual soldering (partial heating method)
Conditions : Temperature 400˚C Max
Times : 5 s max/pin
Document Number: 002-08369 Rev. *B
Page 50 of 53
MB39C011A
29. Package Dimensions
16-pin plastic TSSOP
Lead pitch
0.65 mm
Package width
package length
×
4.40 × 5.00 mm
Gullwing
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.10mm MAX
0.06g
Code
(Reference)
P-TSSOP16-4.4×5.0-0.65
(FPT-16P-M07)
16-pin plastic TSSOP
(FPT-16P-M07)
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max).
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
15.00 0.10(.197 .004)
*
0.17 0.05
(.007 .002)
16
9
2 4.40 0.10 6.40 0.20
*
(.173 .004) (.252 .008)
INDEX
Details of "A" part
1.05 0.05
(Mounting height)
(.041 .002)
1
8
LEAD No.
"A"
0.65(.026)
0.24 0.08
(.009 .003)
0~8
˚
M
0.13(.005)
0.07 +–00..0073 .003 –+..000031
(Stand off)
(0.50(.020))
0.60 0.15
0.25(.010)
(.024 .006)
0.10(.004)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
©2003-2008 FUJITSU MICROELECTRONICS LIMITED F16020S-c-3-4
003 JTLI1602Sc3-3
Document Number: 002-08369 Rev. *B
Page 51 of 53
MB39C011A
Document History
Spansion Publication Number: DS04-27260-2E
Document Title: MB39C011A 2ch DC/DC Converter IC with Synchronous Rectification Datasheet
Document Number: 002-08369
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
TAOA
08/07/2008 Migrated to Cypress and assigned document number 002-08369.
No change to document contents or format.
−
*A
*B
5187215
5830510
TAOA
03/19/2016 Updated to Cypress template
07/24/2017 Adapted Cypress new logo.
MASG
Document Number: 002-08369 Rev. *B
Page 52 of 53
MB39C011A
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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ARM and Cortex are the trademarks of ARM Limited in the EU and other countries
© Cypress Semiconductor Corporation, 2007-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
53
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-08369 Rev. *B
Revised July 24, 2017
Page 53 of 53
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