MB39C015 [CYPRESS]
High efficiency : 96% (Max);
| 型号： | MB39C015 |
| 厂家： | 
CYPRESS |
| 描述： | High efficiency : 96% (Max) |
| 文件： | 总43页 (文件大小：1608K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MB39C015
2ch DC/DC Converter IC Datasheet
The MB39C015 is a current mode type 2-channel DC/DC converter IC built-in voltage detection, synchronous rectifier, and down
conversion support. The device is integrated with a switching FET, oscillator, error amplifier, PWM control circuit, reference voltage
source, and voltage detection circuit.
External inductor and decoupling capacitor are needed only for the external component.
As combining with external parts enables a DC/DC converter with a compact and high load response characteristic, this is suitable
as the built-in power supply for such as mobile phone/PDA, DVDs, and HDDs.
Features
■ High efficiency
: 96% (Max)
■ Output current (DC/DC)
■ Input voltage range
■ Operating frequency
■ No flyback diode needed
■ Low dropout operation
: 800 mA/ch (Max)
: 2.5 V to 5.5 V
: 2.0 MHz (Typ)
: For 100% on duty
■ Built-in high-precision reference voltage generator : 1.30 V 2%
■ Consumption current in shutdown mode
: 1 A or less
■ Built-in switching FET
: P-ch MOS 0.3 Ω (Typ) N-ch MOS 0.2 Ω (Typ)
■ High speed for input and load transient response in the current mode
■ Over temperature protection
■ Packaged in a compact package
: QFN-24
Applications
■ Flash ROMs
■ MP3 players
■ Electronic dictionary devices
■ Surveillance cameras
■ Portable GPS navigators
■ DVD drives
■ IP phones
■ Network hubs
■ Mobile phones etc.
Cypress Semiconductor Corporation
Document Number: 002-08364 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 1, 2016
MB39C015
Contents
Pin Assignment ................................................................3
Pin Descriptions ...............................................................4
I/O Pin Equivalent Circuit Diagram .................................5
Block Diagram ..................................................................6
Function of Each Block ....................................................8
Absolute Maximum Ratings ..........................................10
Recommended Operating Conditions ..........................11
Electrical Characteristics ...............................................12
Test Circuit For Measuring Typical
Operating Characteristics ..............................................14
Application Notes ...........................................................15
Selection of components ...........................................15
Output voltage setting ..............................................16
About conversion efficiency .......................................16
Power dissipation and heat considerations............... 17
XPOR threshold voltage setting
[VPORH, VPORL] .......................................................18
Transient response ....................................................19
Board layout, design example ...................................20
Example Of Standard Operation Characteristics ........21
Application Circuit Examples ........................................29
Application Circuit Examples ........................................30
Usage Precautions .........................................................32
Ordering Information ......................................................32
RoHS Compliance Information of
Lead (Pb) Free Version .................................................. 33
Marking Format (Lead Free Version) ....................... 33
Labeling Sample (Lead Free Version) ......................33
Evaluation Board Specification .....................................34
EV Board Ordering Information ....................................40
Package Dimension ........................................................41
Document Number: 002-08364 Rev. *A
Page 2 of 43
MB39C015
1. Pin Assignment
(Top View)
LX2 DGND2 DGND2 DGND1 DGND1 LX1
18
17
16
15
14
13
DVDD2
DVDD2
OUT2
DVDD1
DVDD1
OUT1
12
11
10
9
19
20
21
22
23
24
MODE2
MODE1
VREFIN2
VREFIN1
8
7
XPOR
VDET
1
2
3
4
5
6
CTLP CTL2 CTL1 AGND AVDD VREF
(LCC-24P-M10)
Document Number: 002-08364 Rev. *A
Page 3 of 43
MB39C015
2. Pin Descriptions
Pin No.
Pin Name
I/O
Description
1
CTLP
I
I
Voltage detection circuit block control input pin.
(L : Voltage detection function stop, H : Normal operation)
2/3
CTL2/CTL1
DC/DC converter block control input pin.
(L : Shut down, H : Normal operation)
4
5
6
7
AGND
–
–
Control block ground pin.
AVDD
Control block power supply pin.
Reference voltage output pin.
Voltage detection input pin.
VREF
O
I
VDET
8/23
9/22
10/21
VREFIN1/VREFIN2
MODE1/MODE2
OUT1/OUT2
DVDD1/DVDD2
I
Error amplifier (Error Amp) non-inverted input pin.
Use pin at L level or leave open.
Output voltage feedback pin.
I
I
11, 12/
19, 20
–
Drive block power supply pin.
13/18
LX1/LX2
O
–
Inductor connection output pin.
High impedance during shut down.
14, 15/
16, 17
DGND1/DGND2
XPOR
Drive block ground pin.
24
O
VDET circuit output pin.
Connected to an N-ch MOS open drain circuit.
Document Number: 002-08364 Rev. *A
Page 4 of 43
MB39C015
3. I/O Pin Equivalent Circuit Diagram
VDD
VDD
∗
∗
LX1, LX2
VREF
GND
GND
VDD
∗
∗
∗
VREFIN1,
VREFIN2,
VDET
OUT1, OUT2
∗
GND
VDD
CTL1, CTL2, CTLP
∗
GND
VDD
XPOR
∗
∗
MODE1,
MODE2
GND
∗
* : ESD Protection device
GND
Document Number: 002-08364 Rev. *A
Page 5 of 43
MB39C015
4. Block Diagram
VIN
AVDD
ERR
DVDD1
DVDD2
5
11, 12 19, 20
CTL1
3
ON/OFF
OUT1
×3
Amplifier
DVDD1
10
−
+
IOUT
Comparator
VREFIN1
MODE1
8
9
DAC
PWM
Logic
LX1
13
VOUT1
Control
GND
VIN
VIN
CTLP
VDET
1
7
ON/OFF
24
−
+
XPOR
1.30 V
VREF
VREF
6
2
CTL2
OUT2
ON/OFF
ERR
×3
DVDD2
Amplifier
21
−
+
IOUT
Comparator
VREFIN2
23
PWM
Logic
LX2
18
VOUT2
Control
MODE2
GND
22
4
16, 17
DGND2
14, 15
DGND1
AGND
Document Number: 002-08364 Rev. *A
Page 6 of 43
MB39C015
■ Current mode
❐ Original voltage mode type :
Stabilize the output voltage by comparing two items below and on-duty control.
• Voltage (VC) obtained through negative feedback of the output voltage by Error Amp
• Reference triangular wave (VTRI)
❐ Current mode type :
Instead of the triangular wave (VTRI), the voltage (VIDET) obtained through I-V conversion of the sum of currents that flow in the
oscillator (rectangular wave generation circuit) and SW FET is used.
Stabilize the output voltage by comparing two items below and on-duty control.
• Voltage (VC) obtained through negative feedback of the output voltage by Error Amp
• Voltage (VIDET) obtained through I-V conversion of the sum of current that flow in the oscillator (rectangular wave generation
circuit) and SW FET
Voltage mode type model
Current mode type model
V
IN
V
IN
Oscillator
−
+
S
R
Vc
+
−
Vc
Q
V
TRI
V
IDET
SR-FF
Vc
V
IDET
V
TRI
Vc
ton
toff
toff
ton
Note : The above models illustrate the general operation and an actual operation will be preferred in the IC.
Document Number: 002-08364 Rev. *A
Page 7 of 43
MB39C015
5. Function of Each Block
■ PWM Logic control circuit
The built-in P-ch and N-ch MOS FETs are controlled for synchronization rectification according to the frequency (2.0 MHz) oscillated
from the built-in oscillator (square wave oscillation circuit).
■ IOUT Comparator circuit
This circuit detects the current (ILX) which flows to the external inductor from the built-in P-ch MOS FET. By comparing VIDET obtained
through I-V conversion of peak current IPK of ILX with the Error Amp output, the built-in P-ch MOS FET is turned off via the PWM Logic
Control circuit.
■ Error Amp phase compensation circuit
This circuit compares the output voltage to reference voltages such as VREF. This IC has a built-in phase compensation circuit that
is designed to optimize the operation of this IC.This needs neither to be considered nor addition of a phase compensation circuit and
an external phase compensation device.
■ VREF circuit
A high accuracy reference voltage is generated with BGR (bandgap reference) circuit. The output voltage is 1.30 V (Typ).
■ Voltage Detection (VDET) circuit
The voltage detection circuit monitors the voltage at the VDET pin. Normally, use the XPOR pin through pull-up with an external
resistor. When the VDET pin voltage reaches 0.6 V, it reaches the H level.
Timing chart example : (XPOR pin pulled up to VIN)
VIN
V
UVLO
CTLP
V
THHPR
THLPR
V
VDET
XPOR
VUVLO : UVLO threshold voltage
VTHHPR, VTHLPR : XPOR threshold voltage
■ Protection circuit
This IC has a built-in over-temperature protection circuit. The over-temperature protection circuit turns off both N-ch and P-ch switching
FETs when the junction temperature reaches 135 °C . When the junction temperature comes down to 110 °C , the switching FET
is returned to the normal operation. Since the PWM control circuit of this IC is in the control method in current mode, the current peak
value is also monitored and controlled as required.
Document Number: 002-08364 Rev. *A
Page 8 of 43
MB39C015
■ Function table
Input
CTL2
Output
CH2 function
MODE
VDET
function
VREF
function
CTL1
CTLP
CH1 function
Shutdown mode
L
Stopped
Operation
Stopped
Stopped
Operation
Stopped
Operation
Operation
H
L
L
L
Stopped
Operation
Stopped
Operation
Operation
Stopped
Stopped
H
L
L
Stopped
L
H
L
Operation
Stopped
Operating mode
Outputs 1.3 V
H
L
H
H
L
H
H
Operation
Operation
H
H
Document Number: 002-08364 Rev. *A
Page 9 of 43
MB39C015
6. Absolute Maximum Ratings
Rating
Parameter
Symbol
VDD
Condition
Unit
Min
Max
Power supply voltage
Signal input voltage
AVDD DVDD1 DVDD2
OUT1/OUT2 pins
0.3
0.3
0.3
6.0
VDD 0.3
VDD 0.3
V
V
VISIG
CTLP, CTL1/CTL2,
MODE1/MODE2 pins
VREFIN1/VREFIN2 pins
VDET pin
0.3
0.3
0.3
0.3
–
VDD 0.3
VDD 0.3
6.0
VDD 0.3
1.8
XPOR pull-up voltage
LX voltage
VIXPOR
VLX
IPK
XPOR pin
V
LX1/LX2 pins
ILX1/ILX2
V
LX Peak current
Power dissipation
A
PD
Ta 25 °C
–
3125*1, *2, *3
1563*1, *2, *4
1250*1, *2, *3
625*1, *2, *4
85
mW
–
Ta 85 °C
–
mW
–
Operating ambient
temperature
Ta
–
–
40
°C
°C
Storage temperature
TSTG
55
125
*1 : Power dissipation value between + 25 °C and + 85 °C is obtained by connecting these two points with straight line.
*2 : When mounted on a four-layer epoxy board of 11.7 cm × 8.4 cm
*3 : Connection at exposure pad with thermal via. (Thermal via 9 holes)
*4 : Connection at exposure pad, without a thermal via.
Notes:
• The use of negative voltages below 0.3 V to the AGND, DGND1, and DGND2 pin may create parasitic
transistors on LSI lines, which can cause abnormal operation.
• This device can be damaged if the LX1 pin and LX2 pin are short-circuited to AVDD and DVDD1/DVDD2,
or AGND and DGND1/DGND2.
WARNING:
Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-08364 Rev. *A
Page 10 of 43
MB39C015
7. Recommended Operating Conditions
Value
Typ
Parameter
Symbol
VDD
Condition
Unit
Min
2.5
Max
Power supply voltage
VREFIN voltage
CTL voltage
AVDD DVDD1 DVDD2
3.7
5.5
V
VREFIN
VCTL
ILX
–
0.15
–
–
–
–
1.30
5.0
V
CTLP, CTL1, CTL2
0
–
–
V
LX current
ILX1/ILX2
800
0.5
mA
mA
VREF output current
IROUT
2.5 V AVDD DVDD1 DVDD2 <
3.0 V
3.0 V AVDD DVDD1 DVDD2
–
–
1
5.5 V
XPOR current
Inductor value
IPOR
L
–
–
–
–
–
1
–
mA
2.2
H
Note :
The output current from this device has a situation to decrease if the power supply voltage (VIN) and the DC/DC converter output
voltage (VOUT) differ only by a small amount. This is a result of slope compensation and will not damage this device.
WARNING:
The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
Document Number: 002-08364 Rev. *A
Page 11 of 43
MB39C015
8. Electrical Characteristics
(Ta 25 °C , AVDD DVDD1 DVDD2 3.7 V, VOUT1/VOUT2 setting value 2.5 V, MODE1/MODE2 0 V)
Value
Sym-
bol
Parameter
Pin No.
Condition
Unit
Min
100
2.45
Typ
Max
100
2.55
Input current
IREFIN
8, 23
10, 21
VREFIN 0.15 V to 1.3 V
0
nA
Output voltage
VOUT
VREFIN 0.833 V,
2.50
V
OUT 100 mA
Input stability
Load stability
LINE
LOAD
ROUT
2.5 V AVDD DVDD1
DVDD2 5.5 V*1
–
–
10
10
1.5
mV
mV
MΩ
100 mA ≥ OUT ≥
–
–
800 mA
OUT pin input
impedance
OUT 2.0 V
0.6
1.0
LX Peak current
IPK
13, 18
Output shorted to GND
–
0.9
1.6
1.2
2.0
1.7
2.4
A
DC/DC
converter
block
Oscillation
frequency
fosc
MHz
Rise delay time
tPG
2, 3,
10, 21
C1/C2 4.7 F, OUT
0 A, OUT1/OUT2 : 0 → 90%
VOUT
–
45
80
s
SW NMOS-FET
OFF voltage
VNOFF
13, 18
–
–
10*
0.30
–
mV
Ω
SWPMOS-FET ON RONP
resistance
LX1/LX2 100 mA
LX1/LX2 100 mA
0 LX VDD*2
VDD 5.5 V, 0 LX VDD*2 2.0
–
–
0.48
0.42
SWNMOS-FETON RONN
resistance
–
0.20
Ω
LX leak current
ILEAKM
ILEAKH
TOTPH
1.0
–
8.0
16.0
160*
A
A
°C
–
Overheating
protection (Junction
Temp.)
–
120*
135*
TOTPL
95*
110*
125*
°C
Protection
circuit block
UVLO threshold
voltage
VTHHUV
VTHLUV
VHYSUV
5, 11,
12, 19, 20
–
2.17
2.03
0.08
2.30
2.15
0.15
2.43
2.27
0.25
V
V
V
UVLO
hysteresis width
–
–
XPOR threshold
voltage
VTHHPR
VTHLPR
VHYSPR
7
575
558
–
600
583
17
625
608
–
mV
mV
mV
Voltage
detection
circuit block
XPOR
hysteresis width
–
XPOR output
voltage
VOL
IOH
24
XPOR 25 A
XPOR 5.5 V
–
–
–
–
0.1
1.0
V
XPOR output
current
A
* : Standard design value
(Continued)
Document Number: 002-08364 Rev. *A
Page 12 of 43
MB39C015
(Continued)
(Ta 25 °C , AVDD DVDD1 DVDD2 3.7 V, VOUT1/VOUT2 setting value 2.5 V, MODE1/MODE2 0 V)
Value
Parameter
Symbol
Pin No.
Condition
Unit
Min
0.55
Typ
0.95
Max
1.45
CTL threshold
voltage
VTHHCT
VTHLCT
IICTL
1, 2, 3
–
–
V
0.40
–
0.80
–
1.30
1.0
V
Control block
CTL pin
input current
0 V CTLP/CTL1/CTL2
A
3.7 V
Reference
voltage block
VREF voltage
VREF
6
VREF 0 mA
VREF 1.0 mA
1.274
–
1.300
–
1.326
20
V
VREF Load
stability
LOADREF
mV
Shut down
power supply
current
IVDD1
CTLP/CTL1/CTL2 0 V
–
–
–
–
1.0
1.0
A
A
State of all circuits OFF*3
IVDD1H
CTLP/CTL1/CTL2 0 V,
VDD 5.5 V
State of all circuits OFF*3
Power supply current IVDD31
(DC/DC mode)
1. CTLP 0 V, CTL1 3.7 V,
CTL2 0 V
–
3.5
10
mA
2. CTLP 0 V, CTL1 0 V,
CTL2 3.7 V
5, 11,
12, 19,
20
General
OUT 0 A
IVDD32
CTLP 0 V, CTL1/CTL2
–
–
7.0
15
20.0
24
mA
3.7 V, OUT 0 A
Power supply current IVDD5
(voltage detection
mode)
CTLP 3.7 V,
A
CTL1/CTL2 0 V,
Power-on
invalid current
IVDD
1. CTL1 3.7 V, CTL2 0 V
2. CTL1 0 V, CTL2 3.7 V
VOUT1/VOUT2 90%
OUT 0 A*4
–
1000
2000
A
*1 : The minimum value of AVDD = DVDD1 = DVDD2 is the 2.5 V or VOUT setting value + 0.6 V, whichever is higher.
*2 : The + leak at the LX1 pin and LX2 pin includes the current of the internal circuit.
*3 : Sum of the current flowing into the AVDD, the DVDD1, and the DVDD2 pins.
*4 : Current consumption based on 100% ON-duty (High side FET in full ON state). The SW FET gate drive current is not included
because the device is in full ON state (no switching operation). Also the load current is not included.
Document Number: 002-08364 Rev. *A
Page 13 of 43
MB39C015
9. Test Circuit For Measuring Typical Operating Characteristics
MB39C015
VDD
V
DD
SW
VIN
CTL1/CTL2
DVDD1/DVDD2
C2
R1
4.7 μF
1 MΩ
AVDD
MODE1/MODE2
C3
4.7 μF
L1
2.2 μH
LX1/LX2
VOUT1/
VOUT2
VREF
VDET
R5
510 kΩ
R3-1
OUT1/OUT2
20 kΩ
R6
100 kΩ
I
OUT
C1
4.7 μF
R3-2
150 kΩ
DGND1/DGND2
VREFIN1/VREFIN2
AGND
C6
0.1 μF
GND
R4
300 kΩ
Output voltage VREFIN × 3.01
Component
Specification
Vendor
KOA
Part Number
Remarks
R1
1 MΩ
RK73G1JTTD D 1 MΩ
R3-1
R3-2
20 kΩ
SSM
SSM
RR0816-203-D
RR0816-154-D
150 kΩ
300 kΩ
510 kΩ
100 kΩ
4.7 F
4.7 F
0.1 F
0.1 F
2.2 H
VOUT1/VOUT2 2.5 V
Setting
R4
R5
R6
C1
C2
C3
C6
L1
SSM
KOA
SSM
TDK
TDK
TDK
TDK
TDK
RR0816-304-D
RK73G1JTTD D 510 kΩ
RR0816-104-D
C2012JB1A475K
C2012JB1A475K
C1608JB1E104K
C1608JB1H104K
VLF4012AT-2R2M
For adjusting slow start time
Note : These components are recommended based on the operating tests authorized.
TDK : TDK Corporation
SSM : SUSUMU Co., Ltd
KOA : KOA Corporation
Document Number: 002-08364 Rev. *A
Page 14 of 43
MB39C015
10. Application Notes
10.1 Selection of components
■ Selection of an external inductor
Basically it dose not need to design inductor. This IC is designed to operate efficiently with a 2.2 H inductor.
The inductor should be rated for a saturation current higher than the LX peak current value during normal operating conditions, and
should have a minimal DC resistance. (100 mΩ or less is recommended.)
LX peak current value IPK is obtained by the following formula.
VIN VOUT
D
1
2
(VIN VOUT) × VOUT
IPK IOUT
×
×
IOUT
L
fosc
2 × L × fosc × VIN
L
: External inductor value
: Load current
IOUT
VIN
VOUT
D
: Power supply voltage
: Output setting voltage
: ON-duty to be switched ( = VOUT/VIN)
: Switching frequency (2.0 MHz)
fosc
ex) When VIN 3.7 V, VOUT 2.5 V, IOUT 0.8 A, L 2.2 H, fosc 2.0 MHz
The maximum peak current value IPK;
(VIN VOUT) × VOUT
2 × L × fosc × VIN
(3.7 V 2.5 V) × 2.5 V
2 × 2.2 H × 2.0 MHz × 3.7 V
IPK IOUT
0.8 A
=: 0.89 A
■ I/O capacitor selection
❐ Select a low equivalent series resistance (ESR) for the VDD input capacitor to suppress dissipation from ripple currents.
❐ Also select a low equivalent series resistance (ESR) for the output capacitor. The variation in the inductor current causes ripple
currents on the output capacitor which, in turn, causes ripple voltages an output equal to the amount of variation multiplied by the
ESR value. The output capacitor value has a significant impact on the operating stability of the device when used as a DC/DC
converter. Therefore, FUJITSU SEMICONDUCTOR generally recommends a 4.7 F capacitor, or a larger capacitor value can
be used if ripple voltages are not suitable. If the VIN/VOUT voltage difference is within 0.6 V, the use of a 10 F output capacitor
value is recommended.
❐ Types of capacitors
Ceramiccapacitors are effective for reducing the ESR and afford smaller DC/DC converter circuit. However, power supply functions
as a heat generator, therefore avoid to use capacitor with the F-temperature rating ( 80% to 20%).Cypress recommends
capacitors with the B-temperature rating ( 10% to 20%). Normal electrolytic capacitors are not recommended due to their
high ESR.Tantalum capacitor will reduce ESR, however, it is dangerous to use because it turns into short mode when damaged.
If you insist on using a tantalum capacitor, Cypress recommends the type with an internal fuse.
Document Number: 002-08364 Rev. *A
Page 15 of 43
MB39C015
10.2 Output voltage setting
The output voltage VOUT (VOUT1 or VOUT2) of this IC is defined by the voltage input to VREFIN (VREFIN1 or VREFIN2) . Supply the
voltage for inputting to VREFIN from an external power supply, or set the VREF output by dividing it with resistors.
The output voltage when the VREFIN voltage is set by dividing the VREF voltage with resistors is shown in the following formula.
R2
VOUT 3.01 × VREFIN, VREFIN
× VREF
R1 R2
(VREF 1.30 V)
MB39C015
VREF
VREF
R1
R2
VREFIN
VREFIN
Note :
Refer to “ Application Circuit Examples” for the an example of this circuit.
Although the output voltage is defined according to the dividing ratio of resistance, select the resistance value so that the current
flowing through the resistance does not exceed the VREF current rating (1 mA) .
10.3 About conversion efficiency
The conversion efficiency can be improved by reducing the loss of the DC/DC converter circuit.
The total loss (PLOSS) of the DC/DC converter is roughly divided as follows :
PLOSS = PCONT + PSW + PC
PCONT : Control system circuit loss (The power used for this IC to operate, including the gate driving power for internal SW FETs)
PSW
PC
: Switching loss (The loss caused during switching of the IC's internal SW FETs)
: Continuity loss (The loss caused when currents flow through the IC's internal SW FETs and external circuits )
Document Number: 002-08364 Rev. *A
Page 16 of 43
MB39C015
The IC's control circuit loss (PCONT) is extremely small, less than 100 mW (with no load).
As the IC contains FETs which can switch faster with less power, the continuity loss (PC) is more predominant as the loss during heavy-
load operation than the control circuit loss (PCONT) and switching loss (PSW) .
Furthermore, the continuity loss (PC) is divided roughly into the loss by internal SW FET ON-resistance and by external inductor series
resistance.
2
PC = IOUT × (RDC + D × RONP + (1 - D) × RONN)
D
: Switching ON-duty cycle ( = VOUT / VIN)
: Internal P-ch SW FET ON resistance
: Internal N-ch SW FET ON resistance
RONP
RONN
RDC : External inductor series resistance
IOUT : Load current
The above formula indicates that it is important to reduce RDC as much as possible to improve efficiency by selecting
components.
10.4 Power dissipation and heat considerations
The IC is so efficient that no consideration is required in most cases. However, if the IC is used at a low power supply voltage, heavy
load, high output voltage, or high temperature, it requires further consideration for higher efficiency.
The internal loss (P) is roughly obtained from the following formula :
2
P = IOUT × (D × RONP + (1 - D) × RONN)
D
: Switching ON-duty cycle ( = VOUT / VIN)
: Internal P-ch SW FET ON resistance
: Internal N-ch SW FET ON resistance
: Output current
RONP
RONN
IOUT
The loss expressed by the above formula is mainly continuity loss. The internal loss includes the switching loss and the control circuit
loss as well but they are so small compared to the continuity loss they can be ignored.
In this IC with RONP greater than RONN, the larger the on-duty cycle, the greater the loss.
When assuming VIN 3.7 V, Ta 70 °C , for example, RONP 0.36 Ω and RONN 0.30 Ω according to the graph “MOS FET
ON resistance vs. Operating ambient temperature”. The IC's internal loss P is 123 mW at VOUT 2.5 V and IOUT 0.6 A. According
to the graph “Power dissipation vs. Operating ambient temperature”, the power dissipation at an operating ambient temperature Ta
of 70 °C is 300 mW and the internal loss is smaller than the power dissipation.
Document Number: 002-08364 Rev. *A
Page 17 of 43
MB39C015
10.5 XPOR threshold voltage setting [VPORH, VPORL]
Set the detection voltage by applying voltage to the VDET pin via an external resistor calculated according to this formula.
R3 R4
VPORH
× VTHHPR
R4
R3 R4
R4
VPORL
× VTHLPR
VTHHPR = 0.600 V
VTHLPR = 0.583 V
Example for setting detection voltage to 3.7 V
R3 = 510 kΩ
R4 = 100 kΩ
510 kΩ 100 kΩ
VPORH
× 0.600 3.66=: 3.7 [V]
× 0.583 3.56=: 3.6 [V]
100 kΩ
510 kΩ 100 kΩ
100 kΩ
VPORL
VIN
MB39C015
AVDD
R3
R4
1 MΩ
VDET
XPOR
XPOR
Document Number: 002-08364 Rev. *A
Page 18 of 43
MB39C015
10.6 Transient response
Normally, IOUT is suddenly changed while VIN and VOUT are maintained constant, responsiveness including the response time and
overshoot/undershoot voltage is checked. As this IC has built-in Error Amp with an optimized design, it shows good transient response
characteristics. However, if ringing upon sudden change of the load is high due to the operating conditions, add capacitor C6 (e.g. 0.1
F). (Since this capacitor C6 changes the start time, check the start waveform as well.) This action is not required for DAC input.
MB39C015
VREF
VREF
R1
VREFIN
VREFIN1/
VREFIN2
R2
C6
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Page 19 of 43
MB39C015
10.7 Board layout, design example
The board layout needs to be designed to ensure the stable operation of this IC.
Follow the procedure below for designing the layout.
• Arrange the input capacitor (Cin) as close as possible to both the VDD and GND pins. Make a through hole (TH) near the pins
of this capacitor if the board has planes for power and GND.
• Large AC currents flow between this IC and the input capacitor (Cin), output capacitor (Co), and external inductor (L). Group
these components as close as possible to this IC to reduce the overall loop area occupied by this group. Also try to mount these
components on the same surface and arrange wiring without through hole wiring. Use thick, short, and straight routes to wire
the net (The layout by planes is recommended.).
• Arrange a bypass capacitor for AVDD as close as possible to both the AVDD and AGND pins. Make a through hole (TH) near
the pins of this capacitor if the board has planes for power and GND.
• The feedback wiring to the OUT should be wired from the voltage output pin closest to the output capacitor (Co). The OUT pin
is extremely sensitive and should thus be kept wired away from the LX1 and pin LX2 pin of this IC as far as possible.
• If applying voltage to the VREFIN1/VREFIN2 pins through dividing resistors, arrange the resistors so that the wiring can be kept
as short as possible. Also arrange them so that the GND pin of VREFIN1/VREFIN2 resistor is close to the IC's AGND pin.
Further, provide a GND exclusively for the control line so that the resistor can be connected via a path that does not carry current.
If installing a bypass capacitor for the VREFIN, put it close to the VREFIN pin.
• If applying voltage to the VDET pin through dividing resistors, arrange the resistors so that the wiring can be kept as short as
possible. Also arrange so that the GND pin of the VDET resistor is close to the IC's AGND pin. Further, provide a GND exclusively
for the control line so that the resistor can be connected via a path that does not carry current.
• Try to make a GND plane on the surface to which this IC will be mounted. For efficient heat dissipation when using the QFN-24
package, Cypress recommends providing a thermal via in the footprint of the thermal pad.
■ Example of arranging IC SW system parts
Co
Co
L
L
GND
Cin
Cin
VIN
VIN
Feedback line
Feedback line
1pin
GND
VIN
AVDD bypass capacitor
■ Notes for circuit design
The switching operation of this IC works by monitoring and controlling the peak current which, incidentally, serves as a form of short-
circuit protection. However, do not leave the output short-circuited for long periods of time. If the output is short-circuited where VIN <
2.9 V, the current limit value (peak current to the inductor) tends to rise. Leaving in the short-circuit state, the temperature of this IC
will continue rising and activate the thermal protection.
Once the thermal protection stops the output, the temperature of the IC will go down and operation will be restarted, after which the
output will repeat the starting and stopping.
Although this effect will not destroy the IC, the thermal exposure to the IC over prolonged hours may affect the peripherals surrounding
it.
Document Number: 002-08364 Rev. *A
Page 20 of 43
MB39C015
11. Example Of Standard Operation Characteristics
(Shown below is an example of characteristics for connection according to “Test Circuit For Measuring Typical Operating
Characteristics”.)
■ Characteristics CH1
Conversion efficiency vs. Load current
Conversion efficiency vs. Load current
100
100
VIN = 3.7 V
90
90
VIN = 3.7 V
80
80
VIN = 3.0 V
70
70
VIN = 3.0 V
VIN = 4.2 V
VIN = 5.0 V
60
50
40
30
20
10
0
VIN = 4.2 V
60
50
40
30
20
10
0
VIN = 5.0 V
Ta = +25 °C
1.2 V
Ta = +25 °C
2.5 V
VOUT
=
VOUT
=
1
10
100
1000
1
10
100
1000
Load current IOUT (mA)
Load current IOUT (mA)
Conversion efficiency vs. Load current
Conversion efficiency vs. Load current
100
100
VIN = 3.7 V
VIN = 3.7 V
90
90
80
70
60
50
40
30
20
10
0
80
VIN = 3.0 V
VIN = 4.2 V
70
VIN = 4.2 V
60
VIN = 5.0 V
50
VIN = 5.0 V
40
30
20
Ta = +25 °C
Ta = +25 °C
3.3 V
10
0
VOUT
=
1.8 V
VOUT
=
1
10
100
1000
1
10
100
1000
Load current IOUT (mA)
Load current IOUT (mA)
(Continued)
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MB39C015
Output voltage vs. Load current
Output voltage vs. Input voltage
2.60
2.58
2.56
2.54
2.52
2.50
2.48
2.46
2.44
2.42
2.40
2.60
2.58
2.56
2.54
2.52
2.50
2.48
2.46
2.44
2.42
2.40
Ta 25 °C
Ta 25 °C
VIN 3.7 V
VOUT 2.5 V setting
VOUT 2.5 V setting
IOUT
= 0 A
IOUT
= 100 mA
2.0
3.0
4.0
5.0
6.0
0
200
400
600
800
Input voltage VIN (V)
Load current IOUT (mA)
Reference voltage vs. Operating
ambient temperature
Reference voltage vs. Input voltage
1.40
1.38
1.36
1.34
1.32
1.30
1.28
1.26
1.24
1.22
1.20
1.40
VIN = 3.7 V
VOUT = 2.5 V
IOUT = 0 V
1.38
1.36
1.34
1.32
1.30
1.28
1.26
1.24
1.22
1.20
Ta = +25 °C
2.5 V
V
OUT
=
I
OUT
= 0 A
I
OUT
= 100 mA
−50
0
+50
+100
2.0
3.0
4.0
5.0
6.0
Operating ambient temperature Ta ( °C )
Input voltage VIN (V)
(Continued)
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Page 22 of 43
MB39C015
Input current vs. Input voltage
Input current vs. Operating ambient
temperature
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
Ta = +25 °C
V
V
IN
=
3.7 V
2.5 V
VOUT
=
2.5 V
OUT
=
−
50
+50
+100
2.0
3.0
4.0
5.0
6.0
0
Input voltage VIN (V)
Operating ambient temperature Ta ( °C )
Oscillation frequency vs. Operating
ambient temperature
Oscillation frequency vs. Input voltage
2.4
2.4
Ta = +25 °C
V
V
IN
=
3.7 V
2.5 V
100 mA
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
V
OUT = 1.8 V
2.3
2.2
2.1
2.0
1.9
1.8
1.7
OUT
=
IOUT = 100 mA
IOUT
=
1.6
−
2.0
3.0
4.0
5.0
6.0
50
+50
+100
0
Operating ambient temperature Ta ( °C )
Input voltage VIN (V)
(Continued)
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MB39C015
MOS FET ON resistance vs.
Input voltage
0.6
0.5
0.4
0.3
0.2
0.1
0
P-ch
N-ch
Ta = +25 °C
2.0
3.0
4.0
5.0
6.0
Input voltage VIN (V)
N-ch MOS FET ON resistance vs.
Operating ambient temperature
P-ch MOS FET ON resistance vs.
Operating ambient temperature
0.6
0.5
0.4
0.3
0.2
0.1
0
0.6
0.5
0.4
0.3
0.2
0.1
0
V = 3.7 V
IN
V = 3.7 V
IN
V = 5.5 V
IN
V
IN
=
5.5 V
+50
−
50
0
+100
−
50
0
+50
+100
Operating ambient temperature Ta ( °C )
Operating ambient temperature Ta ( °C )
(Continued)
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Page 24 of 43
MB39C015
(Continued)
CTL threshold voltage VTH vs. Input voltage
XPOR output voltage VXPOR vs. Input voltage
1.4
6.0
5.0
4.0
3.0
2.0
1.0
0.0
Ta = +25 °C
VPORH = 3.7 V setting
1.2
V
THHCT
1.0
0.8
0.6
0.4
0.2
0.0
V
THLCT
Ta = +25 °C
2.5 V
V
OUT
=
VXPORL
VXPORH
VTHHCT : Circuit OFF → ON
VTHLCT : Circuit ON → OFF
2.0
3.0
4.0
5.0
6.0
2.0
3.0
4.0
5.0
6.0
Input voltage VIN (V)
Input voltage VIN (V)
Power dissipation vs. Operating
ambient temperature
Power dissipation vs. Operating
ambient temperature
(with thermal via)
(without thermal via)
3500
3000
2500
2000
1500
1000
500
3500
3000
2500
2000
1500
1000
500
3125
1563
1250
625
0
0
+85
+100
+85
+100
−50
0
+50
−50
0
+50
Operating ambient temperature Ta ( °C )
Operating ambient temperature Ta ( °C )
Document Number: 002-08364 Rev. *A
Page 25 of 43
MB39C015
■ Switching waveforms
V
OUT : 20 mV/div
VLX : 2.0 V/div
I
LX : 500 mA/div
Ta = +25 °C
V
V
IN = 3.7 V
OUT = 2.5 V
1 µs/div
IOUT = 800 mA
Document Number: 002-08364 Rev. *A
Page 26 of 43
MB39C015
■ Startup waveform
VCTL : 5.0 V/div
I
LX : 500 mA/div
Ta = +25 °C
VIN = 3.7 V
VOUT = 2.5 V
IOUT = 0 A
VREFIN capacitor value =
V
OUT : 1.0 V/div
0.1 F
10 ms/div
V
CTL : 2.0 V/div
I
LX : 500 mA/div
Ta = +25 °C
V
V
IN = 3.7 V
OUT = 2.5 V
VOUT : 1.0 V/div
I
OUT = 0 A
No VREFIN capacitor
10 μs/div
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Page 27 of 43
MB39C015
■ Output waveforms at sudden load changes (0 mA ↔ 800 mA)
IOUT = 0 mA
IOUT = 800 mA
IOUT = 0 mA
VOUT : 100 mV/div
Ta = +25 °C
VIN = 3.7 V
VOUT = 2.5 V
VREFIN capacitor value
0.1 F
10 μs/div
■ Output waveforms at sudden load changes (100 mA ↔ 800 mA)
I
OUT
= 100 mA
I
OUT
= 100 mA
I
OUT
= 800 mA
V
OUT : 100 mV/div
Ta = +25 °C
VIN = 3.7 V
V
OUT = 2.5 V
VREFIN capacitor value
0.1 F
10 μs/div
Document Number: 002-08364 Rev. *A
Page 28 of 43
MB39C015
12. Application Circuit Examples
■ Application Circuit Example 1
❐ An external voltage is input to the reference voltage external input (VREFIN1, VREFIN2) , and the VOUT voltage is set to 3.01 times
the VOUT setting gain.
C3
4.7 μF
VIN
11
12
DVDD1
3
CTL1
CPU
R7
DGND1 14
15
1 MΩ
C4
4.7 μF
19
20
DVDD2
DGND2
8
2
16
17
VREFIN1
CTL2
DAC1
5
4
AVDD
AGND
C5
0.1 μF
R8
1 MΩ
MB39C015
L1
2.2 μH
23
VREFIN2
DAC2
VOUT1
13
10
LX1
C1
4.7 μF
OUT1
APLI1
9
MODE1
MODE2
L2
2.2 μH
22
VOUT2
18
21
LX2
C2
6
VREF
4.7 μF
OUT2
APLI2
7
1
VDET
CTLP
24
XPOR
VOUT = 3.01 × VREFIN
Document Number: 002-08364 Rev. *A
Page 29 of 43
MB39C015
■ Application Circuit Example 2
❐ The voltage of VREF pin is input to the reference voltage external input (VREFIN1, VREFIN2) by dividing resistors. The VOUT1
voltage is set to 2.5 V and VOUT2 voltage is set to 1.8 V.
C3
4.7 μF
VIN
11
12
DVDD1
3
CTL1
CPU
R7
DGND1 14
15
1 MΩ
C4
4.7 μF
19
20
DVDD2
DGND2
R1 170 kΩ
( 20 kΩ + 150 kΩ )
16
17
8
2
VREFIN1
R2
300 kΩ
5
4
AVDD
AGND
C5
0.1 μF
CTL2
R8
1 MΩ
MB39C015
L1
2.2 μH
VOUT1
13
10
LX1
R5 352 kΩ
( 22 kΩ + 330 kΩ )
C1
23
6
VREFIN2
VREF
4.7 μF
OUT1
R6
APLI1
300 kΩ
L2
2.2 μH
VOUT2
18
21
LX2
9
MODE1
MODE2
C2
4.7 μF
22
OUT2
APLI2
1
CTLP
XPOR 24
VOUT1 = 3.01 × VREFIN1
R2
VREFIN1 =
× VREF
R1 + R2
(VREF = 1.30 V)
300 kΩ
170 kΩ + 300 kΩ
VOUT1 = 3.01 ×
× 1.30 V = 2.5 V
× 1.30 V = 1.8 V
300 kΩ
352 kΩ + 300 kΩ
VOUT12 = 3.01 ×
Document Number: 002-08364 Rev. *A
Page 30 of 43
MB39C015
■ Application Circuit Example Components List
Component Item
L1
Part Number
VLF4012AT-2R2M
MIPW3226D2R2M
VLF4012AT-2R2M
MIPW3226D2R2M
C2012JB1A475K
C2012JB1A475K
C2012JB1A475K
C2012JB1A475K
C1608JB1E104K
Specification
2.2 H, RDC 76 mΩ
2.2 H, RDC 100 mΩ
2.2 H, RDC 76 mΩ
2.2 H, RDC 100 mΩ
4.7 F (10 V)
4.7 F (10 V)
4.7 F (10 V)
4.7 F (10 V)
0.1 F (50 V)
Package
Vendor
TDK
Inductor
SMD
SMD
SMD
SMD
2012
2012
2012
2012
2012
FDK
TDK
FDK
TDK
TDK
TDK
TDK
TDK
L2
Inductor
C1
C2
C3
C4
C5
R1
Ceramic capacitor
Ceramic capacitor
Ceramic capacitor
Ceramic capacitor
Ceramic capacitor
Resistor
RK73G1JTTD D 20 kΩ
RK73G1JTTD D 150 kΩ
20 kΩ
150 kΩ
1608
1608
KOA
KOA
R2
R5
Resistor
Resistor
RK73G1JTTD D 300 kΩ
300 kΩ
1608
KOA
RK73G1JTTD D 22 kΩ
RK73G1JTTD D 330 kΩ
22 kΩ
330 kΩ
1608
1608
KOA
KOA
R6
R7
R8
Resistor
Resistor
Resistor
RK73G1JTTD D 300 kΩ
RK73G1JTTD D 1 MΩ
RK73G1JTTD D 1 MΩ
300 kΩ
1608
1608
1608
KOA
KOA
KOA
1 MΩ 0.5%
1 MΩ 0.5%
TDK : TDK Corporation
FDK : FDK Corporation
KOA : KOA Corporation
Document Number: 002-08364 Rev. *A
Page 31 of 43
MB39C015
13. Usage Precautions
1. Do not configure the IC over the maximum ratings
If the lC is used over the maximum ratings, the LSl may be permanently damaged.It is preferable for the device to normally operate
within the recommended usage conditions. Usage outside of these conditions adversely affect the reliability of the LSI.
2. Use the devices within recommended operating conditions
The recommended operating conditions are the conditions under which the LSl is guaranteed to operate.The electrical ratings are
guaranteed when the device is used within the recommended operating conditions and under the conditions stated for each item.
3. Printed circuit board ground lines should be set up with consideration for common impedance
4. Take appropriate static electricity measures
• Containers for semiconductor materials should have anti-static protection or be made of conductive material.
• After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
• Work platforms, tools, and instruments should be properly grounded.
• Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground.
5. Do not apply negative voltages
The use of negative voltages below 0.3 V may create parasitic transistors on LSI lines, which can cause abnormal operation.
14. Ordering Information
Part number
MB39C015WQN
Package
Remarks
Exposed PAD
24-pin plastic QFN
(LCC-24P-M10)
Document Number: 002-08364 Rev. *A
Page 32 of 43
MB39C015
15. RoHS Compliance Information of Lead (Pb) Free Version
The LSI products of Cypress with “E1” are compliant with RoHS Directive, and has observed the standard of lead, cadmium, mercury,
hexavalent chromium, polybrominated biphenyls (PBB), and polybrominated diphenyl ethers (PBDE).
A product whose part number has trailing characters “E1” is RoHS compliant.
15.1 Marking Format (Lead Free Version)
39C015
Lead-free version(E1)
XE1
XXXXXX
INDEX
15.2 Labeling Sample (Lead Free Version)
Lead-free mark
JEITA logo
JEDEC logo
MB123456P - 789 - GE1
(3N) 1MB123456P-789-GE1 1000
G
Pb
(3N)2 1561190005 107210
QC PASS
PCS
1,000
MB123456P - 789 - GE1
ASSEMBLED IN JAPAN
2006/03/01
MB123456P - 789 - GE1
1/1
1561190005
0605 - Z01A 1000
“ASSEMBLED IN CHINA” is printed on the label
of a product assembled in China.
The part number of a lead-free product has
the trailing characters “E1”.
Document Number: 002-08364 Rev. *A
Page 33 of 43
MB39C015
16. Evaluation Board Specification
The MB39C015 Evaluation Board provides the proper for evaluating the efficiency and other characteristics of the MB39C015.
■ Terminal information
Symbol
Functions
VIN
Power supply terminal
In standard condition 3.1 V to 5.5 V*
* : When the VIN/VOUT difference is to be held within 0.6 V or less, such as for devices with a
standard output voltage (VOUT1 2.5 V) when VIN < 3.1 V, Cypress recommends changing
the output capacity (C1, C2) to 10 F.
VOUT1, VOUT2
VCTL
Output terminals
(VOUT1: CH1, VOUT2: CH2)
Power supply terminal for setting the CTL1, CTL2 and CTLP terminals.
Use by connecting with CTL1,CTL2 and CTLP.
CTL1, CTL2
Direct supply terminal of CTL (CTL1 : for CH1, CTL2 : for CH2)
CTL1, CTL2 0 V to 0.8 V (Typ.) : Shutdown
CTL1, CTL2 0.95 V (Typ.) to VIN (5 V Max) : Normal operation
MODE1, MODE2
VREF
TEST terminal
MODE1, MODE2 OPEN or GND
Reference voltage output terminal
VREF 1.30 V (Typ.)
VREFIN1, VREFIN2
External reference voltage input terminals
(VREFIN1 : for CH1, VREFIN2 : for CH2)
When an external reference voltage is supplied, connect it to the terminal for each channel.
VDET
CTLP
Voltage input terminal for voltage detection
Voltage detection circuit block control terminal
CTLP L : Voltage detection circuit block stop
CTLP H : Normal operation
XPOR
Voltage detection circuit output terminal
The N-ch MOS open drain circuit is connected.
VXPOR
PGND
Pull-up voltage terminal for the XPOR terminal
Ground terminal
Connect power supply GND to the PGND terminal next to the VIN terminal.
Connect output (load) GND to the PGND terminal between the VOUT1 terminal and the VOUT2 terminal.
AGND
Ground terminal
■ Startup terminal information
Terminal name
Condition
Functions
CTL1
CTL2
CTLP
L : Open
H : Connect to VCTL
ON/OFF switch for CH1
L : Shutdown
H : Normal operation.
L : Open
H : Connect to VCTL
ON/OFF switch for CH2
L : Shutdown
H : Normal operation.
L : Open
H : Connect to VCTL
ON/OFF switch for the voltage detection block
L: Stops the voltage detection circuit
H: Normal operation.
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MB39C015
■ Jumper information
JP
Functions
Short-circuited in the layout pattern of the board (normally used shorted).
Short-circuited in the layout pattern of the board (normally used shorted).
Normally used shorted (0 Ω)
JP1
JP2
JP3
JP6
Normally used shorted (0 Ω)
■ Setup and checkup
1. Setup
a. Connect the CTL1 terminal and the CTL2 terminal to the VCTL terminal.
b. Put it into “L” state by connecting the CTLP terminal to the AGND pad.
c. Connect the power supply terminal to the VIN terminal, and the power supply GND terminal to the PGND terminal. Make sure
PGND is connected to the PGND terminal next to the VIN terminal. (Example of setting power-supply voltage : 3.7 V)
2. Checkup
Supply power to VIN. The IC is operating normally if VOUT1 = 2.5 V (Typ) and VOUT2 = 1.8 V (Typ).
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MB39C015
■ Component layout on the evaluation board (Top View)
C2
C1
C3
VOUT2
MODE2
PGND
VOUT1
L1
PGND
L2
C4
VREFIN2
VIN
M1
C7
R5
R9
C6
R2
C5
R4 - 1
R7
R6 - 2
R6 - 1
XPOR
MODE1
VREFIN1
JP6
AGND
JP3
SW1
R1 - 3
VCTL
VREF
Short
R3
VXPOR
Open
MB39C015EVB-06
Rev.1.0
CTL2
CTL1
CTLP
VDET
R8
R10
Top Side (Component side)
Bottom Side (Soldering side)
Document Number: 002-08364 Rev. *A
Page 36 of 43
MB39C015
■ Evaluation board layout (Top View)
Top Side (Layer1)
Inside GND (Layer2)
Inside VIN & GND (Layer3)
Bottom Side (Layer4)
Document Number: 002-08364 Rev. *A
Page 37 of 43
MB39C015
■ Connection diagram
I
IN
VIN
VIN
PGND
JP3
SW1*
11
12
DVDD1
DGND1
DVDD2
DGND2
C3
C4
VCTL
CTL1
3
9
CTL1
R8
14
15
SW1*
19
20
MODE1
16
17
MODE1
VREF
JP6
R6-1 R6-2
R7
AVDD
AGND
5
4
8
VREFIN1
C5
VREFIN1
C6
AGND
MB39C015
SW1*
SW1*
2
CTL2
R9
I
OUT
L1
CTL2
13
10
LX1
VOUT1
C1
22
MODE2
JP1
OUT1
MODE2
PGND
VREF
I
OUT
R4-1 R4-2
R5
L2
23
VREFIN2
VREFIN2
VREF
C7
18
LX2
VOUT2
C2
JP2
VREF
OUT2 21
VREF
VIN
6
R1-3
VXPOR
XPOR
VDET
7
1
VDET
CTLP
R1-1
SW1*
R1-2
R3
R2
24
XPOR
R10
CTLP
*
Not mounted
Document Number: 002-08364 Rev. *A
Page 38 of 43
MB39C015
■ Component list
COMPONENT
Part Name
MODEL NUMBER
MB39C015WQN
SPECIFICATION
PACKAGE VENDOR REMARK
M1
L1
IC
–
QFN-24
SMD
Cypress
TDK
Inductor
VLF4012AT-2R2M
2.2 H,
RDC 76 mΩ
L2
Inductor
VLF4012AT-2R2M
2.2 H,
SMD
TDK
RDC 76 mΩ
C1
Ceramic capacitor
Ceramic capacitor
Ceramic capacitor
Ceramic capacitor
Ceramic capacitor
Ceramic capacitor
Ceramic capacitor
Jumper
C2012JB1A475K
C2012JB1A475K
C2012JB1A475K
C2012JB1A475K
C1608JB1H104K
C1608JB1H104K
C1608JB1H104K
RK73Z1J
4.7 F (10 V)
4.7 F (10 V)
4.7 F (10 V)
4.7 F (10 V)
0.1 F (50 V)
0.1 F (50 V)
0.1 F (50 V)
50 mΩ Max, 1 A
300 kΩ 0.5%
50 mΩ Max, 1 A
75 kΩ 0.5%
1 MΩ 0.5%
22 kΩ 0.5%
330 kΩ 0.5%
300 kΩ 0.5%
20 kΩ 0.5%
150 kΩ 0.5%
300 kΩ 0.5%
1 MΩ 0.5%
1 MΩ 0.5%
1 MΩ 0.5%
–
2012
2012
2012
2012
1608
1608
1608
1608
1608
1608
1608
1608
1608
1608
1608
1608
1608
1608
1608
1608
1608
–
TDK
TDK
TDK
TDK
TDK
TDK
TDK
KOA
SSM
KOA
SSM
KOA
SSM
SSM
SSM
SSM
SSM
SSM
KOA
KOA
KOA
–
C2
C3
C4
C5
C6
C7
R1-1
R1-2
R1-3
R2
Resistor
RR0816P-304-D
RK73Z1J
Jumper
Resistor
RR0816P-753-D
RK73G1JTTD D 1 MΩ
RR0816P-223-D
RR0816P-334-D
RR0816P-304-D
RR0816P-203-D
RR0816P-154-D
RR0816P-304-D
RK73G1JTTD D 1 MΩ
RK73G1JTTD D 1 MΩ
RK73G1JTTD D 1 MΩ
–
R3
Resistor
R4-1
R4-2
R5
Resistor
Resistor
Resistor
R6-1
R6-2
R7
Resistor
Resistor
Resistor
R8
Resistor
R9
Resistor
R10
SW1
Resistor
Switch
Not
mounted
JP1
JP2
Jumper
Jumper
–
–
–
–
–
–
–
–
Pattern-
shorted
Pattern-
shorted
JP3
JP6
Jumper
Jumper
RK73Z1J
RK73Z1J
50 mΩ Max, 1 A
50 mΩ Max, 1 A
1608
1608
KOA
KOA
Note:
These components are recommended based on the operating tests authorized.
TDK : TDK Corporation
KOA : KOA Corporation
SSM : SUSUMU Co., Ltd
Document Number: 002-08364 Rev. *A
Page 39 of 43
MB39C015
17. EV Board Ordering Information
EV Board Part No.
EV Board Version No.
MB39C015EVB-06 Rev.1.0
Remarks
MB39C015EVB-06
QFN-24
Document Number: 002-08364 Rev. *A
Page 40 of 43
MB39C015
18. Package Dimension
24-pin plastic QFN
Lead pitch
0.50 mm
Package width ×
4.00 mm × 4.00 mm
Plastic mold
0.80 mm Max
0.04 g
package length
Sealing method
Mounting height
Weight
(LCC-24P-M10)
24-pin plastic QFN
(LCC-24P-M10)
2.60 0.10
(.102 .004)
4.00 0.10
(.157 .004)
2.60 0.10
(.102 .004)
4.00 0.10
(.157 .004)
0.25 0.05
(.010 .002)
INDEX AREA
0.40 0.05
(.016 .002)
1PIN CORNER
(C0.35(C.014))
0.50(.020)
TYP
0.75 0.05
(.030 .002)
(0.20(.008))
0.02 +–00..0023
+.001
(.001
)
–.001
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2009-2010 FUJITSU SEMICONDUCTOR LIMITED C24060S-c-1-2
Document Number: 002-08364 Rev. *A
Page 41 of 43
MB39C015
Document History
Document Title: MB39C015 2ch DC/DC Converter IC Datasheet
Document Number: 002-08364
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
–
TAOA
TAOA
07/16/2008 Initial release
*A
5148534
03/01/2016 Migrated Spansion Datasheet from DS04-27254-3E to Cypress format
Document Number: 002-08364 Rev. *A
Page 42 of 43
MB39C015
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC® Solutions
ARM® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
cypress.com/psoc
cypress.com/psoc
Automotive
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Clocks & Buffers
Interface
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Lighting & Power Control
Memory
Technical Support
cypress.com/support
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation 2008-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify
and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right
to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum
extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or compilation of the Software
is prohibited.
CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or
hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any
component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole
or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify
and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress
products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-08364 Rev. *A
Revised March 1, 2016
Page 43 of 43
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