MB39C022JPN_技术文档

MB39C022G/J/L/N

Buck DC/DC Converter

+ Low Noise LDO

Description

The MB39C022 is a 2 channels power supply IC. It consists of one channel Buck DC/DC Converter and one channel LDO regulator.

The DC/DC converter has fast transient response with current mode control topology. Moreover, the integrated LDO provides an

auxiliary output supply for noise sensitive circuit.

Features

■ Power supply voltage range

: 2.5 V to 5.5 V

■ For Buck DC/DC included SW FET (CH1) : output 0.8 V to 4.5 V, 600 mA Max DC

■ For LDO (CH2)

: output 3.30 V (MB39C022G) 300 mA Max DC

: output 2.85 V (MB39C022J) 300 mA Max DC

: output 1.80 V (MB39C022L) 300 mA Max DC

: output 1.20 V (MB39C022N) 300 mA Max DC

■ Error amplifier threshold voltage

: 0.3 V

(2.5 %) (CH1)

■ Fast line transient response with current mode topology (CH1)

■ PFM mode at light load current with VO1/VIN1 ≤ 80 % (IO1 ≤ 10 mA) (CH1)

■ Power-on-reset with 66 ms delay (CH1)

■ Built-in short circuit protect (CH2)

■ Built-in over current protect (CH1, CH2)

■ Built-in thermal protection function

■ Small size plastic SON-10 (3 mm × 3 mm) package

Applications

■ Portable Equipment

■ PND, GPS

■ PMP

■ Mobile TV, USB-dongle (CMMB, DVB-T, DMB-T)

■ Smart-phone

■ MP3

Cypress Semiconductor Corporation

Document Number: 002-08460 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 19, 2017

MB39C022G/J/L/N

Contents

Description ............................................................................. 1

Features .................................................................................. 1

Applications ........................................................................... 1

10. Application Notes ......................................................... 14

10.1 Selection of components ....................................... 14

10.2 DC/DC Output voltage setting ............................... 15

10.3 Power On Reset (POR) ......................................... 15

10.4 Power dissipation and heat considerations ........... 16

10.5 Board layout, design example ............................... 17

1. Pin Assignment ................................................................ 3

2. Pin Descriptions ............................................................... 4

3. I/O Terminal Equivalent Circuit Diagram ........................ 5

4. Block Diagram .................................................................. 6

11. Example Of Standard Operation Characteristics ...... 18

11.1 DC/DC Conversion Efficiency ............................... 18

11.2 DC/DC Load Regulation ........................................ 18

11.3 DC/DC Line Regulation ......................................... 19

11.4 DC/DC Switching Waveform ................................. 19

11.5 LDO Load Regulation ............................................ 20

11.6 LDO Line Regulation ............................................. 20

11.7 LDO Power Supply Rejection Ratio ...................... 21

11.8 DC/DC Load Transient Waveforms ....................... 21

11.9 DC/DC Power MOS FET ON Resistance .............. 22

5. Function Descriptions ...................................................... 7

5.1 PFM/PWM Logic Control Block (CH1) ...................... 7

5.2 Level converter and Iout Comparator circuit (CH1) ... 7

5.3 Error Amp. circuit (CH1) ............................................ 7

5.4 LDO Block (CH2) ....................................................... 7

5.5 POR Block ................................................................. 7

5.6 Reference Voltage Block (VREF) .............................. 7

5.7 Under Voltage Lockout Protection Circuit Block

(UVLO) ........................................................................ 8

5.8 Over Temperature Protection Block (OTP) ............... 8

5.9 Control Block (CTL) ................................................... 8

12. Application Circuits Examples .................................... 24

13. Usage Precautions ....................................................... 26

14. Ordering Information .................................................... 26

15. RoHS Compliance Information .................................... 26

6. Absolute Maximum Ratings ............................................ 9

7. Recommended Operating Conditions .......................... 10

8. Electrical Characteristics ............................................... 11

16. Package Dimension ...................................................... 27

Document History ................................................................ 28

Sales, Solutions, and Legal Information ........................... 29

9. Test Circuit For Measuring Typical Operating

Characteristics ............................................................... 13

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MB39C022G/J/L/N

1. Pin Assignment

(TOP VIEW)

GND1

10

LX

9

VIN1

EN1

7

FB

6

8

1

2

3

4

5

EN2

VIN2

VOUT2

POR

GND2

(WNK010)

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MB39C022G/J/L/N

2. Pin Descriptions

Block

Pin No.

Pin Name

FB

I/O

I

Descriptions

CH1 Error Amplifier input pin

6

9

CH1 (Buck DC/DC)

CH2 (LDO)

LX

O

I

CH1 Inductor connection pin

CH2 LDO output pin

3

VOUT2

EN1

7

CH1 Control pin (L : shutdown / H : operation)

CH2 Control pin (L : shutdown / H : operation)

CH1 Power supply pin

Control

1

EN2

I

8

VIN1

VIN2

GND1

GND2

POR

–

O

2

CH2 Power supply pin

Power

10

5

CH1 Ground pin

CH2 Ground pin

Power-on Reset

4

CH1 Power on reset output pin (NMOS open drain)

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3. I/O Terminal Equivalent Circuit Diagram

VIN1

EN∗

POR

∗

GND2

VIN1

∗

LX

FB

∗

GND1

GND2

VIN2

∗

VOUT2

GND2

* : ESD Protection device

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MB39C022G/J/L/N

4. Block Diagram

<<CH1 Buck DC/DC>>

VIN1

Error

Amp.

6

8

9

FB

IO1 (600 mA Max)

VO1 (0.8 V to 4.5 V)

ICOMP

LX

PFM

PWM

Logic

DRV

Control

Current

Limit

LEVEL

CONV.

OSC

GND1

VIN2

10

VIN or VO1

POR

<<CH2: LDO>>

2

3

Error

Amp.

4

VOUT2

POR

IO2 (300 mA Max)

VO2

3.3 V: MB39C022G

2.85 V: MB39C022J

1.8 V: MB39C022L

1.2 V: MB39C022N

OCP/SCP

VIN

GND2

(2.5 V to 5.5 V)

5

OTP

VREF

UVLO

EN1

EN2

7

1

enb1 (H: CH1 ON)

enb2 (H: CH2 ON)

<<10 PIN>>

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MB39C022G/J/L/N

5. Function Descriptions

5.1 PFM/PWM Logic Control Block (CH1)

The built-in P-ch and N-ch MOS FETs are controlled for synchronization rectification according to the frequency (2.0 MHz) oscillated

from the built-in oscillator (square wave oscillation circuit). Under light load, it operates intermittently.

This circuit protects the through current caused by synchronous rectification and the reverse current in Discontinuous Conduction

Mode.

Since the PWM control circuit of this IC is in the control method in current mode, the current peak value is monitored and controlled

as required.

5.2 Level Converter and Iout Comparator Circuit (CH1)

The Level converter circuit detects the current (ILX) which flows to the external inductor from the built-in P-ch MOS FET. By comparing

VIDET obtained through I-V conversion of peak current I_PKof ILX with the Error Amp. output, the Iout Comparator turns off the built-in

P-ch MOS FET via the PWM Logic Control circuit.

5.3 Error Amp. Circuit (CH1)

The error amplifier (Error Amp.) detects the output voltage from the DC/DC converter and output to the current comparators (ICOMP).

The output voltage setting resistor externally connected to FB allows an arbitrary output voltage to be set.

5.4 LDO Block (CH2)

The integrated low noise low dropout regulator (LDO) is available up to 300 mA current capability and 700 mA over current protection

(OCP) 350 mA short circuit protection (SCP). The LDO output VOUT2 requires a 4.7 μF capacitor for MB39C022G and MB39C022N

and a 1.0 μF capacitor for MB39C022J and MB39C022L for stability. MB39C022G, MB39C022J, MB39C022L and MB39C022N have

fixed 3.3 V, 2.85 V, 1.8 V and 1.2 V output voltages respectively, eliminating the need for an external resistor divider.

5.5 POR Block

The POR circuit monitors the VO1 through the FB pin voltage. When the FB pin voltage reaches 97% of V_FBTH, POR pin becomes

high level after the hold time of 66 ms. The POR pin is an open-drain output and pulled up to VIN or VO1 with an external resistor.

Timing Chart : (POR Pin Pulled up to VIN With Resistor)

VUVLO

VIN

EN1

VTH × 97%

FB

POR

thold

V_UVLO: UVLO threshold voltage (VT_LH= 2.050 V)

V_TH: FB pin threshold voltage (V_TH= 0.3 V)

5.6 Reference Voltage Block (VREF)

A high accuracy reference voltage is generated with BGR (bandgap reference) circuit.

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MB39C022G/J/L/N

5.7 Under Voltage Lockout Protection Circuit Block (UVLO)

The circuit protects against IC malfunction and system destruction/deterioration in a transitional state or a momentary drop of when

the internal reference voltage starts. It detects a voltage drop at the VIN1 pin and stops IC operation. When voltages at the VIN1 pin

exceed the threshold voltage of the under voltage lockout protection circuit, the system is restored.

5.8 Over Temperature Protection Block (OTP)

The circuit protects an IC from heat-destruction. If the junction temperature reaches 135°C, the circuit turns off the CH1 and CH2

^{operation, When the junction temperature comes down to}+ 110°C, the CH1 and CH2 are returned to the normal operation.

5.9 Control Block (CTL)

■ Control function table

EN1

L

EN2

L

CH1 and POR

CH2

OFF

ON

VREF, UVLO, OTP

OFF

ON

OFF

ON

H

L

H

OFF

ON

H

ON

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6. Absolute Maximum Ratings

Rating

Parameter

Symbol

Condition

Unit

Min

− 0.3

–

Max

+ 6.0

VIN1 + 0.3

+ 6.0

VIN1 + 0.3

1.6

Power supply voltage

VIN1

VIN2

VFB

VEN1

VEN2

VPOR

VLX

VIN1 pin

VIN2 pin

V

Input voltage

FB pin

V

EN1 pin

V

EN2 pin

V

POR pull-up voltage

LX voltage

POR pin

V

LX pin

V

LX peak current

VOUT2 peak current

Power dissipation

ILX

LX pin AC

VOUT2 pin AC

^Ta≤ + 25°C

A

IO2

–

0.8

A

2

PD

–

2632*^1,

*

mW

3

–

980*^1,

*

2,

4

Ta = + 85°C

–

1053*^1,

* *

3,

4

–

392*^1,

* *

Storage temperature

T_STG

–

− 55

+ 125

°C

^*1: When mounted on four layer epoxy board of 11.7 cm × 8.4 cm

^*2: At connect the exposure pad and with thermal via (Thermal via 4 pcs).

^*3: At connect the exposure pad and not thermal via.

^*4: Power dissipation value between + 25°C and + 85°C is obtained by connecting these two points with a straight line

Notes:

• The use of negative voltages below − 0.3 V to the GND pin may create parasitic transistors on LSI lines, which can cause

abnormal operation.

• If LX terminal is short-circuited to VIN1 or VIN2 or GND line, there is a possibility to destroy it. Such usage is prohibit

WARNING:

Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

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MB39C022G/J/L/N

7. Recommended Operating Conditions

Value

Typ

Parameter

Symbol

Condition

Unit

Max

Min

3, 4,

5

Power supply voltage

VIN1

VIN2

VFB

VIN1 pin*^1,

*

2.5

3.7

5.5

V

3

VIN2 pin*^2,

Input voltage

FB pin

–

0

0.30

–

V

VEN1

VEN2

VO1

EN1 pin

EN2 pin

–

5.5

4.5

0.6

0.3

+ 85

0

V

5

Output voltage

Output current

CH1 : Buck DC/DC*^1,

*

0.8

–

V

ILX

LX pin DC

–

A

IVOUT2

Ta

VOUT2 pin DC

–

A

Operating ambient

temperature

− 40

+ 25

°C

^*1: The minimum VIN1 has to meet two conditions : VIN1 ≥ (VIN1 Min) and VIN1 ≥ VO1 + 0.5 V

^*2: The minimum VIN2 has to meet two conditions : VIN2 ≥ (VIN2 Min) and VIN2 ≥ VO2 + Vdrop (VO2 and Vdrop values are specified

in “ Electrical Characteristics”)

^*3: VIN1 ≥ VIN2

^*4: VIN1 startup rise time ≤ 1 ms is recommended

^*5: PFM mode at light load current with VO1/VIN1 ≤ 80% (IO1 ≤ 10 mA)

WARNING:

The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data sheet. Users considering application outside the listed conditions are advised to contact

their representatives beforehand.

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MB39C022G/J/L/N

8. Electrical Characteristics

(Ta = + 25°C, VIN1 = VIN2 = 3.7 V)

Value

Unit

Parameter

Symbol Pin No.

Condition

Min

− 2.5%

− 100

–

Typ

0.3

0

Max

+ 2.5%

+ 100

–

Threshold voltage

Input Bias current

VTH

IFB

6

FB pin

FB = 0 V

V

nA

Ω

SW PMOS-Tr On

resistor

RPON

8,9

ILX = − 100 mA

0.35

CH1

[ Buck

DC/DC ]

SW NMOS-Tr On

resistor

RNON

9,10

ILX = 100 mA

–

0.25

–

Ω

Line regulation

Vline1

Vload1

ILIM1

VO2

–

9

3

VIN1 = 2.5 V to 5.5 V*¹

IO1 = 100 mA to 600 mA

VOUT1 × 0.9

–

10

–

mV

A

Load regulation

Over current protect

0.9

1.2

3.30

1.5

^{IO2 = 0 mA to}− 300 mA

− 2.5%

+ 2.5%

V

MB39C022G

^{IO2 = 0 mA to}− 300 mA

− 2.5%

2.85

1.80

1.20

+ 2.5%

V

MB39C022J

Output voltage

^{IO2 = 0 mA to}− 300 mA

MB39C022L

^{IO2 = 0 mA to}− 300 mA

MB39C022N

Line regulation

Load regulation

Vline2

3

VIN2 = 2.5 V to 5.5 V*²

–

10

25

–

mV

Vload2

^{IO2 = 0 mA to}− 300 mA

IO2 = − 300 mA,

200

Drop out voltage

Vdrop

3

VIN2 = VO2 :

MB39C022G, MB39C022J

MB39C022G*³

MB39C022J*³

MB39C022L*³

MB39C022N*³

f = 1 kHz

f = 10 kHz

f = 1 kHz

f = 10 kHz

f = 1 kHz

f = 10 kHz

f = 1 kHz

f = 10 kHz

–

70*⁴

65*⁴

60*⁴

55*⁴

–

dB

CH2

[ LDO ]

dB

Power supply

rejection ratio

dB

PSRR

3

dB

Output noise

voltage

Vnoise

ILIM2

3

f = 10 Hz to 100 kHz,

EN1 = 0 V

μVrms

Over current

protect

VO2 × 0.9

500

150

700

350

980

700

mA

Short circuit

protect

ISCP2

VO2 = 0 V

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MB39C022G/J/L/N

(Ta = + 25°C, VIN1 = VIN2 = 3.7 V)

Value

Unit

Parameter

Hold time

Symbol

Pin No.

Condition

Min

52.8

–

Typ

66

–

Max

79.2

0.1

Thold

VPOR

IPOR

VTHL

4

fosc = 2 MHz

POR = 250 μA

POR = 5.5 V

VIN1

ms

V

Power On Reset

[ POR ]

Output voltage

Output current

Threshold voltage

4

–

1

μA

V

Under Voltage

Lockout

2, 8

1.95

2.10

2.25

Protection

Circuit Block

[ UVLO ]

Hysteresis width

VH

2, 8

–

0.20

–

V

Over

Stop temperature

Hysteresis width

TOTPH

–

+ 135

+ 25

–

°C

Temperature

Protection Block

[ OTP ]

TOTPHYS

Oscillator Block Output

fosc

9

–

1.6

2.0

2.4

MHz

[ OSC ]

frequency

Control Block

[CTL ]

Input voltage

VIH

VIL

1, 7

8

EN1, EN2 ON

EN1, EN2 OFF

EN1, EN2 = 0 V

1.5

–

0

–

0.4

+ 100

1

V

–

V

Input current

IEN

− 100

–

nA

μA

Shut down

power supply

current

ICC1

2

–

1

Standby power

supply current

(DC/DC)

ICC2

8

2

EN1 = VIN1, EN2 = 0 V

IO1 = 0 mA, VFB = VIN1

–

30

0

60

1

μA

General

Standby power

supply current

(LDO)

ICC3

8

2

EN1 = 0 V, EN2 = VIN1

IO2 = 0 mA

–

10

60

18

μA

120

Power-on

invalid

current

ICC4

8

2

EN1, EN2 = VIN1,

VFB = 0.2 V

–

0.9

60

1.5

mA

120

μA

^*1: The minimum VIN1 has to meet two conditions : VIN1 ≥ (VIN1 Min) and VIN1 ≥ VO1 + 0.5 V

^*2: The minimum VIN2 has to meet two conditions : VIN2 ≥ (VIN2 Min) and VIN2 ≥ VO2 + Vdrop (VO2 and Vdrop

values are specified in “ Electrical Characteristics”)

^*3: VIN2 = VO2 + 1 V, (MB39C022N: VIN2 = 2.5 V), IO2 = 100 mA

^*4: This value is not be specified. This should be used as a reference to support designing the circuits.

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MB39C022G/J/L/N

9. Test Circuit For Measuring Typical Operating Characteristics

EN2

GND1

LX

C2

VIN2

VO1

C4

C5

L1

VO2

VOUT2

POR

VIN1

EN1

FB

VIN

C1

POR

EN1

R3

R5

R6

C3

GND2

Component

Item

Specification

10 μF

Remarks

C1

C2

C3

C4

C5

Ceramic capacitor

4.7 μF

22 pF

4.7 μF

1 μF

for MB39C022J, MB39C022L

for MB39C022G, MB39C022N

4.7 μF

2.2 μH

1 MΩ

L1

R3

R5

R6

Inductor

Resistor

600 kΩ

200 kΩ

at VO1 = 1.2 V*

* : The output voltage of VO1 can be adjusted by the external resistor divider R5.

(R5 + R6)

R6

(600 kΩ + 200 kΩ)

200 kΩ

V_O1= V_ref

×

= 0.3 V ×

= 1.2 V

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MB39C022G/J/L/N

10. Application Notes

10.1 Selection of Components

Selection of an External Inductor for DC/DC

This IC is designed to operate well with a 2.2 μH inductor. Choosing larger values would lead to larger overshoot/undershoot during

load transient. Choosing a smaller value would lead to larger ripple voltage.

The inductor should be rated for a saturation current higher than the LX peak current value during normal operating conditions, and

should have a minimal DC resistance. (100 mΩ or less is recommended to improve efficiency.)

LX peak current value I_PKis obtained by the following formula.

V_IN- V_OUT

L

D

1

2

(V_IN- V_OUT) × V_OUT

2 × L × fosc × V_IN

I_PK= I_OUT

+

×

= I_OUT+

fosc

L

: External inductor value

I_OUT: Load current (DC)

V_IN: Power supply voltage

V_OUT: Output setting voltage

D

: ON- duty to be switched ( = V_OUT/V_IN)

fosc : Switching frequency (2.0 MHz)

ex) At V_IN= 3.7 V, V_OUT= 1.2 V, I_OUT= 0.6 A, L = 2.2 μH, fosc = 2.0 MHz

The maximum peak current value I_PK

;

^(V_IN− V_OUT) × V_OUT

2 × L × fosc × V_IN

^{(3.7 V}− 1.2 V) × 1.2 V

2 × 2.2 μH × 2 MHz × 3.7 V

I_PK= I_OUT

+

= 0.6 A +

= 0.69 A

I/O Capacitor Selection

• DC/DC's output capacitor's finite equivalent series resistance (ESR) causes ripple voltages on output equal to the amount of

current variation multiplied by the ESR value. The output capacitor value also has a significant impact on the operating stability

of the device when used as a DC/DC converter. Therefore, Cypress generally recommends C2 = 4.7 μF as DC/DC output

capacitor, or a larger capacitor value can be used if ripple voltages are not suitable.

• For DC/DC, select a low ESR for the VIN1/VIN2 input capacitor to suppress dissipation from ripple currents. In addition, to

reduce startup overshoot for DC/DC and LDO, it is recommended that larger ceramic capacitor be used for input capacitors C1

and C4. Recommended values are C1 = 10 μF, C4 = 4.7 μF.

• Types of capacitors

Ceramic capacitors are effective for reducing the ESR and afford smaller DC/DC converter circuit. However, power supply

^{functions as a heat generator, therefore avoid using capacitor with the F-temperature rating (}− 80% to + 20%). Cypress

recommends capacitors with the B-temperature rating ( 10% to 20%).

Normal electrolytic capacitors are not recommended due to their high ESR.

Tantalum capacitor will reduce ESR, however, it is dangerous to use because it turns into short mode when damaged. If you

insist on using a tantalum capacitor, Cypress recommends the type with an internal fuse.

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MB39C022G/J/L/N

10.2 DC/DC Output Voltage Setting

The output voltage V_O1of this IC is defined by the external resistive divider R5 & R6. Note that C3 is a capacitor used for improving

stability. Use a 22 pF cap for C3 should be suitable in all cases.

R5 + R6

600 kΩ + 200 kΩ

200 kΩ

V_O1= V_ref

×

= 0.3 V ×

= 1.2 V

R6

VO1

MB39C022

C3

R5

6

FB

Vref

(0.3 V)

-

R6

+

10.3 Power on Reset (POR)

R3 and R4 are the pull-up resistors for POR (Pin 4). A 1 MΩ resistor is required to placed at either R3 or R4. When R3 has a 1 MΩ

resistor and R4 is open; the POR will be connected VIN. When R4 has a 1 MΩ resistor and R3 is open; the POR pin will be connected

to VO1.

By default, only R3 require a 1 MΩ resistor while R4 is open.

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MB39C022G/J/L/N

10.4 Power Dissipation and Heat Considerations

The DC/DC is so efficient that no consideration is required in most cases. The LDO, on the other hand, would be the dominant heat

generator due to its inherent efficiency loss. Thus, if the IC is used at a high power supply voltage, heavy load, and low LDO output

voltage, or high temperature, it requires further consideration.

The internal loss (Pc) is roughly obtained from the following formula :

2

P_C= P_C1+ P_C2= I_O1× (RDC + D × R_ONP+ (1 - D) × R_ONN) + I_O2× V_drop

P_C1

P_C2

RDC

D

: DC/DC continuity loss

: LDO continuity loss

: External inductor series resistance ( < 100 mΩ recommended)

: Switching ON-duty cycle ( = V_OUT/ V_IN)

: Internal P-ch SW FET ON resistance

: Internal N-ch SW FET ON resistance

: DC/DC Load current

R_ONP

R_ONN

I_O1

I_O2

: LDO Load current

V_drop

: LDO Dropout voltage

The loss expressed by the above formula is continuity loss. The internal loss includes the switching loss and the control circuit loss

as well but they are so small compared to the continuity loss they can be ignored.

For P_C1, consider the scenario with high temperature and heavy load (VIN = 3.7 V, V_O1= 1.2 V, I_O1= 0.6 A, Ta = + 70°C). Here,

R_{ONP ≈}0.4 Ω and R_{ONN ≈}0.3 Ω according to the graph “MOS FET ON resistance vs. Operating ambient temperature”.

P_C1= 156 mW.

For P_C2, consider the scenario with low output voltage (MB39C022N), high temperature and heavy load (VIN = 3.7 V,

V

_O2= 1.2 V, I_O2= 0.3 A, Ta = + 70°C). Here, P_C2= 0.75 W. Note that P_C2>> P_C1

.

According to the graph “Power dissipation vs. Operating ambient temperature”, the maximum permissible power dissipation at an

^{operating ambient temperature Ta of}+ 70°C is 1.4 W. The internal loss is lower than the maximum permissible power dissipation.

Document Number: 002-08460 Rev. *C

Page 16 of 29

MB39C022G/J/L/N

10.5 Board Layout, Design Example

Some basic design guidelines should be used when physically placing the MB39C022 on a Printed Circuit Board (PCB).

• Regarding to GND pattern of PCB layout of MB39C022, It needs to separate like AGND (analog ground) and PGND (power

ground). By separating grounds, it is possible to minimize the switching frequency noise on the LDO output.

• Arrange the input capacitor C1 and C4 as close as possible between VIN1 & PGND pins and VIN2 &AGND pins. Make a through

hole near the pins of this capacitor if the board has planes for power and GND.

• Large AC currents flow between this IC and the input capacitor (C1), output capacitor (C2), and external inductor (L1). Group

these components as close as possible to this IC to reduce the overall loop area occupied by this group. Also try to mount these

components on the same surface and arrange wiring without through hole wiring. Use thick, short, and straight routes to wire

the net (The layout by planes is recommended.).

• The C1 and C2 capacitor returns are connected closely together at the PGND plane.

• The LDO input capacitor (C4) and LDO output capacitor (C5) are returned to the AGND plane.

• The analog ground plane and power ground plane are connected at one point.

• All other signals (EN1, EN2, FB) should be referenced to AGND and have the AGND plane underneath them.

• The feedback wiring to the V_O1and the V_O1pin should be wired closest to the output capacitor (C2). The resistive divider and

FB pin is extremely sensitive and should thus be kept wired away from the LX pin of this IC as far as possible.

• Try to make a GND plane on the surface to which this IC will be mounted. For efficient heat dissipation when using the SON-10

package, Cypress recommends providing a thermal via in the footprint of the thermal pad.

Layout Example of IC Components

PGND

Plane

VO1

L1

PGND

C2

AGND Plane

VVIINN22

PGND

C4

AGND

CC11

C5

VIN1

VVOO22

RR66

R5

Document Number: 002-08460 Rev. *C

Page 17 of 29

MB39C022G/J/L/N

11. Example of Standard Operation Characteristics

(Shown below is an example of characteristics for connection according to “ Test Circuit For Measuring Typical Operating

Characteristics”.)

11.1 DC/DC Conversion Efficiency

CH1 Test Condition :

EN1 = VIN; EN2 = 0 V

VO1 = 1.2 V; C1 = 10 μF; C2 = 4.7 μF

100

90

80

70

60

50

40

30

20

10

0

VIN = 3.7 V

VIN = 4.3 V

VIN = 5.5 V

0.001

0.01

0.1

1

Load Current IO1 (A)

11.2 DC/DC Load Regulation

CH1 Test Condition :

EN1 = VIN; EN2 = 0 V

VO1 = 1.2 V; C1 = 10 μF; C2 = 4.7 μF

1.3

1.28

VIN = 3.7 V

VIN = 4.3 V

VIN = 5.5 V

1.26

1.24

1.22

1.2

1.18

1.16

1.14

1.12

1.1

0

0.2

0.4

0.6

Load Current IO1 (A)

Document Number: 002-08460 Rev. *C

Page 18 of 29

MB39C022G/J/L/N

11.3 DC/DC Line Regulation

CH1 Test Condition :

EN1 = VIN; EN2 = 0 V

VO1 = 1.2 V; C1 = 10 μF; C2 = 4.7 μF

1.3

1.28

1.26

1.24

1.22

1.2

IO1 = 0 mA

IO1 = 300 mA

IO1 = 600 mA

1.18

1.16

1.14

1.12

1.1

3.2

3.7

4.2

4.7

5.2

Input Voltage VIN (V)

11.4 DC/DC Switching Waveform

CH1 Test Condition :

EN1 = EN2 = VIN = 3.7 V;

VO1 = 1.8 V; IO1 = 250 mA; C1 = 10 μF; C2 = 4.7 μF

VO2 = 3.3 V; IO2 = 150 mA; C4 = C5 = 4.7 μF

VLx

5 V/div

ILx

100 mA/div

VO1

20 mV/div

VO2

20 mV/div

500 ns/div

Document Number: 002-08460 Rev. *C

Page 19 of 29

MB39C022G/J/L/N

11.5 LDO Load Regulation

MB39C022G CH2 Test Condition :

EN2 = VIN; EN1 = 0 V

VO2 = 3.3 V; C4 = C5 = 4.7 μF

3.4

VIN = 3.7 V

3.38

VIN = 4.3 V

3.36

VIN = 5.5 V

3.34

3.32

3.3

3.28

3.26

3.24

3.22

3.2

0.25

0

0.05

0.1

0.15

0.2

0.3

Load Current IO2 (A)

11.6 LDO Line Regulation

MB39C022G CH2 Test Condition :

EN2 = VIN; EN1 = 0 V

VO2 = 3.3 V; C4 = C5 = 4.7 μF

3.4

3.38

IO2 = 0 mA

3.36

3.34

3.32

3.3

IO2 = 120 mA

IO2 = 300 mA

3.28

3.26

3.24

3.22

3.2

3.6

4.1

4.6

5.1

Input Voltage VIN (V)

Document Number: 002-08460 Rev. *C

Page 20 of 29

MB39C022G/J/L/N

11.7 LDO Power Supply Rejection Ratio

MB39C022G CH2 Test Condition :

EN2 = VIN = 3.7 V; EN1 = 0 V

VO2 = 3.3 V; IO2 = 100 mA; C1 = C4 = 0 μF

0

10

20

30

40

50

60

70

80

90

−

VIN = 3.7 V

VIN = 4.3 V

10

100

1000

10000

100000

1000000

Frequency (Hz)

11.8 DC/DC Load Transient Waveforms

Test Condition :

VIN = EN1 = EN2 = 3.7 V; VO1 = 1.2 V; C1 = 10 μF; C2 = 4.7 μF; VO2 = 3.3 V; C4 = C5 = 4.7 μF

T

IO1 = 10 mA to 400 mA

IO1

500 mA/div

VO1

100 mV/div

VO2

IO2 = 150 mA

20 mV/div

100 μs/div

CH1 Load Transient Waveforms

Document Number: 002-08460 Rev. *C

Page 21 of 29

MB39C022G/J/L/N

11.9 DC/DC Power MOS FET ON Resistance

P-ch MOS FET ON Resistance vs.

Operating Ambient Temperature

MOS FET ON Resistance vs. Input Voltage

0.6

0.5

0.6

0.5

0.4

0.3

0.2

0.1

0.0

P-ch

VIN = 3.7 V

0.4

0.3

0.2

N-ch

VIN = 5.5 V

0.1

0.0

2.0

3.0

4.0

5.0

6.0

-50

0

50

100

Input voltage V_IN(V)

Operating Ambient Temperature Ta (°C)

N-ch MOS FET ON Resistance vs.

Operating Ambient Temperature

0.6

0.5

0.4

0.3

0.2

0.1

0.0

VIN = 3.7 V

VIN = 5.5 V

-50

0

50

100

Operating Ambient Temperature Ta (°C)

Document Number: 002-08460 Rev. *C

Page 22 of 29

MB39C022G/J/L/N

Permissible Power Dissipation vs. Operating Ambient Temperature

3000

2630

2500

2000

1500

1000

500

0

-40

-20

0

20

40

60

80

100

Operating Ambient Temperature Ta (°C)

Document Number: 002-08460 Rev. *C

Page 23 of 29

MB39C022G/J/L/N

12. Application Circuits Examples

Example 1 (VIN1 = VIN2)

VIN1 and VIN2 are connected together and POR is pulled up to VIN

(MB39C022)

EN2

GND1

LX

C2

VO1

VIN2

IO1 ≤ 600 mA

C4

C5

L1

VO2

IO2 ≤ 300 mA

VOUT2

POR

VIN1

EN1

FB

VIN

C1

POR

EN1

R3

R6

R5

C3

GND2

Example 2 (VIN2 = VO1)

• VIN2 is connected to VO1 and POR is pulled up to VIN

• It is possible to maximize LDO efficiency by connecting DC/DC Output to LDO supply.

• Maximum DC/DC output current ( = IO1) is limited by VIN2 input current (≈ IO2)

(MB39C022)

EN2

GND1

LX

C2

VO1

VIN2

IO1 ≤ 600 mA - IO2

C4

C5

L1

VO2

VOUT2

POR

VIN1

EN1

FB

IO2 ≤ 300 mA

VIN

C1

POR

EN1

R3

R6

C3

GND2

R5

Document Number: 002-08460 Rev. *C

Page 24 of 29

MB39C022G/J/L/N

Example 3 (POR and RC Delay Channel Control)

• EN1 is controlled by RC delay and EN2 is controlled by POR output.

• It is possible to control each channel without signal from MCU

R3

(MB39C022)

EN2

GND1

LX

C2

VO1

VIN2

IO1 ≤ 600 mA

C4

C5

L1

VO2

IO2 ≤ 300 mA

VOUT2

POR

VIN1

EN1

FB

VIN

C1

100 kΩ

POR

1 μF

R5

R6

C3

GND2

Timing chart

VIN

VUVLO

Vth(POR)

VO1

(1.2 V)

VO2

tc

td

(1.8 V)

ta

tb

Start up control

t_a: RC delay time (28 ms at VIN = 3.7 V, R = 100 kΩ, C = 1 μF)

t_b: POR hold time (66 ms fixed)

Power down control

t_c, t_d: depend on internal discharge path and output loading

Document Number: 002-08460 Rev. *C

Page 25 of 29

MB39C022G/J/L/N

13. Usage Precautions

1. Never Use Setting Exceeding Maximum Rated Conditions.

Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of

absolute maximum ratings. Do not exceed these ratings.

2. Use the Devices Within Recommended Conditions

It is recommended that devices be operated within recommended conditions.

Exceeding the recommended operating condition may adversely affect devices reliability.

Nominal electrical characteristics are warranted within the range of recommended operating conditions otherwise specified on each

parameter in the section of electrical characteristics.

3. Design the Ground Line on Printed Circuit Boards With Consideration of Common Impedance.

4. Take Appropriate Measures Against Static Electricity.

The LX pin has less built-in ESD protection than other pins.

LX pin : 150 V (MM), 1500 V (HBM), Other pins : 200 V (MM), 2000 V (HBM)

Containers for semiconductor materials should have anti-static protection or be made of conductive material.

After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.

Work platforms, tools, and instruments should be properly grounded.

Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground.

5. Do not Apply Negative Voltages

^{The use of negative voltages below}− 0.3 V may activate parasitic transistors on the device, which can cause abnormal operation.

14. Ordering Information

Part Number

MB39C022GPN

MB39C022JPN

MB39C022LPN

MB39C022NPN

Package

Remarks

10-pin plastic SON

(WNK010)

–

15. RoHS Compliance Information

The LSI products of Cypress with “E1” are compliant with RoHS Directive, and has observed the standard of lead, cadmium, mercury,

chromium, polybrominated biphenyls (PBB), and polybrominated diphenylethers (PBDE).

A product whose part number has trailing characters “E1” is RoHS compliant.

Document Number: 002-08460 Rev. *C

Page 26 of 29

MB39C022G/J/L/N

16. Package Dimension

Package Code: WNK010

D

0.10

C

A

B

A

D2

6

10

0.10

2X

C

0.10

C A B

E2

E

9

5

1

INDEX MARK

8

⁴b

L

B

0.10

0.05

C A B

C

TOP VIEW

e

0.10

2X

C

5

(ND-1)×

e

BOTTOM VIEW

0.10

C

A

SEATING PLANE

0.05

C

9

C

A1

SIDE VIEW

NOTE

1. ALL DIMENSIONS ARE IN MILLIMETERS.

MILLIMETER

SYMBOL

A

2. DIMENSIONING AND TOLERANCINC CONFORMS TO ASME Y14.5-1994.

3. N IS THE TOTAL NUMBER OF TERMINALS.

MIN. NOM. MAX.

0.75

4. DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED

BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP.IF THE TERMINAL HAS

THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL. THE

DIMENSION "b"SHOULD NOT BE MEASURED IN THAT RADIUS AREA.

A

D

E

0.00

0.05

1

3.00 BSC

0.25

5. ND REFER TO THE NUMBER OF TERMINALS ON D OR E SIDE.

6. MAX. PACKAGE WARPAGE IS 0.05mm.

0.22

0.28

b

D

2.40 BSC

1.70 BSC

0.50 BSC

0.30 REF

0.40

2

7. MAXIMUM ALLOWABLE BURRS IS 0.076mm IN ALL DIRECTIONS.

8. PIN #1 ID ON TOP WILL BE LOCATED WITHIN INDICATED ZONE.

E

e

c

9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT

SINK SLUG AS WELL AS THE TERMINALS.

10. JEDEC SPECIFICATION NO. REF : N/A

L

0.30

0.50

002-15676 Rev. **

Document Number: 002-08460 Rev. *C

Page 27 of 29

MB39C022G/J/L/N

Document History

Document Title: MB39C022G/J/L/N Buck DC/DC Converter + Low Noise LDO

Document Number: 002-08460

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

**

–

TAOA

04/13/2009 Initial release

*A

5150068

02/24/2016 Migrated Spansion Datasheet from DS04-27271-2E to Cypress format

Updated Pin Assignment:

Change the package name from LCC-10P-M04 to WNK010

*B

*C

5640458

5777611

HIXT

02/23/2017

06/19/2017

Updated Ordering Information:

Change the package name from LCC-10P-M04 to WNK010

Updated Package Dimension: Updated to Cypress format

MASG

Adapted Cypress new logo.

Document Number: 002-08460 Rev. *C

Page 28 of 29

MB39C022G/J/L/N

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

Products

PSoC^®Solutions

ARM^®Cortex^®Microcontrollers

cypress.com/arm

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cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

| Components

Internet of Things

Memory

Technical Support

cypress.com/memory

cypress.com/mcu

cypress.com/support

Microcontrollers

PSoC

cypress.com/psoc

cypress.com/pmic

cypress.com/touch

cypress.com/usb

Power Management ICs

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/wireless

including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the

device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably

expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,

damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other

liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners..

Document Number: 002-08460 Rev. *C

Revised June 19, 2017

Page 29 of 29


型号：	MB39C022JPN
厂家：	CYPRESS
描述：	Buck DC/DC Converter Low Noise LDO
文件：	总29页 (文件大小：809K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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