MB89P945PF_技术文档

FUJITSU MICROELECTRONICS

DATA SHEET

DS07-12536-6E

8-bit Proprietary Microcontroller

CMOS

F²MC-8L MB89940 Series

MB89943/945/P945/PV940

■ DESCRIPTION

The MB89940 series is specially designed for automotive instrumentation applications. It features a combination

of two PWM pulse generators and four high-drive-current outputs for controlling a stepping motor. It also contains

two analog inputs, two PWM pulse generators and 10-digit LCD controller/driver for various sensor/indicator

devices. The MB89940 series is manufactured with high performance CMOS technologies and packaged in a

48-pin QFP.

■ FEATURES

• 8-bit core CPU: 4 MHz system clock (8 MHz external, 500 ns instruction cycle)

• 21-bit timebase timer

• Watchdog timer

• Clock generator/controller

• 16-bit interval timer

• Two PWM pulse generators with four high-drive-current outputs

• Two-channel 8-bit A/D converter

• Three external interrupt

• Low supply voltage reset

• External voltage monitor interrupt

• Two more PWM pulse generators for controlling indicator devices

• 4-common 17-segment LCD driver/controller

• Package: 48-pin plastic QFP, 48-pin ceramic MQFP

• 5.0 V single power supply (V^PPrequired for MB89P945)

• On-chip voltage regulator for internal 3.0 V power supply (MB89943, MB89945)

For the information for microcontroller supports, see the following web site.

http://edevice.fujitsu.com/micom/en-support/

2008.10

MB89940 Series

■ PRODUCT LINEUP

Part number

MB89943

MB89945

MB89P945

MB89PV940

Item

Classification

ROM size

Mass-produced products

(mask ROM products)

One-time PROM

Piggyback

8 K × 8 bits 16 K × 8 bits

(internal mask ROM) (internal mask ROM)

16 K × 8 bits

(internal ROM)

32 K × 8 bits

(external on piggyback)

RAM size

512 × 8 bits

1 K × 8 bits

CPU functions

The number of instructions: 136

Instruction cycle:

0.5 µs*¹@8 MHz

Interrupt response time:

Multiply instruction time:

Divide instruction time:

4.0 µs*¹@8 MHz

19 instruction cycles

21 instruction cycles

Direct addressing memory-to/from-register data transfer:

7 instruction cycles

Ports

Output:

Input/Output:

5-bit N-ch open-drain

Two 8-bit CMOS schmitt I/Os and 8-bit CMOS I/Os

Timebase timer

21 bits

Interrupt interval: 1 ms, 4.1 ms, 32.8 ms or 524.3 ms

8-bit/16-bit interval

timer

Can be used as two 8-bit timers or one 16-bit timer

Operation clock: 1 µs, 16 µs, 256 µs or external input *¹

Watchdog timer

Reset interval: Approx. 524 ms to 1049 ms

Stepping motor

controller

Two 8-bit PWM pulse generators

Synchronized 4-channel high current output

Operation clock: 250 ns, 500 ns, 1 µs or 4 µs*¹

8-bit PWM timers

External interrupt

A/D converter

Two 8-bit PWM timers

3 channels, selective positive edge or negative edge trigger

8-bit resolution, two-channel input

A/D conversion time : (MB89943/945 : 26 µs*¹/8 MHz oscillation,

MB89P945/MB89PV940 : 22 µs*¹/8MHz oscillation)

LCD controller &

driver

4-common and 17-segment outputs

Number of outputs programmable

Low supply voltage

reset

Autonomous reset when low supply voltage

Reset voltage: 3.3 V, 3.6 V, 4.0 V

External voltage

monitor interrupt

Interrupts when voltage at external pin is lower than the reference voltage

Standby modes

Stop mode and sleep mode

3.5 V to 5.5 V

Operating

voltage*²

Process

CMOS

External EPROM

MBM27C256A-20TVM

*1: Execution times and clock cycle times are dependent on the use of MCU.

*2: Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics”.) In the case

of the MB89PV940, the voltage varies with the restrictions of the EPROM for use.

2

DS07-12536-6E

MB89940 Series

■ PACKAGE AND CORRESPONDING PRODUCTS

MB89943

Package

MB89945

MB89PV940

MB89P945

FPT-48P-M16

MQP-48C-P01

×

: Available

×: Not available

Note: For more information about each package, see section “■ Package Dimensions”.

■ DIFFERENCES AMONG PRODUCTS

1. Memory Size

Prior to evaluating/developing the software for the MB89940 series, please check the differences between the

product types.

• RAM/ROM configurations are dependent on the product type.

• If the bottom address of the stack is set to the upper limit of the RAM address, it should be relocated when

changing the product type.

2. Power Dissipation

• For the piggyback product, add the power dissipation of the EPROM on the piggyback.

• The power dissipation differs between the product types.

3. Technology

The mask ROM product is fabricated with a 0.5 µm CMOS technology whereas the other products with 0.8 µm

CMOS technology.

Also the mask ROM product contains the on-chip voltage regulator for the internal 3.0 power supply. For details,

refer.

4. Mask Option

Functions that can be selected as options and how to designate these options vary by the product.

Before using options check section “■ Mask Options”.

• No options are available for the piggyback product.

• The power-on reset and reset output options are always activated with the mask ROM product.

• Pull-up option must not be specified with the pins used as LCD outputs.

DS07-12536-6E

3

MB89940 Series

■ PIN ASSIGNMENT

(Top view)

AV^CC

1

2

3

4

5

6

7

8

36

35

34

33

32

31

30

29

28

27

26

25

DV^CC

RST

P41/COM0

P42/COM1

X0

P30/FUELO

P00/SEG00

P01/SEG01

P02/SEG02

P03/SEG03

P04/SEG04

P05/SEG05

P06/SEG06

P07/SEG07

P10/SEG08

P11/SEG09

X1

V^CC

P43/COM2

P44/COM3

P27/INT2

P26/INT1

P25/INT0

9

10

11

12

(FPT-48P-M16)

(Continued)

4

DS07-12536-6E

MB89940 Series

(Continued)

(Top view)

AV^CC

RST

P41/COM0

P42/COM1

X0

1

2

3

4

5

6

7

8

36

35

34

33

32

31

30

29

28

27

26

25

DV^CC

P30/FUELO

P00/SEG00

P01/SEG01

P02/SEG02

P03/SEG03

P04/SEG04

P05/SEG05

P06/SEG06

P07/SEG07

P10/SEG08

P11/SEG09

69

70

71

72

73

74

75

76

60

59

58

57

56

55

54

53

X1

V^CC

P43/COM2

P44/COM3

P27/INT2

P26/INT1

P25/INT0

9

10

11

12

(MQP-48C-P01)

• Pin assignment on package top (MB89PV940 only)

Pin no.

49

Pin name

A15

A12

A7

Pin no.

57

Pin name

N.C.

A2

Pin no.

65

Pin name

Pin no.

73

Pin name

OE

O4

O5

50

58

66

74

N.C.

A11

A9

51

59

A1

67

O6

75

52

A6

60

A0

68

O7

76

53

A5

61

O1

69

O8

77

A8

54

A4

62

O2

70

CE

A10

N.C.

78

A13

A14

VCC

55

A3

63

O3

71

79

56

N.C.

64

V^SS

72

80

N.C.: Internally connected. Do not use.

DS07-12536-6E

5

MB89940 Series

■ PIN DESCRIPTION

Pin no.

Circuit

type

Pin name

Function

QFP*¹

MQFP*²

5

X0

X1

A

Pin for connecting the crystal resonator.

X0 and X1 can be directly connected to a crystal

oscillator.

When the oscillation clock is provided to X0

externally, X1 should be left open.

6

48

MODE

RST

B

C

The mode input is used for entering the MCU into

the test mode.

In user applications, MODE is connected to V^SS.

2

Applying a reset pulse to this pin forces the MCU to

enter the initial state. RST is active low and drives

low state when an internal reset occurs.

Reset pulses of the duration less than the minimum

pulse width may cause the MCU to enter undefined

states.

34 to 27

P00/SEG00 to

P07/SEG07

H

J

These pins have two functions.

Their functions can be switched between Port 0 and

LCD segment signal outputs by setting the internal

registers of the LCD controller.

26 to 20,

18

26 to 20,

18

P10/SEG08 to

P17/SEG15

These pins have two functions.

Their functions can be switched between Port 1 and

LCD segment signal outputs by setting the internal

registers of the LCD controller.

17

16

15

17

16

15

P20/SEG16

P21/V0

I

This pin can be used as the bit 0 of Port 2 or an LCD

segment signal output by setting the internal register

of the LCD controller.

F

This pin is the bit 1 of Port 2.

This pin can also be used for an external LCD bias

voltage input.

P22/EC/V1

This pin can be used as the bit 2 of Port 2 or the

external clock input for the interval timer.

This pin can also be used for an external LCD bias

voltage input.

14

P23/TO/V2

F

This pin can be used as the bit 3 of Port 2 or the

output for the interval timer.

Its function can be switched by setting the internal

register of the interval timer.

This pin can also be used for an external LCD bias

voltage input.

13

12, 11, 10

35

13

P24/V3

F

E

D

This pin can be used as the bit 4 of Port 2 or an

external LCD bias voltage input.

12, 11, 10 P25/INT0 to

P27/INT2

These pins are used for Port 2.

They can also be used for external interrupt inputs.

35

P30/FUELO

This pin can be used for the bit 0 of Port 3 or the

output from PWM3.

The function of this pin can be switched by setting

the internal register of PWM3.

(Continued)

*1: FPT-48P-M16

*2: MQP-48C-P01

6

DS07-12536-6E

MB89940 Series

(Continued)

Pin no.

Circuit

type

Pin name

Function

QFP*¹

MQFP*²

37

P31/TEMPO

G

This pin can be used for the bit 1 of Port 3 or the

output from PWM4.

The function of this pin can be switched by setting

the internal register of PWM4. This output has a high

drive-current capability.

38,

39

38,

39

P32/PWM1P,

P33/PWM1M

These pins are the pair of high-current driver outputs

for one of two motor coils.

They can be also used for the bits 2 and 3 of Port 3

by setting the internal register of the stepper motor

controller.

40,

41

40,

41

P34/PWM2P,

P35/PWM2M

These pins are the pair of high-current driver outputs

for one of two motor coils.

They can be also used for the bits 4 and 5 of Port 3

by setting the internal register of the stepper motor

controller.

44

45

46

44

45

46

P36/TEMPI

P37/FUELI

P40/PW

M

L

This analog input is connected to channel 1 of the

A/D converter.

It can also be used for the bit 6 of Port 3 when this

A/D input enable register bit is set to ‘0’.

This analog input is connected to channel 0 of the

A/D converter.

It can also be used for the bit 7 of Port 3 when this

A/D input enable register bit is set to ‘0’.

This pin has two functions.

When this pin is used as an open-drain output of

Port 4, the external voltage monitor reset should be

in the power down mode.

When it is used as the PW input of external voltage

monitor reset, the corresponding bit of the port data

register should be set to ‘1’.

3, 4,

8, 9

3, 4,

8, 9

P41/COM0 to

P44/COM3

K

These pins are the LCD common signal outputs.

When LCD is not used, these pins can be also used

for Port 4.

47

VINT

—

An external capacitor should be connected to this

pin for stabilizing the internal 3.0 V power supply.

For MB89PV940 and MB89P945, this pin should be

left open.

7

19

1

7

19

1

V_CC

—

VCC

VSS

AVCC

The power supply pin for the analog circuit

The same voltage should be applied as V^CC.

The power supply pin for the analog circuit

The same voltage should be applied as V^SS.

43

36

43

36

AV^SS

DV^CC

—

The dedicated power supply pin for the high-current

driver output

The same voltage should be applied as V^CC.

42

DV^SS

—

The dedicated power supply pin for the high-current

driver output

The same voltage should be applied as V^SS.

*1: FPT-48P-M16

*2: MQP-48C-P01

DS07-12536-6E

7

MB89940 Series

• External EPROM pins (MB89PV940 only)

Pin no.

Pin name

A15

I/O

Function

49

50

51

52

53

54

55

58

59

60

O

Address output pins

A12

A7

A6

A5

A4

A3

A2

A1

A0

61

62

63

65

66

67

68

69

O1

O2

O3

O4

O5

O6

O7

O8

I

Data input pins

70

CE

O

ROM chip enable pin

Outputs “H” during standby.

71

73

A10

OE

O

Address output pin

ROM output enable pin

Outputs “L” at all times.

75

76

77

78

79

A11

A9

A8

A13

A14

O

Address output pin

80

64

V_CC

V^SS

O

EPROM power supply pin

Power supply (GND) pin

56

57

72

74

N.C.

—

Internally connected pins

Be sure to leave them open.

8

DS07-12536-6E

MB89940 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

A

• Oscillator I/O

X1

With feedback resistor of approx. 1 MΩ.

X0

Standby control signal

B

C

• Schmitt-trigger input

(Pull-down resistance only for MB89943, MB89945)

R

• Open-drain output with pull-up resistor

(Approx. 50 kΩ).

• Schmitt-trigger input

• Hysteresis input

R

P-ch

N-ch

D

• CMOS I/O

P-ch

N-ch

E

• CMOS I/O (Schmitt trigger)

• Pull-up resistor optional

R

P-ch

N-ch

Mask Option

(Continued)

DS07-12536-6E

9

MB89940 Series

Type

Circuit

Remarks

• CMOS I/O (Schmitt trigger)

F

R

• External bias input

P-ch

• Pull-up resistor optional

Mask Option

N-ch

Standby

control

signal

P-ch

N-ch

G

• CMOS I/O (High output current)

P-ch

N-ch

H

• CMOS I/O

• LCD controller/driver output

P-ch

N-ch

Standby

control

signal

P-ch

N-ch

P-ch

N-ch

I

• CMOS I/O

• LCD controller/driver output

• Pull-up resistor optional

• Hysteresis input

R

P-ch

N-ch

Standby

control

signal

P-ch

N-ch

P-ch

N-ch

(Continued)

10

DS07-12536-6E

MB89940 Series

(Continued)

Type

Circuit

Remarks

J

• CMOS I/O

• LCD controller/driver output

• Pull-up resistor optional

(Except P11/SEG09, P10/SEG08)

R

P-ch

Mask Option

N-ch

Standby

control

signal

P-ch

N-ch

P-ch

N-ch

K

• N-ch open-drain output

• LCD controller/driver output

N-ch

P-ch

N-ch

P-ch

N-ch

L

• N-ch open-drain output

• Analog input

N-ch

M

• CMOS I/O

• Analog input

P-ch

N-ch

Standby

control

signal

DS07-12536-6E

11

MB89940 Series

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins

other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in section “■ Electrical Characteristics” is applied between V^CCand VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also, take care to prevent the analog power supply (AV^CCand AVR) and analog input from exceeding the digital

power supply (V^CC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down

resistor.

The VINT pin of MB89PV940 and MB89P945 is the only exception.

3. Treatment of Power Supply Pins on Microcontrollers with A/D Converter

Connect to be AVCC = VCC and AVSS = VSS even if the A/D converter are not in use.

4. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

5. Power Supply Voltage Fluctuations

Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage

could cause malfunctions, even if it occurs within the rated range. Stabilizingvoltage supplied to the IC is therefore

important. As stabilization guidelines, it is recommended to control power so that V^CCripple fluctuations (P-P

value) will be less than 10% of the standard V^CCvalue at the commercial frequency (50 to 60 Hz) and the transient

fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.

6. Note to Noise in the External Reset Pin (RST)

If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause

malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset

pin (RST).

12

DS07-12536-6E

MB89940 Series

■ PROGRAMMING TO THE EPROM ON THE MB89P945

1. Programming MB89P945

Using the EPROM adapter (provided by Sun Hayato Co., Ltd.) and a standard EPROM programmer, user-defined

data can be written into the OTPROM andoption PROM. The EPROM programmer should be set to MB27C256A-

20TVM and electro-signature mode should not be used. When programming the data, the internal addresses

are mapped as follows.

2. Memory Space

Address

0000H

Single chip

EPROM mode

(Corresponding addresses on the EPROM programmer)

8000H

C000H

0000H

Option PROM

3FF0H

4000H

One Time PROM

16 KB

One Time PROM

16 KB

7FFFH

FFFF^H

3. Screening MB89P945

It is recommended that high-temperature aging is performed on the MB89P945 prior to the assembly.

Program, verify

Aging

+150 °C, 48 h

Data verification

Assembly

DS07-12536-6E

13

MB89940 Series

4. Setting PROM Options

For MB89P945, mask options are described in the internal option PROM area. The table below shows the bit

map of the option PROM. The option data can be written by a standard EPROM programmer.

• PROM option bit map

PROM

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

3FF0^HUnused

Unused

Reserved Reset

output

Power-on

reset

1: Active

Oscillation stabilization

time

11: 2¹⁸TOSC 10: 2¹⁷TOSC

01: 2¹⁴TOSC

1: Active

0: Inactive 0: Inactive

3FF1^HP17

Pull-up

P16

Pull-up

P15

Pull-up

P14

Pull-up

P13

Pull-up

P12

Pull-up

Unused

1: Inactive 1: Inactive 1: Inactive 1: Inactive 1: Inactive 1: Inactive

0: Active

3FF2^HP27

P26

Pull-up

P25

Pull-up

P24

Pull-up

P23

Pull-up

P22

Pull-up

P21

Pull-up

P20

Pull-up

1: Inactive 1: Inactive 1: Inactive 1: Inactive 1: Inactive 1: Inactive 1: Inactive 1: Inactive

0: Active

3FF3^HUnused

Unused

Low volt.

PDX bit

Low volt.

S1 bit

Low volt.

S0 bit

Low volt.

LVE bit

Low volt.

1: Register

active

0: Option

active

3FF4^HUnused

3FF5^HUnused

3FF6^HUnused

Unused

Notes: • Default values are all ‘1’.

• T^OSC: One oscillation clock cycle time

• When the bit0 of “3FF3^H” is “0”, it activates the option setting for the Low Voltage Reset Control register.

• When this option is activated, software setting in the register has no effect.

5. Programming Yield

All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.

For this reason, a programming yield of 100% cannot be assured at all times.

14

DS07-12536-6E

MB89940 Series

■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE

1. EPROM for Use

MBM27C256A-20TVM

2. Memory Space

The memory space of the piggyback EPROM is mapped onto the internal memory space as shown in the figure

below.

Address

0000H

Single chip

Corresponding addresses on the EPROM programmer

8000H

0000H

Piggy Back

EPROM

32 KB

7FFFH

FFFF^H

For EPROM devices suitable for MB89PV940, please contact sales representatives.

3. Programming to the EPROM

(1) Set the EPROM programmer to the MBM27C256A-20TVM.

(2) Load program data into the EPROM programmer at 0000^Hto 7FFFH.

(3) Program to 0000^Hto 7FFFH with the EPROM programmer.

DS07-12536-6E

15

MB89940 Series

■ BLOCK DIAGRAM

X0

X1

Interrupt

controller

Oscillator

Clock controller

Timebase timer

Reset circuit

Low supply

voltage reset

RST

Port 4

4

P41/COM0 to

P44/COM3

External voltage

monitor interrupt

Port 0, 1 and 4

P40/PW

8

P10/SEG08 to

P17/SEG15

P00/SEG00 to

P07/SEG07

P37/FUELI

P36/TEMPI

LCD

controller driver

8-bit A/D

converter

P20/SEG16

P21/V0

DV^CC

DVSS

High-drive-current

P22/EC/V1

P23/TO/V2

P24/V3

Stepper motor

macro

P32/PWM1P

Interval timer

P33/PWM1M

P34/PWM2P

P35/PWM2M

PWM1

PWM2

3

P25/INT0 to

P27/INT2

MODE

Port 2

RAM

P30/FUELO

High-drive-current

P31/TEMPO

PWM3

PWM4

F²MC-8L

core CPU

ROM

Port 3

Other pins

V^CC,VSS

AVCC, AVSS

VINT

16

DS07-12536-6E

MB89940 Series

■ CPU CORE

1. Memory Space

The MB89940 Series has a memory space of 64 Kbytes. All peripheral registers, RAM and ROM areas are

mapped onto the 0000^Hto FFFFH range. The peripheral registers address below 007FH and the RAM addresses

the range 0080^Hto 027FH (0080H to 047FH for MB89PV940). A part of this RAM area is also assigned as the

general-purpose registers. The ROM addresses above E000^Hfor MB89943, or C000H for MB89945. The One-

Time PROM addresses the range above C000^H. The external ROM for the piggy sample addresses the range

above 8000^H. The reset vector, interrupt vectors and vectors for vector-call instructions are stored in the highest

addresses of the memory space.

Memory Space

MB89943

MB89945/P945

MB89PV940

0000H

Peripheral

registers

Peripheral

registers

Peripheral

registers

007FH

0100H

007FH

0100H

007FH

0100H

General-

purpose

registers

RAM

purpose

registers

RAM

purpose

registers

RAM

0200H

027FH

0200H

027FH

0200H

512 B

1 KB

047FH

8000^H

C000^H

External

ROM

E000^H

FFFF^H

MB89945 : ROM

MB89P945 :

OTPROM

ROM

8 KB

32 KB

16 KB

FFFF^H

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17

MB89940 Series

2. Registers

The F²MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers

in the memory. The following dedicated registers are provided:

Program counter (PC):

Accumulator (A):

A 16-bit register for indicating instruction storage positions

A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator

Whentheinstructionisan8-bitdataprocessinginstruction, thelowerbyteisused.

Index register (IX):

Extra pointer (EP):

Stack pointer (SP):

Program status (PS):

A 16-bit register for index modification

A 16-bit pointer for indicating a memory address

A 16-bit register for indicating a stack area

A 16-bit register for storing a register pointer, a condition code

16 bits

Initial value

FFFD^H

PC

A

: Program counter

: Accumulator

Indeterminate

T

: Temporary accumulator Indeterminate

IX

: Index register

: Extra pointer

: Stack pointer

: Program status

Indeterminate

EP

SP

PS

I-flag = 0, IL1, 0 = 11

The other bit values are indeterminate.

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR). (See the diagram below.)

Structure of the Program Status Register

15

14

13

12

11

10

9

8

7

6

I

5

4

3

2

Z

1

0

PS

RP

Vacancy Vacancy Vacancy

H

IL1, 0

N

V

C

RP

CCR

18

DS07-12536-6E

MB89940 Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

Rule for Conversion of Actual Addresses of the General-purpose Register Area

Lower OP codes

RP

“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0

↓

Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and

bits for control of CPU operations at the time of an interrupt.

H-flag:Set to ‘1’ when a carry or a borrow from bit3 to bit4 occurs as a result of an arithmetic operation. Cleared

otherwise. This flag is for decimal adjustment instructions.

I-flag:Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared

to ‘0’ at the reset.

IL1, 0:Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

IL1

0

IL0

0

Interrupt level

High-low

High

1

0

1

0

2

3

1

Low

N-flag:Set to ‘1’ if the MSB becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ otherwise.

Z-flag:Set to ‘1’ when an arithmetic operation results in 0. Cleared to ‘0’ otherwise.

V-flag:Set to ‘1’ if the complement on ‘2’ overflows as a result of an arithmetic operation. Cleared to ‘0’ if the

overflow does not occur.

C-flag:Set to ‘1’ when a carry or a borrow from bit7 occurs as a result of an arithmetic operation. Cleared to

‘0’ otherwise. Set to ‘1’ to the shift-out value in the case of a shift instruction.

DS07-12536-6E

19

MB89940 Series

The following general-purpose registers are provided:

General-purpose registers: An 8-bit register for storing data

The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains

eight registers and up to a total of 32 banks can be used on the MB89940 series. The bank currently in use is

indicated by the register bank pointer (RP).

Register Bank Configuration

This address = 0100H + 8 × (RP)

R 0

R 1

R 2

R 3

R 4

R 5

R 6

R 7

32 banks

Memory area

20

DS07-12536-6E

MB89940 Series

■ I/O MAP

Address

00^H

Read/write

(R/W)

(W)

Register name

PDR0

Register description

Port 0 data register

01^H

PDD0

Port 0 data direction register

Port 1 data register

02^H

(R/W)

(W)

PDR1

03^H

PDD1

Port 1 data direction register

Vacancy

04^Hto 06H

07^H

(R/W)

(W)

SCC

SMC

System clock control register

Standby mode control register

Watchdog timer control register

Timebase timer control register

Low voltage reset control

Port 2 data register

08^H

09^H

WDTC

TBTC

LVRC

PDR2

PDD2

PDR3

PDD3

PDR4

ADE

0A^H

0B^H

0C^H

0D^H

Port 2 data direction register

Port 3 data register

0E^H

(R/W)

(W)

0F^H

Port 3 data direction register

Port 4 data register

10^H

(R/W)

11^H

Port 3 A/D input enable register

Vacancy

12^Hto 17H

18^H

(R/W)

T2CR

T1CR

T2DR

T1DR

Timer 2 control register

Timer 1 control register

Timer 2 data register

19^H

1A^H

1B^H

Timer 1 data register

1C^Hto 1FH

20^H

Vacancy

(R/W)

(W)

ADC1

ADC2

A/D converter control register 1

A/D converter control register 2

A/D converter data register

PWM control register

PWM1 compare register

Vacancy

21^H

22^H

ADCD

CNTR

COMP1

23^H

24^H

25^H

26^H

(W)

COMP2

SELR1

SELR2

CNTR3

COMP3

CNTR4

PWM2 compare register

PWM1 select register

PWM2 select register

PWM3 control register

PWM3 compare register

PWM4 control register

27^H

(R/W)

(W)

28^H

29^H

2A^H

2B^H

(R/W)

(Continued)

DS07-12536-6E

21

MB89940 Series

(Continued)

Address

2C^H

Read/write

(W)

Register name

COMP4

SELT

Register description

PWM4 compare register

2D^H

(R/W)

Selector test register

2E^H

PFC

Power fail control register

External interrupt control 1 register

External interrupt control 2 register

Vacancy

2F^H

EIR1

30^H

EIR2

31^Hto 5FH

60^Hto 68H

69^Hto 71H

72^H

(R/W)

VRAM

Display data RAM

Vacancy

(R/W)

LCR1

LCR2

LCD controller/driver 1register

LCD controller/driver 2 register

Vacancy

73^H

74^Hto 7BH

7C^H

(W)

ILR1

ILR2

ILR3

Interrupt level setting register 1

Interrupt level setting register 2

Interrupt level setting register 3

Vacancy

7D^H

7E^H

7F^H

22

DS07-12536-6E

MB89940 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(VSS = 0.0 V)

Rating

Symbol

Unit

Remarks

Parameter

Min

Max

V^CC

AV^CC

DVCC

V^I1

VSS – 0.3

VSS + 6.5

VCC + 0.3

DVCC + 0.3

V

Power supply voltage

Should not exceed VCC

Except P31 to P35 and P41 to P44

P31 to P35

V^I2

P41 to P44

MB89PV940/P945

Input voltage

V^I3

V^I4

VSS – 0.3

VSS + 6.5

VCC + 0.3

V

P41 to P44

MB89943/945

V^O1

V^O2

VSS – 0.3

VCC + 0.3

V

Except P31 to P35 and P41 to P44

P31 to P35

DVCC + 0.3

P41 to P44

MB89PV940/P945

Output voltage

V^O3

V^O4

VSS – 0.3

VSS + 6.5

VCC + 0.3

V

P41 to P44

MB89943/945

—

–40

–55

20

50

mA Except P31 to P35

mA P31 to P35

mA Except P31 to P35

mA P31 to P35

mA Except P31 to P35

mA P31 to P35

mA Except P31 to P35

mA P31 to P35

mA Except P31 to P35

mA P31 to P35

mA Except P31 to P35

mA P31 to P35

mA Except P31 to P35

mA P31 to P35

mA Except P31 to P35

mA P31 to P35

mW

“L” level maximum output

current

I^OL

4

“L” level average output

current

I^OLAV

Σ I^OL

Σ I^OLAV

I^OH

40

100

200

40

“L” level total maximum

output current

“L” level total average

output current

100

–20

–50

–4

“H” level maximum output

current

“H” level average output

current

I^OHAV

Σ I^OH

Σ I^OHAV

–40

–50

–200

–20

–100

300

+85

+150

“H” level total maximum

output current

“H” level total average

output current

Power consumption

Operating temperature

Storage temperature

P^D

T^A

°C

Tstg

°C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

DS07-12536-6E

23

MB89940 Series

2. Recommended Operating Conditions

(AVCC = VCC = DVCC = 5.0 V, VSS = AVSS = DVSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min

Typ

Max

V^CC

AVCC

DVCC

Operating supply voltage range

3.5

—

5.5

V

V^CC

RAM data retention supply voltage range AVCC

3.0

—

5.5

V

DVCC

MB89943/MB89945

only*

Smoothing capacitor

C^VINT

T^A

0.1

—

1.0

µF

°C

Operating temperature range

–40

+85

*: Use either a ceramic capacitor or a capacitor with similar frequency characteristics. The bypass capacitor of VCC

pin should be greater than C^VINT.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data sheet. Users considering application outside the listed conditions are advised to contact

their representatives beforehand.

Figure1 VINT Pin Connection Diagram

VINT

CVINT

24

DS07-12536-6E

MB89940 Series

Figure2 Operating voltage - Operating frequency

6

5.5

5

Operation assurance range

4

3.5

3

2

1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0

Oparating frequency (MHz) (At instruction cycle = 4/FCH)

0.5

Minimum execution time (Instruction cycle) (µs)

4.0 2.0

0.8

0.4

DS07-12536-6E

25

MB89940 Series

3. DC Characteristics

(AVCC = VCC = DVCC = 5.0 V, VSS = AVSS = DVSS = 0.0 V)

Value

Symbol

Parameter

Pin name

Condition

Unit Remarks

Min

Typ

Max

P00 to P07, P10 to P17,

P30 to P37, P40 to P47

V^CC+

0.3

V^IH

—

0.7 V^CC

—

V

“H” level input

voltage

RST, MODE, P20 to

P27

V^CC+

0.3

V^IHS

V^IL

0.8 V^CC

—

P00 to P07, P10 to P17,

P30 to P37, P40 to P47

VSS −

0.3

0.3 V^CC

0.2 V^CC

“L” level input

voltage

RST, MODE, P20 to

P27

VSS −

0.3

V^ILS

V^SS−

VCC +

0.3

V^D

—

V

P40

0.3

Open-drain

output

pin application

voltage

V^SS−

0.3

V^SS+

5.5

MB89PV940/

P945

V^D2

V

P41 to P44

V^SS−

0.3

VCC +

0.3

MB89943/

945

VD3

—

V

P10 to P17, P20 to P27,

P30, P36, P37

V^OH

I^OH= –2.0 mA

4.0

—

V

“H” level output

voltage

I^OH= –30,

V^CC= DVCC

VCC −

0.5

V^OH2

P31 to P35

P10 to P17, P20 to P27,

P30, P36, P37, P40 to

P44

V^OL

I^OL= 4.0 mA

—

0.4

0.5

V

“L” level output

voltage

I^OL= 30 mA,

V^SS= DVSS

V^OL2

P31 to P35

MODE, P10 to P17,

P20 to P27, P30 to P37, V^CC,

P40 to P44

0.0 V< V^I<

Without

µA pull-up

option

Input leakage

current

I^IL1

–5

25

50

—

50

+5

V^CC= DVCC

With

kΩ pull-up

option

Pull-up

resistance

RST, P12 to P17,

P20 to P27

R^PULL

—

100

200

LCD internal

bias voltage

resister

V0-V1, V1-V2,

V2-V3

R^LCD

100

kΩ

(Continued)

26

DS07-12536-6E

MB89940 Series

(Continued)

(AVCC = VCC = DVCC = 5.0 V, VSS = AVSS = DVSS = 0.0 V)

Value

Symbol

Parameter

Pin name

Condition

Unit Remarks

Min

Typ

Max

12

20

mA MB89PV940

—

FC = 8 MHz,

t^inst* = 0.5 µs,

I^CC= I(VCC)

+ I(DV^CC)

I^CC

MB89943,

mA MB89945,

MB89P945

12

3

20

7

—

FC = 8 MHz,

t^inst* = 0.5 µs,

I^CCS= I(VCC)

+ I(DV^CC)

Power supply

current

VCC

I^CCS

mA

in Sleep mode

In Stop mode,

T^A= 25°C,

I^CCH= I(VCC)

+ I(DV^CC)

I^CCH

—

5

10

—

µA

Input capacitance C^IN

—

f = 1 MHz

10

pF

*: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics”.

DS07-12536-6E

27

MB89940 Series

”

4. AC Characteristics

(1) Reset Timing

(AVSS = VSS = DVSS, TA = –40°C to +85°C)

Value

Symbol

Condition

Unit

Remarks

Parameter

Min

Max

RST “L” pulse width

tZLZH

—

48 tHCYL

—

ns

tHCYL: One oscillation clock cycle time

tZLZH

RST

0.8 VCC

0.2 VCC

Notes: • If power-on reset option is not activated, the external reset signal must be kept asserted until the oscillation

is stabilized.

• If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause

malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external

reset pin (RST).

(2) Power-on Profile

(AVSS = VSS = DVSS, TA = –40°C to +85°C)

Value

Symbol

Condition

Unit

Remarks

Parameter

Min

Max

MB89PV940,

MB89P945

—

50

ms

Power supply voltage rising time

t^R

—

MB89943,

MB89945

2¹⁹tHCYL

—

1

ns

Power-off minimum period

t^OFF

—

ms

tHCYL: One oscillation clock cycle time

Note: Power supply voltage should reach the minimum operation voltage within the specified default duration of the

oscillation stabilization time.

tOFF

t^R

3.5 V

0.2 V

V

CC

28

DS07-12536-6E

MB89940 Series

(3) Clock Timing

(AVSS = VSS = DVSS, TA = –40°C to +85°C)

Value

Symbol

F^C

Condition

Unit

Remarks

Parameter

Min

1

Max

8

Clock frequency

Clock cycle time

MHz

ns

t^CYC

125

1000

t^WH

tWL

—

Input clock pulse width

20

—

ns

t^CR

tCF

Input clock rising/falling time

10

X0 and X1 Timing and Conditions

t^CYC

tWL

t^CR

tCF

0.8 VCC

X0

0.2 VCC

Clock Conditions

When a crystal

or

ceramic resonator is used

When an external clock is used

X0

X1

X0

X1

Open

(4) Instruction Cycle

Parameter

Symbol

Value (typical)

Unit

Remarks

Instruction cycle

(minimum execution time)

(4/F^C) tinst = 0.5 µs when operating at

F^C= 8 MHz

t^inst

4/FC, 8/FC, 16/FC, 64/FC

µs

Note : When operating at 8 MHz, the cycle varies with the set execution time.

DS07-12536-6E

29

MB89940 Series

(5) Peripheral Input Timing

Parameter

(AVSS = VSS= DVSS, TA = –40°C to +85°C)

Value

Symbol

t^WH

t^WL

Pin name

Unit

Remarks

Min

Max

INT0, INT1,

INT2, EC

Peripheral input “H” pulse width

Peripheral input “L” pulse width

2 t^inst*

—

µs

INT0, INT1,

INT2, EC

2 t^inst*

—

*: For information on tinst, see “(4) Instruction Cycle”.

tWL

0.8 VCC

INT0, INT1,

INT2, EC

0.2 VCC

30

DS07-12536-6E

MB89940 Series

5. A/D Converter Electrical Characteristics

(AVSS = VSS = DVSS, TA = –40°C to +85°C)

Value

Typ

—

Symbol

Parameter

Condition

Unit

Remarks

name

Min

—

Max

8

Resolution

bit

Total error

—

1.5

1.0

LSB

—

Nonlinearity error

—

Differential linearity

error

—

0.9

LSB

V

AVSS – 1.0

LSB

AVSS + 0.5

LSB

AVSS + 2.0

LSB

MB89PV940/

MB89P945

Zero transition

voltage

V^OT

AV^SS– 1.0

LSB

AVSS + 1.0

LSB

AVSS + 2.0

LSB

MB89943/

MB89945

V

—

MB89943/

MB89945/

MB89PV940/

MB89P945

Full-scale transition

voltage

AVCC – 3.0

LSB

AVCC – 1.5

LSB

V^FST

AV^CC

V

Interchannel

disparity

—

0.5

LSB

µs

MB89PV940/

MB89P945

—

44 t^inst*

52 t^inst*

A/D mode

conversion time

MB89943/

MB89945

µs

FC = 8 MHz,

I^A= I(AVCC)

A/D in

I^A

AVCC

—

6

5

8

mA

Power supply

current

operation

F^C= 8 MHz,

I^AH= I(AVCC)

A/D stopped

I^AH

10

µA

Analog input

current

—

I^AIN

—

0

—

10

µA

—

Analog input

voltage range

AV^CC

V

*: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics”.

DS07-12536-6E

31

MB89940 Series

6. A/D Converter Glossary

• Resolution

Analog changes that are identifiable with the A/D converter

When the number of bits is 8, analog voltage can be divided into 2⁸= 256.

• Linearity error (unit: LSB)

The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the

full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics

• Differential linearity error (unit: LSB)

The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value

• Total error (unit: LSB)

The difference between theoretical and actual conversion values

Digital output

Theoretical conversion value

Actual conversion value

1111 1111

1111 1110

•

(1 LSB × N + V^OT)

AV_CC- AV_SS

256

•

1 LSB =

•

V^NTÐ (1 LSB × N + VOT)

•

Linearity error =

•

1 LSB

•

V( N + 1 ) T Ð VNT

•

Ð 1

Differential linearity error =

Total error =

•

1 LSB

Linearity error

•

VNT Ð (1 LSB × N + 1 LSB)

•

1 LSB

•

0000 0010

0000 0001

0000 0000

VOT

VNT

V(N + 1)T

VFST

Analog input

32

DS07-12536-6E

MB89940 Series

7. Notes on Using A/D Converter

• Input impedance of the analog input pins

The A/D converter used for the MB89940 series contains a sample & hold circuit as illustrated below to fetch

analog input voltage into the sample hold capacitor for eight instruction cycles after activating A/D conversion.

For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage

might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output

impedance of the external circuit low (below 10 kΩ).

Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about

0.1 µF for the analog input pin.

Analog Input Equivalent Circuit

Sample & hold circuit

.

C = 33 pF

.

Analog input pin

Comparator

If the analog input

impedance is higher

than 10 kΩ, it is

recommended to

connect an external

capacitor of approx.

0.1 µF.

.

R = 6 kΩ

.

Close for 8 instruction cycles after activating

A/D conversion.

Analog channel selector

• Error

The smaller the | AV^CC– AVSS |, the greater the error would become relatively.

DS07-12536-6E

33

MB89940 Series

8. Low Supply Voltage Reset Electrical Characteristics

Value

Symbol

Unit

Remarks

Parameter

Min

3.0

3.3

3.7

Max

3.6

3.9

4.3

V^DL1

V^DL2

V^DL3

V

When the voltage is

dropping.

Reset voltage

When the voltage is

recovering.

Hysteresis of reset voltage

V^HYS

0.1

—

V

Delay time to reset

t^D

—

2.0

0.1

µs

Supply voltage slew rate

dV/dt

V/µs

9. External Voltage Monitor Interrupt Electrical Characteristics

Value

Symbol

Unit

Remarks

Parameter

Min

1.18

—

Max

1.38

2.0

Reference voltage

V^REF

T^D

V

Delay time to interrupt

Input slew rate

µs

dV/dt

—

0.1

V/µs

34

DS07-12536-6E

MB89940 Series

■ MASK OPTIONS

Part number

MB89943/MB89945

MB89P945

MB89PV940

Specify when

ordering

No.

Set with EPROM

Programmer

Setting not

possible

Specifying procedure

masking

Selectable per pin

(P20 and P12 to

P17 must be set to

without pull-up

resistor when they

are used as LCD

outputs.)

Pull-up resistors

Fixed to without

pull-up resistor

1

P12 to P17,

P20 to P27

Can be set per pin

Power-on reset

Fixed to with

power-on reset

Fixed to with

power-on reset

2

3

4

With power-on reset

Without power-on reset

Setting possible

Main clock oscillation stabilization time

selection (when operating at 8 MHz)

Approx. 2¹⁸/FC (Approx. 32.8 ms)

Approx. 2¹⁷/FC (Approx. 16.4 ms)

Approx. 2¹⁴/FC (Approx. 2.0 ms)

Fixed to

approx. 2¹⁸/FC

(Approx. 32.8 ms)

Selectable

Reset pin output

With reset output

Without reset output

Fixed to with reset

output

Fixed to with reset

output

■ ORDERING INFORMATION

Part number

Package

Remarks

MB89943PF

MB89945PF

MB89P945PF

48-pin Plastic QFP

(FPT-48P-M16)

48-pin Ceramic MQFP

(MQP-48C-P01)

MB89PV940CF

DS07-12536-6E

35

MB89940 Series

■ PACKAGE DIMENSION

48-pin plastic QFP

Lead pitch

0.80 mm

12 × 12 mm

Package width ×

package length

Lead shape

Sealing method

Mounting height

Gullwing

Plastic mold

2.70 mm MAX

P-QFP48-12×12-0.80

Code

(Reference)

(FPT-48P-M16)

48-pin plastic QFP

(FPT-48P-M16)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

17.20±0.40(.677±.016)SQ

12.00±0.10(.472±.004)SQ

*

0.17±0.06

(.007±.002)

36

25

Details of "A" part

2.40 ⁺^–0⁰^.^.²³⁰⁰

37

24

(Mouting height)

.094 ⁺^–.^.⁰⁰⁰¹⁸²

0.15(.006)

0~8

°

INDEX

48

13

1.80±0.30

(.071±.012)

0.25 ⁺^–0⁰^.^.²¹⁰⁰

.010 ⁺^–.^.⁰⁰⁰⁰⁸⁴

(Stand off)

"A"

1

12

0.80(.031)

0.32±0.05

(.013±.002)

M

0.20(.008)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2003-2008 FUJITSU MICROELECTRONICS LIMITED F48026S-c-3-5

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/

(Continued)

36

DS07-12536-6E

MB89940 Series

(Continued)

48-pin ceramic MQFP

Lead pitch

0.8 mm

Straight

Ceramic

Lead shape

Motherboard

material

Mounted package

material

Plastic

(MQP-48C-P01)

48-pin ceramic MQFP

(MQP-48C-P01)

17.20(.677)TYP

15.00±0.25

(.591±.010)

1.50(.059)TYP

1.00(.040)TYP

8.80(.346)REF

PIN No.1 INDEX

14.82±0.35

(.583±.014)

0.80±0.22

(.0315±.0087)

PIN No.1 INDEX

1.02±0.13

(.040±.005)

10.92 ⁺^–0⁰^.^.⁰¹³

8.71(.343)

TYP

7.14(.281)

TYP

.430 ⁺^–0^.005

PAD No.1 INDEX

4.50(.177)TYP

1.10 ⁺^–0⁰^.^.²⁴⁵⁵

0.40±0.08

(.016±.003)

0.60(.024)TYP

0.30(.012)TYP

.043 ⁺^–.^.⁰⁰¹¹⁰⁸

8.50(.335)MAX

0.15±0.05

(.006±.002)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

1994-2008 FUJITSU MICROELECTRONICS LIMITED M48001SC-4-3

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/

DS07-12536-6E

37

MB89940 Series

■ MAIN CHANGES IN THIS EDITION

Page

Section

Change Results

■ PROGRAMMING TO THE EPROM ON

THE MB89P945

13

Deleted the “3. EPROM Programmer Socket Adapter”

■ PROGRAMMING TO THE EPROM WITH

PIGGYBACK/EVALUATION DEVICE

15

Deleted the “2. Programming Socket Adapter”

The vertical lines marked in the left side of the page show the changes.

38

DS07-12536-6E

MB89940 Series

MEMO

DS07-12536-6E

39

MB89940 Series

FUJITSU MICROELECTRONICS LIMITED

Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,

Shinjuku-ku, Tokyo 163-0722, Japan

Tel: +81-3-5322-3347 Fax: +81-3-5322-3387

http://jp.fujitsu.com/fml/en/

For further information please contact:

North and South America

Asia Pacific

FUJITSU MICROELECTRONICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

151 Lorong Chuan,

#05-08 New Tech Park 556741 Singapore

Tel : +65-6281-0770 Fax : +65-6281-0220

http://www.fmal.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.

Rm. 3102, Bund Center, No.222 Yan An Road (E),

Shanghai 200002, China

Tel : +86-21-6146-3688 Fax : +86-21-6335-1605

http://cn.fujitsu.com/fmc/

FUJITSU MICROELECTRONICS EUROPE GmbH

Pittlerstrasse 47, 63225 Langen, Germany

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/microelectronics/

Korea

FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.

10/F., World Commerce Centre, 11 Canton Road,

Tsimshatsui, Kowloon, Hong Kong

Tel : +852-2377-0226 Fax : +852-2376-3269

http://cn.fujitsu.com/fmc/en/

FUJITSU MICROELECTRONICS KOREA LTD.

206 Kosmo Tower Building, 1002 Daechi-Dong,

Gangnam-Gu, Seoul 135-280, Republic of Korea

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://kr.fujitsu.com/fmk/

Specifications are subject to change without notice. For further information please contact each office.

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose

of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS

does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating

the device based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS

or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or

other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured

as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to

the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear

facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon

system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising

in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current

levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of

the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited: Business & Media Promotion Dept.


型号：	MB89P945PF
厂家：	CYPRESS
描述：	Microcontroller, 8-Bit, OTPROM, F2MC-8L CPU, 8MHz, CMOS, PQFP48, 12 X 12 MM, 2.70 MM HEIGHT, 0.80 MM PITCH, PLASTIC, QFP-48 可编程只读存储器时钟微控制器外围集成电路
文件：	总41页 (文件大小：1182K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB89P945PF [CYPRESS]

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