MB90F352ASPMC1 [CYPRESS]
F2MC-16LX 16-bit Microcontroller;型号: | MB90F352ASPMC1 |
厂家: | CYPRESS |
描述: | F2MC-16LX 16-bit Microcontroller 微控制器 |
文件: | 总83页 (文件大小:1275K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MB90350 Series
F2MC-16LX 16-bit Microcontroller
The MB90350-series with 1 channel FULL-CAN interface and Flash ROM is especially designed for automotive and industrial appli-
cations. Its main feature is the on-board CAN interface, which conforms to V2.0 Part A and Part B, while supporting a very flexible
message buffer scheme and so offering more functions than a normal full CAN approach. With the new 0.35μm CMOS technology,
Cypress now offers on-chip Flash-ROM program memory up to 128 Kbytes.
The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates a major advantage in terms
of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction execution time from an external 4 MHz clock. Also,
the clock monitor function can monitor main clock and sub clock independently.
As the peripheral resources, the unit features a 4-channel Output Compare Unit, 6-channel Input Capture Unit, 2 separate 16-bit
freerun timers, 2-channel UART and 15-channel 8/10-bit A/D converter.
Features
Clock
Increased processing speed
■ Built-in PLL clock frequency multiplication circuit
■ 4-byte instruction queue
■ Selection of machine clocks (PLL clocks) is allowed among
frequencydivisionbytwoonoscillationclock,andmultiplication
of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock,
4 MHz to 24 MHz).
Powerful interrupt function
■ Powerful 8-level, 34-condition interrupt feature
■ Up to 8 channels external interrupts are supported.
■ Operation by sub clock (up to 50 kHz : 100 kHz oscillation clock
divided by two) is allowed. (devices without S-suffix only)
Automatic data transfer function independent of CPU
■ Extended intelligent I/O service function (EI2OS) : up to 16
channels
■ Minimum execution time of instruction : 42 ns (when operating
with 4-MHz oscillation clock, and 6-time multiplied PLL clock).
■ DMA: up to 16 channels
■ Built-in clock modulation circuit
Low power consumption (standby) mode
16 Mbytes CPU memory space
■ Sleep mode (a mode that halts CPU operating clock)
■ 24-bit internal addressing
■ Main timer mode (a timebase timer mode switched from the
main clock mode)
Clock monitor function (MB90x356x and MB90x357x
only)
■ PLLtimer mode (a timebase timer mode switched from the PLL
clock mode)
■ Main clock or sub clock is monitored independently.
■ Internal CR oscillation clock (100 kHz typical) can be used as
sub clock.
■ Watch mode (a mode that operates sub clock and watch timer
only)
Instruction system best suited to controller
■ Wide choice of data types (bit, byte, word, and long word)
■ Wide choice of addressing modes (23 types)
■ Stop mode (a mode that stops oscillation clock and sub clock)
■ CPU intermittent operation mode
Process
■ Enhanced multiply-divide instructions with sign and RETI
instructions
■ CMOS technology
I/O port
■ Enhanced high-precision computing with 32-bit accumulator
■ General-purpose input/output port (CMOS output)
❐ 49 ports (devices without S-suffix : devices that correspond
to sub clock)
Instruction system compatible with high-level
language (C language) and multitask
❐ 51 ports (devices with S-suffix : devices that do not corre-
spond to sub clock)
■ Employing system stack pointer
■ Enhanced various pointer indirect instructions
■ Barrel shift instructions
Cypress Semiconductor Corporation
Document Number: 002-07872 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 31, 2017
MB90350 Series
Sub clock pin (X0A, X1A)
8/10-bit A/D converter: 15 channels
■ Yes (using the external oscillation) : devices without S-suffix
■ Resolution is selectable between 8-bit and 10-bit.
■ Activation by external trigger input is allowed.
■ No (using the sub clock mode at internal CR oscillation) :
devices with S-suffix
■ Conversion time: 3 μs (at 24-MHz machine clock, including
sampling time)
Timer
Program patch function
■ Timebase timer, watch timer, watchdog timer: 1 channel
■ 8/16-bit PPG timer: 8-bit × 10 channels or 16-bit × 6 channels
■ 16-bit reload timer: 4 channels
■ Address matching detection for 6 address pointers.
Capable of changing input voltage level for port
■ 16- bit input/output timer
■ Automotive/CMOS-Schmitt (initial level is Automotive in single
❐ 16-bit freerun timer : 2 channels (FRT0: ICU0/1, FRT1: ICU
chip mode)
4/5/6/7, OCU 4/5/6/7)
■ TTL level (corresponds to external bus pins only, initial level of
these pins is TTL in external bus mode)
❐ 16- bit input capture: (ICU): 6 channels
❐ 16-bit output compare: (OCU): 4 channels
Low voltage/CPU operation detection reset (devices
with T-suffix)
FULL-CAN interface 1 channel
■ Compliant with Ver2.0 part A and Ver2.0 part B CAN specifica-
tions
■ Detects low voltage (4.0 V 0.3 V) and resets automatically
■ Resets automatically when program is runaway and counter is
not cleared within interval time (approx. 262 ms : external 4
MHz)
■ Flexible message buffering (mailbox and FIFO buffering can
be mixed)
■ CAN wake-up function
Dual operation flash memory (only flash memory
devices with A-suffix)
UART (LIN/SCI): 2 channels
■ Equipped with full-duplex double buffer
■ Erase/write and read can be executed in the different bank
(Upper Bank/Lower Bank) at the same time.
■ Clock-asynchronous or clock-synchronous serial transmission
is available.
Models that support 125 °C
■ Devices without A-suffix (excluding evaluation device)
: The maximum operating frequency is 16 MHz
(at TA 125 °C) .
■ Devices with A-suffix (excluding evaluation device)
: The maximum operating frequency is 24 MHz
(at TA 125 °C) .
2
I C interface: 1 channel
■ Up to 400 Kbit/s transfer rate
DTP/External interrupt: 8 channels, CAN wakeup: 1
channel
■ Module for activation of extended intelligent I/O service
(EI2OS), DMA, and generation of external interrupt by external
input.
Flash security function
■ Protects the content of Flash memory (MB90F352x and
MB90F357x only)
Delay interrupt generator module
■ Generates interrupt request for task switching.
External bus interface
■ 4 Mbytes external memory space
Document Number: 002-07872 Rev. *A
Page 2 of 83
MB90350 Series
Contents
Product Lineup 1 .............................................................4
Product Lineup 2 .............................................................6
Product Lineup 3 .............................................................8
Product Lineup 4 ...........................................................10
Packages and Product Correspondence .....................12
Pin Assignments ............................................................13
Pin Description ...............................................................14
I/O Circuit Type ...............................................................18
Handling Devices ............................................................22
Preventing latch-up ...................................................22
Handling unused pins ................................................22
Using external clock ..................................................23
Precautions for when not using a sub clock signal ....23
Notes on during operation of PLL clock mode ..........23
Power supply pins (VCC/VSS) .................................23
Pull-up/down resistors ...............................................23
Crystal Oscillator Circuit ............................................23
Turning-on Sequence of Power Supply to
(External-bus mode) ..................................................24
Notes on using CAN Function ...................................24
Flash security Function .............................................25
Correspondence with TA 105 °C or more ...........25
Low voltage/CPU operation reset circuit ...................25
Internal CR oscillation circuit .....................................26
Block Diagrams ..............................................................27
Memory Map ....................................................................31
I/O Map ............................................................................32
CAN Controllers ..............................................................40
Interrupt Factors, Interrupt Vectors,
Interrupt Control Register ..............................................46
Electrical Characteristics ...............................................48
Absolute Maximum Ratings .......................................48
Recommended Operating Conditions .......................50
DC Characteristics ....................................................51
AC Characteristics .....................................................56
A/D Converter ............................................................71
Definition of A/D Converter Terms ...........................74
Flash Memory Program/Erase Characteristics ..........76
Ordering Information .....................................................77
Package Dimensions ......................................................79
Major Changes ................................................................81
Document History ...........................................................82
Sales, Solutions, and Legal Information ......................83
A/D Converter and Analog Inputs ..............................24
Connection of Unused Pins of A/D Converter if
A/D Converter is not used .........................................24
Notes on Energization ...............................................24
Stabilization of power supply voltage ........................24
Initialization ................................................................24
Port 0 to port 3 output during Power-on
Document Number: 002-07872 Rev. *A
Page 3 of 83
MB90350 Series
1. Product Lineup 1
Part Number
MB90F351,
MB90F352
MB90F351S,
MB90F352S
MB90F351A,
MB90F352A
MB90F351TA, MB90F351AS,
MB90F352TA MB90F352AS
MB90F351TAS,
MB90F352TAS
Parameter
CPU
F2MC-16LX CPU
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6)
System clock
Flash memory
64Kbytes :MB90F351(S)
128Kbytes :MB90F352(S)
Dual operation flash memory
64Kbytes :MB90F351A(S), MB90F351TA(S)
128Kbytes :MB90F352A(S), MB90F352TA(S)
ROM
RAM
4 Kbytes
Emulator-specific power
supply*
—
Sub clock pin
(X0A, X1A)
(Max 100 kHz)
Yes
No
Yes
No
No
Clock monitor
function
Low voltage/CPU
operation detection
reset
No
No
Yes
No
Yes
3.5 V to 5.5 V : at normal operating (not using A/D converter)
4.0 V to 5.5 V : at using A/D converter/Flash programming
4.5 V to 5.5 V : at using external bus
Operating
voltage range
Operating
temperature range
40 °C to 105 °C (125 °C up to
40 °C to 125 °C
16 MHz machine clock)
Package
LQFP-64
2 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
UART
I2C (400 Kbps)
A/D Converter
1 channel
15 channels
10-bit or 8-bit resolution
Conversion time : Min 3 s includes sample time (per one channel)
16-bit Reload Timer
(4 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys Machine clock frequency)
Supports External Event Count function.
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1.
I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7.
16-bit I/O Timer
(2 channels)
Signals an interrupt when overflowing.
Supports Timer Clear when a match with Output Compare (Channel 0, 4) .
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys Machine clock frequency)
4 channels
16-bit Output
Compare
Signals an interrupt when 16-bit I/O Timer matches with output compare registers.
A pair of compare registers can be used to generate an output signal.
6 channels
16-bit Input Capture
Retains freerun timer value by (rising edge, falling edge or rising & falling edge), signals an interrupt.
(Continued)
Document Number: 002-07872 Rev. *A
Page 4 of 83
MB90350 Series
(Continued)
Part Number
MB90F351,
MB90F352
MB90F351S,
MB90F352S
MB90F351A,
MB90F352A
MB90F351TA, MB90F351AS,
MB90F352TA MB90F352AS
MB90F351TAS,
MB90F352TAS
Parameter
6 channels (16-bit)/10 channels (8-bit)
8-bit reload counters × 12
8-bit reload registers for L pulse width × 12
8-bit reload registers for H pulse width × 12
8/16-bit
Programmable Pulse
Generator
Supports 8-bit and 16-bit operation modes.
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler 8-bit reload counter.
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 μs@fosc 4 MHz
(fsys Machine clock frequency, fosc Oscillation clock frequency)
1 channel
Conforms to CAN Specification Version 2.0 Part A and B.
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID
Supports multiple messages.
CAN Interface
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps.
8 channels
External Interrupt
D/A converter
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
extended intelligent I/O services (EI2OS) and DMA.
—
Virtually all external pins can be used as general purpose I/O port.
All push-pull outputs
Bit-wise settable as input/output or peripheral signal
Settable as CMOS schmitt trigger/ automotive inputs
TTL input level settable for external bus (only for external bus pin)
I/O Ports
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10,000 times
Flash Memory
Data retention time : 10 years
Boot block configuration
Erase can be performed on each block.
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash (MB90F352x only)
Corresponding EVA
name
MB90V340A-
102
MB90V340A-
101
MB90V340A-102
MB90V340A-101
* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
Document Number: 002-07872 Rev. *A
Page 5 of 83
MB90350 Series
2. Product Lineup 2
Part Number
MB90351A,
MB90352A
MB90351TA,
MB90352TA
MB90351AS, MB90351TAS,
MB90352AS MB90352TAS
MB90V340A-
101
MB90V340A-
102
Parameter
CPU
F2MC-16LX CPU
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
System clock
Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6)
MASK ROM
64Kbytes :MB90351A(S), MB90351TA(S)
128Kbytes :MB90352A(S), MB90352TA(S)
ROM
RAM
External
4 Kbytes
30 Kbytes
Yes
Emulator-specific power
supply*
—
Sub clock pin
(X0A, X1A)
(Max 100 kHz)
Yes
No
No
No
Yes
Clock monitor
function
Low voltage/CPU
operation detection
reset
No
Yes
No
Yes
No
3.5 V to 5.5 V : at normal operating (not using A/D converter)
4.0 V to 5.5 V : at using A/D converter
4.5 V to 5.5 V : at using external bus
Operating
voltage range
5 V 10%
Operating
temperature range
40 °C to 125 °C
—
Package
LQFP-64
2 channels
PGA-299
5 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
UART
I2C (400 Kbps)
A/D Converter
1 channel
2 channels
15 channels
24 channels
10-bit or 8-bit resolution
Conversion time : Min 3 s includes sample time (per one channel)
16-bit Reload Timer
(4 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys Machine clock frequency)
Supports External Event Count function.
I/O Timer 0 corresponds to ICU
0/1/2/3, OCU 0/1/2/3.
I/O Timer 1 corresponds to ICU
4/5/6/7, OCU 4/5/6/7.
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1.
I/O Timer 1 (clock input FRCK1) corresponds to
ICU 4/5/6/7, OCU 4/5/6/7.
16-bit I/O Timer
(2 channels)
Signals an interrupt when overflowing.
Supports Timer Clear when a match with Output Compare (Channel 0, 4) .
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys Machine clock frequency)
4 channels
8 channels
16-bit Output
Compare
Signals an interrupt when 16-bit I/O Timer matches output compare registers.
A pair of compare registers can be used to generate an output signal.
6 channels
8 channels
16-bit Input Capture
Retains freerun timer value by (rising edge, falling edge or rising & falling edge), signals an interrupt.
(Continued)
Page 6 of 83
Document Number: 002-07872 Rev. *A
MB90350 Series
(Continued)
Part Number
MB90351A,
MB90352A
MB90351TA,
MB90352TA
MB90351AS, MB90351TAS,
MB90352AS MB90352TAS
MB90V340A-
101
MB90V340A-
102
Parameter
8 channels (16-bit)/
16 channels (8-bit)
8-bit reload counters × 16
8-bit reload registers for
L pulse width × 16
8-bit reload registers for
H pulse width × 16
6 channels (16-bit)/10 channels (8-bit)
8-bit reload counters × 12
8-bit reload registers for L pulse width × 12
8-bit reload registers for H pulse width × 12
8/16-bit
Programmable Pulse
Generator
Supports 8-bit and 16-bit operation modes.
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler 8-bit reload counter.
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 μs@fosc 4 MHz
(fsys Machine clock frequency, fosc Oscillation clock frequency)
1 channel
3 channels
Conforms to CAN Specification Version 2.0 Part A and B.
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID
Supports multiple messages.
CAN Interface
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps.
8 channels
16 channels
External Interrupt
D/A converter
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
extended intelligent I/O services (EI2OS) and DMA.
—
2 channels
Virtually all external pins can be used as general purpose I/O port.
All push-pull outputs
Bit-wise settable as input/output or peripheral signal
Settable as CMOS schmitt trigger/ automotive inputs
TTL input level settable for external bus (only for external bus pin)
I/O Ports
Flash Memory
—
Corresponding EVA
name
MB90V340A-102
MB90V340A-101
—
* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
Document Number: 002-07872 Rev. *A
Page 7 of 83
MB90350 Series
3. Product Lineup 3
Part Number
MB90F356A,
MB90F357A
MB90F356TA,
MB90F357TA
MB90F356AS,
MB90F357AS
MB90F356TAS,
MB90F357TAS
Parameter
CPU
F2MC-16LX CPU
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6)
System clock
Dual operation flash memory
64Kbytes :MB90F356A(S), MB90F356TA(S)
128Kbytes :MB90F357A(S), MB90F357TA(S)
ROM
RAM
4 Kbytes
—
Emulator-specific power
supply*
No
Sub clock pin
(X0A, X1A)
Yes
(internal CR oscillation can be used as
sub clock)
Clock monitor
function
Yes
Low voltage/CPU
operation detection
reset
No
Yes
No
Yes
3.5 V to 5.5 V : at normal operating (not using A/D converter)
3.5 V to 5.5 V : at using A/D converter/Flash programming
3.5 V to 5.5 V : at using external bus
Operating
voltage range
Operating
temperature range
40 °C to 125 °C
Package
LQFP-64
2 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
UART
I2C (400 Kbps)
A/D Converter
1 channel
15 channels
10-bit or 8-bit resolution
Conversion time : Min 3 s includes sample time (per one channel)
16-bit Reload Timer
(4 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys Machine clock frequency)
Supports External Event Count function.
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1.
I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7.
16-bit I/O Timer
(2 channels)
Signals an interrupt when overflowing.
Supports Timer Clear when a match with Output Compare (Channel 0, 4) .
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys Machine clock frequency)
4 channels
16-bit Output
Compare
Signals an interrupt when 16-bit I/O Timer matches with output compare registers.
A pair of compare registers can be used to generate an output signal.
6 channels
16-bit Input Capture
Retains freerun timer value by (rising edge, falling edge or rising & falling edge), signals an interrupt.
(Continued)
Document Number: 002-07872 Rev. *A
Page 8 of 83
MB90350 Series
(Continued)
Part Number
MB90F356A,
MB90F357A
MB90F356TA,
MB90F357TA
MB90F356AS,
MB90F357AS
MB90F356TAS,
MB90F357TAS
Parameter
6 channels (16-bit)/10 channels (8-bit)
8-bit reload counters × 12
8-bit reload registers for L pulse width × 12
8-bit reload registers for H pulse width × 12
8/16-bit
Programmable Pulse
Generator
Supports 8-bit and 16-bit operation modes.
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler 8-bit reload counter.
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 μs@fosc 4 MHz
(fsys Machine clock frequency, fosc Oscillation clock frequency)
1 channel
Conforms to CAN Specification Version 2.0 Part A and B.
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID
Supports multiple messages.
CAN Interface
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps.
8 channels
External Interrupt
D/A converter
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
extended intelligent I/O services (EI2OS) and DMA.
—
Virtually all external pins can be used as general purpose I/O port.
All push-pull outputs
Bit-wise settable as input/output or peripheral module signal
Settable as CMOS schmitt trigger/ automotive inputs
TTL input level settable for external bus (only for external bus pin)
I/O Ports
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10,000 times
Flash Memory
Data retention time : 10 years
Boot block configuration
Erase can be performed on each block.
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash (MB90F357x only)
Corresponding EVA
name
MB90V340A-104
MB90V340A-103
* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
Document Number: 002-07872 Rev. *A
Page 9 of 83
MB90350 Series
4. Product Lineup 4
Part Number
MB90356A,
MB90357A
MB90356TA,
MB90357TA
MB90356AS, MB90356TAS,
MB90357AS MB90357TAS
MB90V340A-
103
MB90V340A-
104
Parameter
CPU
F2MC-16LX CPU
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
System clock
Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6)
MASK ROM
64Kbytes :MB90356A(S), MB90356TA(S)
128Kbytes :MB90357A(S), MB90357TA(S)
ROM
RAM
External
4 Kbytes
30 Kbytes
Yes
Emulator-specific power
supply*
—
No
No
(internal CR
Sub clock pin
(X0A, X1A)
Yes
(internal CR oscillation can be
used as sub clock)
oscillation can
be used as sub
Yes
clock)
Clock monitor
function
Yes
Low voltage/CPU
operation detection
reset
No
Yes
No
Yes
No
3.5 V to 5.5 V : at normal operating (not using A/D converter)
4.0 V to 5.5 V : at using A/D converter
4.5 V to 5.5 V : at using external bus
Operating
voltage range
5 V 10%
Operating
temperature range
40 °C to 125 °C
—
Package
LQFP-64
PGA-299
2 channels
5 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
UART
I2C (400 Kbps)
A/D Converter
1 channel
2 channels
15 channels
24 channels
10-bit or 8-bit resolution
Conversion time : Min 3 s includes sample time (per one channel)
16-bit Reload Timer
(4 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys Machine clock frequency)
Supports External Event Count function.
I/O Timer 0 corresponds to ICU
0/1/2/3, OCU 0/1/2/3.
I/O Timer 1 corresponds to ICU
4/5/6/7, OCU 4/5/6/7.
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1.
I/O Timer 1 (clock input FRCK1) corresponds to
ICU 4/5/6/7, OCU 4/5/6/7.
16-bit I/O Timer
(2 channels)
Signals an interrupt when overflowing.
Supports Timer Clear when a match with Output Compare (Channel 0, 4) .
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys Machine clock frequency)
4 channels
8 channels
16-bit Output
Compare
Signals an interrupt when 16-bit I/O Timer matches with output compare registers.
A pair of compare registers can be used to generate an output signal.
(Continued)
Document Number: 002-07872 Rev. *A
Page 10 of 83
MB90350 Series
(Continued)
Part Number
MB90356A,
MB90357A
MB90356TA,
MB90357TA
MB90356AS, MB90356TAS,
MB90357AS MB90357TAS
MB90V340A-
103
MB90V340A-
104
Parameter
6 channels
8 channels
16-bit Input Capture
Retains freerun timer value by (rising edge, falling edge or rising & falling edge), signals an interrupt.
8 channels (16-bit)/16 channels
(8-bit)
6 channels (16-bit)/10 channels (8-bit)
8-bit reload counters × 16
8-bit reload counters × 12
8-bit reload registers for
8-bit reload registers for L pulse width × 12
L pulse width × 16
8-bit reload registers for H pulse width × 12
8/16-bit
8-bit reload registers for
Programmable Pulse
Generator
H pulse width × 16
Supports 8-bit and 16-bit operation modes.
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler 8-bit reload counter.
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 μs@fosc 4 MHz
(fsys Machine clock frequency, fosc Oscillation clock frequency)
1 channel
3 channels
Conforms to CAN Specification Version 2.0 Part A and B.
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID
Supports multiple messages.
CAN Interface
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps.
8 channels
16 channels
External Interrupt
D/A converter
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
extended intelligent I/O services (EI2OS) and DMA.
—
2 channels
Virtually all external pins can be used as general purpose I/O port.
All push-pull outputs
Bit-wise settable as input/output or peripheral module signal
Settable as CMOS schmitt trigger/ automotive inputs
TTL input level settable for external bus (only for external bus pin)
I/O Ports
Flash Memory
—
Corresponding EVA
name
MB90V340A-104
MB90V340A-103
—
* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
Document Number: 002-07872 Rev. *A
Page 11 of 83
MB90350 Series
5. Packages and Product Correspondence
MB90F351A (S) , MB90F351TA (S)
MB90F352A (S) , MB90F352TA (S)
MB90F356A (S) , MB90F356TA (S)
MB90F357A (S) , MB90F357TA (S)
MB90351A (S) , MB90351TA (S)
MB90352A (S) , MB90352TA (S)
MB90356A (S) , MB90356TA (S)
MB90357A (S) , MB90357TA (S)
MB90V340A
-101
MB90F351
MB90F351S
MB90F352
MB90F352S
Package
-102
-103
-104
PGA-299C-A01
×
×
×
FPT-64P-M23
(12 mm , 0.65 mm pitch)
×
×
FPT-64P-M24
(10 mm , 0.50 mm pitch)
*
* : This device is under development.
: Yes, × : No
Note : Refer to “Package Dimensions” for detail of each package.
Document Number: 002-07872 Rev. *A
Page 12 of 83
MB90350 Series
6. Pin Assignments
■ MB90F351(S), MB90F352(S),MB90F351A(S), MB90F351TA(S), MB90F352A(S), MB90F352TA(S),
MB90F356A(S), MB90F356TA(S), MB90F357A(S), MB90F357TA(S),MB90351A(S), MB90351TA(S),
MB90352A(S), MB90352TA(S),MB90356A(S), MB90356TA(S), MB90357A(S), MB90357TA(S),
(TOP VIEW)
(LQFP-64P)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P10/AD08/TIN1
Vcc
C
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P07/AD07/INT15
P25/A21/IN1/ADTG
P44/SDA0/FRCK0
P45/SCL0/FRCK1
P30/ALE/IN4
P31/RD/IN5
P06/AD06/INT14
P05/AD05/INT13
P04/AD04/INT12
P03/AD03/INT11
P02/AD02/INT10
P01/AD01/INT9
P00/AD00/INT8
MD0
P32/WRL/WR/INT10R
P33/WRH
P34/HRQ/OUT4
P35/HAK/OUT5
P36/RDY/OUT6
P37/CLK/OUT7
P60/AN0
MD1
MD2
P41/X1A*
P40/X0A*
P61/AN1
Vss
AVcc
P43/IN7/TX1
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
(FPT-64P-M23, FPT-64P-M24)
* : Devices without S-suffix
Devices with S-suffix
: X0A, X1A
: P40, P41
Document Number: 002-07872 Rev. *A
Page 13 of 83
MB90350 Series
7. Pin Description
Pin No.
Circuit
type
Pin name
Function
LQFP64*
46
47
45
X1
X0
Oscillation output pin
A
E
Oscillation input pin
RST
Reset input pin
P62 to P67
AN2 to AN7
General purpose I/O ports
Analog input pins for A/D converter
3 to 8
I
PPG4 (5) , 6 (7) , 8
(9) , A (B) , C (D) , E
(F)
Output pins for PPGs
P50
AN8
General purpose I/O port
9
O
I
Analog input pin for A/D converter
Serial data input pin for UART2
General purpose I/O port
SIN2
P51
10
11
12
AN9
Analog input pin for A/D converter
Serial data output pin for UART2
General purpose I/O port
SOT2
P52
AN10
SCK2
P53
I
Analog input pin for A/D converter
Serial clock I/O pin for UART2
General purpose I/O port
AN11
TIN3
I
Analog input pin for A/D converter
Event input pin for reload timer3
General purpose I/O port
P54
13
AN12
TOT3
P55, P56
AN13, AN14
P42
I
I
Analog input pin for A/D converter
Output pin for reload timer3
General purpose I/O ports
14, 15
Analog input pins for A/D converter
General purpose I/O port
IN6
Data sample input pin for input capture ICU6
RX input pin for CAN1
16
17
F
F
RX1
INT9R
P43
External interrupt request input pin for INT9
General purpose I/O port
IN7
Data sample input pin for input capture ICU7
TX output pin for CAN1
TX1
General purpose I/O ports
(devices with S-suffix and MB90V340A-101/103)
P40, P41
X0A, X1A
P00 to P07
F
B
19, 20
X0A : Oscillation input pins for sub clock
X1A : Oscillation output pins for sub clock
(devices without S-suffix and MB90V340A-102/104)
General purpose I/O ports. The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
24 to 31
G
Input/output pins of external address data bus lower 8 bits. This function is enabled
when the external bus is enabled.
AD00 to AD07
INT8 to INT15
External interrupt request input pins for INT8 to INT15
(Continued)
Document Number: 002-07872 Rev. *A
Page 14 of 83
MB90350 Series
Pin No.
Circuit
type
Pin name
Function
LQFP64*
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
P10
32
33
G
G
Input/output pin for external bus address data bus bit 8.
This function is enabled when external bus is enabled.
AD08
TIN1
P11
Event input pin for reload timer1
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
Input/output pin for external bus address data bus bit 9. This function is enabled when
external bus is enabled.
AD09
TOT1
P12
Output pin for reload timer1
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
Input/output pin for external bus address data bus bit 10. This function is enabled when
external bus is enabled.
AD10
34
N
SIN3
Serial data input pin for UART3
INT11R
External interrupt request input pin for INT11
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
P13
35
36
G
G
Input/output pin for external bus address data bus bit 11.
This function is enabled when external bus is enabled.
AD11
SOT3
P14
Serial data output pin for UART3
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
Input/output pin for external bus address data bus bit 12.
This function is enabled when external bus is enabled.
AD12
SCK3
P15
Clock input/output pin for UART3
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
37
38
39
N
G
G
Input/output pin for external bus address data bus bit 13.
This function is enabled when external bus is enabled.
AD13
P16
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
Input/output pin for external bus address data bus bit 14.
This function is enabled when external bus is enabled.
AD14
P17
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
Input/output pin for external bus address data bus bit 15.
This function is enabled when external bus is enabled.
AD15
General purpose I/O ports. The register can be set to select whether to use a pull-up
resistor. In external bus mode, the pins are enabled as a general purpose I/O port when
the corresponding bit in the external address output control register (HACR) is 1.
P20 to P23
A16 to A19
Output pins for A16 to A19 of the external address data bus.
When the corresponding bit in the external address output control register (HACR) is 0,
the pins are enabled as high address output pins A16 to A19.
40 to 43
G
PPG9 (8) ,
PPGB (A) ,
PPGD (C) ,
PPGF (E)
Output pins for PPGs
(Continued)
Document Number: 002-07872 Rev. *A
Page 15 of 83
MB90350 Series
Pin No.
Circuit
type
Pin name
Function
LQFP64*
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. In external bus mode, the pin is enabled as a general-
purpose I/O port when the corresponding bit in the external address output control
register (HACR) is 1.
P24
44
G
Output pin for A20 of the external address data bus. When the corresponding bit in the
external address output control register (HACR) is 0, the pin is
enabled as high address output pin A20.
A20
IN0
Data sample input pin for input capture ICU0
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. In external bus mode, the pin is enabled as a general-
purpose I/O port when the corresponding bit in the external address output control
register (HACR) is 1.
P25
Output pin for A21 of the external address data bus. When the corresponding bit in the
external address output control register (HACR) is 0, the pin is enabled as high address
output pin A21.
51
G
A21
IN1
ADTG
P44
Data sample input pin for input capture ICU1
Trigger input pin for A/D converter
General purpose I/O port
52
53
SDA0
FRCK0
P45
H
H
Serial data I/O pin for I2C 0
Input pin for the 16-bit I/O Timer 0
General purpose I/O port
Serial clock I/O pin for I2C 0
SCL0
FRCK1
Input pin for the 16-bit I/O Timer 1
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
P30
54
55
G
G
ALE
IN4
Address latch enable output pin. This function is enabled when external bus is enabled.
Data sample input pin for input capture ICU4
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
P31
Read strobe output pin for data bus. This function is enabled when external bus is
enabled.
RD
IN5
Data sample input pin for input capture ICU5
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled either in single-chip mode or with the WR/WRL pin
output disabled.
P32
Write strobe output pin for the data bus. This function is enabled when both the external
bus and the WR/WRL pin output are enabled. WRL is used to write-strobe 8 lower bits
of the data bus in 16-bit access. WR is used to write-strobe 8 bits of the data bus in 8-bit
access.
56
57
G
G
WR/WRL
INT10R
P33
External interrupt request input pin for INT10
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled either in single-chip mode, in
external bus 8-bit mode or with the WRH pin output disabled.
Write strobe output pin for the 8 higher bits of the data bus. This function is enabled when
the external bus is enabled, when the external bus 16-bit mode is selected, and when
the WRH output pin is enabled.
WRH
(Continued)
Document Number: 002-07872 Rev. *A
Page 16 of 83
MB90350 Series
Pin No.
Circuit
type
Pin name
Function
LQFP64*
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled either in single-chip mode or with the hold function
disabled.
P34
58
59
60
G
G
G
Hold request input pin. This function is enabled when both the external bus and the hold
function are enabled.
HRQ
OUT4
Waveform output pin for output compare OCU4
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled either in single-chip mode or with the hold function
disabled.
P35
Hold acknowledge output pin. This function is enabled when both the
external bus and the hold function are enabled.
HAK
OUT5
Waveform output pin for output compare OCU5
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled either in single-chip mode or with the external ready
function disabled.
P36
Ready input pin. This function is enabled when both the external bus and the external
ready function are enabled.
RDY
OUT6
Waveform output pin for output compare OCU6
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled either in single-chip mode or with the CLK output
disabled.
P37
61
G
I
CLK output pin. This function is enabled when both the external bus and CLK output are
enabled.
CLK
OUT7
P60, P61
AN0, AN1
AVCC
Waveform output pin for output compare OCU7
General purpose I/O ports
62, 63
Analog input pins for A/D converter
64
2
K
L
VCC power input pin for analog circuits
Reference voltage input for the A/D converter. This power supply must be turned on or
AVRH
off while a voltage higher than or equal to AVRH is applied to AVCC
VSS power input pin for analog circuits
Input pins for specifying the operating mode
Input pin for specifying the operating mode
Power (3.5 V to 5.5 V) input pin
.
1
AVSS
MD1, MD0
MD2
K
C
22, 23
21
D
49
VCC
—
—
18, 48
VSS
Power (0 V) input pins
This is the power supply stabilization capacitor pin. It should be connected to a higher
than or equal to 0.1 μF ceramic capacitor.
50
C
K
* : FPT-64P-M23, FPT-64P-M24
Document Number: 002-07872 Rev. *A
Page 17 of 83
MB90350 Series
8. I/O Circuit Type
Type
Circuit
Remarks
Oscillation circuit
X1
Xout
• High-speed oscillation feedback
resistor = approx. 1 M
A
X0
Standby control signal
Xout
X1A
X0A
Oscillation circuit
• Low-speed oscillation feedback
resistor = approx. 10 M
B
Standby control signal
CMOS
Mask ROM device:
R
R
• CMOS hysteresis input pin
C
hysteresis
Flash memory device:
• CMOS input pin
inputs
Mask ROM device:
CMOS
hysteresis
inputs
• CMOS hysteresis input pin
• Pull-down resistor value: approx. 50 k
D
Pull-down
resistor
Flash memory device:
• CMOS input pin
• No Pull-down
CMOS hysteresis input pin
• Pull-up resistor value: approx. 50 k
Pull-up
resistor
E
R
CMOS
hysteresis
inputs
(Continued)
Document Number: 002-07872 Rev. *A
Page 18 of 83
MB90350 Series
Type
Circuit
P-ch
Remarks
• (CIOMLO=S4lemvAel, oIOuHtput4 mA)
Pout
Nout
• CMOS hysteresis inputs (With the standby-time
input shutdown function)
N-ch
• Automotive input (With the standby-time input
shutdown function)
R
F
CMOS
hysteresis inputs
Automotive inputs
Standby control for
input shutdown
• (CIOMLO=S4lemvAel, oIOuHtput4 mA)
Pull-up control
Pout
Pull-up
resistor
• CMOS hysteresis inputs (With the standby-time
input shutdown function)
P-ch
P-ch
N-ch
• Automotive input (With the standby-time input
shutdown function)
• TTL input (With the standby-time input shut-
down function)
Nout
• Programmable pull-up resistor:
approx. 50 k
R
G
CMOS
hysteresis inputs
Automotive inputs
TTL input
Standby control for
input shutdown
• (CIOMLO=S3lemvAel, oIOuHtput3 mA)
P-ch
N-ch
Pout
Nout
• CMOS hysteresis inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time input
shutdown function)
H
R
CMOS
hysteresis inputs
Automotive inputs
Standby control for
input shutdown
(Continued)
Document Number: 002-07872 Rev. *A
Page 19 of 83
MB90350 Series
Type
Circuit
Pout
Remarks
• CMOS level output
P-ch
N-ch
(IOL = 4 mA, IOH = 4 mA)
• CMOS hysteresis inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time input
shutdown function)
Nout
• A/D analog input
R
I
CMOS
hysteresis inputs
Automotive inputs
Standby control for
input shutdown
Analog input
• Power supply input protection circuit
P-ch
N-ch
K
• A/D converter reference voltage power supply
input pin, with the protection circuit
• Flash memory devices do not have a
protection circuit against VCC for pin
AVRH.
ANE
AVR
P-ch
N-ch
L
ANE
(Continued)
Document Number: 002-07872 Rev. *A
Page 20 of 83
MB90350 Series
(Continued)
Type
Circuit
Remarks
• (CIOMLO=S4lemvAel, oIOuHtput4 mA)
pull-up control
pull-up
resistor
• CMOS inputs (With the standby-time
input shutdown function)
Pout
Nout
• Automotive input (With the standby-time input
shutdown function)
• TTL input (With the standby-time input shut-
down function)
• Programmable pull-up resistor:
approx. 50 k
R
N
CMOS inputs
Automotive inputs
TTL input
Standby control for
input shutdown
• (CIOMLO=S4lemvAel, oIOuHtput4 mA)
P-ch
N-ch
Pout
Nout
• CMOS inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time input
shutdown function)
• A/D analog input
R
O
CMOS inputs
Automotive inputs
Standby control for
input shutdown
Analog input
Document Number: 002-07872 Rev. *A
Page 21 of 83
MB90350 Series
9. Handling Devices
Special care is required for the following when handling the device :
■ Preventing latch-up
■ Treatment of unused pins
■ Using external clock
■ Precautions for when not using a sub clock signal
■ Notes on during operation of PLL clock mode
■ Power supply pins (VCC/VSS
)
■ Pull-up/down resistors
■ Crystal Oscillator Circuit
■ Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
■ Connection of Unused Pins of A/D Converter
■ Notes on Energization
■ Stabilization of power supply voltage
■ Initialization
■ Port0 to port3 output during Power-on (External-bus mode)
■ Notes on using CAN Function
■ Flash security Function
■ Correspondence with TA 105 °C or more
■ Low voltage/CPU operation detection reset circuit
■ Internal CR oscillation circuit
9.1 Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
■ A voltage higher than VCC or lower than VSS is applied to an input or output pin.
■ A voltage higher than the rated voltage is applied between VCC pin and VSS pin.
■ The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
In using the devices, take sufficient care to avoid exceeding maximum ratings.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage.
9.2 Handling unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefore they
must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 kΩ.
Unused I/O pins should be set to the output state and can be left open, or the input state with the above described connection.
Document Number: 002-07872 Rev. *A
Page 22 of 83
MB90350 Series
9.3 Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
MB90350 Series
X0
X1
Open
9.4 Precautions for when not using a sub clock signal
If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the X1A pin open.
9.5 Notes on during operation of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempts to be working with the self-oscillating circuit even when there is no
external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed.
9.6 Power supply pins (V /V
)
CC SS
■ If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected inside
of the device to prevent such malfunctioning as latch up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard
for total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally.
Connect VCC and VSS pins to the device from the current supply source at a low impedance.
■ As a measure against power supply noise, connect a capacitor of about 0.1 μF as a bypass capacitor between VCC and VSS pins
in the vicinity of VCC and VSS pins of the device.
Vcc
Vss
Vcc
Vss
Vss
Vcc
MB90350
Series
Vcc
Vss
Vcc
Vss
9.7 Pull-up/down resistors
The MB90350 series does not support internal pull-up/down resistors (Port 0 to Port 3: built-in pull-up resistors). Use external compo-
nents where needed.
9.8 Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest
distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of
oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground area for stabilizing the
operation.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
Document Number: 002-07872 Rev. *A
Page 23 of 83
MB90350 Series
9.9 Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on theA/D converter power supply (AVCC, AVRH) and analog inputs (AN0 to AN14) after turning-on the digital power
supply (VCC) .
Turn-off the digital power after turning off the A/D converter power supply and analog inputs. In this case, make sure that the voltage
does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable).
9.10 Connection of Unused Pins of A/D Converter if A/D Converter is not used
Connect unused pins of A/D converter to AVCC VCC, AVSS AVRH VSS
.
9.11 Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at
50 μs or more (0.2 V to 2.7 V) .
9.12 Stabilization of power supply voltage
Asudden change in the power supply voltage may cause the device to malfunction even within the specified VCC power supply voltage
operating range. Therefore, the VCC power supply voltage should be stabilized.
For reference, the power supply voltage should be controlled so that VCC ripple variations (peak-to-peak value) at commercial
frequencies (50 Hz to 60 Hz) fall below 10% of the standard VCC power supply voltage and the coefficient of fluctuation does not
exceed 0.1 V/ms at instantaneous power switching.
9.13 Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers, turn on the power
again.
9.14 Port 0 to port 3 output during Power-on (External-bus mode)
As shown below, when power is turned on in external-bus mode, there is a possibility that output signal of
Port 0 to Port 3 might be unstable.
1/2 VCC
V
CC
Port0 to Port3
Port0 to Port3 outputs Port0 to Port3 outputs = Hi-Z
might be unstable.
9.15 Notes on using CAN Function
To use CAN function, please set “1” to DIRECT bit of CAN direct mode register (CDMR).
If DIRECT bit is set to “0” (initial value), wait states will be performed when accessing CAN registers.
Note : Please refer to section “22.15 CAN Direct Mode Register” in Hardware Manual of MB90350 series for detail of CAN direct mode
register.
Document Number: 002-07872 Rev. *A
Page 24 of 83
MB90350 Series
9.16 Flash security Function
The security byte is located in the area of the flash memory.
If protection code 01H is written in the security byte, the flash memory is in the protected state by security.
Therefore please do not write 01H in this address if you do not use the security function.
Please refer to following table for the address of the security byte.
Flash memory size
Address for security bit
MB90F352(S)
MB90F352A(S)
MB90F352TA(S)
MB90F357A(S)
MB90F357TA(S)
Embedded 1 Mbit Flash Memory
FE0001H
9.17 Correspondence with T 105 °C or more
A
If used exceeding TA 105 °C, please contact sales representatives for reliability limitations.
9.18 Low voltage/CPU operation reset circuit
The low voltage detection reset circuit is a function that monitors power supply voltage in order to detect when a voltage drops below
a given voltage level. When a low voltage condition is detected, an internal reset signal is generated.
The CPU operation detection reset circuit is a 20-bit counter that uses oscillation as a count clock and generates an internal reset
signal if not cleared within a given time after startup.
9.18.1 Low voltage detection reset circuit
Detection voltage
4.0 V 0.3 V
When a low voltage condition is detected, the low voltage detection flag (LVRC: LVRF) is set to “1” and an internal reset signal is output.
Because the low voltage detection reset circuit continues to operate even in stop mode, detection of a low voltage condition generates
an internal reset and releases stop mode.
During an internal RAM write cycle, low voltage reset is generated after the completion of writing. During the output of this internal
reset, the reset output from the low voltage detection reset circuit is suppressed.
9.18.2 CPU operation detection reset circuit
The CPU operation detection reset circuit is a counter that prevents program runaway. The counter starts automatically after a
power-on reset, and must be continually cleared within a given time. If the given time interval elapses and the counter has not been
cleared, a cause such as infinite program looping is assumed and an internal reset signal is generated. The internal reset generated
from the CPU operation detection circuit has a width of 5 machine cycles.
Interval time
220/FC (approx. 262 ms*)
* : This value assumes the interval time at an oscillation clock frequency of 4 MHz.
During recovery from standby mode, the detection period is the maximum interval plus 20 μs.
This circuit does not operate in modes where CPU operation is stopped.
The CPU operation detection reset circuit counter is cleared under any of the following conditions.
■ “0” writing to CL bit of LVRC register
■ Internal reset
■ Main oscillation clock stop
■ Transit to sleep mode
■ Transit to timebase timer mode and watch mode
Document Number: 002-07872 Rev. *A
Page 25 of 83
MB90350 Series
9.19 Internal CR oscillation circuit
Value
Typ
100
—
Parameter
Symbol
Unit
Min
50
Max
Oscillation frequency
fRC
200
100
kHz
Oscillation stabilization wait time
tstab
—
μs
Document Number: 002-07872 Rev. *A
Page 26 of 83
MB90350 Series
10. Block Diagrams
■ MB90V340A-101/102
X0
X0A*
Clock
controller
RST
X1
16LX CPU
X1A*
RAM
30 Kbytes
I/O Timer 0
FRCK0
Input
Capture
8 channels
IN7 to IN0
Output
Compare
8 channels
OUT7 to OUT0
FRCK1
Prescaler
5 channels
I/O Timer 1
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
CAN
Controller
3 channels
UART
5 channels
RX2 to RX0
TX2 to TX0
16-bit
Reload Timer
4 channels
AVCC
TIN3 to TIN0
10-bit
A/D
Converter
24 channels
AVSS
TOT3 to TOT0
AN23 to AN0
AVRH
AD15 to AD00
A21 to A16
ALE
AVRL
ADTG
10-bit
D/A
Converter
2 channels
RD
External
Bus
Interface
WRL
DA00,DA01
WRH
HRQ
HAK
8/16-bit
PPG
16 channels
PPGF to PPG0
RDY
CLK
I2C interface
2 channels
SDA0,SDA1
SCL0,SCL1
INT7 to INT0
INT15 to INT8
External
Interrupt
(INT11R to INT9R)
DMAC
Clock
CKOT
Monitor
* : MB90V340A-102 only
Document Number: 002-07872 Rev. *A
Page 27 of 83
MB90350 Series
■ MB90V340A-103/104
X0
X0A *
RST
X1
X1A*
Clock
controller/Monit
or
F2MC-16LX
Core
FRCK0
I/O Timer 0
CR oscillation
circuit
Input
Capture
8 channels
IN7 to IN0
RAM
30 Kbytes
Output
Compare
8 channels
OUT7 to OUT0
FRCK1
Prescaler
5 channels
I/O Timer 1
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
CAN
Controller
3 channels
UART
5 channels
RX2 to RX0
TX2 to TX0
16-bit
Reload
Timer
AVCC
AVSS
AN23 to AN0
AVRH
AVRL
TIN3 to TIN0
TOT3 to TOT0
8/10-bit
A/D
Converter
24 channels
4 channels
AD15 to AD00
A23 to A16
ALE
ADTG
10-bit
D/A
Converter
2 channels
RD
WRL
WRH
External
Bus
Interface
DA01, DA00
HRQ
HAK
RDY
CLK
8/16-bit
PPG
16 channels
PPGF to PPG0
I2C interface
2 channels
SDA1, SDA0
SCL1, SCL0
INT15 to INT8
(INT15R to INT8R)
INT7 to INT0
DTP/External
Interrupt
DMA
Clock
Monitor
CKOT
* : MB90V340A-104 only
Document Number: 002-07872 Rev. *A
Page 28 of 83
MB90350 Series
■ MB90F352 (S) , MB90F351 (S) , MB90F352A (S) , MB90F352TA (S) , MB90F351A (S) , MB90F351TA (S) , MB90352A (S) ,
MB90352TA (S) , MB90351A (S) , MB90351TA (S)
X0
X0A *1
Clock
RST
controller
16LX CPU
X1
X1A*1
Low voltage/
CPU operation
detection
I/O Timer 0
FRCK0
reset*2
Input
Capture
6 channels
RAM
4 Kbytes
IN7 to IN4,
IN1, IN0
ROM/Flash
128 K/64
Kbytes
Output
Compare
4 channels
OUT7 to OUT4
FRCK1
Prescaler
2 channels
I/O Timer 1
SOT3, SOT2
SCK3, SCK2
SIN3, SIN2
CAN
Controller
1 channel
UART
2 channels
RX1
TX1
16-bit
Reload Timer
4 channels
AVCC
TIN3, TIN1
AVSS
8/10-bit
A/D
Converter
15 channels
TOT3, TOT1
AN14 to AN0
AVRH
AD15 to AD00
A21 to A16
ALE
ADTG
RD
External
Bus
WRL
Interface
WRH
8/16-bit
PPG
PPGF to PPG8
PPG6, PPG4
HRQ
10/6 channels
HAK
RDY
CLK
I2C interface
1 channel
SDA0
SCL0
External
Interrupt
INT15 to INT8
(INT11R to INT9R)
DMAC
*1 : Only for devices without “S”-suffix
*2 : Only for devices with “T”-suffix
Document Number: 002-07872 Rev. *A
Page 29 of 83
MB90350 Series
■ MB90F357A (S) , MB90F357TA (S) , MB90F356A (S) , MB90F356TA (S) , MB90357A (S) , MB90357TA (S) , MB90356A (S) ,
MB90356TA (S)
X0
Clock
controller/
monitor
X0A*1
RST
16LX CPU
X1
X1A*1
CR
oscillation
circuit
I/O Timer 0
FRCK0
Input
Capture
6 channels
Low voltage detector*2
CPU operation
detector*2
IN7 to IN4,
IN1, IN0
Output
Compare
4 channels
OUT7 to OUT4
FRCK1
RAM
4 Kbytes
I/O Timer 1
ROM/Flash
128 K/64 K
bytes
CAN
Controller
1 channel
RX1
TX1
Prescaler
2 channels
16-bit
Reload Timer
4 channels
TIN3, TIN1
SOT3, SOT2
SCK3, SCK2
SIN3, SIN2
UART
2 channels
TOT3, TOT1
AVCC
AD15 to AD00
A21 to A16
ALE
AVSS
8/10-bit
A/D
Converter
15 channels
AN14 to AN0
RD
External
Bus
Interface
AVRH
ADTG
WRL
WRH
HRQ
HAK
8/16-bit
PPG
10/6 channels
PPGF to PPG8
PPG6, PPG4
RDY
CLK
SDA0
SCL0
I2C interface
1 channel
External
Interrupt
INT15 to INT8
(INT11R to INT9R)
DMAC
*1 : Only for devices without “S”-suffix
*2 : Only for devices with “T”-suffix
Document Number: 002-07872 Rev. *A
Page 30 of 83
MB90350 Series
11. Memory Map
MB90352A (S)
MB90352TA (S)
MB90357A (S)
MB90357TA (S)
MB90F352A (S)
MB90F352TA (S)
MB90F357A (S)
MB90F357TA (S)
MB90F352 (S)
MB90351A (S)
MB90351TA (S)
MB90356A (S)
MB90356TA (S)
MB90F351A (S)
MB90F351TA (S)
MB90F356A (S)
MB90F356TA (S)
MB90F351 (S)
MB90V340A-101
MB90V340A-102
MB90V340A-103
MB90V340A-104
FFFFFFH
FFFFFFH
FFFFFFH
FF0000H
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM (F8 bank)
FF0000H
FEFFFFH
ROM (FF bank)
ROM (FE bank)
ROM (FF bank)
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FDFFFFH
External access
area
External access
area
FC0000H
FBFFFFH
FB0000H
FAFFFFH
C00100H
00FFFFH
C00100H
00FFFFH
FA0000H
F9FFFFH
F90000H
F8FFFFH
ROM (image of
FF bank)
ROM (image of
FF bank)
F80000H
00FFFFH
008000H
007FFFH
008000H
007FFFH
ROM (image of
FF bank)
Peripheral
Peripheral
008000H
007FFFH
007900H
007900H
Peripheral
007900H
0078FFH
RAM 30 Kbytes
001100H
0010FFH
0010FFH
000100H
RAM 4 Kbytes
External access area
Peripheral
RAM 4 Kbytes
External access area
Peripheral
000100H
000100H
0000EFH
000000H
0000EFH
000000H
0000EFH
000000H
Peripheral
: No access
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective.
Since the low-order 16 bits are the same, the table in ROM can be referenced without using the far specification in the pointer
declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF7FFFH is visible
only in bank FF.
Document Number: 002-07872 Rev. *A
Page 31 of 83
MB90350 Series
12. I/O Map
Address
Register
Port 0 Data Register
Port 1 Data Register
Abbreviation Access
Resource name
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00H
01H
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
02H
Port 2 Data Register
Port 3 Data Register
Port 4 Data Register
Port 5 Data Register
Port 6 Data Register
03H
04H
05H
06H
07H to 0AH
0BH
Reserved
Port 5 Analog Input Enable Register
Port 6 Analog Input Enable Register
ADER5
ADER6
R/W
R/W
Port 5, A/D
Port 6, A/D
11111111B
11111111B
0CH
0DH
Reserved
0EH
Input Level Select Register 0
Input Level Select Register 1
Port 0 Direction Register
Port 1 Direction Register
Port 2 Direction Register
Port 3 Direction Register
Port 4 Direction Register
Port 5 Direction Register
Port 6 Direction Register
ILSR0
ILSR1
DDR0
DDR1
DDR2
DDR3
DDR4
DDR5
DDR6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Ports
Ports
00000000B
00000000B
00000000B
00000000B
XX000000B
00000000B
XX000000B
X0000000B
00000000B
0FH
10H
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
11H
12H
13H
14H
15H
16H
17H to 19H
1AH
Reserved
DDRA
Reserved
SIN input Level Setting Register
W
UART2, UART3
X00XXXXXB
1BH
1CH
Port 0 Pull-up Control Register
Port 1 Pull-up Control Register
Port 2 Pull-up Control Register
Port 3 Pull-up Control Register
PUCR0
PUCR1
PUCR2
PUCR3
R/W
R/W
R/W
R/W
Port 0
Port 1
Port 2
Port 3
00000000B
00000000B
00000000B
00000000B
1DH
1EH
1FH
20H to 37H
38H
Reserved
PPG 4 Operation Mode Control Register
PPG 5 Operation Mode Control Register
PPG 4/5 Count Clock Select Register
PPGC4
PPGC5
PPG45
W, R/W
W, R/W
R/W
0X000XX1B
0X000001B
000000X0B
16-bit Programmable
Pulse Generator 4/5
39H
3AH
Address Match
Detection 1
3BH
Address Detect Control Register 1
PACSR1
R/W
00000000B
3CH
3DH
3EH
3FH
40H
41H
42H
43H
PPG 6 Operation Mode Control Register
PPG 7 Operation Mode Control Register
PPG 6/7 Count Clock Select Register
PPGC6
PPGC7
PPG67
W, R/W
W, R/W
R/W
0X000XX1B
0X000001B
000000X0B
16-bit Programmable
Pulse Generator 6/7
Reserved
PPG 8 Operation Mode Control Register
PPG 9 Operation Mode Control Register
PPG 8/9 Count Clock Select Register
PPGC8
PPGC9
PPG89
W, R/W
W, R/W
R/W
0X000XX1B
0X000001B
000000X0B
16-bit Programmable
Pulse Generator 8/9
Reserved
(Continued)
Document Number: 002-07872 Rev. *A
Page 32 of 83
MB90350 Series
Address
44H
Register
Abbreviation Access
Resource name
Initial value
0X000XX1B
0X000001B
000000X0B
PPG A Operation Mode Control Register
PPG B Operation Mode Control Register
PPG A/B Count Clock Select Register
PPGCA
PPGCB
PPGAB
W, R/W
W, R/W
R/W
16-bit Programmable
Pulse Generator A/B
45H
46H
47H
Reserved
48H
PPG C Operation Mode Control Register
PPG D Operation Mode Control Register
PPG C/D Count Clock Select Register
PPGCC
PPGCD
PPGCD
W,R/W
W,R/W
R/W
0X000XX1B
0X000001B
000000X0B
16-bit Programmable
Pulse Generator C/D
49H
4AH
4BH
4CH
4DH
4EH
4FH
Reserved
PPG E Operation Mode Control Register
PPG F Operation Mode Control Register
PPG E/F Count Clock Select Register
PPGCE
PPGCF
PPGEF
W,R/W
W,R/W
R/W
0X000XX1B
0X000001B
000000X0B
16-bit Programmable
Pulse Generator E/F
Reserved
50H
Input Capture Control Status Register 0/1
Input Capture Edge Register 0/1
ICS01
ICE01
R/W
00000000B
Input Capture 0/1
51H
R/W, R
XXX0X0XXB
52H, 53H
54H
Reserved
Input Capture Control Status Register 4/5
Input Capture Edge Register 4/5
ICS45
ICE45
ICS67
ICE67
R/W
R
00000000B
XXXXXXXXB
00000000B
XXX000XXB
Input Capture 4/5
Input Capture 6/7
55H
56H
Input Capture Control Status Register 6/7
Input Capture Edge Register 6/7
R/W
R/W, R
57H
58H to 5BH
5CH
5DH
5EH
5FH
Reserved
Output Compare Control Status Register 4
Output Compare Control Status Register 5
Output Compare Control Status Register 6
Output Compare Control Status Register 7
Timer Control Status Register 0
Timer Control Status Register 0
Timer Control Status Register 1
Timer Control Status Register 1
Timer Control Status Register 2
Timer Control Status Register 2
Timer Control Status Register 3
Timer Control Status Register 3
A/D Control Status Register 0
A/D Control Status Register 1
A/D Data Register 0
OCS4
OCS5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0000XX00B
0XX00000B
0000XX00B
0XX00000B
00000000B
XXXX0000B
00000000B
XXXX0000B
00000000B
XXXX0000B
00000000B
XXXX0000B
000XXXX0B
0000000XB
00000000B
XXXXXX00B
00000000B
00000000B
Output Compare 4/5
Output Compare 6/7
16-bit Reload Timer 0
16-bit Reload Timer 1
16-bit Reload Timer 2
16-bit Reload Timer 3
OCS6
OCS7
60H
TMCSR0
TMCSR0
TMCSR1
TMCSR1
TMCSR2
TMCSR2
TMCSR3
TMCSR3
ADCS0
ADCS1
ADCR0
ADCR1
ADSR0
ADSR1
61H
62H
63H
64H
65H
66H
67H
68H
69H
6AH
6BH
6CH
6DH
A/D Converter
A/D Data Register 1
R
ADC Setting Register 0
R/W
R/W
ADC Setting Register 1
Low Voltage/CPU
Operation Detection
Reset
Low Voltage/CPU Operation Detection Reset
Control Register
6EH
LVRC
R/W, W
00111000B
(Continued)
Document Number: 002-07872 Rev. *A
Page 33 of 83
MB90350 Series
Abbrevia-
tion
Address
Register
Access
Resource name
ROM Mirror
Initial value
6FH
ROM Mirror Function Select Register
ROMM
W
XXXXXXX1B
70H to 7FH
Reserved
80H to 8FH Reserved for CAN Interface 1. Refer to “CAN Controllers”
90H to 9AH
Reserved
DMA Descriptor Channel Specification
Register
9BH
DCSR
R/W
00000000B
DMA
9CH
9DH
DMA Status Register L
DMA Status Register H
DSRL
DSRH
R/W
R/W
00000000B
00000000B
Address Match
Detection 0
9EH
9FH
A0H
Address Detect Control Register 0
PACSR0
DIRR
R/W
R/W
00000000B
XXXXXXX0B
00011000B
Delayed Interrupt/Release Register
Delayed Interrupt
Low-power Consumption Mode Control
Register
Low Power Consumption
Control Circuit
LPMCR
W,R/W
Low Power Consumption
Control Circuit
A1H
Clock Selection Register
CKSCR
R,R/W
11111100B
A2H, A3H
A4H
Reserved
DMA Stop Status Register
Automatic Ready Function Selection Register
External Address Output Control Register
Bus Control Signal Selection Register
Watchdog Control Register
DSSR
ARSR
HACR
ECSR
WDTC
TBTC
WTC
R/W
W
DMA
00000000B
0011XX00B
00000000B
0000000XB
XXXXX111B
1XX00100B
1X001000B
A5H
External Memory
Access
A6H
W
A7H
W
A8H
R,W
W,R/W
R,R/W
Watchdog Timer
Timebase timer
Watch Timer
A9H
Timebase Timer Control Register
Watch Timer Control Register
AAH
ABH
ACH
ADH
Reserved
DMA Enable Register L
DMA Enable Register H
DERL
DERH
R/W
R/W
00000000B
00000000B
DMA
Flash Control Status Register
(Flash Devices only. Otherwise reserved)
AEH
AFH
FMCS
R,R/W
Flash Memory
000X0000B
Reserved
(Continued)
Document Number: 002-07872 Rev. *A
Page 34 of 83
MB90350 Series
Address
B0H
Register
Interrupt Control Register 00
Interrupt Control Register 01
Interrupt Control Register 02
Interrupt Control Register 03
Interrupt Control Register 04
Interrupt Control Register 05
Interrupt Control Register 06
Interrupt Control Register 07
Interrupt Control Register 08
Interrupt Control Register 09
Interrupt Control Register 10
Interrupt Control Register 11
Interrupt Control Register 12
Interrupt Control Register 13
Interrupt Control Register 14
Interrupt Control Register 15
Abbreviation Access
Resource name
Initial value
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
Reserved
ENIR1
EIRR1
ELVR1
ELVR1
EISSR
PSCCR
BAPL
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
B1H
B2H
B3H
B4H
B5H
B6H
B7H
Interrupt Control
B8H
B9H
BAH
BBH
BCH
BDH
BEH
BFH
C0H to C9H
CAH
CBH
CCH
CDH
CEH
CFH
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
D8H
D9H
DAH
DBH
External Interrupt Enable Register 1
External Interrupt Source Register 1
External Interrupt Level Register 1
External Interrupt Level Register 1
External Interrupt Source Select Register
PLL/Sub clock Control register
DMA Buffer Address Pointer L
DMA Buffer Address Pointer M
DMA Buffer Address Pointer H
DMA Control Register
R/W
R/W
R/W
R/W
R/W
W
00000000B
XXXXXXXXB
00000000B
00000000B
00000000B
XXXX0000B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
00000000B
00000000B
00001000B
External Interrupt 1
PLL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W,R/W
W,R/W
R/W
R,R/W
BAPM
BAPH
DMACS
IOAL
DMA
I/O Register Address Pointer L
I/O Register Address Pointer H
Data Counter L
IOAH
DCTL
Data Counter H
DCTH
SMR2
SCR2
Serial Mode Register 2
Serial Control Register 2
Reception/Transmission Data Register 2
Serial Status Register 2
RDR2/TDR2
SSR2
UART2
R,W,
R/W
DCH
Extended Communication Control Register 2
ECCR2
000000XXB
DDH
DEH
Extended Status/Control Register 2
Baud Rate Generator Register 20
Baud Rate Generator Register 21
ESCR2
BGR20
BGR21
Reserved
R/W
R/W
R/W
00000100B
00000000B
00000000B
DFH
E0H to EFH
(Continued)
Document Number: 002-07872 Rev. *A
Page 35 of 83
MB90350 Series
Address
Register
Abbreviation Access
Resource name
Initial value
F0H to FFH
External area
7900H to
7907H
Reserved
7908H
7909H
790AH
790BH
790CH
790DH
790EH
790FH
7910H
7911H
7912H
7913H
7914H
7915H
7916H
7917H
7918H
7919H
791AH
791BH
791CH
791DH
791EH
791FH
7920H
7921H
7922H
7923H
Reload Register L4
PRLL4
PRLH4
PRLL5
PRLH5
PRLL6
PRLH6
PRLL7
PRLH7
PRLL8
PRLH8
PRLL9
PRLH9
PRLLA
PRLHA
PRLLB
PRLHB
PRLLC
PRLHC
PRLLD
PRLHD
PRLLE
PRLHE
PRLLF
PRLHF
IPCP0
IPCP0
IPCP1
IPCP1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
16-bit Programmable
Pulse
Reload Register H4
Reload Register L5
Reload Register H5
Reload Register L6
Reload Register H6
Reload Register L7
Reload Register H7
Reload Register L8
Reload Register H8
Reload Register L9
Reload Register H9
Reload Register LA
Reload Register HA
Reload Register LB
Reload Register HB
Reload Register LC
Reload Register HC
Reload Register LD
Reload Register HD
Reload Register LE
Reload Register HE
Reload Register LF
Reload Register HF
Input Capture Register 0
Input Capture Register 0
Input Capture Register 1
Input Capture Register 1
Generator 4/5
16-bit Programmable
Pulse
Generator 6/7
16-bit Programmable
Pulse
Generator 8/9
16-bit Programmable
Pulse
Generator A/B
16-bit Programmable
Pulse
Generator C/D
16-bit Programmable
Pulse
Generator E/F
R
Input Capture 0/1
Input Capture 4/5
R
R
7924H to
7927H
Reserved
7928H
7929H
792AH
792BH
Input Capture Register 4
Input Capture Register 4
Input Capture Register 5
Input Capture Register 5
IPCP4
IPCP4
IPCP5
IPCP5
R
R
R
R
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
Document Number: 002-07872 Rev. *A
Page 36 of 83
MB90350 Series
Address
792CH
792DH
792EH
792FH
Register
Input Capture Register 6
Abbreviation Access
Resource name
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
IPCP6
IPCP6
IPCP7
IPCP7
R
R
R
R
Input Capture Register 6
Input Capture Register 7
Input Capture Register 7
Input Capture 6/7
7930H to
7937H
Reserved
7938H
7939H
793AH
793BH
793CH
793DH
793EH
793FH
7940H
7941H
7942H
7943H
7944H
7945H
7946H
7947H
7948H
7949H
794AH
794BH
794CH
794DH
794EH
794FH
7950H
7951H
7952H
7953H
Output Compare Register 4
Output Compare Register 4
Output Compare Register 5
Output Compare Register 5
Output Compare Register 6
Output Compare Register 6
Output Compare Register 7
Output Compare Register 7
Timer Data Register 0
OCCP4
OCCP4
OCCP5
OCCP5
OCCP6
OCCP6
OCCP7
OCCP7
TCDT0
TCDT0
TCCSL0
TCCSH0
TCDT1
TCDT1
TCCSL1
TCCSH1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W, R/W
W, R/W
R/W
R,R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
Output Compare 4/5
Output Compare 6/7
I/O Timer 0
Timer Data Register 0
00000000B
Timer Control Status Register 0
Timer Control Status Register 0
Timer Data Register 1
00000000B
0XXXXXXXB
00000000B
Timer Data Register 1
00000000B
I/O Timer 1
Timer Control Status Register 1
Timer Control Status Register 1
00000000B
0XXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
TMR0/TMRL
R0
Timer Register 0/Reload Register 0
Timer Register 1/Reload Register 1
Timer Register 2/Reload Register 2
Timer Register 3/Reload Register 3
16-bit Reload Timer 0
16-bit Reload Timer 1
16-bit Reload Timer 2
16-bit Reload Timer 3
TMR1/TMRL
R1
TMR2/TMRL
R2
TMR3/TMRL
R3
Serial Mode Register 3
SMR3
SCR3
Serial Control Register 3
00000000B
Reception/Transmission Data Register 3
Serial Status Register 3
RDR3/TDR3
SSR3
00000000B
00001000B
UART3
R,W,
R/W
7954H
Extended Communication Control Register 3
ECCR3
000000XXB
7955H
7956H
7957H
Extended Status/Control Register 3
Baud Rate Generator Register 30
Baud Rate Generator Register 31
ESCR3
BGR30
BGR31
R/W
R/W
R/W
00000100B
00000000B
00000000B
7958H,
7959H
Reserved
(Continued)
Document Number: 002-07872 Rev. *A
Page 37 of 83
MB90350 Series
Address
Register
Abbreviation Access
Resource name
Initial value
7960H
Clock Monitor Function Control Register
CSVCR
Reserved
CDMR
Reserved
R, R/W
Clock Monitor
00011100B
7961H to
796DH
796EH
796FH
7970H
7971H
7972H
7973H
7974H
7975H
7976H
7977H
7978H
CAN Direct Mode Register
R/W
CAN Clock Sync
XXXXXXX0B
I2C Bus Status Register 0
I2C Bus Control Register 0
IBSR0
IBCR0
ITBAL0
ITBAH0
ITMKL0
ITMKH0
ISBA0
R
W,R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
11111111B
00111111B
00000000B
01111111B
00000000B
I2C 10-bit Slave Address Register 0
I2C Interface 0
I2C 10-bit Slave Address Mask Register 0
I2C 7-bit Slave Address Register 0
I2C 7-bit Slave Address Mask Register 0
I2C data register 0
ISMK0
IDAR0
7979H,
797AH
Reserved
ICCR0
Reserved
797BH
I2C Clock Control Register 0
R/W
I2C Interface 0
00011111B
797CH to
79A1H
79A2H
79A3H
79A4H
Flash Write Control Register 0
Flash Write Control Register 1
Sector Change Setting Register
FWR0
FWR1
SSR0
R/W
R/W
R/W
00000000B
00000000B
00XXXXX0B
Dual Operation
Flash
79A5H to
79C1H
Reserved
79C2H
Setting Prohibited
Reserved
79C3H to
79DFH
79E0H
79E1H
79E2H
79E3H
79E4H
79E5H
79E6H
79E7H
79E8H
Detect Address Setting Register 0
Detect Address Setting Register 0
Detect Address Setting Register 0
Detect Address Setting Register 1
Detect Address Setting Register 1
Detect Address Setting Register 1
Detect Address Setting Register 2
Detect Address Setting Register 2
Detect Address Setting Register 2
PADR0
PADR0
PADR0
PADR1
PADR1
PADR1
PADR2
PADR2
PADR2
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address Match
Detection 0
79E9H to
79EFH
Reserved
(Continued)
Document Number: 002-07872 Rev. *A
Page 38 of 83
MB90350 Series
(Continued)
Address
79F0H
79F1H
79F2H
79F3H
79F4H
79F5H
79F6H
79F7H
79F8H
Register
Abbreviation Access
Resource name
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Detect Address Setting Register 3
Detect Address Setting Register 3
Detect Address Setting Register 3
Detect Address Setting Register 4
Detect Address Setting Register 4
Detect Address Setting Register 4
Detect Address Setting Register 5
Detect Address Setting Register 5
Detect Address Setting Register 5
PADR3
PADR3
PADR3
PADR4
PADR4
PADR4
PADR5
PADR5
PADR5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address Match
Detection 1
79F9H to
7BFFH
Reserved
7C00H to
7CFFH
Reserved for CAN Interface 1. Refer to “CAN Controllers”
Reserved for CAN Interface 1. Refer to “CAN Controllers”
Reserved
7D00H to
7DFFH
7E00H to
7FFFH
Notes :
■ Initial value of “X” represents unknown value.
■ Any write access to reserved addresses in I/O map should not be performed.Aread access to reserved addresses results reading “X”.
Document Number: 002-07872 Rev. *A
Page 39 of 83
MB90350 Series
13. CAN Controllers
The CAN controller has the following features :
■ Conforms to CAN Specification Version 2.0 Part A and B
❐ Supports transmission/reception in standard frame and extended frame formats
■ Supports transmitting of data frames by receiving remote frames
■ 16 transmitting/receiving message buffers
❐ 29-bit ID and 8-byte data
❐ Multi-level message buffer configuration
■ Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as ID acceptance
mask
❐ Two acceptance mask registers in either standard frame format or extended frame formats
■ Bit rate programmable from 10 Kbps to 2 Mbps (when input clock is at 16 MHz)
List of Control Registers
Address
Register
Abbreviation
BVALR
TREQR
TCANR
TCR
Access
R/W
R/W
W
Initial Value
CAN1
000080H
000081H
000082H
000083H
000084H
000085H
000086H
000087H
000088H
000089H
00008AH
00008BH
00008CH
00008DH
00008EH
00008FH
007D00H
007D01H
007D02H
007D03H
007D04H
007D05H
007D06H
007D07H
007D08H
007D09H
007D0AH
007D0BH
00000000B
00000000B
Message buffer enable register
Transmit request register
Transmit cancel register
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
Transmission complete register
Receive complete register
Remote request receiving register
Receive overrun register
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
RCR
00000000B
00000000B
RRTRR
ROVRR
RIER
00000000B
00000000B
Reception interrupt
enable register
00000000B
00000000B
R/W, W
R/W, R
0XXXX0X1B
00XXX000B
Control status register
Last event indicator register
Receive/transmit error counter
Bit timing register
CSR
000X0000B
XXXXXXXXB
LEIR
R/W
R
00000000B
00000000B
RTEC
11111111B
X1111111B
BTR
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
IDE register
IDER
00000000B
00000000B
Transmit RTR register
TRTRR
(Continued)
Document Number: 002-07872 Rev. *A
Page 40 of 83
MB90350 Series
(Continued)
Address
Register
Abbreviation
RFWTR
Access
R/W
Initial Value
CAN1
007D0CH
007D0DH
007D0EH
007D0FH
007D10H
007D11H
007D12H
007D13H
007D14H
007D15H
007D16H
007D17H
007D18H
007D19H
007D1AH
007D1BH
Remote frame receive waiting
register
XXXXXXXXB
XXXXXXXXB
Transmit interrupt
enable register
00000000B
00000000B
TIER
R/W
XXXXXXXXB
XXXXXXXXB
Acceptance mask
select register
AMSR
AMR0
AMR1
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Acceptance mask register 0
Acceptance mask register 1
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Document Number: 002-07872 Rev. *A
Page 41 of 83
MB90350 Series
List of Message Buffers (ID Registers)
Abbreviation
Address
CAN1
Register
Access
Initial Value
007C00H
to
007C1FH
XXXXXXXXB
to
XXXXXXXXB
General-purpose RAM
ID register 0
—
R/W
007C20H
007C21H
007C22H
007C23H
007C24H
007C25H
007C26H
007C27H
007C28H
007C29H
007C2AH
007C2BH
007C2CH
007C2DH
007C2EH
007C2FH
007C30H
007C31H
007C32H
007C33H
007C34H
007C35H
007C36H
007C37H
007C38H
007C39H
007C3AH
007C3BH
007C3CH
007C3DH
007C3EH
007C3FH
007C40H
007C41H
007C42H
007C43H
XXXXXXXXB
XXXXXXXXB
IDR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID register 1
ID register 2
ID register 3
ID register 4
ID register 5
ID register 6
ID register 7
ID register 8
IDR1
IDR2
IDR3
IDR4
IDR5
IDR6
IDR7
IDR8
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
Document Number: 002-07872 Rev. *A
Page 42 of 83
MB90350 Series
(Continued)
Address
Register
Abbreviation
Access
Initial Value
CAN1
007C44H
007C45H
007C46H
007C47H
007C48H
007C49H
007C4AH
007C4BH
007C4CH
007C4DH
007C4EH
007C4FH
007C50H
007C51H
007C52H
007C53H
007C54H
007C55H
007C56H
007C57H
007C58H
007C59H
007C5AH
007C5BH
007C5CH
007C5DH
007C5EH
007C5FH
XXXXXXXXB
XXXXXXXXB
ID register 9
IDR9
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID register 10
ID register 11
ID register 12
ID register 13
ID register 14
ID register 15
IDR10
IDR11
IDR12
IDR13
IDR14
IDR15
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Document Number: 002-07872 Rev. *A
Page 43 of 83
MB90350 Series
List of Message Buffers (DLC Registers and Data Registers)
Address
CAN1
Register
Abbreviation
DLCR0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
007C60H
007C61H
007C62H
007C63H
007C64H
007C65H
007C66H
007C67H
007C68H
007C69H
007C6AH
007C6BH
007C6CH
007C6DH
007C6EH
007C6FH
007C70H
007C71H
007C72H
007C73H
007C74H
007C75H
007C76H
007C77H
007C78H
007C79H
007C7AH
007C7BH
007C7CH
007C7DH
007C7EH
007C7FH
DLC register 0
DLC register 1
DLC register 2
DLC register 3
DLC register 4
DLC register 5
DLC register 6
DLC register 7
DLC register 8
DLC register 9
DLC register 10
DLC register 11
DLC register 12
DLC register 13
DLC register 14
DLC register 15
DLCR1
DLCR2
DLCR3
DLCR4
DLCR5
DLCR6
DLCR7
DLCR8
DLCR9
DLCR10
DLCR11
DLCR12
DLCR13
DLCR14
DLCR15
007C80H
to
007C87H
XXXXXXXXB
to
XXXXXXXXB
Data register 0
(8 bytes)
DTR0
R/W
(Continued)
Document Number: 002-07872 Rev. *A
Page 44 of 83
MB90350 Series
Address
CAN1
Register
Abbreviation
Access
Initial Value
007C88H
to
007C8FH
XXXXXXXXB
to
XXXXXXXXB
Data register 1
(8 bytes)
DTR1
R/W
007C90H
to
007C97H
XXXXXXXXB
to
XXXXXXXXB
Data register 2
(8 bytes)
DTR2
DTR3
DTR4
DTR5
DTR6
DTR7
DTR8
DTR9
DTR10
DTR11
DTR12
DTR13
DTR14
DTR15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
007C98H
to
007C9FH
XXXXXXXXB
to
XXXXXXXXB
Data register 3
(8 bytes)
007CA0H
to
007CA7H
XXXXXXXXB
to
XXXXXXXXB
Data register 4
(8 bytes)
007CA8H
to
007CAFH
XXXXXXXXB
to
XXXXXXXXB
Data register 5
(8 bytes)
007CB0H
to
007CB7H
XXXXXXXXB
to
XXXXXXXXB
Data register 6
(8 bytes)
007CB8H
to
007CBFH
XXXXXXXXB
to
XXXXXXXXB
Data register 7
(8 bytes)
007CC0H
to
007CC7H
XXXXXXXXB
to
XXXXXXXXB
Data register 8
(8 bytes)
007CC8H
to
007CCFH
XXXXXXXXB
to
XXXXXXXXB
Data register 9
(8 bytes)
007CD0H
to
007CD7H
XXXXXXXXB
to
XXXXXXXXB
Data register 10
(8 bytes)
007CD8H
to
007CDFH
XXXXXXXXB
to
XXXXXXXXB
Data register 11
(8 bytes)
007CE0H
to
007CE7H
XXXXXXXXB
to
XXXXXXXXB
Data register 12
(8 bytes)
007CE8H
to
007CEFH
XXXXXXXXB
to
XXXXXXXXB
Data register 13
(8 bytes)
007CF0H
to
007CF7H
XXXXXXXXB
to
XXXXXXXXB
Data register 14
(8 bytes)
007CF8H
to
007CFFH
XXXXXXXXB
to
XXXXXXXXB
Data register 15
(8 bytes)
Document Number: 002-07872 Rev. *A
Page 45 of 83
MB90350 Series
14. Interrupt Factors, Interrupt Vectors, Interrupt Control Register
EI2OS
Interrupt control
register
Interrupt vector
DMA ch
number
Interrupt cause
corre-
sponding
Number
#08
#09
#10
#11
#12
#13
#14
#15
#16
#17
#18
#19
#20
#21
#22
#23
#24
#25
#26
#27
#28
#29
#30
#31
#32
#33
#34
#35
#36
#37
#38
#39
#40
#41
#42
Address
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
FFFFCCH
FFFFC8H
FFFFC4H
FFFFC0H
FFFFBCH
FFFFB8H
FFFFB4H
FFFFB0H
FFFFACH
FFFFA8H
FFFFA4H
FFFFA0H
FFFF9CH
FFFF98H
FFFF94H
FFFF90H
FFFF8CH
FFFF88H
FFFF84H
FFFF80H
FFFF7CH
FFFF78H
FFFF74H
FFFF70H
FFFF6CH
FFFF68H
FFFF64H
FFFF60H
FFFF5CH
FFFF58H
FFFF54H
Number
Address
Reset
N
N
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
INT9 instruction
Exception
N
Reserved
N
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
0000B9H
0000BAH
0000BBH
0000BCH
0000BDH
0000BEH
0000BFH
Reserved
N
CAN 1 RX / Input Capture 6
CAN 1 TX/NS / Input Capture 7
I2C
Y1
Y1
N
Reserved
N
16-bit Reload Timer 0
16-bit Reload Timer 1
16-bit Reload Timer 2
16-bit Reload Timer 3
PPG 4/5
Y1
Y1
Y1
Y1
N
1
2
—
—
—
—
—
—
3
PPG 6/7
N
PPG 8/9/C/D
N
PPG A/B/E/F
N
Timebase Timer
External Interrupt 8 to 11
Watch Timer
N
Y1
N
—
4
External Interrupt 12 to 15
A/D Converter
Y1
Y1
N
5
I/O Timer 0 / I/O Timer 1
Input Capture 4/5
Output Compare 4/5
Input Capture 0/1
Output Compare 6/7
Reserved
—
6
Y1
Y1
Y1
Y1
N
7
8
9
10
11
12
13
14
15
—
—
Reserved
N
UART 3 RX
Y2
Y1
Y2
Y1
N
UART 3 TX
UART 2 RX
UART 2 TX
Flash Memory
Delayed interrupt
N
Y1 : Usable
Y2 : Usable, with EI2OS stop function
N
: Unusable
Document Number: 002-07872 Rev. *A
Page 46 of 83
MB90350 Series
Notes :
■ The peripheral resources sharing the ICR register have the same interrupt level.
■ When two peripheral resources share the ICR register, only one can use EI2OSat a time.
■ When either of the two peripheral resources sharing the ICR register specifies EI2OS, the other one cannot use interrupts.
Document Number: 002-07872 Rev. *A
Page 47 of 83
MB90350 Series
15. Electrical Characteristics
15.1 Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
VCC
AVCC
AVRH
VI
VSS 0.3 VSS 6.0
VSS 0.3 VSS 6.0
VSS 0.3 VSS 6.0
VSS 0.3 VSS 6.0
VSS 0.3 VSS 6.0
V
2
Power supply voltage*1
V
VCC AVCC
*
V
AVCC ≥ AVRH*2
Input voltage*1
Output voltage*1
V
*3
*3
*5
*5
*4
*4
*4
*4
*4
*4
*4
*4
VO
V
Maximum Clamp Current
ICLAMP
|ICLAMP
IOL
4.0
—
4.0
40
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Total Maximum Clamp Current
“L” level maximum output current
“L” level average output current
“L” level maximum overall output current
“L” level average overall output current
“H” level maximum output current
“H” level average output current
“H” level maximum overall output current
“H” level average overall output current
|
—
15
IOLAV
IOL
IOLAV
IOH
—
4
—
100
50
—
—
15
4
100
50
IOHAV
IOH
IOHAV
—
—
—
MB90F351(S), MB90F352(S)
105 °C < TA ≤ 125 °C,
Normal operation : maximum
frequency 16 MHz
—
—
240
mW
mW
Power consumption
PD
MB90F351(S), MB90F352(S)
40 °C < TA ≤ 105 °C,
Normal operation : maximum
frequency 24 MHz
320
—
320
mW Device other than above
°C
40
40
55
105
125
150
Operating temperature
Storage temperature
TA
°C
°C
*6
TSTG
(Continued)
Document Number: 002-07872 Rev. *A
Page 48 of 83
MB90350 Series
(Continued)
*1: This parameter is based on VSS AVSS 0 V
*2: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the analog inputs
does not exceed AVCC when the power is switched on.
*3: VI and VO should not exceed VCC 0.3 V. V should not exceed the specified ratings. However if the maximum current to/from
I
an input is limited by some means with external components, the I
rating supersedes the V rating.
I
CLAMP
*4: Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45, P50 to P56, P60 to P67
*5: • Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45,
P50 to P56 (for evaluation device : P50 to P55) , P60 to P67
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The B signal should always be applied a limiting resistance placed between the B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the B signal is applied the input current to the microcontroller
pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the B input potential may pass
through the protective diode and increase the potential at the VCC pin, and this may affect other devices.
• Note that if a B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided
from the pins, so that incomplete operation may result.
• Note that if the B input is applied during power-on, the power supply is provided from the pins and the resulting power supply
voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the B input pin open.
• Sample recommended circuits:
■ Input/output equivalent circuits
Protective diode
VCC
Limiting
resistance
P-ch
N-ch
B input (0 V to 16 V)
R
*6 : If used exceeding TA 105 °C, be sure to contact sales for reliability limitations.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in
excess of absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-07872 Rev. *A
Page 49 of 83
MB90350 Series
15.2 Recommended Operating Conditions
(VSS AVSS 0 V)
Value
Typ
Parameter
Symbol
Unit
Remarks
Under normal operation
Min
Max
4.0
5.0
5.5
V
V
Under normal operation, when not using the A/D
converter and not Flash programming.
3.5
5.0
5.5
VCC
,
Power supply voltage
AVCC
4.5
3.0
5.0
—
5.5
5.5
V
V
When External bus is used.
Maintains RAM data in stop mode
Use a ceramic capacitor or capacitor of better AC
μF characteristics. Bypass capacitor at the VCC pin
Smooth capacitor
CS
TA
0.1
—
1.0
should be greater than this capacitor.
40
40
—
—
105
125
°C MB90F352(S) fCP ≤ 24MHz
Operating temperature
*, MB90F352(S) fCP ≤ 16MHz,
Devices with A-suffix
°C
* : If used exceeding TA 105 °C, be sure to contact sales for reliability limitations.
■ C Pin Connection Diagram
C
CS
Operation guaranteed range
24
16
MB90F351(S),
MB90F352(S)
Device other
than above
− 40
+105
+125
Operation temperature TA (°C)
WARNING:
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor
device. All of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their representatives beforehand.
Document Number: 002-07872 Rev. *A
Page 50 of 83
MB90350 Series
15.3 DC Characteristics
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
Value
Parameter Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
Pin inputs if CMOS
hysteresis input levels are
selected (except P12, P15,
P44, P45, P50)
VIHS
—
—
0.8 VCC
—
VCC 0.3
V
Pin inputs if
AUTOMOTIVE input
levels are selected
VIHA
—
—
0.8 VCC
—
VCC 0.3
V
Input H
voltage
(At VCC
5 V 10%)
Pin inputs if TTL input levels
are selected
VIHT
VIHS
—
—
—
—
2.0
—
—
VCC 0.3
VCC 0.3
V
V
P12, P15, P50 inputs if CMOS
input levels are selected
0.7 VCC
P44, P45 inputs if CMOS
hysteresis input levels are
selected
VIHI
—
—
0.7 VCC
—
VCC 0.3
V
RST input pin (CMOS
hysteresis)
VIHR
VIHM
—
—
—
—
0.8 VCC
—
—
VCC 0.3
VCC 0.3
V
V
VCC 0.3
MD input pin
Pin inputs if CMOS
hysteresis input levels are
selected (except P12, P15,
P44, P45, P50)
VILS
—
—
—
—
VSS 0.3
VSS 0.3
—
—
0.2 VCC
V
V
Pin inputs if
AUTOMOTIVE input
levels are selected
VILA
0.5 VCC
Input L
voltage
(At VCC
5 V 10%)
Pin inputs if TTL
input levels are selected
VILT
VILS
—
—
—
—
VSS 0.3
VSS 0.3
—
—
0.8
V
V
P12, P15, P50 inputs if CMOS
input levels are selected
0.3 VCC
P44, P45 inputs if CMOS
hysteresis input levels are
selected
VILI
—
—
VSS 0.3
—
0.3 VCC
V
RST input pin (CMOS
hysteresis)
VILR
VILM
VOH
—
—
—
—
VSS 0.3
VSS 0.3
VCC 0.5
—
—
—
0.2 VCC
VSS 0.3
—
V
V
V
MD input pin
Output H
voltage
Normal
outputs
VCC 4.5 V,
IOH 4.0 mA
Output H
voltage
I2C current VCC 4.5 V,
VOHI
VCC 0.5
—
—
V
outputs
IOH 3.0 mA
(Continued)
Document Number: 002-07872 Rev. *A
Page 51 of 83
MB90350 Series
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
Value
Parameter
Output L
Symbol
Pin
Normal
outputs
I2C current
outputs
Condition
Unit
Remarks
Min
Typ
Max
VCC 4.5 V,
VOL
VOLI
IIL
—
—
0.4
V
V
voltage
IOL 4.0 mA
Output L
voltage
VCC 4.5 V,
—
—
—
0.4
1
IOL 3.0 mA
Input leak
current
VCC 5.5 V,
—
1
µA
V
SS<VI<VCC
P00 to P07,
P10 to P17,
P20 to P25,
P30 to P37,
RST
Pull-up
resistance
RUP
—
—
25
50
100
kΩ
Pull-down
resistance
Except Flash
memory devices
RDOWN
MD2
25
—
50
48
100
60
kΩ
VCC 5.0 V,
Internal frequency : 24 MHz,
At normal operation.
mA
VCC 5.0 V,
Flash memory
devices
ICC
Internal frequency : 24 MHz,
At writing FLASH memory.
—
—
—
53
58
25
65
70
35
mA
mA
mA
VCC 5.0 V,
Flash memory
devices
Internal frequency : 24 MHz,
At erasing FLASH memory.
VCC 5.0 V,
ICCS
Internal frequency : 24 MHz,
At Sleep mode.
Devices
mA without
“T”-suffix
—
—
0.3
0.4
0.8
1.0
VCC 5.0 V,
ICTS
Internal frequency : 2 MHz,
At Main Timer mode
Power supply
current
VCC
Devices
mA
with “T”-suffix
VCC 5.0 V,
ICTSPLL
Internal frequency : 24 MHz,
At PLL Timer mode,
—
4
7
mA
6
external frequency 4 MHz
MB90F351
MB90F352
MB90F351A
MB90F352A
MB90F356A
MB90F357A
MB90351A
MB90352A
MB90356A
MB90357A
VCC = 5.0 V,
Internal frequency: 8 kHz,
During stopping clock
monitor function,
At sub clock operation
TA = 25C
ICCL
—
70
140
μA
(Continued)
Document Number: 002-07872 Rev. *A
Page 52 of 83
MB90350 Series
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
Value
Parameter
Symbol
Pin
Condition
VCC = 5.0 V,
Unit
Remarks
Min
Typ
Max
Internal frequency: 8 kHz,
During operating clock
monitor function,
MB90F356A
MB90F357A
MB90356A
MB90357A
—
100
200
µA
At sub clock operation
TA = 25C
VCC = 5.0 V,
MB90F356AS
MB90F357AS
MB90356AS
MB90357AS
Internal CR oscillation/
4 division,
At sub clock operation
TA = 25C
—
—
100
120
200
240
µA
µA
MB90F351TA
MB90F352TA
MB90F356TA
MB90F357TA
MB90351TA
MB90352TA
MB90356TA
MB90357TA
VCC = 5.0 V,
Internal frequency: 8 kHz,
During stopping clock
monitor function,
At sub clock operation
TA = 25C
ICCL
Power supply
current
V
CC = 5.0 V,
VCC
Internal frequency: 8 kHz,
During operating clock
monitor function,
MB90F356TA
MB90F357TA
MB90356TA
MB90357TA
—
—
150
150
300
300
µA
µA
At sub clock operation
TA = 25C
VCC = 5.0 V,
MB90F356TAS
MB90F357TAS
MB90356TAS
MB90357TAS
Internal CR oscillation/
4 division,
At sub clock operation
TA = 25C
MB90F351
MB90F352
MB90F351A
MB90F352A
MB90F356A
MB90F357A
MB90351A
MB90352A
MB90356A
MB90357A
VCC = 5.0 V,
Internal frequency: 8 kHz,
During stopping clock
monitor function,
At sub sleep
ICCLS
—
20
50
μA
TA = 25C
(Continued)
Document Number: 002-07872 Rev. *A
Page 53 of 83
MB90350 Series
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
Value
Parameter
Symbol
Pin
Condition
VCC = 5.0 V,
Unit
Remarks
Min
Typ
Max
Internal frequency: 8 kHz,
During operating clock monitor
function,
MB90F356A
MB90F357A
MB90356A
MB90357A
—
60
200
μA
At sub sleep
TA = 25C
V
CC = 5.0 V,
MB90F356AS
MB90F357AS
MB90356AS
MB90357AS
Internal CR oscillation/
4 division,
At sub sleep
TA = 25C
—
—
60
70
200
150
μA
μA
MB90F351TA
MB90F352TA
MB90F356TA
MB90F357TA
MB90351TA
MB90352TA
MB90356TA
MB90357TA
VCC = 5.0 V,
Internal frequency: 8 kHz,
During stopping clock
monitor function,
At sub sleep
ICCLS
TA = 25C
Power supply
current
V
CC = 5.0 V,
VCC
Internal frequency: 8 kHz,
During operating clock
monitor function,
At sub sleep
MB90F356TA
MB90F357TA
MB90356TA
MB90357TA
—
—
110
110
300
300
μA
μA
TA = 25C
VCC = 5.0 V,
MB90F356TAS
MB90F357TAS
MB90356TAS
MB90357TAS
Internal CR oscillation/
4 division,
At sub sleep
TA = 25C
MB90F351
MB90F352
MB90F351A
MB90F352A
MB90F356A
MB90F357A
MB90351A
MB90352A
MB90356A
MB90357A
VCC = 5.0 V,
Internal frequency: 8 kHz,
During stopping clock
monitor function,
At watch mode
ICCT
—
10
35
μA
TA = 25C
(Continued)
Document Number: 002-07872 Rev. *A
Page 54 of 83
MB90350 Series
(Continued)
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
Value
Parameter
Symbol
Pin
Condition
VCC = 5.0 V,
Unit
Remarks
Min
Typ
Max
Internal frequency: 8 kHz,
During operating clock monitor
function,
MB90F356A
MB90F357A
MB90356A
MB90357A
—
25
150
μA
At watch mode
TA = 25C
V
CC = 5.0 V,
MB90F356AS
MB90F357AS
MB90356AS
MB90357AS
Internal CR oscillation/
4 division,
At watch mode
TA = 25C
—
—
25
60
150
140
μA
μA
MB90F351TA
MB90F352TA
MB90F356TA
MB90F357TA
MB90351TA
MB90352TA
MB90356TA
MB90357TA
VCC = 5.0 V,
Internal frequency: 8 kHz,
During stopping clock
monitor function,
At watch mode
ICCT
Power supply
current
TA = 25C
VCC
V
CC = 5.0 V,
Internal frequency: 8 kHz,
During operating clock monitor
function,
MB90F356TA
MB90F357TA
MB90356TA
MB90357TA
—
80
250
μA
μA
At watch mode
TA = 25C
VCC = 5.0 V,
MB90F356TAS
MB90F357TAS
MB90356TAS
MB90357TAS
Internal CR oscillation/
4 division,
At watch mode
TA = 25C
—
—
80
7
250
25
Devices
μA without
VCC 5.0 V,
At Stop mode,
TA 25C
“T”-suffix
ICCH
Devices
with “T”-suffix
—
—
60
5
130
15
μA
Other than C, AVCC, AVSS
AVRH, VCC, VSS
,
Input capacity
CIN
—
pF
,
Document Number: 002-07872 Rev. *A
Page 55 of 83
MB90350 Series
15.4 AC Characteristics
15.4.1 Clock Timing
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
Value
Parameter
Symbol
Pin
Unit
Remarks
1/2 (at PLL stop)
Min
Typ
Max
3
—
16
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
When using an oscillation circuit
1 multiplied PLL
When using an oscillation circuit
4
4
—
—
—
—
—
—
—
—
—
—
—
16
12
8
2 multiplied PLL
When using an oscillation circuit
X0, X1
3 multiplied PLL
When using an oscillation circuit
4
4 multiplied PLL
When using an oscillation circuit
4
6
6 multiplied PLL
When using an oscillation circuit
—
3
4
fC
Clock frequency
1/2 (at PLL stop),
When using an external clock
24
24
12
8
1 multiplied PLL
When using an external clock
4
2 multiplied PLL
When using an external clock
4
X0
3 multiplied PLL
When using an external clock
4
4 multiplied PLL
When using an external clock
4
6
6 multiplied PLL
When using an external clock
—
4
fCL
X0A, X1A
X0, X1
X0
—
62.5
41.67
10
32.768
—
100
333
333
—
kHz
ns
When using an oscillation circuit
When using an external clock
tCYL
Clock cycle time
—
ns
tCYLL
X0A, X1A
X0
30.5
—
s
ns
PWH, PWL
10
—
Input clock pulse width
Duty ratio is about 30% to 70%.
When using an external clock
P
WHL, PWLL
X0A
5
15.2
—
s
Input clock rise and fall
time
t
CR, tCF
X0
—
—
5
ns
(Continued)
Document Number: 002-07872 Rev. *A
Page 56 of 83
MB90350 Series
(Continued)
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Typ
Max
MB90F352/(S), MB90F351/(S)
When using main clock
(TA ≤ 105 °C)
MB90F352/(S), MB90F351/(S)
When using main clock
(TA ≤ 125 °C)
24
1.5
—
MHz
MHz
Internal operating clock
frequency
(machine clock)
fCP
fCPL
tCP
—
—
—
—
16
Device other than above,
When using main clock
1.5
—
—
24
50
8.192
kHz When using sub clock
MB90F352/(S), MB90F351/(S)
When using main clock
(TA ≤ 105 °C)
MB90F352/(S), MB90F351/(S)
41.67
62.5
—
666
ns
Internal operating clock
cycle time
(machine clock)
When using main clock
(TA ≤ 125 °C)
Device other than above,
When using main clock
41.67
20
—
666
—
ns
tCPL
122.1
s
When using sub clock
■ Clock Timing
t
CYL
0.8 VCC
X0
0.2 VCC
P
WH
PWL
t
CF
tCR
t
CYLL
0.8 VCC
0.2 VCC
X0A
P
WHL
PWLL
t
CF
tCR
Document Number: 002-07872 Rev. *A
Page 57 of 83
MB90350 Series
■ PLL guaranteed operation range
Guaranteed operation range
Guaranteed PLL operation range (CS2=1)
5.5
4.5
Guaranteed A/D converter
operation range
3.5
Guaranteed PLL operation range (CS2=0)
1.5
4
8
20
24
Internal clock fCP (MHz)
Guaranteed operation range of MB90350 series
CS2(bit0 of PSCCR register) = 0
Guaranteed oscillation frequency range
4 multiplied 3 multiplied 2 multiplied
(CS=11) (CS=10) (CS=01)
1 multiplied
(CS=00)
20
16
12
8
×1/2
(PLL off)
4.0
1.5
3
4
8
12
20
24
16
External clock fC (MHz) *1
CS2(bit0 of PSCCR register) = 1
Guaranteed oscillation frequency range
6 multiplied 4 multiplied
(CS=10) (CS=01)
2 multiplied
(CS=00)
24
16
12
8
×1/2
(PLL off)
4.0
1.5
3
4
8
12
24
16
External clock fC (MHz) *2
*1 : Guaranteed 1 multiplied PLL operation range is 4.0 MHz to 20 MHz.
*2 : When using crystal oscillator or ceramic oscillator, the maximum clock frequency is 16 MHz.
External clock frequency and internal operation clock frequency
Document Number: 002-07872 Rev. *A
Page 58 of 83
MB90350 Series
15.4.2 Reset Standby Input
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Max
500
—
ns
Under normal operation
In Stop mode, Sub Clock
mode, Sub Sleep mode and
Watch mode
Oscillation time of oscillator*
—
—
μs
μs
Reset input time
tRSTL
RST
100 μs
In Main timer mode and PLL
timer mode
100
* : Oscillation time of oscillator is the time that the amplitude reaches 90%.
In the crystal oscillator, the oscillation time is between several ms to tens of ms. In FAR / ceramic oscillators, the oscillation time
is between hundreds of μs to several ms. With an external clock, the oscillation time is 0 ms.
Under normal operation:
tRSTL
RST
0.2 VCC
0.2 VCC
In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode:
tRSTL
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal operation
clock
100 μs
Oscillation time
of oscillator
Oscillation stabilization
waiting time
Instruction execution
Internal reset
Document Number: 002-07872 Rev. *A
Page 59 of 83
MB90350 Series
15.4.3 Power On Reset
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
0.05
1
Max
30
Power on rise time
Power off time
tR
VCC
VCC
ms
ms
—
tOFF
—
Due to repetitive operation
tR
2.7 V
VCC
0.2 V
0.2 V
0.2 V
tOFF
If you change the power supply voltage too rapidly, a power on reset may occur.
We recommend that you start up smoothly by restraining voltages when changing
the power supply voltage during operation, as shown in the figure below. Perform
while not using the PLL clock. However, if voltage drops are within 1 V/s, you can
operate while using the PLL clock.
VCC
We recommend the slope for
a rise of 50 mV/ms maximum.
3 V
Holds RAM data
VSS
15.4.4 Clock Output Timing
(TA 40 °C to 105 °C, VCC 5.0 V 10%, VSS 0.0 V, fCP ≤ 24 MHz)
Value
Min
Parameter
Cycle time
CLK ↑ → CLK ↓
Symbol
Pin
CLK
CLK
Condition
Unit
Remarks
Max
—
62.5
41.67
20
ns
ns
ns
ns
fCP 16 MHz
fCP 24 MHz
fCP 16 MHz
fCP 24 MHz
tCYC
—
—
—
—
tCHCL
13
—
tCYC
tCHCL
2.4 V
2.4 V
CLK
0.8 V
Document Number: 002-07872 Rev. *A
Page 60 of 83
MB90350 Series
15.4.5 Bus Timing (Read)
(TA = –40C to +105C, VCC = 5.0 V 10 %, VSS = 0.0 V, fCP ≤ 24 MHz)
Value
Parameter
Symbol
Pin
Condition
Unit Remarks
Min
Max
ALE pulse width
tLHLL
ALE
tCP/2 10
—
ns
ALE, A21 to
A16, AD15 to
AD00
Valid address → ALE time
ALE → Address valid time
Valid address → RD time
tAVLL
t
CP/2 20
CP/2 15
tCP 15
—
—
—
—
ns
ns
ns
ALE, AD15 to
AD00
tLLAX
t
A21 toA16,
tAVRL AD15 to AD00,
RD
A21 to A16,
tAVDV
Valid address → Valid data input
RD pulse width
5 tCP/2 60
ns
ns
AD15 to AD00
tRLRH RD
(n*+3/2) tCP 20
—
—
RD, AD15 to
RD → Valid data input
tRLDV
AD00
—
(n*+3/2) tCP 50 ns
RD, AD15 to
RD → Data hold time
tRHDX
AD00
0
—
ns
RD → ALE time
tRHLH RD, ALE
tCP/2 15
tCP/2 10
—
—
ns
ns
RD → Address valid time
tRHAX RD, A21 to A16
A21 to A16,
tAVCH AD15 to AD00,
CLK
Valid address → CLK time
tCP/2 16
—
ns
RD → CLK time
ALE → RD time
tRLCH RD, CLK
tCP/2 15
tCP/2 15
—
—
ns
ns
tLLRL
ALE, RD
* : n: number of ready cycles
Document Number: 002-07872 Rev. *A
Page 61 of 83
MB90350 Series
For 1 cycle of auto-ready
tRLCH
tAVCH
2.4 V
2.4 V
CLK
tLLAX
tAVLL
tLHLL
tRHLH
2.4 V
2.4 V
0.8 V
2.4 V
ALE
RD
tAVRL
tRLRH
2.4 V
0.8 V
tLLRL
tRHAX
2.4 V
0.8 V
2.4 V
0.8 V
A21 to A16
tRLDV
tRHDX
tAVDV
2.4 V
0.8 V
VIH
2.4 V
0.8 V
VIH
VIL
AD15 to AD00
Address
Read data
VIL
Document Number: 002-07872 Rev. *A
Page 62 of 83
MB90350 Series
15.4.6 Bus Timing (Write)
(TA = –40C to +105C, VCC = 5.0 V 10 %, VSS = 0.0 V, fCP ≤ 24 MHz)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
—
A21 to A16, AD15
to AD00, WR
Valid address → WR time
WR pulse width
tAVWL
tCP15
ns
ns
ns
tWLWH WR
AD15 to AD00,
(n*+3/2)tCP 20
(n*+3/2)tCP 20
—
Valid data output → WR time
tDVWH
—
WR
—
AD15 to AD00,
WR
WR → Data hold time
tWHDX
15
—
ns
WR → Address valid time
WR → ALE time
tWHAX A21 to A16, WR
tWHLH WR, ALE
tCP/2 10
tCP/2 15
tCP/2 15
—
—
—
ns
ns
ns
WR → CLK time
tWLCH WR, CLK
* : n: Number of ready cycles
For 1 cycle of auto-ready
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tAVWL
tWLWH
2.4 V
WR (WRL, WRH)
0.8 V
tWHAX
2.4 V
0.8 V
2.4 V
0.8 V
A21 to A16
tDVWH
tWHDX
2.4 V
0.8 V
2.4 V
2.4 V
0.8 V
AD15 to AD00
Address
Write data
0.8 V
Document Number: 002-07872 Rev. *A
Page 63 of 83
MB90350 Series
15.4.7 Ready Input Timing
(TA = –40C to +105C, VCC = 5.0 V 10 %, VSS = 0.0 V, fCP ≤ 24 MHz)
Value
Parameter
Symbol
Pin
Condition
Units
Remarks
Min
45
32
0
Max
—
ns
ns
ns
fCP 16 MHz
fCP 24 MHz
RDY set-up time
RDY hold time
tRYHS
tRYHH
RDY
RDY
—
—
—
Note : If the RDY set-up time is insufficient, use the auto-ready function.
2.4 V
CLK
ALE
RD/WR
tRYHS
tRYHH
RDY
VIH
VIH
(When WAIT is not used.)
RDY
(When WAIT is used.)
VIL
Document Number: 002-07872 Rev. *A
Page 64 of 83
MB90350 Series
15.4.8 Hold Timing
(TA = –40C to +105C, VCC = 5.0 V 10 %, VSS = 0.0 V, fCP ≤ 24 MHz)
Value
Parameter
Symbol
Pin
Condition
Units
Remarks
Min
30
Max
tCP
Pin floating → HAK time
tXHAL
HAK
HAK
ns
ns
—
HAK time → Pin valid time tHAHV
tCP
2 tCP
Note : There is more than 1 machine cycle from when HRQ pin reads in until the HAK is changed.
2.4 V
HAK
0.8 V
tHAHV
tXHAL
Hi-Z
2.4 V
0.8 V
2.4 V
0.8 V
Each pin
Document Number: 002-07872 Rev. *A
Page 65 of 83
MB90350 Series
15.4.9 UART 2/3
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit Remarks
Min
Max
Serial clock cycle time
tSCYC
tSLOV
SCK2, SCK3
8 tCP
*
—
ns
ns
SCK2, SCK3,
SOT2, SOT3
SCK ↓ → SOT delay time
80
100
60
80
—
Internal shift clock
CL
mode8o0uptpFut p1inTsTaLre
SCK2, SCK3,
SIN2, SIN3
Valid SIN → SCK ↑
tIVSH
ns
ns
SCK2, SCK3,
SIN2, SIN3
SCK ↑ → Valid SIN hold time
tSHIX
tSHSL
tSLSH
—
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK2, SCK3
SCK2, SCK3
4 tCP
4 tCP
—
—
ns
ns
SCK2, SCK3,
SOT2, SOT3
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
tSLOV
tIVSH
tSHIX
External shift clock
—
60
60
150
—
ns
ns
ns
CL
mode8o0uptpFut p1inTsTaLre
SCK2, SCK3,
SIN2, SIN3
SCK2, SCK3,
SIN2, SIN3
SCK ↑ → Valid SIN hold time
—
* : Refer to “ (1) Clock timing” rating for tCP (internal operating clock cycle time).
Notes :
■ AC characteristic in CLK synchronized mode.
■ CL is load capacity value of pins when testing.
■ Internal Shift Clock Mode
tSCYC
2.4 V
SCK
SOT
0.8 V
0.8 V
tSLOV
2.4 V
0.8 V
tIVSH
tSHIX
VIH
VIL
VIH
VIL
SIN
Document Number: 002-07872 Rev. *A
Page 66 of 83
MB90350 Series
■ External Shift Clock Mode
tSLSH
tSHSL
VIH
VIH
SCK
VIL
VIL
tSLOV
2.4 V
0.8 V
SOT
SIN
tIVSH
tSHIX
VIH
VIL
VIH
VIL
15.4.10 Trigger Input Timing
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: T 40 °C to 125 °C, VCC 5.0 V 10%, f ≤ 24 MHz, VSS AVSS 0 V)
A
CP
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
INT8 to INT15,
INT9R to INT11R,
ADTG
tTRGH
tTRGL
Input pulse width
—
5 tCP
—
ns
VIH
VIH
INT8 to INT15,
INT9R to INT11R,
ADTG
VIL
VIL
tTRGH
tTRGL
Document Number: 002-07872 Rev. *A
Page 67 of 83
MB90350 Series
15.4.11 Timer Related Resource Input Timing
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: T 40 °C to 125 °C, VCC 5.0 V 10%, f ≤ 24 MHz, VSS AVSS 0 V)
A
CP
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
tTIWH
tTIWL
TIN1, TIN3,
IN0, IN1,
IN4 to IN7
Input pulse width
—
4 tCP
—
ns
VIH
VIH
TIN1, TIN3,
IN0, IN1,
VIL
VIL
IN4 to IN7
tTIWH
tTIWL
15.4.12 Timer Related Resource Output Timing
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: T 40 °C to 125 °C, VCC 5.0 V 10%, f ≤ 24 MHz, VSS AVSS 0 V)
A
CP
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
TOT1, TOT3,
PPG4, PPG6,
PPG8 to PPGF
CLK → TOUT change time
tTO
—
30
—
ns
2.4 V
CLK
2.4 V
0.8 V
TOT1, TOT3,
PPG4, PPG6
PPG8 to PPGF
tTO
Document Number: 002-07872 Rev. *A
Page 68 of 83
MB90350 Series
15.4.13 I2C Timing
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC AVCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC AVCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: T 40 °C to 125 °C, VCC AVCC 5.0 V 10%, f ≤ 24 MHz, VSS AVSS 0 V)
A
CP
Standard-mode
Fast-mode*4
Parameter
Symbol
Condition
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
0
100
0
400
kHz
Hold time for (repeated) START condition
SDA↓→SCL↓
tHDSTA
4.0
—
0.6
—
μs
“L” width of the SCL clock
“H” width of the SCL clock
tLOW
tHIGH
4.7
4.0
—
—
1.3
0.6
—
—
μs
μs
Set-up time for a repeated START condition
SCL↑→SDA↓
tSUSTA
tHDDAT
tSUDAT
tSUSTO
tBUS
4.7
0
—
3.45*2
—
0.6
0
—
0.9*3
—
μs
μs
ns
μs
μs
R 1.7 kΩ,
C 50 pF*1
Data hold time
SCL↓→SDA↓↑
Data set-up time
SDA↓↑→SCL↑
250*5
4.0
100*5
0.6
Set-up time for STOP condition
SCL↑→SDA↑
—
—
Bus free time between STOP condition and START
condition
4.7
—
1.3
—
*1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHDDAT has only to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C -bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must then be met.
*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
*5 : Refer to “Note of SDA, SCL set-up time”.
■ Note of SDA, SCL set-up time
SDA
Input data set-up time
SCL
6 tcp
Document Number: 002-07872 Rev. *A
Page 69 of 83
MB90350 Series
Note : Theratingoftheinputdataset-uptimeinthedeviceconnectedtothebuscannotbesatisfieddependingontheloadcapacitance
or pull-up resistor.
Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be satisfied.
■ Timing definition
SDA
tBUF
tHDSTA
tSUDAT
tLOW
SCL
tHDSTA
tSUSTA
tHIGH
tSUSTO
tHDDAT
fSCL
Document Number: 002-07872 Rev. *A
Page 70 of 83
MB90350 Series
15.5 A/D Converter
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, 3.0 V ≤ AVRH, VCC AVCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, 3.0 V ≤ AVRH, VCC AVCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(
Device other than above: TA
40 °C to
125 °C
,
3.0 V ≤ AVRH, VCC AVCC 5.0 V
10%
,
f
≤ 24 MHz, VSS AVSS 0 V
)
CP
Value
Parameter
Resolution
Symbol
Pin
Unit
Remarks
Min
—
Typ
—
Max
—
—
—
—
—
—
10
bit
Total error
—
—
3.0
2.5
LSB
LSB
Nonlinearity error
—
—
Differential
nonlinearity error
—
—
—
—
1.9
LSB
V
Zero reading
voltage
AVSS
1.5 LSB
AVSS
0.5 LSB
AVSS
2.5 LSB
VOT
VFST
AN0 to AN14
AN0 to AN14
Full scale reading
voltage
AVRH
AVRH
AVRH
V
3.5 LSB
1.5 LSB
0.5 LSB
1.0
2.0
0.5
1.2
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
Compare time
Sampling time
—
—
—
—
—
—
16,500
¥
s
s
Analog port input
current
IAIN
VAIN
—
AN0 to AN14
AN0 to AN14
AVRH
0.3
AVSS
—
—
—
+0.3
AVRH
AVCC
A
V
Analog input
voltage range
Reference
voltage range
AVSS 2.7
V
IA
AVCC
AVCC
—
—
3.5
—
7.5
5
mA
Power supply
current
IAH
μA
*
*
IR
IRH
—
AVRH
AVRH
—
—
—
600
—
900
5
μA
μA
Reference
voltage supply
current
Offset between
input channels
AN0 to AN14
—
4
LSB
* : If A/D converter is not operating, a current when CPU is stopped is applicable (VCC AVCC AVRH 5.0 V) .
Document Number: 002-07872 Rev. *A
Page 71 of 83
MB90350 Series
Notes on A/D Converter Section
■ About the external impedance of the analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage
charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore to satisfy the A/D conversion precision standard, consider the relationship between the external
impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external
impedance so that the sampling time is longer than the minimum value. Also if the sampling time cannot be sufficient, connect a
capacitor of about 0.1 μF to the analog input pin.
· Analog input equivalence circuit
R
Analog input
Comparator
C
ON at sampling
MB90F352(S), MB90F351A(S), MB90F352A(S), MB90F351TA(S), MB90F352TA(S),
MB90F356A(S), MB90F357A(S), MB90F356TA(S), MB90F357TA(S),
R
C
4.5 V AVCC 5.5 V 2.0 kΩ (Max) 16.0 pF (Max)
4.0 V AVCC 4.5 V 8.2 kΩ (Max) 16.0 pF (Max)
MB90V340A-101/102/103/104, MB90351A(S), MB90352A(S), MB90351TA(S), MB90352TA(S),
MB90356A(S), MB90357A(S), MB90356TA(S), MB90357TA(S),
R
C
4.5 V AVCC 5.5 V 2.0 kΩ (Max) 14.4 pF (Max)
4.0 V AVCC 4.5 V 8.2 kΩ (Max) 14.4 pF (Max)
Note : The value is reference value.
Document Number: 002-07872 Rev. *A
Page 72 of 83
MB90350 Series
■ Flash memory device
· Relation between External impedance and minimum sampling time
(MB90F352(S), MB90F351A(S), MB90F352A(S), MB90F351TA(S), MB90F352TA(S), MB90F356A(S),
MB90F357A(S), MB90F356TA(S), MB90F357TA(S))
[External impedance = 0 kΩ to 100 kΩ]
[External impedance = 0 kΩ to 20 kΩ]
4.5 V AVCC 5.5 V
4.5 V AVCC 5.5 V
100
90
80
70
60
50
40
30
20
10
0
20
18
16
14
12
10
8
4.0 V AVCC 4.5 V
4.0 V AVCC 4.5 V
6
4
2
0
0
5
10
15
20
25
30
35
0
1
2
3
4
5
6
7
8
Minimum sampling time [μs]
Minimum sampling time [μs]
■ MASK ROM device
· Relation between External impedance and minimum sampling time
(MB90V340A-101/102/103/104, MB90351A(S), MB90352A(S), MB90351TA(S), MB90352TA(S),
MB90356A(S), MB90357A(S), MB90356TA(S), MB90357TA(S))
[External impedance = 0 kΩ to 100 kΩ]
[External impedance = 0 kΩ to 20kΩ]
4.5 V AVCC 5.5 V
4.5 V AVCC 5.5 V
100
90
80
70
60
50
40
30
20
10
0
20
18
16
14
12
10
8
4.0 V AVCC 4.5 V
4.0 V AVCC 4.5 V
6
4
2
0
0
5
10
15
20
25
30
35
0
1
2
3
4
5
6
7
8
Minimum sampling time [μs]
Minimum sampling time [μs]
■ About the error
Values of relative errors grow larger, as |AVRH AVSS| becomes smaller.
Document Number: 002-07872 Rev. *A
Page 73 of 83
MB90350 Series
15.6 Definition of A/D Converter Terms
Resolution
: Analog variation that is recognized by an A/D converter.
: Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” ) and full-scale
transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion characteristics.
Non linearity error
Differential
linearity error
: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
Difference between an actual value and a theoretical value. A total error includes zero transition error,
full-scale transition error, and linear error.
Total error
:
Total error
3FFH
1.5 LSB
3FEH
3FDH
Actual conversion
characteristics
{1 LSB × (N − 1) + 0.5 LSB}
004H
003H
002H
001H
VNT
(Actual measurement value)
Actual conversion
characteristics
Ideal characteristics
0.5 LSB
AVSS
AVRH
Analog input
V
NT {1 LSB × (N 1) 0.5 LSB}
[LSB]
Total error of digital output “N”
1 LSB
AVRH AV
SS
1 LSB (Ideal value)
[V]
1024
N : A/D converter digital output value
VOT (Ideal value) AVSS 0.5 LSB [V]
VFST (Ideal value) AVRH 1.5 LSB [V]
VNT : A voltage at which digital output transits from (N 1) to N.
(Continued)
Document Number: 002-07872 Rev. *A
Page 74 of 83
MB90350 Series
(Continued)
Non linearity error
Differential linearity error
Ideal
characteristics
3FFH
Actual conversion
characteristics
3FEH
3FDH
N + 1
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
VFST (actual
measurement
value)
N
VNT (actual
measurement value)
004H
003H
002H
001H
V (N + 1) T
(actual measurement
value)
Actual conversion
characteristics
N − 1
N − 2
VNT
(actual measurement value)
Ideal characteristics
Actual conversion
characteristics
VOT (actual measurement value)
Analog input
AVSS
AVRH
AVSS
AVRH
Analog input
V
NT {1 LSB × (N 1) V
}
OT
[LSB]
Non linearity error of digital output N
1 LSB
V ( ) V
N+1 T
1 LSB
NT
Differential linearity error of digital output N
1 LSB [LSB]
[V]
V
FST V
OT
1 LSB
1022
N : A/D converter digital output value
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
Document Number: 002-07872 Rev. *A
Page 75 of 83
MB90350 Series
15.7 Flash Memory Program/Erase Characteristics
Flash Memory
Value
Typ
Parameter
Sector erase time
Conditions
Unit
Remarks
Min
Max
Excludes programming prior to
erasure
—
1
9
15
s
s
TA 25 °C
VCC 5.0 V
Excludes programming prior to
erasure
Chip erase time
—
—
Word (16-bit width)
programming time
Except for the overhead time of
the system level
—
10,000
20
16
—
—
3,600
—
μs
Program/Erase cycle
—
cycle
year
Flash Memory Data
Retention Time
Average
TA 85 °C
—
*
* : This value comes from the technology qualification.
(Using Arrhenius equation to translate high temperature measurements into normalized value at 85 °C)
Dual Operation Flash Memory
Value
Parameter
Sector erase time
Conditions
Unit
Remarks
Min
Typ
Max
Excludes programming prior to
erasure
—
0.2
0.5
s
s
s
(4 Kbytes sector)
Sector erase time
(16 Kbytes sector)
Excludes programming prior to
erasure
—
—
0.5
4.6
7.5
—
TA 25 °C
VCC 5.0 V
Excludes programming prior to
erasure
Chip erase time
Word (16-bit width)
programming time
Except for the overhead time of
the system level
—
10,000
20
64
—
—
3,600
—
μs
Program/Erase cycle
—
cycle
year
Flash Memory Data
Retention Time
Average
TA 85 °C
—
*
* : This value comes from the technology qualification.
(Using Arrhenius equation to translate high temperature measurements into normalized value at 85 °C)
Document Number: 002-07872 Rev. *A
Page 76 of 83
MB90350 Series
16. Ordering Information
Part number
MB90F351PMC
Package
Remarks
Flash memory products
64-pin plastic LQFP
FPT-64P-M23
12mm, 0.65mm pitch
(64 Kbytes)
MB90F351SPMC
MB90F352PMC
Flash memory products
(128 Kbytes)
MB90F352SPMC
MB90F351APMC
MB90F351ASPMC
MB90F351TAPMC
MB90F351TASPMC
MB90F356APMC
MB90F356ASPMC
MB90F356TAPMC
MB90F356TASPMC
MB90F352APMC
MB90F352ASPMC
MB90F352TAPMC
MB90F352TASPMC
MB90F357APMC
MB90F357ASPMC
MB90F357TAPMC
MB90F357TASPMC
MB90351APMC
64-pin plastic LQFP
FPT-64P-M23
12mm, 0.65mm pitch
Dual operation
Flash memory products
(64 Kbytes)
64-pin plastic LQFP
FPT-64P-M23
12mm, 0.65mm pitch
Dual operation
Flash memory products
(128 Kbytes)
MB90351ASPMC
MB90351TAPMC
MB90351TASPMC
MB90356APMC
64-pin plastic LQFP
FPT-64P-M23
12mm, 0.65mm pitch
MASK ROM products
(64 Kbytes)
MB90356ASPMC
MB90356TAPMC
MB90356TASPMC
MB90352APMC
MB90352ASPMC
MB90352TAPMC
MB90352TASPMC
MB90357APMC
64-pin plastic LQFP
FPT-64P-M23
12mm, 0.65mm pitch
MASK ROM products
(128 Kbytes)
MB90357ASPMC
MB90357TAPMC
MB90357TASPMC
(Continued)
Document Number: 002-07872 Rev. *A
Page 77 of 83
MB90350 Series
(Continued)
Part number
Package
Remarks
MB90F351APMC1
MB90F351ASPMC1
MB90F351TAPMC1
MB90F351TASPMC1
MB90F356APMC1
MB90F356ASPMC1
MB90F356TAPMC1
MB90F356TASPMC1
MB90F352APMC1
MB90F352ASPMC1
MB90F352TAPMC1
MB90F352TASPMC1
MB90F357APMC1
MB90F357ASPMC1
MB90F357TAPMC1
MB90F357TASPMC1
MB90351APMC1
64-pin plastic LQFP
FPT-64P-M24
10 mm , 0.50 mm pitch
Dual operation
Flash memory products*
(64 Kbytes)
64-pin plastic LQFP
FPT-64P-M24
10 mm , 0.50 mm pitch
Dual operation
Flash memory products*
(128 Kbytes)
MB90351ASPMC1
MB90351TAPMC1
MB90351TASPMC1
MB90356APMC1
64-pin plastic LQFP
FPT-64P-M24
10 mm , 0.50 mm pitch
MASK ROM products*
(64 Kbytes)
MB90356ASPMC1
MB90356TAPMC1
MB90356TASPMC1
MB90352APMC1
MB90352ASPMC1
MB90352TAPMC1
MB90352TASPMC1
MB90357APMC1
64-pin plastic LQFP
FPT-64P-M24
10 mm , 0.50 mm pitch
MASK ROM products*
(128 Kbytes)
MB90357ASPMC1
MB90357TAPMC1
MB90357TASPMC1
MB90V340A-101
MB90V340A-102
299-pin ceramic PGA
PGA-299C-A01
Device for evaluation
MB90V340A-103
MB90V340A-104
* : These devices are under development.
Document Number: 002-07872 Rev. *A
Page 78 of 83
MB90350 Series
17. Package Dimensions
64-pin plastic LQFP
Lead pitch
0.65 mm
12.0 × 12.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm MAX
0.47 g
Code
(Reference)
P-LQFP64-12×12-0.65
(FPT-64P-M23)
64-pin plastic LQFP
(FPT-64P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00 0.20(.551 .008)SQ
*12.00 0.10(.472 .004)SQ
0.145 0.055
(.006 .002)
48
33
49
32
0.10(.004)
Details of "A" part
1.50 +0.20
–
0.10
(Mounting height)
.059 +.008
–.004
0.25(.010)
INDEX
0~8°
64
17
0.50 0.20
0.10 0.10
(.020 .008)
(.004 .004)
(Stand off)
"A"
1
16
0.60 0.15
(.024 .006)
0.65(.026)
0.32 0.05
(.013 .002)
M
0.13(.005)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F64034S-c-1-4
(Continued)
Document Number: 002-07872 Rev. *A
Page 79 of 83
MB90350 Series
(Continued)
64-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
10.0 mm × 10.0 mm
Lead shape
Gullwing
Plastic mold
Sealing method
Code
(Reference)
P-LFQFP64-10×10-0.50
(FPT-64P-M24)
64-pin plastic LQFP
(FPT-64P-M24)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00 0.20(.472 .008)SQ
Details of "A" part
*10.00 0.10(.394 .004)SQ
0.145 0.055
(.006 .002)
48
33
0.15(.006)
MAX
49
32
0.40(.016)
MAX
0.08(.003)
Details of "B" part
1.50 +0.20
11.00(.433)
NOM.
–
0.10
.004
(Mounting height)
.059 +.008
–
0.25(.010)
INDEX
0~8°
"A"
64
17
0.50 0.20
0.10 0.10
(.020 .008)
(.004 .004)
(Stand off)
"B"
1
16
LEAD No.
0.60 0.15
(.024 .006)
0.50(.020)
0.20 0.05
(.008 .002)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
C
2006-2010 FUJITSU SEMICONDUCTOR LIMITED F64036S-1c(D)-1-3
Document Number: 002-07872 Rev. *A
Page 80 of 83
MB90350 Series
18. Major Changes
Spansion Publication Number: DS07-13737-6E
Page
Section
Change Results
Deleted the following package.
FPT-64P-M09
—
—
Changed the correspondence package for MB90F351, MB90F351S,
MB90F352 and MB90F352S.
FPT-64P-M09 → FPT-64P-M23
5. Packages and Product Correspon-
dence
13
26
Corrected a typo in number 10.
“is used”→ “is not used”
9. Handling Devices
15. Electrical Characteristics
15.4. AC Characteristics
15.4.4. Clock Output Timing
Changed the Minimum value of cycle time.
41.76 → 41.67
64
75
15.5. A/D Converter
Changed the notation of “Zero reading voltage” and “Full scale reading voltage”.
Changed the part numbers and the package.
MB90F351PFM → MB90F351PMC
MB90F351SPFM → MB90F351SPMC
MB90F352PFM → MB90F352PMC
MB90F352SPFM → MB90F352SPMC
FPT-64P-M09 → FPT-64P-M23
81
16. Ordering Information
NOTE: Please see “Document History” about later revised information.
Document Number: 002-07872 Rev. *A
Page 81 of 83
MB90350 Series
Document History
Document Title: MB90350 Series F2MC-16LX 16-bit Microcontroller
Document Number: 002-07872
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
Migrated to Cypress and assigned document number 002-07872.
No change to document contents or format.
**
—
AKFU
AKFU
09/29/2003
*A
5755299
05/31/2017 Updated to Cypress format.
Document Number: 002-07872 Rev. *A
Page 82 of 83
MB90350 Series
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
ARM® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
cypress.com/mcu
cypress.com/support
Microcontrollers
PSoC
cypress.com/psoc
cypress.com/pmic
cypress.com/touch
cypress.com/usb
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/wireless
© Cypress Semiconductor Corporation, 2003-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-07872 Rev. *A
Revised May 31, 2017
Page 83 of 83
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