MT58L256L18D1T-5IT [CYPRESS]
Standard SRAM, 256KX18, 2.8ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100;
| 型号： | MT58L256L18D1T-5IT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 256KX18, 2.8ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100 静态存储器 |
| 文件： | 总23页 (文件大小：605K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
4Mb SYNCBURST™
SRAM
MT58L256L18D1, MT58L128L32D1,
MT58L128L36D1
3.3V VDD, 3.3V I/O, Pip e lin e d , Do u b le -
Cycle De se le ct
FEATURES
• Fast clock and OE# access times
• Single +3.3V +0.3V/-0.165V power supply (VDD)
• Separate +3.3V isolated output buffer supply
(VDDQ)
100-PIN TQFP*
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL
WRITE
• Three chip enables for simple depth expansion and
address pipelining
• Clock-controlled and registered addresses, data
I/Os and control signals
• Internally self-timed WRITE cycle
• Burst control pin (interleaved or linear burst)
• Automatic power-down for portable applications
• 100-lead TQFP package for high density, high
speed
119-PIN BGA
• 119-pin BGA package
• Low capacitive bus loading
• x18, x32 and x36 versions available
OPTIONS
MARKING
• Timing (Access/Cycle/MHz)
2.6ns/5ns/200 MHz
3.5ns/6ns/166 MHz
4.0ns/7.5ns/133 MHz
5ns/10ns/100 MHz
-5
-6
-7.5
-10
*JEDEC-standard MS-026 BHA (LQFP).
• Configurations
256K x 18
MT58L256L18D1
MT58L128L32D1
MT58L128L36D1
128K x 32
128K x 36
GENERAL DESCRIPTION
The Micron® SyncBurst™ SRAM family employs
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
• Packages
100-pin TQFP
119-pin, 14mm x 22mm BGA
T
B
Micron’s 4Mb SyncBurst SRAMs integrate a 256K x
18, 128K x 32, or 128K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single clock
input (CLK). The synchronous inputs include all ad-
dresses, all data inputs, active LOW chip enable (CE#),
two additional chip enables for easy depth expansion
(CE2, CE2#), burst control inputs (ADSC#, ADSP#,
ADV#), byte write enables (BWx#) and global write
(GW#).
• Operational Temperature Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
None
IT
Part Number Example:
MT58L256L18D1T-6 IT
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1.p65 – Rev 12/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
1
PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
FUNCTIONAL BLOCK DIAGRAM
256K x 18
18
16
18
18
2
ADDRESS
REGISTER
SA0, SA1, SA
MODE
SA0-SA1
Q1
SA1'
SA0'
ADV#
CLK
BINARY
COUNTER AND
LOGIC
CLR
Q0
ADSC#
ADSP#
BYTE “b”
WRITE DRIVER
BYTE “b”
WRITE REGISTER
9
9
9
9
OUTPUT
BUFFERS
BWb#
256K x 9 x 2
MEMORY
ARRAY
DQs
DQPa
DQPb
OUTPUT
REGISTERS
SENSE
AMPS
18
18
18
18
BYTE “a”
WRITE DRIVER
E
BYTE “a”
WRITE REGISTER
BWa#
BWE#
INPUT
REGISTERS
GW#
18
ENABLE
REGISTER
CE#
CE2
PIPELINED
ENABLE
CE2#
OE#
2
FUNCTIONAL BLOCK DIAGRAM
128K x 32/36
17
15
17
17
ADDRESS
REGISTER
SA0, SA1, SA
MODE
SA0-SA1
SA1'
SA0'
Q1
BINARY
COUNTER
ADV#
CLK
CLR
Q0
ADSC#
ADSP#
BYTE “d”
WRITE DRIVER
BYTE “d”
WRITE REGISTER
BWd#
BWc#
128K x 8 x 4
(x32)
BYTE “c”
WRITE DRIVER
DQs
DQPa
BYTE “c”
WRITE REGISTER
OUTPUT
BUFFERS
OUTPUT
REGISTERS
128K x 9 x 4
(x36)
SENSE
AMPS
E
BYTE “b”
WRITE DRIVER
MEMORY
ARRAY
DQPd
BYTE “b”
WRITE REGISTER
BWb#
BYTE “a”
WRITE DRIVER
BYTE “a”
WRITE REGISTER
BWa#
BWE#
INPUT
REGISTERS
GW#
CE#
CE2
ENABLE
REGISTER
PIPELINED
ENABLE
CE2#
OE#
4
NOTE: Functional block diagrams illustrate simplified device operation. See truth tables, pin descriptions and timing diagrams
for detailed information.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1.p65 – Rev 12/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
2
PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
GENERAL DESCRIPTION (co n t in u e d )
Asynchronous inputs include the output enable
(OE#), clock (CLK) and snooze enable (ZZ). There is also
a burst mode input (MODE) that selects between inter-
leaved and linear burst modes. The data-out (Q), en-
abled by OE#, is also asynchronous. WRITE cycles can
be from one to two bytes wide (x18) or from one to four
bytes wide (x32/x36), as controlled by the write control
inputs.
devices, BWa# controls DQa’s and DQPa; BWb# con-
trols DQb’s and DQPb; BWc# controls DQc’s and DQPc;
BWd# controls DQd’s and DQPd. GW# LOW causes all
bytes to be written. Parity bits are only available on the
x18 and x36 versions.
This device incorporates an additional pipelined
enable register which delays turning off the output
buffer an additional cycle when a deselect is executed.
This feature allows depth expansion without penaliz-
ing system performance.
Micron’s 4Mb SyncBurst SRAMs operate from a
+3.3V VDD power supply, and all inputs and outputs are
TTL-compatible. The device is ideally suited for
Pentium® and PowerPC pipelined systems and systems
that benefit from a very wide, high-speed data bus. The
device is also ideal in generic 16-, 18-, 32-, 36-, 64- and
72-bit-wide applications.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be
internally generated as controlled by the burst advance
input (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device,
BWa# controls DQa’s and DQPa; BWb# controls DQb’s
and DQPb. During WRITE cycles on the x32 and x36
PleaserefertoMicron’sWebsite(www.micron.com/
mti/msp/html/sramprod.html)forthelatestdatasheet.
TQFP PIN ASSIGNMENT TABLE
PIN #
1
2
3
4
5
6
7
8
x18
NC
NC
NC
x32/x36
NC/DQPc*
DQc
PIN #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
x18
x32/x36
VSS
VDDQ
DQd
DQd
NC/DQPd*
MODE
PIN #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
x18
NC
NC
NC
x32/x36
NC/DQPa*
DQa
PIN #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
x18
x32/x36
VSS
VDDQ
DQb
DQb
NC/DQPb*
SA
SA
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
CLK
DQc
NC
NC
NC
DQa
NC
NC
SA
VDDQ
VSS
VDDQ
VSS
NC
NC
DQb
DQb
DQc
DQc
DQc
DQc
NC
NC
DQa
DQa
SA
SA
SA
DQa
DQa
VSS
VDDQ
DQa
DQa
ZZ
VDD
NC
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
VDDQ
SA
SA1
SA0
DNU
DNU
VSS
VDD
NF**
NF**
SA
DQb
DQb
DQc
DQc
VDD
VDD
NC
VSS
VDD
VSS
CE2#
BWa#
BWb#
DQb
DQb
DQd
DQd
DQa
DQa
DQb
DQb
VDDQ
VSS
SA
SA
SA
SA
SA
SA
VDDQ
VSS
NC
NC
BWc#
BWd#
DQb
DQb
DQPb
NC
DQd
DQd
DQd
DQd
DQa
DQa
DQPa
NC
DQb
DQb
DQb
DQb
CE2
CE#
SA
SA
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
**Pins 43 and 42 are reserved for address expansion, 8Mb and 16Mb respectively.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1.p65 – Rev 12/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
3
PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
PIN ASSIGNMENT (TOP VIEW)
100-PIN TQFP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SA
SA
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SA
SA
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
CLK
SA
SA
SA
SA
SA
NF**
NF**
VDD
VSS
VSS
VDD
x18
CE2#
BWa#
BWb#
NC
DNU
DNU
SA0
SA1
SA
NC
CE2
SA
CE#
SA
SA
SA
SA
100
MODE
1
2
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SA
81
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SA
SA
ADV#
ADSP#
ADSC#
OE#
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
SA
SA
SA
SA
SA
BWE#
GW#
SA
NF**
NF**
CLK
V
SS
DD
V
DD
SS
V
V
x32/x36
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
DNU
DNU
SA0
SA1
SA
SA
CE#
SA
SA
SA
SA
100
MODE
1
2
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
**Pins 43 and 42 are reserved for address expansion, 8Mb and 16Mb respectively.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1.p65 – Rev 12/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4
PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
TQFP PIN DESCRIPTIONS
x18
x32/x36
SYMBOL TYPE
DESCRIPTION
37
36
37
36
SA0
SA1
SA
Input Synchronous Address Inputs: These inputs are registered and must
meet the setup and hold times around the rising edge of CLK.
32-35, 44-50, 32-35, 44-50,
80-82, 99,
100
81, 82, 99,
100
93
94
–
93
94
95
96
BWa#
BWb#
BWc#
BWd#
Input Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa pins and DQPa; BWb# controls DQb pins and
DQPb. For the x32 and x36 versions, BWa# controls DQa pins and
DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. Parity is only
available on the x18 and x36 versions.
–
87
88
89
87
88
89
BWE#
GW#
CLK
Input Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
Input Global Write: This active LOW input allows a full 18-, 32- or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
Input Clock: This signal registers the address, data, chip enable, byte write
enables and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
98
92
64
98
92
64
CE#
CE2#
ZZ
Input Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
Input Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
Input Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
97
97
CE2
Input Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
86
83
86
83
OE#
Input Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
ADV#
Input Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after
the external address is loaded. A HIGH on this pin effectively causes
wait states to be generated (no address advance). To ensure use of
correct address during a WRITE cycle, ADV# must be HIGH at the
rising edge of the first clock after an ADSP# cycle is initiated.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1.p65 – Rev 12/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
5
©1999, Micron Technology, Inc.
PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
TQFP PIN DESCRIPTIONS (co n t in u e d )
x18
x32/x36
SYMBOL TYPE
DESCRIPTION
84
84
ADSP#
Input Synchronous Address Status Processor: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is HIGH. Power-
down state is entered if CE2 is LOW or CE2# is HIGH.
85
85
ADSC#
MODE
Input Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
31
31
Input Mode: This input selects the burst sequence. A LOW on this pin
selects “linear burst.” NC or HIGH on this pin selects “interleaved
burst.” Do not alter input state while device is operating.
(a) 58, 59,
62, 63, 68, 69, 56-59, 62, 63
72, 73
(b) 8, 9, 12,
13, 18, 19, 22, 72-75, 78, 79
(a) 52, 53,
DQa
DQb
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa pins; Byte “b”
Output is DQb pins. For the x32 and x36 versions, Byte “a” is DQa pins;
Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is DQd pins.
Input data must meet setup and hold times around the rising edge
of CLK.
(b) 68, 69
23
(c) 2, 3, 6-9,
12, 13
(d) 18, 19,
22-25, 28, 29
DQc
DQd
74
24
–
51
80
1
NC/DQPa
NC/DQPb
NC/DQPc
NC/DQPd
NC/
I/O
No Connect/Parity Data I/Os: On the x32 version, these pins are No
Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte “b”
parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte
“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.
–
30
14, 15, 41, 65, 14, 15, 41, 65,
91 91
V
DD
Supply Power Supply: See DC Electrical Characteristics and Operating
Conditions for range.
4, 11, 20, 27, 4, 11, 20, 27,
54, 61, 70, 77 54, 61, 70, 77
V
DD
Q
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
Operating Conditions for range.
5, 10, 17, 21, 5, 10, 17, 21,
26, 40, 55, 60, 26, 40, 55, 60,
67, 71, 76, 90 67, 71, 76, 90
V
SS
Supply Ground: GND.
38, 39
38, 39
DNU
NC
–
–
Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
1-3, 6, 7,
16, 25, 28-30,
51-53, 56, 57,
66, 75, 78, 79,
95, 96
16, 66
No Connect: These signals are not internally connected and may be
connected to ground to improve package heat dissipation.
42, 43
42, 43
NF
–
No Function: These pins are internally connected to the die and will
have the capacitance of input pins. It is allowable to leave these
pins unconnected or driven by signals. Reserved for address
expansion, pin 43 becomes an SA at 8Mb density and pin 42
becomes an SA at 16Mb density.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1.p65 – Rev 12/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
6
©1999, Micron Technology, Inc.
PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
PIN ASSIGNMENT (TOP VIEW)
119-PIN BGA
x18
x32/x36
1
2
3
4
5
6
7
1
2
3
4
5
6
7
A
B
C
D
E
A
B
C
D
E
V
DD
Q
SA
CE2**
SA
SA ADSP# SA
SA
V
DDQ
V
DD
Q
SA
CE2**
SA
SA
SA
SA
ADSP#
ADSC#
SA
SA
V
DDQ
NC
NC
SA ADSC# SA CE2#** NC
NC
NC
SA CE2#** NC
SA
V
DD
SA
SA
DQPa
NC
NC
NC
V
DD
SA
SA
NC
DQb
NC
NC
V
V
V
SS
SS
SS
NC
CE#
OE#
V
V
V
V
V
SS
SS
SS
SS
SS
DQc NC/DQPc*
V
V
V
SS
SS
SS
NC
CE#
OE#
V
V
V
SS NC/DQPb* DQb
DQb
NC
DQa
DQc
DQc
DQc
SS
SS
DQb
DQb
DQb
F
F
V
DD
Q
DQa
NC
V
DD
DQa
NC
Q
VDD
Q
V
DDQ
G
H
J
G
H
J
NC
DQb BWb# ADV#
DQc
DQc
DQc BWc# ADV# BWb# DQb
DQb
DQb
DQb
NC
V
SS
GW#
DQa
DQc
VSS
GW#
V
SS
DQb
V
DD
Q
V
DD
DQb
NC
NC
V
DD
NC
V
DD
V
DD
DQa
NC
Q
V
DD
Q
V
DD
NC
V
DD
NC
V
DD
V
DDQ
K
L
K
L
NC
VSS
VSS
VSS
VSS
VSS
CLK
NC
VSS
NC
DQd
DQd
DQd
VSS
CLK
NC
VSS
DQa
DQa
DQa
DQb
BWa# DQa
DQd BWd#
BWa# DQa
M
N
P
M
N
P
V
DD
DQb
NC
Q
DQb
NC
BWE#
SA1
VSS
VSS
VSS
NC
DQa
NC
V
DD
Q
V
DD
Q
DQd
DQd
V
V
V
SS
SS
SS
BWE#
SA1
V
V
V
SS
DQa
DQa
V
DDQ
NC
DQd
SS
DQa
DQPb
SA0
DQa
NC
DQd NC/DQPd*
SA0
SS NC/DQPa* DQa
R
T
R
T
NC
SA MODE
V
DD
V
DD
SA
NC
NC
SA
NC
MODE
SA
V
DD
VDD
SA
NC
NC
NC
ZZ
NC
SA
SA
NC
SA
SA
ZZ
SA
SA
U
U
V
DD
Q
DNU DNU DNU DNU
NC
VDDQ
V
DD
Q
DNU
DNU
DNU
TOP VIEW
DNU
VDDQ
TOP VIEW
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
**Pins 6B and 2B are reserved for address expansion, 8Mb and 16Mb respectively.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1.p65 – Rev 12/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
7
PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
BGA PIN DESCRIPTIONS
x18
x32/x36
SYMBOL TYPE
DESCRIPTION
4P
4N
4P
4N
SA0
SA1
SA
Input Synchronous Address Inputs: These inputs are registered and must
meet the setup and hold times around the rising edge of CLK.
2A, 3A, 5A,
6A, 3B, 5B,
2C, 3C, 5C,
6C, 2R, 6R,
2T, 3T, 5T, 6T
2A, 2C, 2R,
3A, 3B, 3C,
3T, 4T, 5A,
5B, 5C, 5T,
6A, 6C, 6R
5L
3G
–
5L
5G
3G
3L
BWa#
BWb#
BWc#
BWd#
Input Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb.
For the x32 and x36 versions, BWa# controls DQa’s and DQPa;
BWb# controls DQb’s and DQPb; BWc# controls DQc’s and DQPc;
BWd# controls DQd’s and DQPd. Parity is only available on the x18
and x36 versions.
–
4M
4H
4K
4M
4H
4K
BWE#
GW#
CLK
Input Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
Input Global Write: This active LOW input allows a full 18-, 32- or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
Input Clock: This signal registers the address, data, chip enable, byte write
enables and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
4E
6B
7T
2B
4E
6B
7T
2B
CE#
CE2#
ZZ
Input Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
Input Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
Input Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When active, all other inputs are ignored.
CE2
Input Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded. Pin 6B becomes an SA at 8Mb density.
4F
4F
OE#
Input Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers. Pin 2B becomes an SA at 16Mb density.
4G
4G
ADV#
Input Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after
the external address is loaded. A HIGH on ADV# effectively causes
wait states to be generated (no address advance). To ensure use of
correct address during a WRITE cycle, ADV# must be HIGH at the
rising edge of the first clock after an ADSP# cycle is initiated.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1.p65 – Rev 12/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
8
©1999, Micron Technology, Inc.
PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
BGA PIN DESCRIPTIONS (co n t in u e d )
x18
x32/x36
SYMBOL TYPE
DESCRIPTION
4A
4A
ADSP#
Input Synchronous Address Status Processor: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is HIGH. Power-
down state is entered if CE2 is LOW or CE2# is HIGH.
4B
3R
4B
3R
ADSC#
MODE
Input Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
Input Mode: This input selects the burst sequence. A LOW on this input
selects “linear burst.” NC or HIGH on this input selects “interleaved
burst.” Do not alter input state while device is operating.
(a) 6F, 6H, 6L,
6N, 7E, 7G,
7K, 7P
(b) 1D, 1H,
1L, 1N, 2E,
2G, 2K, 2M
(a) 6K, 6L,
6M, 6N, 7K,
7L, 7N, 7P
(b) 6E, 6F,
6G, 6H, 7D,
7E, 7G, 7H
(c) 1D, 1E,
1G, 1H, 2E,
2F, 2G, 2H
(d) 1K, 1L,
1N, 1P, 2K,
2L, 2M, 2N
DQa
DQb
DQc
DQd
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa’s; Byte “b”
Output is DQb’s. For the x32 and x36 versions, Byte “a” is DQa’s; Byte “b”
is DQb’s; Byte “c” is DQc’s; Byte “d” is DQd’s. Input data must
meet setup and hold times around the rising edge of CLK.
6D
2P
–
6P
6D
2D
2P
NC/DQPa
NC/DQPb
NC/DQPc
NC/DQPd
NC/
I/O
No Connect/Parity Data I/Os: On the x32 version, these are No
Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte “b”
parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte
“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.
–
2J, 4C, 4J,
4R, 5R, 6J
2J, 4C, 4J,
4R, 5R, 6J
V
DD
Supply Power Supply: See DC Electrical Characteristics and Operating
Conditions for range.
1A, 1F, 1J,
1M, 1U, 7A,
7F, 7J, 7M,
7U
1A, 1F, 1J,
1M, 1U, 7A,
7F, 7J, 7M,
7U
V
DD
Q
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
Operating Conditions for range.
3D, 3E, 3F,
3H, 3K, 3L,
3M, 3N, 3P,
5D, 5E, 5F,
5G, 5H, 5K,
5M, 5N, 5P
3D, 3E, 3F,
3H, 3K, 3M,
3N, 3P, 5D,
5E, 5F, 5H,
5K, 5M, 5N,
5P
V
SS
Supply Ground: GND.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1.p65 – Rev 12/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
9
©1999, Micron Technology, Inc.
PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
BGA PIN DESCRIPTIONS (CONTINUED)
x18
x32/x36
SYMBOL TYPE
DESCRIPTION
2U, 3U, 4U,
5U
2U, 3U, 4U,
5U
DNU
–
Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
1B, 1C, 1E,
1G, 1K, 1P,
1R, 1T, 2D,
2F, 2H, 2L,
2N, 3J, 4D,
4L, 4T, 5J,
6E, 6G, 6K,
6M, 6P, 6U,
7B, 7C, 7D,
7H, 7L, 7N,
7R
1B, 1C, 1R,
1T, 2T, 3J,
4D, 4L, 5J,
6T, 6U, 7B,
7C, 7R
NC
–
No Connect: These signals are not internally connected and may be
connected to ground to improve package heat dissipation.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1.p65 – Rev 12/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
10
©1999, Micron Technology, Inc.
PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X...X00
X...X01
X...X10
X...X11
X...X01
X...X00
X...X11
X...X10
X...X10
X...X11
X...X00
X...X01
X...X11
X...X10
X...X01
X...X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X...X00
X...X01
X...X10
X...X11
X...X01
X...X10
X...X11
X...X00
X...X10
X...X11
X...X00
X...X01
X...X11
X...X00
X...X01
X...X10
PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x18)
FUNCTION
GW#
H
BWE#
BWa #
BWb #
READ
H
L
X
H
L
X
H
H
L
READ
H
WRITE Byte “a”
WRITE Byte “b”
WRITE All Bytes
WRITE All Bytes
H
L
H
L
H
L
H
L
L
L
X
X
X
PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x32/x36)
FUNCTION
READ
GW#
H
BWE#
BWa #
BWb #
BWc#
BWd #
H
L
X
H
L
X
H
H
L
X
H
H
L
X
H
H
L
READ
H
WRITE Byte “a”
WRITE All Bytes
WRITE All Bytes
H
L
H
L
L
L
X
X
X
X
X
NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1.p65 – Rev 12/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
11
PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
TRUTH TABLE
OPERATION
ADDRESS
USED
CE# CE2# CE2
ZZ ADSP# ADSC# ADV# WRITE# OE#
CLK
DQ
DESELECTE Cycle, Power-Down
DESELECTE Cycle, Power-Down
DESELECTE Cycle, Power-Down
DESELECTE Cycle, Power-Down
DESELECTE Cycle, Power-Down
SNOOZE MODE, Power-Down
READ Cycle, Begin Burst
None
None
H
L
X
X
H
X
H
X
L
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H
High-Z
L-H
L-H
L-H
L-H
X
High-Z
High-Z
High-Z
High-Z
High-Z
Q
None
L
X
L
L
None
L
H
H
X
L
None
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
L
X
X
X
L
External
External
External
External
External
Next
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
READ Cycle, Begin Burst
L
L
L
H
X
L
High-Z
D
WRITE Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
READ Cycle, Begin Burst
L
L
L
H
H
H
H
H
H
L
Q
READ Cycle, Begin Burst
L
L
L
H
L
High-Z
Q
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Next
L
H
L
High-Z
Q
Next
L
Next
L
H
X
X
L
High-Z
D
Next
L
Next
L
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
High-Z
Q
H
X
X
High-Z
D
L
D
NOTE: 1. X means “Don’t Care.” # means active LOW. H means logic HIGH. L means logic LOW.
2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc# or BWd#) and BWE# are LOW or
GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH.
3. BWa# enables WRITEs to DQa’s and DQPa. BWb# enables WRITEs to DQb’s and DQPb. BWc# enables WRITEs to DQc’s
and DQPc. BWd# enables WRITEs to DQd’s and DQPd. DQPa and DQPb are only available on the x18 and x36 versions.
DQPc and DQPd are only available on the x36 version.
4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held
HIGH throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more
byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing
diagram for clarification.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1.p65 – Rev 12/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
12
PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
**Maximum junction temperature depends upon pack-
age type, cycle time, loading, ambient temperature and
airflow. See Micron Technical Note TN-05-14 for more
information.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD Supply
Relative to VSS ................................-0.5V to +4.6V
Voltage on VDDQ Supply
Relative to VSS ................................-0.5V to +4.6V
VIN .............................................. -0.5V to VDDQ + 0.5V
Storage Temperature (plastic) ............ -55°C to +150°C
Storage Temperature (BGA) ............... -55°C to +125°C
Junction Temperature** ................................... +150°C
Short Circuit Output Current........................... 100mA
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0°C ≤ TA ≤ 70°C; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL MIN
MAX
VDD + 0.3
0.8
UNITS
V
NOTES
1, 2
1, 2
3
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
VIH
VIL
ILI
2.0
-0.3
-1.0
-1.0
V
0V ≤ VIN ≤ VDD
1.0
µA
µA
Output(s) disabled,
ILO
1.0
0V ≤ VIN ≤ VDD
Output High Voltage
Output Low Voltage
Supply Voltage
IOH = -4.0mA
VOH
VOL
2.4
–
–
V
V
V
V
1, 4
1, 4
1
IOL = 8.0mA
0.4
3.6
3.6
VDD
3.135
3.135
Isolated Output Buffer Supply
VDDQ
1, 5
NOTE: 1. All voltages referenced to VSS (GND).
t
2. Overshoot:
VIH ≤ +4.6V for t ≤ KC/2 for I ≤ 20mA
t
Undershoot: VIL ≥ -0.7V for t ≤ KC/2 for I ≤ 20mA
Power-up: VIH ≤ +3.6V and VDD ≤ 3.135V for t ≤ 200ms
3. MODE pin has an internal pull-up, and input leakage = ±10µA.
4. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the stated DC values. AC I/O
curves are available upon request.
5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1.p65 – Rev 12/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
13
PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
TQFP THERMAL RESISTANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
UNITS NOTES
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51.
θJA
46
°C/W
1
Thermal Resistance
(Junction to Top of Case)
θJC
2.8
°C/W
1
BGA THERMAL RESISTANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
UNITS NOTES
Junction to Ambient
(Airflow of 1m/s)
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51.
θJA
40
°C/W
1
Junction to Case (Top)
θJC
θJB
9
°C/W
°C/W
1
1
Junction to Pins
(Bottom)
17
NOTE: 1. This parameter is sampled.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1.p65 – Rev 12/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
14
PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
IDD OPERATING CONDITIONS AND MAXIMUM LIMITS
(0°C ≤ TA ≤ +70°C; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted)
MAX
-7.5
DESCRIPTION
CONDITIONS
SYM
TYP
-5
-6
-10 UNITS NOTES
Power Supply
Current:
Operating
Device selected; All inputs ≤ VIL
or ≥ VIH; Cycle time ≥ tKC MIN;
I
DD
225
525 475 375 300
mA
mA
1, 2, 3
1, 2, 3
VDD = MAX; Outputs open
Power Supply
Current: Idle
Device selected; VDD = MAX;
ADSC#, ADSP#, GW#, BWx#, ADV# ≥
IDD
1
55
120 110
90
85
V
IH; All inputs ≤ VSS + 0.2 or ≥ VDD - 0.2;
Cycle time ≥ tKC MIN
CMOS Standby
TTL Standby
Device deselected; VDD = MAX;
All inputs ≤ VSS + 0.2 or ≥ VDD - 0.2;
All inputs static; CLK frequency = 0
I
SB
SB
SB
2
0.4
8
10
25
10
25
10
25
90
10
25
85
mA
mA
mA
2, 3
2, 3
2, 3
Device deselected; VDD = MAX;
All inputs ≤ VIL or ≥ VIH
;
I
3
All inputs static; CLK frequency = 0
Clock Running
Device deselected; VDD = MAX;
ADSC#, ADSP#, GW#, BWx#, ADV# ≥
I
4
55
120 110
V
IH; All inputs ≤ VSS + 0.2 or ≥ VDD - 0.2;
Cycle time ≥ tKC MIN
TQFP CAPACITANCE
DESCRIPTION
CONDITIONS
TA = 25°C; f = 1 MHz;
VDD = 3.3V
SYMBOL
TYP
3
MAX
4
UNITS
NOTES
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
Clock Capacitance
CI
CO
CA
CCK
pF
pF
pF
pF
4
4
4
4
4
5
3
3.5
3.5
3
BGA CAPACITANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
4
MAX
7
UNITS
pF
NOTES
Address/Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
CI
CO
CA
4
4
4
4
TA = 25°C; f = 1 MHz
4.5
4
5.5
7
pF
pF
Clock Capacitance
CCK
4.5
5.5
pF
NOTE: 1. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and
greater output loading.
2. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means
device is active (not in power-down mode).
3. Typical values are measured at 3.3V, 25°C and 10ns cycle time.
4. This parameter is sampled.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1.p65 – Rev 12/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
15
PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 1) (0°C ≤ TA ≤ +70°C; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted)
-5
-6
-7.5
-10
DESCRIPTION
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
Clo ck
t
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
KC
KF
5
6.0
7.5
10
ns
MHz
ns
f
200
2.8
166
3.5
133
4.0
100
5.0
t
KH
2
2
2.3
2.3
2.5
2.5
3.0
3.0
2
2
t
KL
ns
Ou t p u t Tim e s
t
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE# to output valid
OE# to output in Low-Z
OE# to output in High-Z
Se t u p Tim e s
KQ
ns
ns
ns
ns
ns
ns
ns
t
KQX
KQLZ
KQHZ
OEQ
OELZ
OEHZ
1
0
1.5
0
1.5
0
1.5
1.5
3
t
3, 4, 5, 6
3, 4, 5, 6
7
3, 4, 5, 6
3, 4, 5, 6
t
2.8
2.8
3.5
3.5
4.2
4.2
5.0
5.0
t
t
0
0
0
0
t
2.8
3.5
4.2
4.5
t
Address
Address status (ADSC#, ADSP#)
Address advance (ADV#)
AS
1.3
1.3
1.3
1.3
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0
ns
ns
ns
ns
8, 9
8, 9
8, 9
8, 9
t
ADSS
t
AAS
t
Write signals
WS
(BWa#-BWd#, BWE#, GW#)
t
Data-in
Chip enables (CE#, CE2#, CE2)
Ho ld Tim e s
DS
1.3
1.3
1.5
1.5
1.5
1.5
2.0
2.0
ns
ns
8, 9
8, 9
t
CES
t
Address
Address status (ADSC#, ADSP#)
Address advance (ADV#)
AH
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
8, 9
8, 9
8, 9
8, 9
t
ADSH
t
AAH
t
Write signals
WH
(BWa#-BWd#, BWE#, GW#)
t
Data-in
Chip enables (CE#, CE2#, CE2)
DH
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
8, 9
8, 9
t
CEH
NOTE: 1. Test conditions as specified with the output loading shown in Figure 1 unless otherwise noted.
2. Measured as HIGH above VIH and LOW below VIL.
3. This parameter is measured with the output loading shown in Figure 2 unless otherwise noted.
4. This parameter is sampled.
5. Transition is measured ±500mV from steady state voltage.
6. Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough
discussion on these parameters.
7. OE# is a “Don’t Care” when a byte write enable is sampled LOW.
8. A WRITE cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold
times. A READ cycle is defined by all byte write enables HIGH and ADSC# or ADV# LOW or ADSP# LOW for the
required setup and hold times.
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when either ADSP# or ADSC# is LOW and chip enabled. All other synchronous inputs must meet the setup and hold
times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at
each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1.p65 – Rev 12/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
16
PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
Ou t p u t Lo a d Eq u iva le n t s
AC TEST CONDITIONS
Input pulse levels .................. VIH = (VDD/2.2) + 1.5V
.................... VIL = (VDD/2.2) - 1.5V
Q
ZO= 50
50
Input rise and fall times .................................... 1ns
Input timing reference levels ...................... VDD/2.2
Output reference levels............................ VDDQ/2.2
Output load .............................See Figures 1 and 2
VT = 1.5V
Fig u re 1
+3.3V
317
LOAD DERATING CURVES
Q
Micron 256K x 18, 128K x 32, and 128K x 36
SyncBurst SRAM timing is dependent upon the capaci-
tive loading on the outputs.
5pF
351
Consult the factory for copies of I/O current versus
voltage curves.
Fig u re 2
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1.p65 – Rev 12/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
17
PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
SNOOZE MODE
SNOOZE MODE is a low-current, “power-down”
mode in which the device is deselected and current is
reduced to ISB2Z. The duration of SNOOZE MODE is
dictated by the length of time ZZ is in a HIGH state.
After the device enters SNOOZE MODE, all inputs
except ZZ become gated inputs and are ignored.
ZZ is an asynchronous, active HIGH input that
causes the device to enter SNOOZE MODE. When ZZ
becomes a logic HIGH, ISB2Z is guaranteed after the
setup time tZZ is met. Any READ or WRITE operation
pending when the device enters SNOOZE MODE is not
guaranteedtocompletesuccessfully.Therefore,SNOOZE
MODE must not be initiated until valid pending opera-
tions are completed.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
CONDITIONS
SYMBOL
ISB2Z
tZZ
tRZZ
tZZI
tRZZI
MIN
MAX
10
2(tKC)
UNITS NOTES
Current during SNOOZE MODE
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to snooze current
ZZ inactive to exit snooze current
ZZ ≥ VIH
mA
ns
ns
ns
ns
1
1
1
1
2(tKC)
0
2(tKC)
NOTE: 1. This parameter is sampled.
SNOOZE MODE WAVEFORM
CLK
t
ZZ
t
RZZ
ZZ
t
ZZI
I
SUPPLY
I
ISB2Z
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1.p65 – Rev 12/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
18
PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
3
READ TIMING
t
KC
CLK
t
t
KL
KH
t
t
ADSH
ADSS
ADSP#
ADSC#
t
t
ADSH
ADSS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address.
t
t
WH
WS
GW#, BWE#,
BWa#-BWd#
Deselect (NOTE 4)
cycle.
t
t
CEH
CES
CE#
(NOTE 2)
t
t
AAH
AAS
ADV#
OE#
ADV# suspends burst.
t
t
OEQ
KQ
(NOTE 3)
High-Z
t
t
KQHZ
t
t
t
OELZ
KQLZ
OEHZ
KQX
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A3)
Q(A1)
Q
t
KQ
Burst wraps around
to its initial state.
(NOTE 1)
Single READ
BURST READ
DON’T CARE
UNDEFINED
READ TIMING PARAMETERS
-5
-6
-7.5
-10
-5
-6
-7.5
-10
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
t
t
t
t
t
t
t
t
t
KC
5
6.0
7.5
10
ns
MHz
ns
AS
1.3
1.3
1.3
1.3
1.3
0.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
f
KF
200
2.8
166
3.5
133
4.0
100
5.0
ADSS
AAS
WS
t
KH
2
2
2.3
2.3
2.5
2.5
3.0
3.0
t
KL
ns
t
KQ
ns
CES
t
KQX
1
0
1.5
0
1.5
0
1.5
1.5
ns
AH
t
KQLZ
ns
ADSH
AAH
WH
CEH
t
KQHZ
2.8
2.8
3.5
3.5
4.2
4.2
5.0
5.0
ns
t
OEQ
ns
t
OELZ
0
0
0
0
ns
t
OEHZ
2.8
3.5
4.2
4.5
ns
NOTE: 1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q
to be driven until after the following clock rising edge.
4. Outputs are disabled within two clock cycles after deselect.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1.p65 – Rev 12/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
19
PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
WRITE TIMING
t
KC
CLK
t
t
KL
KH
t
t
ADSH
ADSS
ADSP#
ADSC# extends burst.
t
t
ADSH
ADSS
t
t
ADSH
ADSS
ADSC#
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP# initiates burst.
t
WS
t
WH
BWE#,
BWa#-BWd#
(NOTE 5)
t
t
WH
WS
GW#
t
t
CEH
CES
CE#
(NOTE 2)
t
AAS
t
AAH
ADV#
OE#
ADV# suspends burst.
(NOTE 4)
D(A2)
(NOTE 3)
t
t
DH
DS
D
Q
D(A2 + 1)
(NOTE 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE UNDEFINED
WRITE TIMING PARAMETERS
-5
-6
-7.5
-10
-5
-6
-7.5
-10
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
t
t
t
t
t
t
t
KC
5
6.0
7.5
10
ns
MHz
ns
DS
1.3
1.3
0.5
0.5
0.5
0.5
0.5
0.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
f
KF
200
2.8
166
3.5
133
4.2
100
4.5
CES
AH
t
KH
2
2
2.3
2.3
2.5
2.5
3.0
3.0
t
KL
ns
ADSH
AAH
WH
DH
t
OEHZ
ns
t
AS
1.3
1.3
1.3
1.3
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0
ns
t
ADSS
ns
t
AAS
ns
CEH
t
WS
ns
NOTE: 1. D(A2) refers to input for address A2. D(A2 + 1) refers to input for the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/
output data contention for the time period prior to the byte write enable inputs being sampled.
4. ADV# must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW# LOW; or by GW# HIGH, BWE# LOW and BWa#-BWb# LOW for x18 device;
or GW# HIGH, BWE# LOW and BWa#-BWd# LOW for x32 and x36 devices.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1.p65 – Rev 12/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
20
PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
6
READ/WRITE TIMING
t
KC
CLK
t
t
KL
KH
t
t
ADSH
ADSS
ADSP#
ADSC#
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WH
WS
BWE#,
BWa#-BWd#
(NOTE 4)
t
t
CEH
CES
CE#
(NOTE 2)
ADV#
OE#
t
t
DH
t
KQ
DS
t
OELZ
D
Q
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
KQLZ
(NOTE 1)
Q(A4)
Q(A1)
Q(A2)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back READs
(NOTE 5)
Single WRITE
BURST READ
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
WRITE TIMING PARAMETERS
-5
-6
-7.5
-10
-5
-6
-7.5
-10
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
KC
5
6.0
7.5
10
ns
MHz
ns
ADSS
1.3
1.3
1.3
1.3
0.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
f
t
KF
200
2.8
2.8
166
3.5
3.5
133
4.0
4.2
100
5.0
4.5
WS
t
t
KH
2
2
2.3
2.3
2.5
2.5
3.0
3.0
DS
t
t
KL
ns
CES
t
t
KQ
ns
AH
t
t
KQLZ
0
0
0
0
0
0
1.5
0
ns
ADSH
t
t
OELZ
ns
WH
t
t
OEHZ
ns
DH
t
t
AS
1.3
1.5
1.5
2.0
ns
CEH
NOTE: 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed.
4. GW# is HIGH.
5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
6. Timing is shown assuming that the device was not enabled before entering into this sequence.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1.p65 – Rev 12/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
21
PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
100-PIN PLASTIC TQFP (JEDEC LQFP)
PIN #1 INDEX
+0.06
0.32
-0.10
+0.10
-0.15
0.65
22.10
20.10 ±0.10
DETAIL A
1.50 ±0.10
0.25
0.10
14.00 ±0.10
+0.20
-0.05
16.00
GAGE PLANE
1.40 ±0.05
0.60 ±0.15
DETAIL A
MAX
MIN
NOTE: 1. All dimensions in millimeters
or typical where noted.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1.p65 – Rev 12/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
22
PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
119-PIN BGA
22.00 ±0.20
19.94 ±0.10
Substrate material:
BT resin laminate
0.60 ±0.10
0.90 ±0.10
14.00 ±0.10
11.94 ±0.10
0.15
2.40 MAX
SEATING PLANE
A1 CORNER
A1 CORNER
(dimension applies to a
noncollapsed solder ball)
0.75 ±0.15
Ø
1.27 (TYP)
7.62
1.27 (TYP)
20.32
MAX
NOTE: 1. All dimensions in millimeters
or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
3. Solder ball land pad is 0.6mm.
8000 S. Fe d e ra l Wa y, P.O. Bo x 6, Bo ise , ID 83707-0006, Te l: 208-368-3900
E-m a il: p ro d m kt g @m icro n .co m , In t e rn e t : h t t p ://w w w .m icro n .co m , Cu st o m e r Co m m e n t Lin e : 800-932-4992
Micron is a registered trademark and SyncBurst is a trademark of Micron Technology, Inc.
Pentium is a registered trademark of Intel Corporation.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1.p65 – Rev 12/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
23
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