S6BT112A02SSBB002 [CYPRESS]
Interface Circuit,;
| 型号： | S6BT112A02SSBB002 |
| 厂家： | 
CYPRESS |
| 描述： | Interface Circuit, 接口集成电路 |
| 文件： | 总38页 (文件大小：1373K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S6BT112A01/S6BT112A02
ASSP CXPI Transceiver IC for
Automotive Network
The S6BT112A01 and S66BT112A02 are integrated transceiver ICs for automotive communication network with Clock Extension
Peripheral Interface (CXPI). It has a flexible bit rate ranging from 2.4 Kbps to 20 Kbps and is JASO CXPI compliant. This CXPI
transceiver IC connects the CXPI data link controller and the CXPI Bus line, and enables direct connection to the vehicle battery
with a high surge protection. Additionally, these devices have an optional Spread Spectrum Clock Generator (SSCG) function.
During Sleep mode, S6BT112A01 and S6BT112A02 reduce power consumption. The Cypress CXPI transceiver IC supports master
node and slave node as selected SELMS pins.
Features
Compliant with the JASO CXPI (JASO D 015-3-15) standard
Compliant with the SAE CXPI ( J3076_201510) standard
Supports 2.4 Kbps to 20 Kbps bitrate
Overtemperature protection
Low-voltage detection.
Supports Sleep and Wakeup modes
Sleep mode current: 6 µA (typical at Slave)
Halogen-free 8-pin SOIC package
Waveshaping for low Electromagnetic Interference (EMI)
Operating voltage range: 5.3 V to 18 V
Direct battery operation with protection against load dump,
jump start, and transients
ESD protection HBM (1.5 kΩ, 100 pF) ±8 kV (BUS pin, BAT
pin)
BUS short to VBAT overcurrent protection.
Voltage tolerance ±40 V (BUS pin)
Loss of ground protection; BUS pin leakage is lower than
±1 mA.
S6BT112A01: With SSCG.
S6BT112A02: Without SSCG.
Easy selection of master node or slave node.
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Document Number: 002-10203 Rev.*C
Revised December 9, 2016
S6BT112A01/S6BT112A02
S6BT112A Block Diagram
Document Number: 002-10203 Rev.*C
Page 2 of 38
S6BT112A01/S6BT112A02
Table of Contents
Features
............................................................................................................................................................. 1
S6BT112A Block Diagram...................................................................................................................................................... 2
1. Applications
............................................................................................................................................................. 4
............................................................................................................................................................. 5
2. Pin Assignment
3. Pin Descriptions ............................................................................................................................................................. 6
4. Block Diagram ............................................................................................................................................................. 7
5. Function Description.......................................................................................................................................................... 8
5.1
5.2
Operation Modes........................................................................................................................................................... 8
Master Node.................................................................................................................................................................. 9
5.2.1 Normal Mode.................................................................................................................................................................. 9
5.2.2 Sleep Mode.................................................................................................................................................................. 10
5.2.3 Standby Mode.............................................................................................................................................................. 11
5.2.4 Power-on Sequence..................................................................................................................................................... 11
5.3
Slave Node.................................................................................................................................................................. 12
5.3.1 Normal Mode................................................................................................................................................................ 12
5.3.2 Sleep Mode.................................................................................................................................................................. 13
5.3.3 Standby Mode.............................................................................................................................................................. 15
5.3.4 Power-on Sequence..................................................................................................................................................... 15
5.4
Common Functions ..................................................................................................................................................... 16
5.4.1 Overtemperature Protection......................................................................................................................................... 16
5.4.2 WP_ThermalShutdown ................................................................................................................................................ 16
5.4.3 Low-voltage Reset ....................................................................................................................................................... 17
5.4.4 Overcurrent Protection................................................................................................................................................. 18
5.4.5 Secondary Clock Master.............................................................................................................................................. 18
5.4.6 Arbitration..................................................................................................................................................................... 20
5.4.7 TXD Toggle.................................................................................................................................................................. 21
6. Absolute Maximum Ratings............................................................................................................................................. 23
7. Recommended Operating Conditions ............................................................................................................................ 24
8. Electrical Characteristics................................................................................................................................................. 25
9. Ordering Information........................................................................................................................................................ 36
10. Package Dimensions...................................................................................................................................................... 36
Document History
........................................................................................................................................................... 37
Sales, Solutions, and Legal Information............................................................................................................................. 38
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S6BT112A01/S6BT112A02
1. Applications
The following figures illustrate the typical applications of S6BT112A01 or S6BT112A02.
S6BT112A AS MASTER
12V Battery
CXPI BUS LINE
BAT
Regulator
S6BT112A: CXPI Transceiver IC
RC
LDO Regulator
OSC
5 V
VCC
Thermal Shutdown
Low Voltage Detection
Over Current Protection
SELMS
MCU
CLK
TXD
CXPI
Control
Logic
UART
RXD
NSLP
VSS
BUS
CXPI
PHY
GND
S6BT112A AS SLAVE
12V Battery
CXPI BUS LINE
BAT
Regulator
S6BT112A: CXPI Transceiver IC
RC
LDO Regulator
OSC
5 V
VCC
Thermal Shutdown
Low Voltage Detection
Over Current Protection
SELMS
MCU
CLK
TXD
CXPI
Control
Logic
UART
RXD
NSLP
VSS
BUS
CXPI
PHY
GND
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S6BT112A01/S6BT112A02
2. Pin Assignment
Figure 2-1 Pin Assignment
(TOP VIEW)
RXD
SELMS
1
2
3
4
8
7
6
5
BAT
BUS
GND
NSLP
CLK
TXD
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S6BT112A01/S6BT112A02
3. Pin Descriptions
Table 3-1 Pin Descriptions
Pin
Symbol
Number
Direction
Description
Receive data output (open-drain).
1
2
RXD
Output
Requires external pull-up resistor. (refer to Table 7-1 )
Sleep control input.
Low: Sleep mode or Standby mode
High: Normal mode.
NSLP
Input
Refer to section 5.2.2 or section 5.3.2
When the SELMS pin is Low, the CLK pin is the Baud rate clock input.
Input clock signal with baud rate frequency.
(When the input clock frequency is 20 kHz, the bit rate is 20 Kbps)
When the SELMS pin is High, the CLK pin is Baud rate clock output.
Outputs clock signal with baud rate frequency.
(When the output clock frequency is 20 kHz , the bit rate is 20 Kbps)
Open drain output.
3
CLK
I/O
Requires external pull-up resistor. (refer to Table 7-1)
Transmit data input
4
5
6
7
TXD
GND
BUS
BAT
Input
Ground
-
I/O
-
CXPI BUS line Input/Output
Battery (voltage source) supply.
Master / slave node select input.
8
SELMS
Input
Low: Master
High: Slave
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S6BT112A01/S6BT112A02
4. Block Diagram
Figure 4-1 Block Diagram
RXD
SELMS
BAT
Filter
Power On Rest
Low Voltage
RPU_TXD
BUS
NSLP
Control logic
CLK
TXD
Waveform Shaping
RPD_NSLP
Thermal Shutdown
GND
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S6BT112A01/S6BT112A02
5. Function Description
5.1 Operation Modes
Figure 5-1 State Transition Diagram
Notes
[1] : “Hi-z” means high-impedance.
[2] : Switching of the master / slave during operation is prohibited. Refer to section 5.4.5.
[3] : The operation mode, after the transceiver powers on, has to start from sleep mode.
[4] : If TXD is Low when releasing the thermal shutdown, TXD has to toggle "High" before valid.
TXD is a Low signal input. For details, refer to section 5.4.7.
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S6BT112A01/S6BT112A02
5.2 Master Node
There is only one node in a system, which functions as a schedule manager and a primary clock master.
The transceiver works in Master mode when low-level is applied on SELMS.
The baud rate clock is applied on the CLK pin in the Master state.
The transceiver is usually used as the "Master" or "Slave", except for the “Secondary Clock master function”.
The SELMS input should not be changed in normal mode.
The SELMS input should not be changed during wakeup pulse transmission in Sleep mode.
The CLK pin inputs for the baud rate clock in Master state.
Table 5-1 SELMS Pin State for Master
Pin
Input Signal
Master/Slave
SELMS
Low
Master
Figure 5-2 CLK Input -> BUS signal (Master)
5.2.1
Normal Mode
The Normal mode denotes the state to which communication is possible. The master node transmits the clock to the CXPI BUS,
which means that the clock is master. During the Normal mode, the transmitted signal is encoded and the received signal is
decoded. When the transmitting node transmits data to the CXPI BUS, it transmits to the TXD pin after converting the data to UART
format by 1 byte. The data is transmitted to the CXPI BUS as LSB first.
When the receiving node receives data from the CXPI BUS, it receives from the RXD pin in the UART format by 1 byte. The UART
format is listed in Table 5-2. Refer to the JASO CXPI (JASO D 015-3:2015) standard for details of the operation.
Table 5-2 UART Format
Start bit bit 0 (LSB) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7(MSB) Stop bit
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5.2.2
Sleep Mode
The Sleep mode denotes a power-saving state during which each node stops transmitting and receiving data. All nodes transition to
Sleep mode immediately after power-on. The nodes also transition to Sleep mode after the Sleep processing is executed from the
Normal mode and transition from Standby mode or Normal mode due to CXPI BUS error.
When each node receives the Wakeup factor during the Sleep mode, it transitions to the Standby mode.The Wakeup factor (for
example, detecting that the ignition has been turned on) of each node is different from each application (for example, detecting that
the ignition has been turned on) and the external factor that receives the Wakeup pulse from the CXPI BUS. During the Sleep mode,
the reception signal is received without decoding. The MCU can detect a wakeup pulse width monitor using the RXD signal.
The sleep mode is initiated by a falling edge on the NSLP pin while TXD is already set High. The CXPI BUS transmit path is
immediately disabled when the NSLP pin goes Low. All wake-up events must be maintained for a specific period (refer to the
TMODE_CHG parameter in Table 8-7).
Table 5-3 Transition from Normal to Sleep mode
Pin
TXD
Pin State
High
Description
No data transmitting
CLK
High
No clock receiving
NSLP
RXD
High to Low
High impedance
High impedance
Low
-
High level with external pull-up resistor.
BUS
High level with external pull-up resistor.
-
SELMS
Note: The “Pin State” indicates before the falling edge in the NSLP pin
Table 5-4 Transition from Sleep to Normal mode
Pin
TXD
Pin State
High
Description
No data transmitting
CLK
High
No clock receiving
NSLP
RXD
Low to High
High impedance
High impedance
Low
-
High level with external pull-up resistor.
BUS
High level with external pull-up resistor.
-
SELMS
Note: The “Pin State” indicates the state before the rising edge in the NSLP pin
Figure 5-3 Transition Sequence Between Sleep and Normal Mode
Note:
[1] “Hi-Z” means high-impedance.
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S6BT112A01/S6BT112A02
Table 5-5 Bitrate of 20 Kbps (50 µs/Bit)
UART Receive Data Number of Bits of L Level Wakeup Pulse Width
FCH
F8H
F0H
E0H
C0H
80H
00H
3-bit
4-bit
5-bit
6-bit
7-bit
8-bit
9-bit
150 µs
200 µs
250 µs
300 µs
350 µs
400 µs
450 µs
5.2.3
Standby Mode
The Standby mode denotes the prepared state to the Normal mode after releasing the Sleep mode. During the CLK state (in slave
node), the RXD pin and the BUS pin are in a high-impedance state. After TMODE_CHG, the state changes to the Normal mode.
5.2.4
Power-on Sequence
The power-on sequence occurs at power-up while setting up Sleep mode. When VBAT is above 5.3 V, the NSLP pin should be in a
High state. After transition to the normal mode, activate the BUS pin after a clock input of 33 periods.
Figure 5-4 Power-on Sequence of Master Node
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S6BT112A01/S6BT112A02
5.3 Slave Node
All the nodes, except the master node, are connected with the system. The transceiver works as Slave when High level is applied on
SELMS. The CLK pin outputs the baud rate clock during the Slave state.
The transceiver is usually used as the "Master" or "Slave", except for the “Secondary Clock master function”.
Table 5-6 SELMS Pin State for Slave
Pin
Input Signal
Master/Slave
SELMS
High
Slave
The SELMS input should not be changed during the Normal mode or during wakeup pulse transmission in the Sleep mode. The
CLK pin outputs the baud rate clock in Slave node.
Figure 5-5 CLK Pin Clock Output (Slave)
5.3.1
Normal Mode
The Normal mode can perform data transmit and receive. During the Normal mode, the signal that is transmitted is encoded and the
signal that is received is decoded. When the transmitting node transmits data to the CXPI BUS, it transmits to the TXD pin after
converting the data to UART format by 1 byte. The data is transmitted to the CXPI BUS by LSB first. When the receiving node
receives data from the CXPI BUS , it revises from the RXD pin in the UART format by 1 byte. The UART format is shown in Table 5-7.
Refer to the JASO CXPI (JASO D 015-3:2015) standard for details of the operation.
Table 5-7 UART Format
Start bit bit 0 (LSB) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7(MSB) Stop bit
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S6BT112A01/S6BT112A02
5.3.2
Sleep Mode
The Sleep mode denotes a state of power saving during which each node stops transmit and receive of data. All nodes transition to
the Sleep mode immediately after power-on. They also transition to the Sleep mode after the sleep processing is executed from the
Normal mode and transition from the Standby mode or the Normal mode due to CXPI BUS error.
During the Sleep mode, when each node receives the Wakeup factor, it transitions to the Standby mode. The Wakeup factor is
different from each application and is composed of the internal factor (for example, detecting that the ignition has been turned on)
and the external factor that receives the Wakeup pulse from the CXPI BUS.
During the Sleep mode, the reception signal is received without decoding. The sleep mode is initiated by a falling edge on the NSLP
pin while the TXD pin is already set High. The CXPI BUS transmit path is immediately disabled when the NSLP pin goes Low.
All wake-up events must be maintained for a specific period (refer to TMODE_CHG in Table 8-7).
Figure 5-6 Transition Sequence Between Sleep and Normal Mode
Table 5-8 Transition from Normal to Sleep mode
Pin
TXD
Pin State
High
Description
No data transmitting
CLK
High impedance
High to Low
High impedance
High impedance
High
High level with external pull-up resistor.
NSLP
RXD
-
High level with external pull-up resistor.
BUS
High level with external pull-up resistor.
-
SELMS
Note: The “Pin State” indicates the state before the falling edge of the NSLP pin.
Table 5-9 Transition from Sleep to Normal mode
Pin
TXD
Pin State
High
Description
No data transmitting
CLK
High impedance
Low to High
High impedance
High impedance
High
High level with external pull-up resistor.
NSLP
RXD
-
High level with external pull-up resistor.
BUS
High level with external pull-up resistor.
-
SELMS
Note: The “Pin State” indicates the state before the rising edge of the NSLP pin.
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S6BT112A01/S6BT112A02
■Receiver function in Sleep mode
During the Sleep mode, the received signal will be output from the CLK pin without decoding a received signal. The RXD pin outputs
at High level. When the Master node transmits the encoded PWM clock signal to the CXPI BUS during a wake-up sequence, Slave
MCUs receive shorter low-level width signals than the UART communication period and possibly get errors. This is because the
Slave node is received without decoding. To avoid these errors, S6BT112A01 or S6BT112A02 CXPI transceiver IC outputs receive
signals on the CLK pin in the Sleep mode.
MCU can detect a wake-up pulse width to monitor the CLK signal. (Figure 5-7)
Figure 5-7 CLK Output of Receive Signal、RXD stays High (for Slave node)
■Wakeup function
The WakeupPulseOutput state transmits out the wakeup pulse in the Slave node. When the slave device returns from the Sleep
mode, it must transmit a wake-up pulse. As the NSLP pin is in a Low state, the TXD pin transmits a Low state. The TXD signal is
transmitted to the BUS pin without encode. The TXD pin outputs the signal width, which is a value obtained by subtracting the
TTXD_BT
:
Signal width = TXD signal (“L”) – TTXD_BT(“L”)
Figure 5-8 Wake-Up Pulse Transmission
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S6BT112A01/S6BT112A02
5.3.3
Standby Mode
This is the standby state during the Normal mode after releasing the Sleep mode. During this state, CLK (in slave node), the RXD
pin, and the BUS pin enter the high-impedance state. After "TMODE_CHG," this state changes to the Normal mode.
5.3.4
Power-on Sequence
This sequence occurs at power-up, while setting up the Sleep mode. When VBAT is above 5.3 V, the NSLP pin should be in a High
state.
Figure 5-9 Power-on Sequence of Slave Node
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S6BT112A01/S6BT112A02
5.4 Common Functions
5.4.1 Overtemperature Protection
The overtemperature protection (OTP) monitors the die temperature. If the junction temperature exceeds the shutdown junction
temperature, TSD_H, the thermal protection circuit disables the output driver.
The driver is enabled again when the junction temperature falls below TSD_L and theTXD pin is toggled. (see Table 5-10)
5.4.2
WP_ThermalShutdown
The WP_ThermalShutdown state detects the "shutdown temperature" during the WakeupPulseOutput mode. The overtemperature
protection is inactive during the Sleep mode.
Table 5-10 Input Signal Change after Recovery from thermal shutdown
Master/Slave
Master
Pin
TXD
TXD
Toggle of Input Signal
Required
Required
Slave
Table 5-11 State Under Thermal Shutdown
Master/Slave
Pin
Description
TXD
Normal function
High: Normal mode / Low: Sleep mode (Thermal protection inactive)
NSLP
CLK(input)
RXD
Normal function
Master
Normal function
BUS
High impedance
Normal function
TXD
High: Normal mode / Low: Sleep mode (Thermal protection inactive)
NSLP
CLK
Slave
Normal function
Normal function
High impedance
RXD
BUS
Figure 5-10 Sequence of Thermal Shutdown
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S6BT112A01/S6BT112A02
5.4.3
Low-voltage Reset
The low-voltage reset state detects the low voltage of the BAT pin. This device has an integrated power-on reset and low-voltage
detection at the supply BAT.
If the supply voltage, VBAT, is dropping below the power-on reset level (that is, VBAT<VPOR_L), then change the LowPowerReset mode.
In the LowPowerReset mode, the output stage is disabled and communication to the CXPI BUS is not possible.
If the power supply reaches a higher level than the low-voltage reset level, VBAT> VPOR_H, then change the Standby mode (the NSLP
pin is High) or Sleep mode (the NSLP pin is Low).
After releasing LowPowerRest mode, enable the Power-up sequence.
Table 5-12 Input Signal Change after Recovery from Low Voltage Reset
Master/Slave
Master
Pin
TXD
TXD
Toggle of Input Signal
Required
Required
Slave
Table 5-13 State Under Low voltage Reset
Master/Slave
Pin
Description
SELMS
Reset
Reset
Reset
TXD
NSLP
CLK
Master
Reset(High impedance)
High impedance
RXD
BUS
High impedance
SELMS
TXD
Reset
Reset
Reset
NSLP
Slave
Reset(High impedance)
High impedance
CLK
RXD
BUS
High impedance
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S6BT112A01/S6BT112A02
Figure 5-11 Low-Voltage Detection
After releasing the low-voltage reset mode, the logical value high is output to the BUS pin after a clock input of 33 periods. The TXD
data is valid from the falling edge on the TXD pin.
5.4.4
Overcurrent Protection
The current in the transmitter output stage is limited to protect the transmitter against short-circuit to BAT or GND pins.
Table 5-14 Overcurrent Protection
Master/Slave
Pin
Description
Normal function
TXD
NSLP
CLK
Normal function
Master
Normal function
Normal function
RXD
BUS
TXD
NSLP
CLK
Output current limited by IBUS_LIM
Normal function
Normal function
Normal function
Slave
Normal function
RXD
BUS
Output current limited by IBUS_LIM
5.4.5
Secondary Clock Master
The node that detects the wakeup event transmits the wakeup pulse on to the CXPI BUS. If the primary clock master cannot
transmit the clock to the CXPI BUS due to failure, the wakeup pulse is retransmitted. If the clock is not transmitted to the CXPI BUS,
each node detects the CXPI BUS error.
The secondary clock master may transmit the clock to the CXPI BUS instead of the primary clock master if it detects that the clock
does not exist, and confirms that the clock does not exist on the CXPI BUS for the period during which it transitions from the Sleep
mode
■Operation sequence from master to slave
The TXD input pin is set High and the CLK pin is high-impedance. A Low setting on the NSLP pin initiates a transition to the Sleep
mode. After the RXD pin is confirmed to High state, the SELMS pin goes to High state. Table 5-15 shows the pin states just before
the SELMS pin input signal change.
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Table 5-15 Pin State Table (from Master to Slave)
Pin Pin State Description
TXD High No data transmitting
CLK
High impedance
Low
High level with external pull-up resistor.
NSLP
SELMS
RXD
Sleep mode
Low to High
High
-
No data receiving
BUS
High
No wakeup signal receiving preferred
Figure 5-12 Application example Secondary Clock Master
S6BT112A AS SLAVE (SECONDARY CLOCK MASTER )
12V Battery
CXPI BUS LINE
BAT
Regulator
S6BT112A: CXPI Transceiver IC
RC
LDO Regulator
OSC
5 V
VCC
Thermal Shutdown
Low Voltage Detection
Over Current Protection
SELMS
MCU
CLK
TXD
CXPI
Control
Logic
UART
RXD
NSLP
VSS
BUS
CXPI
PHY
GND
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S6BT112A01/S6BT112A02
Figure 5-13 Transition Sequence from Master to Slave
■Operation sequence from slave to master
The TXD pin inputs high and the slave node transitions to the Sleep mode after the CLK pin was confirmed to High, and the SELMS
pin goes to Low.
Table 5-16 Pin State Table (from Slave to Master)
Pin
TXD
Pin State
High
Description
No data transmitting
CLK
High impedance
Low
No wakeup signal receiving
NSLP
SELMS
RXD
Sleep mode
High to Low
High
-
-
BUS
High
No wakeup signal receiving preferred
Note: The pin states just before the SELMS input signal change.
Figure 5-14 Transition Sequence from Slave to Master
5.4.6
Arbitration
Transceivers arbitrate bit-by-bit. Arbitration in bytes is done in the MCU.
In the Normal mode, each node always compares the received bit from the CXPI BUS with the transmitted bit to the CXPI BUS.
When the value of the bit is corresponding, the node may continuously transmit to the CXPI BUS. When the value of the bit is not
corresponding, the loss of arbitration is detected, and the transmission of the bit after that shall discontinue. If the transmitting node
detects the arbitration loss, it behaves as the receiving node. The data of each bit transmitted on the CXPI BUS performs arbitration
from the start by the bit. Moreover, arbitration is targeted at the entire field of the frame. When two or more nodes begin transmitting
at the same time, by arbitration only the node that transmits the highest priority frame can complete the transmission.
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The MCU compares between the transmitted data (TXD) and received data (RXD). If the data difference is detected, MCU has to
stop data transmission until finding IFS.
5.4.7
TXD Toggle
If the TXD pin is short to ground or open, the BUS pin output is not fixed Low (logic value). Therefore, it does not interfere with the
communication of the other device.
An initial TXD dominant check prevents the bus line being driven to a permanent dominant state (blocking all network
communications) if the TXD pin is forced permanently Low by a hardware and/or software application failure. The TXD input level is
checked after a transition to the Normal mode.
If the TXD pin is Low, the transmit path remains disabled and is only enabled when the TXD pin goes High.
A TXD toggle is required in the following cases.
Data transmission after recovery from low-voltage reset.
Data transmission after recovery from thermal shutdown.
First TXD data transmission in the Normal mode.
First wake-up pulse transmission in sleep mode.
■Short-circuit from the TXD pin to ground.(failure detect)
In the event of a short-circuit to ground or an open-wire on the TXD pin, the BUS pin output remains High (logical value ‘1’) by this
toggle function. In this case, by comparing the sent data to the TXD pin and received data from the RXD pin of the transceiver IC,
the MCU can detect the permanent Low on the TXD pin by the data difference. In this case too, the receiver is active.
Figure 5-15 Normal Transmission Sequence of Master
Figure 5-16 TXD Toggle of Master after Transition to Normal mode
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Figure 5-17 Slave TXD Toggle after Recovery from Low voltage State
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6. Absolute Maximum Ratings
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or
temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.
Rating
Parameters
Symbol
VBAT
Conditions
BAT pin
Unit
V
Min
Max
-0.3
40
Power supply voltage
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-40
6.9
18
V
VNSLP
VSELMS
VCLK
NSLP pin
SELMS pin
CLK pin
TXD pin
RXD pin
CLK pin
BUS pin
V
Input voltage
6.9
6.9
6.9
6.9
40
V
V
VTXD
VRXD
VCLK
V
Output voltage
V
V
BUS pin voltage
VBUS
BUS pin ESD
-8
-8
8
8
kV
kV
VESDBUS
BUS pin
BAT pin
(1.5 kΩ, 100 pF)
BAT pin ESD
VESDBAT
(1.5 kΩ, 100 pF)
NSLP pin
SELMS pin
CLK pin
ESD
-2
2
kV
VESD
(1.5 kΩ, 100 pF)
TXD pin
RXD pin
-55
-40
150
150
°C
°C
Storage temperature
TSTG
-
-
Maximum
TJMAX
junction temperature
Document Number: 002-10203 Rev.*C
Page 23 of 38
S6BT112A01/S6BT112A02
7. Recommended Operating Conditions
Table 7-1 Recommended condition
Value
Unit
Parameters
Symbol
Conditions
Min
Typ
Max
Power supply voltage
BAT pin [1]
VBAT
TA
5.3
-
18
V
Operating ambient temperature
BUS pin pull-up resistance
RXD pin pull-up resistance
CLK pin pull-up resistance
-
－40
+25
+125
°C
RMASTER
RRXD
BUS pin (Master node：SELMS=0V)
RXD pin
900
2.4
2.4
1000
10
1100
Ω
-
-
kΩ
kΩ
RCLK
CLK pin (SELMS=5V)
10
Note
[1]: (18 V < VBAT ≤ 27 V) less than 2 minutes.
WARNING:
1. The recommended operating conditions are requiredir to ensure the normal operation of the semiconductor device. All of the
device's electrical characteristics are warranted when the device is operated under these conditions.
2. Any use of semiconductor devices will be under their recommended operating condition.
3. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device
failure.
4. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you
are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
Document Number: 002-10203 Rev.*C
Page 24 of 38
S6BT112A01/S6BT112A02
8. Electrical Characteristics
Table 8-1 DC Characteristics
VBAT = 5.3 V~27 V[1], TA = -40~125 °C; All voltages are referenced to Pin 8 (GND); Positive currents flow into the IC; unless
otherwise specified.
Pin
Name
Parameters
Symbol
Conditions
Min
Typ
Max
Unit
Normal mode
-
1.4
2.9
mA
TXD=5 V
CLK=20 kHz, Duty 50%
Normal mode
-
-
2.0
4.0
mA
µA
TXD=0 V
CLK=20 kHz, Duty 50%
Sleep mode
VBAT =12 V
TXD=5 V
6
-
SELMS=5 V
BUS= VBAT
TA=25 °C
Sleep mode
VBAT =12 V
TXD=5 V
Power supply current
IBAT
BAT
-
16
-
µA
SELMS=0 V
BUS= VBAT
TA=25 °C
Sleep mode
VBAT =12 V
TXD=5 V
-
-
-
-
50
60
µA
µA
SELMS=5 V
BUS= VBAT
Sleep mode
VBAT =12 V
TXD=5 V
SELMS=0 V
BUS= VBAT
BUS pin pull-up
resistance
RBUSpu
BUS
BUS
20
40
30
-
47
kΩ
-
BUS short circuit
current
IBUS_LIM
200
mA
VBUS=18 V
Document Number: 002-10203 Rev.*C
Page 25 of 38
S6BT112A01/S6BT112A02
Pin
Name
Parameters
Symbol
Conditions
BUS=18 V
Min
Typ
Max
Unit
BUS input leak current
(HIGH)
VBAT =5.3 V
TXD=5 V
TA=25 °C
IBUS_PAS_rec
BUS
BUS
-
-
20
µA
BUS=0 V
VBAT =12 V
TXD=5 V
BUS input leak current
(LOW)
IBUS_PAS_dom
-1
-
-
mA
loss of ground BUS
leak current
VBAT =GND=18 V
BUS=0 V
IBUS_NO_GND
IBUS_NO_BAT
VBUSDR
BUS
BUS
BUS
-1
-
-
-
-
1
mA
µA
V
VBAT =0 V
BUS=18 V
TA=25 °C
loss of battery BUS
leak current
30
5.7
VBAT =13.5 V
IBUSsource=-100 µA
BUS drop voltage
2.4
TXD=0 V
VBAT =7 V
BUS pull-up resistance=
500 Ω
VO_dom
BUS
BUS
-
-
-
1.4
2
V
V
BUS low level output
voltage
TXD=0 V
VBAT =18 V
BUS pull-up resistance=
500 Ω
VO_dom
-
-
Receiver low level
threshold voltage
0.423
VBAT
VBUSdom
VBUSrec
VHYS
BUS
BUS
BUS
BAT
-
-
V
V
V
V
VBAT =12V, TA=25 °C
VBAT =12V, TA=25 °C
VBAT =12V, TA=25°C
-
Receiver high level
threshold voltage
0.556
VBAT
-
Receiver hysteresis
voltage
0.133
VBAT
-
-
Low level power-on
reset threshold voltage
VPOR_L
3.1
3.8
4.7
High level power-on
reset threshold
voltage
VPOR_H
BAT
3.3
4.1
4.9
V
-
power-on reset
hysteresis voltage
VPOR_HYS
TSD_H
BAT
0.2
156
151
0.3
165
159
0.5
174
168
V
-
Temperature shutdown
threshold
-
-
°C
°C
[2]
[2]
Temperature shutdown
release threshold
TSD_L
Notes
[1]: (18 V < VBAT ≤ 27 V) less than 2 minutes.
[2]: Guaranteed by design
Document Number: 002-10203 Rev.*C
Page 26 of 38
S6BT112A01/S6BT112A02
Table 8-2 DC Characteristics CLK Pin
(If SELMS = 5 V, this pin operates as Open Drain Output Pin. If SELMS = 0 V, this pin operates as an input pin)
VBAT = 5.3 V～27 V[1], TA = -40～125 °C; all voltages are referenced to Pin 8 (GND). Positive current flow into the IC; unless
otherwise specified.
Pin
Name
Parameters
Symbol
Conditions
Min
Typ Max
Unit
VIH_CLK
CLK
2
-
-
-
6
V
High level input voltage
SELMS = 0 V
VIL_CLK
CLK
CLK
-0.3
0.8
0.5
V
V
Low level input voltage
SELMS = 0 V
SELMS = 0 V
VHYS_CLK
0.03
Hysteresis range of input voltage
ICLK = 2.2 mA
SELMS = 5 V
VOL_CLK
CLK
-
-
0.6
V
Low level output voltage
IOL_CLK
IILH_CLK
IILL_CLK
CLK
CLK
CLK
1.3
-3
3
-
-
mA
µA
µA
Low level current
SELMS = 5 V
SELMS = 5 V
SELMS = 5 V
3
3
High level leak current
Low level leak current
-3
-
Note
[1]: (18 V < VBAT ≤ 27 V) less than 2 minutes.
Table 8-3 DC Characteristics NSLP Pin
VBAT = 5.3 V~27 V[1], TA = -40~125 °C; all voltages are referenced to Pin 8 (GND). Positive current flow into the IC; unless otherwise
specified.
Pin
Name
Parameters
Symbol
Conditions
Min
Typ Max
Unit
High level input voltage
VIH_NSLP
NSLP
2
-
6
0.8
0.5
650
3
V
-
-
-
NSLP
NSLP
NSLP
NSLP
Low level input voltage
VIL_NSLP
VHYS_NSLP
RPD_NSLP
IILL_NSLP
-0.3
0.03
100
-3
-
V
V
Hysteresis range of input voltage
Internal pull-down resistance
Low level leak current
-
250
-
kΩ
µA
NSLP = 5 V
NSLP = 0 V
Note
[1]: (18 V < VBAT ≤ 27 V) less than 2 minutes
Document Number: 002-10203 Rev.*C
Page 27 of 38
S6BT112A01/S6BT112A02
Table 8-4 TXD Pin
VBAT = 5.3 V~27 V[1], TA = -40~125 °C; all voltages are referenced to Pin 8 (GND). Positive current flow into the IC; unless otherwise
specified.
Pin
Name
Parameters
Symbol
Conditions
Min
Typ
Max
Unit
VIH_TXD
TXD
2
-
6
V
High level input voltage
-
VIL_TXD
VHYS_TXD
RPU_TXD
IILH_TXD
TXD
TXD
TXD
TXD
-0.3
0.03
50
-
0.8
0.5
325
3
V
V
Low level input voltage
-
-
125
-
Hysteresis range of input voltage
Internal pull-up resistance
High level leak current
-
kΩ
µA
TXD = 0 V
TXD = 5 V
-3
Note
[1]: (18V < VBAT ≤ 27V) less than 2 minutes
Table 8-5 SELMS Pin
VBAT = 5.3 V~27 V[1], TA = -40~125 °C; all voltages are referenced to Pin 8 (GND). Positive current flow into the IC; unless otherwise
specified.
Pin
Name
Parameters
Symbol
Conditions
Min
Typ
Max
Unit
VIH_SELMS
SELMS
2
-
6
V
High level input voltage
-
-
-
SELMS
SELMS
SELMS
SELMS
VIL_SELMS
VHYS_SELMS
RPU_SELMS
IILH_SELMS
-0.3
0.03
200
-3
-
0.8
0.5
1300
3
V
V
Low level input voltage
-
500
-
Hysteresis range of input voltage
Internal pull-up resistance
High level leak current
kΩ
µA
SELMS = 0 V
SELMS = 5 V
Note
[1]: (18 V < VBAT ≤ 27 V) less than 2 minutes.
Document Number: 002-10203 Rev.*C
Page 28 of 38
S6BT112A01/S6BT112A02
Table 8-6 RXD Pin (Open Drain Output)
VBAT = 5.3 V~27 V[1], TA = -40~125 °C; all voltages are referenced to Pin 8 (GND). Positive current flow into the IC; unless otherwise
specified.
Parameters
Symbol
Pin Name
Conditions
Min
Typ
Max
Unit
RXD
Low level output voltage
VOL_RXD
-
-
0.6
V
IRXD = 2.2 mA
RXD
RXD
RXD
Low level current
IOL_RXD
IOLH_RXD
IOLL_RXD
1.3
-3
3
-
-
mA
µA
µA
RXD = 0.4 V
RXD = 5 V
RXD = 0 V
High level leak current
Low level leak current
3
3
-3
-
Note
[1]: (18 V < VBAT≦ 27 V) less than 2 minutes.
Table 8-7 AC Characteristics
VBAT = 5.3 V~27 V[1], TA = -40~125 °C BUS Load 1 kΩ /1 nF; unless otherwise specified.
Pin
Parameters
Bitrate
Symbol
Conditions
Min
Typ
Max
Unit
Name
TBUAD
BUS
2.4
-
20
kbps
VTH(bus) [3] = 0.5VBAT
Mode transition time
(Sleep to Normal or
Normal to Sleep.)
VTH(5v)[4] = 50%
TMODE_CHG
NSLP
-
-
1
ms
CLK
NSLP wait time
VTH(5 V) [4] = 50%
-
TSLP_WT
TSLP_MN
100
1
-
-
-
-
µs
NSLP
Minimum sleep time
NSLP
ms
NLSP = 0 V
Driver boot time under
sleep mode. [2]
SELMS = 5 V
VTH(5v)[4]=50%
VTH(bus)[3]=0.3VBAT
TTXD_BT
TXD
-
-
-
-
195
µs
NLSP = 5 V
SELMS = 0 V
CLK=input clock
TXD=5 V
CLK transmission delay
time
TCLK_PD
CLK
0.9
Tbit[5]
VTH(5v)[4]=50%
VTH(bus)[3]=0.3VBAT
Document Number: 002-10203 Rev.*C
Page 29 of 38
S6BT112A01/S6BT112A02
Pin
Name
Parameters
Symbol
Conditions
NLSP = 5 V
Min
Typ
Max
Unit
SELMS = 0 V
CLK=input clock
TXD=5 V
Time of Low level of
logic value '1'
0.39Tbit
+6τ
Ttx_1_lo_rec
BUS
BUS
-
-
-
VTH(bus)[3] = 0.7VBAT
NLSP = 5 V
SELMS = 0 V
CLK=input clock
TXD=5 V
Time of Low level of
logic value '1'
Ttx_1_lo_dom
0.11
-
-
Tbit
VTH(bus)[3] = 0.3 VBAT
NLSP = 5 V
Ttx_1_lo_rec
+0.06Tbit
Time of Low level of
logic value '0'
Ttx_0_lo_rec
BUS
BUS
-
-
-
-
-
-
TXD = 0 V
VTH(bus) [3] = 0.7 VBAT
NLSP = 5 V
Ttx_1_lo_dom
+0.06Tbit
Time of Low level of
logic value '0'
Ttx_0_lo_dom
TXD=0 V
VTH(bus) [3] = 0.3 VBAT
NLSP = 5 V
TXD = 0 V
VTH(bus)[3]
High level time at
receiving node.
Ttx_0_hi
BUS
RXD
0.06
-
-
-
Tbit
Tbit
=
0.556
VBAT
NSLP = 5 V
VTH(bus)[3]
VBUSdom
Receiver delay time
TRXD_PD
-
2.4
=
Delay time of
transmission if logic
value '0'.
NSLP = 5 V
VTH(bus) [3]=0.3 VBAT
TTXD_PD
TICLK_DY
TOCLK_DY
TXD
CLK
CLK
-
-
-
-
3.3
70
50
Tbit
%
SELMS = 0 V
VTH(5 V)[4] = 50%
Input clock duty
30
14
SELMS = 5 V
VTH(5 V)[4] = 50%
Output clock duty[6]
%
NSLP = 0 V
Wakeup pulse filter
constant(Master)
Trx_wakeup_master
BUS
SELMS = 0 V
30
-
150
µs
VTH(bus) [3]=42.3%
Document Number: 002-10203 Rev.*C
Page 30 of 38
S6BT112A01/S6BT112A02
Pin
Parameters
Symbol
Conditions
NSLP = 0 V
Min
Typ
Max
Unit
Name
Wakeup pulse filter
constant(Slave)
Trx_wakeup_slave
BUS
0.5
-
5
µs
SELMS = 5 V
VTH(bus) [3] = 42.3%
NSLP = 5 V
Time of bus slope from
minimum
SELMS = 0 V
Ttx_1_dom_m
BUS
BUS
-
-
-
0.16
-
Tbit
VBAT = 7V
VTH(bus) [3] = 0.3 VBAT
Recessive level of
logical value ‘0’.
V_rec_0
0.93
V_rec_1
NSLP = 5 V
Notes
[1]: (18 V < VBAT ≤ 27 V) less than 2 minutes
RXD pin load: 20 pF
[2]: CXPI BUS load (Figure 8-11) : 10 nF/500 Ω
[3]: VTH(bus)：threshold of BUS pin
[4]: VTH(5v)：threshold of NSLP,CLK,TXD,SELMS,RXD pins.
[5]: Tbit stands for 1bit time.(Figure 8-1)
[6]: logic '0/1' threshold clock
Figure 8-1 Definition of Tbit
Figure 8-2 Mode Transition Time
Document Number: 002-10203 Rev.*C
Page 31 of 38
S6BT112A01/S6BT112A02
Figure 8-3 NSLP Wait Time
Figure 8-4 Minimum Sleep Time
Figure 8-5 Driver boot Time Under Sleep Mode
Document Number: 002-10203 Rev.*C
Page 32 of 38
S6BT112A01/S6BT112A02
Figure 8-6 CLK Transmission Delay Time
Figure 8-7 Logic low and high CXPI BUS Waveform
Document Number: 002-10203 Rev.*C
Page 33 of 38
S6BT112A01/S6BT112A02
Figure 8-8 Receiver Delay Time
Figure 8-9 Logic low Transmission Delay Time
Document Number: 002-10203 Rev.*C
Page 34 of 38
S6BT112A01/S6BT112A02
Figure 8-10 Wakeup Pulse Waveform
Figure 8-11 CXPI BUS Load Connection
Document Number: 002-10203 Rev.*C
Page 35 of 38
S6BT112A01/S6BT112A02
9. Ordering Information
Part Number
Package
S6BT112A01SSBB002
8-pin 150-mil SOIC Tape and Reel (SOA008)
8-pin 150-mil SOIC Tape and Reel (SOA008)
S6BT112A02SSBB002
10.Package Dimensions
Package Type
Package Code
SOP 8
SOA 008
SIDE VIEW
TOP VIEW
SIDE VIEW
Document Number: 002-10203 Rev.*C
Page 36 of 38
S6BT112A01/S6BT112A02
Document History
Document Title: S6BT112A01/S6BT112A02 ASSP CXPI Transceiver IC for Automotive Network
Document Number: 002-10203
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
Initial release
New Spec.
**
5046456
AKFU
12/11/2015
04/06/2016
Revised the sentence style of the cover page
Changed all section 5 for easy to understand.
Changed figure of application.
*A
5208207
AKFU
Changed Figure 4-1 and Figure 5-1.
Removed “Driver recovery time when over-temperature detection is released.”
Changed figure of application.
Changed Figure 4-1 Block Diagram
Changed Figure 5-12 Application example Secondary clock master
Added the conditions of VBUSdom/VBUSrec/ VHYS/Ttx_1_dom_m.
Removed the prameter of Receiver center level voltage (VBUS_CNT).
Changed Figure 8-11 CXPI BUS Load Connection
*B
5528948
AKFU
11/24/2016
Changed Ordering Information.
Changed Package Dimensions.
Updated Introduction.
Updated Note [3] (Page 8).
Updated 5.2 Master Node.
Updated 5.2.2 Sleep Mode.
*C
5547736
AKFU
12/09/2016
Document Number: 002-10203 Rev.*C
Page 37 of 38
S6BT112A01/S6BT112A02
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2015-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress
products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support
devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the
failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can
be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 002-10203 Rev.*C
December 9, 2016
Page 38 of 38
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