S71WS128JB0BAIAY2_技术文档

S71WSxxxJ based MCPs

Stacked Multi-Chip Product (MCP)

128/64 Megabit (8M/4M x 16-bit) CMOS 1.8 Volt-only,

Simultaneous Read/Write, Burst Mode Flash Memory

with CosmoRAM

ADVANCE

DATASHEET

Distinctive Characteristics

Packages

— 8 x 11.6mm, 84 ball FBGA

MCP Features

Power supply voltage of 1.7 to 1.95V

— 7 x 9mm, 80-ball FBGA

Operating Temperature

— –25°C to +85°C

Speed: 66MHz

— –40°C to +85°C

General Description

The S71WS series is a product line of stacked Multi-Chip Product (MCP) packages

and consists of:

One or more flash memory die

pSRAM

The products covered by this document are listed in the table below. For details

about their specifications, please refer to the individual constituent datasheets for

further details:

Flash Memory Density

256Mb

128Mb

64Mb

32Mb

16Mb

S71WS256JC0

S71WS128JC0

S71WS128JB0

S71WS128JA0

pSRAM

Density

S71WS064JB0

S71WS064JA0

Publication Number S71WS256/128/064J_CS Revision A Amendment 0 Issue Date October 27, 2004

Product Selector Guide

Flash Speed pSRAM Speed

Availability

Status

Device-Model#

Flash Density pSRAM Density

(MHz)

(MHz/ns)

Supplier

Package

S71WS064JA0-2Y

S71WS064JB0-2Y

S71WS128JA0-AY

S71WS128JB0-AY

S71WS128JC0-AY

S71WS256JC0-TY

16Mb

Cosmo RAM

Advanced

Preliminary

Advanced

64Mb

TLC080

32Mb

66

66/70

128Mb

256Mb

TLA084

FTA084

64Mb

2

S71WSxxxJ based MCPs

S71WS256/128/064J_CSA0 October 27, 2004

A d v a n c e I n f o r m a t i o n

Automatic Sleep Mode ......................................................................................41

RESET#: Hardware Reset Input .................................................................41

S71WSxxxJ based MCPs

Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1

MCP Features ........................................................................................................ 1

General Description . . . . . . . . . . . . . . . . . . . . . . . . 1

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2

Connection Diagram (CosmoRAM Type-based) . .7

Special Handling Instructions For FBGA Package ...................................8

Connection Diagram (CosmoRAM Type-based) . .9

Special Handling Instructions For FBGA Package ................................. 10

Lookahead Connection Diagram . . . . . . . . . . . . . 11

Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 12

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 13

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 16

TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA)

Output Disable Mode ...................................................................................42

Figure 1. Temporary Sector Unprotect Operation ................... 42

Figure 2. In-System Sector Protection/Sector Unprotection

Algorithms........................................................................ 43

Table 7. SecSi™ Sector Addresses ...................................... 44

SecSi™ Sector Protection Bit ......................................................................45

Hardware Data Protection .........................................................................45

Write Protect (WP#) .......................................................................................45

Low V Write Inhibit .................................................................................46

CC

Write Pulse “Glitch” Protection ...............................................................46

Logical Inhibit ...................................................................................................46

Power-Up Write Inhibit ...............................................................................46

Common Flash Memory Interface (CFI) . . . . . . . 47

Table 8. CFI Query Identification String ................................ 47

Table 9. System Interface String ......................................... 48

Table 10. Device Geometry Definition................................... 48

Table 11. Primary Vendor-Specific Extended Query ................ 49

Table 12. WS128J Sector Address Table ............................... 50

Table 13. WS064J Sector Address Table ............................... 58

8 x 11.6 mm Package ........................................................................................... 16

FTA084—84-ball Fine-Pitch Ball Grid Array (FBGA)

8 x 11.6 mm Package ............................................................................................17

TLC080—80-ball Fine-Pitch Ball Grid Array

(FBGA) 7 x 9 mm Package ............................................................................... 18

Command Definitions . . . . . . . . . . . . . . . . . . . . . .64

Reading Array Data ...........................................................................................64

Set Configuration Register Command Sequence .....................................64

Figure 3. Synchronous/Asynchronous State Diagram.............. 65

Read Mode Setting .........................................................................................65

Programmable Wait State Configuration ...............................................65

Table 14. Programmable Wait State Settings ......................... 66

Standard wait-state Handshaking Option ...............................................66

Table 15. Wait States for Standard wait-state Handshaking .... 66

Read Mode Configuration ...........................................................................66

Table 16. Read Mode Settings ............................................. 67

Burst Active Clock Edge Configuration .................................................. 67

RDY Configuration ........................................................................................67

Table 17. Configuration Register .......................................... 68

Reset Command .................................................................................................68

Autoselect Command Sequence ....................................................................68

Enter SecSi™ Sector/Exit SecSi™ Sector Command Sequence .............69

Program Command Sequence ........................................................................70

Unlock Bypass Command Sequence ........................................................70

Figure 4. Program Operation............................................... 71

Chip Erase Command Sequence ....................................................................71

Sector Erase Command Sequence ................................................................72

Erase Suspend/Erase Resume Commands .................................................. 73

Figure 5. Erase Operation................................................... 74

Password Program Command .......................................................................74

Password Verify Command .............................................................................74

Password Protection Mode Locking Bit Program Command .............. 75

Persistent Sector Protection Mode Locking Bit Program Command 75

SecSi™ Sector Protection Bit Program Command ................................... 75

PPB Lock Bit Set Command ............................................................................ 75

DPB Write/Erase/Status Command .............................................................76

Password Unlock Command ..........................................................................76

PPB Program Command ..................................................................................76

All PPB Erase Command .................................................................................. 77

PPB Status Command ....................................................................................... 77

PPB Lock Bit Status Command ...................................................................... 77

Command Definitions .......................................................................................78

Table 18. Command Definitions .......................................... 78

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 81

DQ7: Data# Polling .............................................................................................81

Figure 6. Data# Polling Algorithm........................................ 82

S29WS128/064J

General Description . . . . . . . . . . . . . . . . . . . . . . . .22

Product Selector Guide . . . . . . . . . . . . . . . . . . . . .24

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Block Diagram of Simultaneous

Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . .25

Input/Output Descriptions . . . . . . . . . . . . . . . . . . .26

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .27

Table 1. Device Bus Operations .......................................... 27

VersatileIO™ (V ) Control .............................................................................27

IO

Requirements for Asynchronous Read Operation (Non-Burst) ..........27

Requirements for Synchronous (Burst) Read Operation ...................... 28

8-, 16-, and 32-Word Linear Burst with Wrap Around ..................... 29

Table 2. Burst Address Groups ............................................ 29

Configuration Register ..................................................................................... 29

Handshaking ......................................................................................................... 29

Simultaneous Read/Write Operations with Zero Latency ................... 30

Writing Commands/Command Sequences ................................................ 30

Accelerated Program Operation .................................................................. 30

Autoselect Mode ..................................................................................................31

Table 3. Autoselect Codes (High Voltage Method) ................. 32

Sector/Sector Block Protection and Unprotection ..................................32

Table 4. S29WS128/064J_MCP Boot Sector/Sector Block Addresses

for Protection/Unprotection ................................................. 32

Table 5. S29WS064J Boot Sector/Sector Block Addresses for

Protection/Unprotection ..................................................... 34

Sector Protection ...........................................................................................36

Persistent Sector Protection ...........................................................................36

Persistent Protection Bit (PPB) ..................................................................37

Persistent Protection Bit Lock (PPB Lock) .............................................37

Dynamic Protection Bit (DYB) ...................................................................37

Table 6. Sector Protection Schemes ..................................... 38

Persistent Sector Protection Mode Locking Bit ........................................39

Password Protection Mode .............................................................................39

Password and Password Mode Locking Bit ................................................39

64-bit Password ..................................................................................................40

Persistent Protection Bit Lock .......................................................................40

Standby Mode ......................................................................................................40

October 27, 2004 S71WS256/128/064J_CSA0

3

A d v a n c e I n f o r m a t i o n

DQ6: Toggle Bit I ................................................................................................83

CosmoRAM

Figure 7. Toggle Bit Algorithm.............................................. 84

DQ2: Toggle Bit II .............................................................................................. 84

Table 19. DQ6 and DQ2 Indications ..................................... 85

Reading Toggle Bits DQ6/DQ2 ..................................................................... 85

DQ5: Exceeded Timing Limits ....................................................................... 86

DQ3: Sector Erase Timer ................................................................................ 86

Table 20. Write Operation Status ......................................... 87

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .88

Figure 8. Maximum Negative Overshoot Waveform................. 88

Figure 9. Maximum Positive Overshoot Waveform .................. 88

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 89

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .90

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 10. Test Setup ......................................................... 91

Table 21. Test Specifications ............................................... 91

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Pin Description (32M) . . . . . . . . . . . . . . . . . . . . . . .117

Functional Description . . . . . . . . . . . . . . . . . . . . . 118

Asynchronous Operation (Page Mode) .......................................................118

Functional Description . . . . . . . . . . . . . . . . . . . . . 119

Synchronous Operation (Burst Mode) ........................................................119

State Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Initial/Standby State ...........................................................................................120

Figure 38. Initial Standby State Diagram ............................ 120

Asynchronous Operation State ....................................................................120

Figure 39. Asynchronous Operation State Diagram............... 120

Synchronous Operation State ........................................................................121

Figure 40. Synchronous Operation Diagram ........................ 121

Functional Description . . . . . . . . . . . . . . . . . . . . . 121

Key to Switching Waveforms . . . . . . . . . . . . . . . 91

Power-up ...............................................................................................................121

Configuration Register ......................................................................................121

CR Set Sequence ................................................................................................121

Power Down .......................................................................................................124

Burst Read/Write Operation .........................................................................124

Figure 41. Burst Read Operation........................................ 125

Figure 42. Burst Write Operation ....................................... 125

CLK Input Function ..........................................................................................125

ADV# Input Function .......................................................................................126

WAIT# Output Function ................................................................................126

Figure 43. Read Latency Diagram ...................................... 127

Address Latch by ADV# .................................................................................128

Burst Length ........................................................................................................128

Single Write .........................................................................................................128

Write Control ....................................................................................................129

Figure 44. Write Controls.................................................. 129

Burst Read Suspend ..........................................................................................129

Figure 45. Burst Read Suspend Diagram............................. 130

Burst Write Suspend ........................................................................................130

Figure 46. Burst Write Suspend Diagram ............................ 130

Burst Read Termination ..................................................................................130

Figure 47. Burst Read Termination Diagram........................ 131

Burst Write Termination .................................................................................131

Figure 48. Burst Write Termination Diagram........................ 131

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 132

Recommended Operating Conditions (See

Warning Below) . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Package Pin Capacitance . . . . . . . . . . . . . . . . . . . 132

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 133

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 134

Read Operation .................................................................................................134

Write Operation ...............................................................................................136

Synchronous Operation - Clock Input (Burst Mode) ............................137

Synchronous Operation - Address Latch (Burst Mode) .......................137

Synchronous Read Operation (Burst Mode) ............................................138

Synchronous Write Operation (Burst Mode) ..........................................139

Power Down Parameters ...............................................................................140

Other Timing Parameters ...............................................................................140

AC Test Conditions .........................................................................................140

AC Measurement Output Load Circuit ......................................................141

Figure 49. Output Load Circuit........................................... 141

Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 91

Figure 11. Input Waveforms and Measurement Levels............. 91

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .92

V

Power-up ..................................................................................................... 92

CC

Figure 12. V_CCPower-up Diagram ........................................ 92

CLK Characterization ....................................................................................... 92

Figure 13. CLK Characterization ........................................... 92

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .93

Synchronous/Burst Read @ V = 1.8 V ......................................................93

IO

Figure 14. CLK Synchronous Burst Mode Read

(rising active CLK).............................................................. 94

Figure 15. CLK Synchronous Burst Mode Read

(Falling Active Clock).......................................................... 94

Figure 16. Synchronous Burst Mode Read.............................. 95

Figure 17. 8-word Linear Burst with Wrap Around................... 95

Figure 18. Linear Burst with RDY Set One Cycle Before Data.... 96

Asynchronous Mode Read @ V = 1.8 V ..................................................97

IO

Figure 19. Asynchronous Mode Read with Latched Addresses... 98

Figure 20. Asynchronous Mode Read..................................... 98

Figure 21. Reset Timings..................................................... 99

Erase/Program Operations @ V = 1.8 V ................................................100

IO

Figure 22. Asynchronous Program Operation Timings: AVD#

Latched Addresses ........................................................... 101

Figure 23. Asynchronous Program Operation Timings: WE#

Latched Addresses ........................................................... 102

Figure 24. Synchronous Program Operation Timings: WE# Latched

Addresses ....................................................................... 103

Figure 25. Synchronous Program Operation Timings: CLK Latched

Addresses ....................................................................... 104

Figure 26. Chip/Sector Erase Command Sequence................ 105

Figure 27. Accelerated Unlock Bypass Programming Timing ... 106

Figure 28. Data# Polling Timings

(During Embedded Algorithm)............................................ 107

Figure 29. Toggle Bit Timings (During Embedded Algorithm).. 107

Figure 30. Synchronous Data Polling

Timings/Toggle Bit Timings................................................ 108

Figure 31. DQ2 vs. DQ6.................................................... 108

Temporary Sector Unprotect .......................................................................109

Figure 32. Temporary Sector Unprotect Timing Diagram........ 109

Figure 33. Sector/Sector Block Protect and Unprotect Timing

Diagram.......................................................................... 110

Figure 34. Latency with Boundary Crossing.......................... 111

Figure 35. Latency with Boundary Crossing into Program/Erase

Bank .............................................................................. 112

Figure 36. Example of Wait States Insertion ........................ 113

Figure 37. Back-to-Back Read/Write Cycle Timings............... 114

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 142

Figure 50. Asynchronous Read Timing #1-1 (Basic Timing)... 142

Figure 51. Asynchronous Read Timing #1-2 (Basic Timing)... 142

4

S71WS256/128/064J_CSA0 October 27, 2004

A d v a n c e I n f o r m a t i o n

Figure 52. Asynchronous Read Timing #2

(OE# & Address Access) ................................................... 143

Figure 53. Asynchronous Read Timing #3

Figure 72. Synchronous Read - WAIT# Output Timing (Continuous

Read)............................................................................. 155

Figure 73. 64M Synchronous Read Timing #1 (OE# Control). 156

Figure 74. 64M Synchronous Read Timing #2 (CE1# Control) 157

Figure 75. 64M Synchronous Read Timing #3 (ADV# Control) 158

Figure 76. Synchronous Write Timing #1 (WE# Level Control) 159

Figure 77. Synchronous Write Timing #2 (WE# Single Clock Pulse

Control) ......................................................................... 160

Figure 78. Synchronous Write Timing #3 (ADV# Control) ..... 161

Figure 79. Synchronous Write Timing #4 (WE# Level Control,

Single Write)................................................................... 162

Figure 80. 32M Synchronous Read to Write Timing #1(CE1#

Control) ......................................................................... 163

Figure 81. 32M Synchronous Read to Write Timing #2(ADV#

Control) ......................................................................... 164

Figure 82. 64M Synchronous Read to Write Timing #1(CE1#

Control) ......................................................................... 165

Figure 83. 64M Synchronous Read to Write Timing #2(ADV#

Control) ......................................................................... 166

Figure 84. Synchronous Write to Read Timing #1

(LB# / UB# Byte Access) .................................................. 143

Figure 54. Asynchronous Read Timing #4 (Page Address Access

after CE1# Control Access)................................................ 144

Figure 55. Asynchronous Read Timing #5 (Random and Page

Address Access)............................................................... 144

Figure 56. Asynchronous Write Timing #1-1 (Basic Timing) ... 145

Figure 57. Asynchronous Write Timing #1-2 (Basic Timing) ... 145

Figure 58. Asynchronous Write Timing #2 (WE# Control)...... 146

Figure 59. Asynchronous Write Timing #3-1 (WE# / LB# / UB#

Byte Write Control) .......................................................... 146

Figure 60. Asynchronous Write Timing #3-2 (WE# / LB# / UB#

Byte Write Control) .......................................................... 147

Figure 61. Asynchronous Write Timing #3-3 (WE# / LB# / UB#

Byte Write Control) .......................................................... 147

Figure 62. Asynchronous Write Timing #3-4 (WE# / LB# / UB#

Byte Write Control) .......................................................... 148

Figure 63. Asynchronous Read / Write Timing #1-1

(CE1# Control)................................................................ 148

Figure 64. Asynchronous Read / Write Timing #1-2 (CE1# / WE# /

OE# Control)................................................................... 149

Figure 65. Asynchronous Read / Write Timing #2 (OE#, WE#

Control).......................................................................... 149

Figure 66. Asynchronous Read / Write Timing #3 (OE,# WE#, LB#,

UB# Control)................................................................... 150

Figure 67. Clock Input Timing............................................ 150

Figure 68. Address Latch Timing (Synchronous Mode)........... 151

Figure 69. 32M Synchronous Read Timing #1 (OE# Control).. 152

Figure 70. 32M Synchronous Read Timing #2 (CE1# Control) 153

Figure 71. 32M Synchronous Read Timing #3 (ADV# Control) 154

(CE1# Control) ............................................................... 167

Figure 85. Synchronous Write to Read Timing #2

(ADV# Control)............................................................... 168

Figure 86. Power-up Timing #1......................................... 169

Figure 87. Power-up Timing #2........................................ 169

Figure 88. Power Down Entry and Exit Timing ..................... 169

Figure 89. Standby Entry Timing after Read or Write............ 170

Figure 90. Configuration Register Set Timing #1 (Asynchronous

Operation)...................................................................... 170

Figure 91. Configuration Register Set Timing #2 (Synchronous

Operation)...................................................................... 171

Revision Summary

October 27, 2004 S71WS256/128/064J_CSA0

5

A d v a n c e I n f o r m a t i o n

MCP Block Diagram

F-VCC

Flash-only Address

Shared Address

V

ID

CC

DQ15 to DQ0

CLK

WP#

A22

16

DQ15 to DQ0

CLK

F-WP#

F-ACC

(Note 3) F1-CE#

OE#

ACC

CE#

OE#

WE#

Flash 1

Flash 2

(Note 4)

WE#

F-RST#

AVD#

RESET#

AVD#

RDY

(Note 3) F2-CE#

V

SS

R-V

CC

A22

V

CCQ

CC

WAIT#

(Note 5)

CLK

16

R-CE1#

CE#

WE#

OE#

I/O15 to I/O0

pSRAM

R-UB#

R-LB#

UB#

LB#

V

SSQ

(Note 1) R-CE2

(Note 5)

AVD#

(Note 2) R-CRE

Notes:

1. R-CRE is only present in CellularRAM-compatible pSRAM.

2. R-CE2 is only present in CosmoRAM-compatible pSRAM.

3. For 1 Flash = pSRAM, F1-CE# = CE#. For 2 Flash + pSRAM, CE# = F1-CE# and F2-CE# is the chip-enable pin for

the second Flash.

4. Only needed for S71WS256JC0, and S70WS256J00.

5. CLK and AVD# not applicable for 16Mb pSRAM.

October 27, 2004 S71WS256/128/064J_CSA0

6

A d v a n c e I n f o r m a t i o n

Connection Diagram (CosmoRAM Type-based)

84-ball Fine-Pitch Ball Grid Array

CosmoRAM-based Pinout (Top View, Balls Facing Down)

A1

NC

A10

NC

Legend

Shared

B2

B3

B4

B5

B6

B7

B8

B9

AVD#

RFU

CLK

F2-CE#

RFU

C2

C3

A7

C4

LB#s

D4

C5

ACC

D5

C6

WE#

D6

C7

A8

C8

A11

D9

C9

RFU

D10

A15

E9

WP#

D2

1st Flash only

2nd Flash only

1st RAM only

D3

A6

D7

A3

UB#s RESET#

CE2s

E6

A19

E7

A12

E8

E2

A2

E3

E4

A18

F4

E5

RDY

F5

A5

A20

F6

A9

A13

F8

A21

F9

F2

F3

F7

RFU

A23

A1

A4

A17

G4

A10

G7

A14

G8

A22

G9

G2

G3

VSS

H3

G5

RFU

H5

G6

RFU

H6

A0

DQ1

H4

DQ6

H7

RFU

H8

A16

Reserved for

Future Use

H2

H9

RFU

J9

CE1#f

J2

OE#

J3

DQ9

J4

DQ3

J5

DQ4

J6

DQ13

J7

DQ15

J8

CE1#s

K2

DQ0

K3

DQ10

K4

VCCf

K5

VCCs

K6

DQ12

K7

DQ7

K8

VSS

K9

RFU

DQ8

DQ2

DQ11

RFU

DQ5

DQ14

RFU

L5

L2

L3

L4

L6

L7

L8

L9

RFU

VCCf

RFU

M1

NC

M10

NC

Notes:

1. In MCP’s based on a single S29WSxxxJ (S71WSxxxJ), ball B5 is RFU. In MCP’s based on two S29WSxxxJ

(S71WS256J), ball B5 is CE#f2 or F2-CE#.

2. Addresses are shared btween Flash and RAM depending on the density of the pSRAM.

MCP

Flash-only Addresses

Shared Addresses

A19-A0

S71WS064JA0

S71WS064JB0

S71WS128JA0

S71WS128JB0

S71WS128JC0

S71WS256JC0

A21-A20

A21

A20-A0

A22-A20

A22-A21

A22

A19-A0

A21-A0

A22

A21-A0

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S71WS256/128/064J_CSA0 October 27, 2004

A d v a n c e I n f o r m a t i o n

Special Handling Instructions For FBGA Package

Special handling is required for Flash Memory products in FBGA packages.

Flash memory devices in FBGA packages may be damaged if exposed to ultra-

sonic cleaning methods. The package and/or data integrity may be compromised

if the package body is exposed to temperatures above 150°C for prolonged peri-

ods of time.

October 27, 2004 S71WS256/128/064J_CSA0

8

A d v a n c e I n f o r m a t i o n

Connection Diagram (CosmoRAM Type-based)

80-ball Fine-Pitch Ball Grid Array

CosmoRAM-based Pinout (Top View, Balls Facing Down)

Legend

Shared

A1

A2

A3

A4

A5

A6

A7

A8

AVD#

RFU

CLK

F2-CE#

RFU

B1

B2

A7

B3

LB#s

C3

B4

ACC

C4

B5

WE#

C5

B6

A8

B7

A11

C7

B8

RFU

C8

WP#

C1

1st Flash only

2nd Flash only

1st RAM only

C2

C6

A3

A6

UB#s RESET#

CE2s

D5

A19

D6

A12

D7

A15

D8

D1

A2

D2

A5

D3

A18

E3

D4

RDY

E4

A20

E5

A9

A13

E7

A21

E8

E1

E2

E6

RFU

A23

A1

A4

A17

F3

A10

F6

A14

F7

A22

F8

F1

F2

F4

RFU

G4

F5

RFU

G5

A0

VSS

G2

OE#

H2

DQ1

G3

DQ6

G6

RFU

G7

A16

Reserved for

Future Use

G1

G8

RFU

H8

CE1#f

H1

DQ9

H3

DQ3

H4

DQ4

H5

DQ13

H6

DQ15

H7

CE1#s

J1

DQ0

J2

DQ10

J3

VCCf

J4

VCCs

J5

DQ12

J6

DQ7

J7

VSS

J8

RFU

DQ8

DQ2

DQ11

RFU

DQ5

DQ14

RFU

K4

K1

K2

K3

K5

K6

K7

K8

RFU

VCCf

RFU

Notes:

1. In MCP’s based on a single S29WSxxxJ (S71WSxxxJ), ball B5 is RFU. In MCP’s based on two S29WSxxxJ

(S71WS256J), ball B5 is CE#f2 or F2-CE#.

2. Addresses are shared btween Flash and RAM depending on the density of the pSRAM.

3. The 80-ball pinout is applicable only to those MCPs with Flash density of 64Mb or 32Mb. For all the other MCPs

included in this datasheet, please use the 84-ball pinout for design.

MCP

Flash-only Addresses

Shared Addresses

A19-A0

S71WS064JA0

S71WS064JB0

S71WS128JA0

S71WS128JB0

S71WS128JC0

S71WS256JC0

A21-A20

A21

A20-A0

A22-A20

A22-A21

A22

A19-A0

A21-A0

A22

A21-A0

9

S71WS256/128/064J_CSA0 October 27, 2004

A d v a n c e I n f o r m a t i o n

Special Handling Instructions For FBGA Package

Special handling is required for Flash Memory products in FBGA packages.

Flash memory devices in FBGA packages may be damaged if exposed to ultra-

sonic cleaning methods. The package and/or data integrity may be compromised

if the package body is exposed to temperatures above 150°C for prolonged peri-

ods of time.

October 27, 2004 S71WS256/128/064J_CSA0

10

A d v a n c e I n f o r m a t i o n

Lookahead Connection Diagram

Legend:

A9

A2

A10

A1

DNU

Shared

or DNU

(Do Not Use)

DNU

B9

B1

B2

B10

DNU

MirrorBit Data-storage Only

Flash/Data Shared Only

C4

C5

C6

C7

C8

C9

C2

C3

AVD#

VSS

CLK

F2-CE#

F-VCC

F-CLK

R-OE# F2-OE#

D2

D3

A7

D6

D7

A8

D8

D9

D4

D5

F-WP#

R-LB# WP#/ACC WE#

E5 E6

R-UB# F-RST# R1-CE2

A11

F3-CE#

E2

A3

E3

A6

E7

E8

E9

E4

1st Flash Only

Flash Only

A19

A12

A15

F2

A2

F3

A5

F4

F5

F6

F7

A9

F8

F9

A18

RDY

A20

A13

A21

G2

A1

G3

A4

G4

GG55

G6

G7

G8

G9

A17

R2-CE1

A23

A10

A14

A22

1st RAM Only

2nd RAM Only

xRAM Shared Only

H2

A0

H3

H4

HH55

H6

H7

H8

H9

VSS

DQ1

R2-VCC R2-CE2

DQ6

A24

A16

J2

J3

J4

J5

J6

J7

J8

J2

DQ9

DQ3

DQ4

DQ13

DQ15

DNU

F1-CE#

OE#

K2

K3

K4

KK55

K6

K7

K8

K9

DQ12

VSS

R1-CE1#

DQ0

DQ10

F-VCC

R1-VCC

DQ7

L2

L4

L5

L6

L7

L8

L9

L3

DQ2

DQ11

A25

DQ5

DQ14 WP#/ACC

R-VCC

DQ8

M2

M3

M4

M5

M6

M7

M8

M9

R-CLK

A27

A26

VSS

F-VCC

F4-CE# R-VCCQ F-VCCQ

N9

N1

N2

N10

DNU

F-DQS-1

F-DQS0

DNU

P1

P9

P2

P10

DNU

Notes:

1. F1 and F2 denote XIP/Code Flash, while F3 and F4 denote Data/Companion Flash.

2. In addition to being defined as F2-CE#, Ball C5 can also be assigned as F1-CE2# for code flash that has two chip

enable signals.

3. For MCPs requiring 3.0V Vcc and 1.8V Vio, use the 1.8V Look-ahead Pinout in order to accommodate extra AVD,

MRS and CLK pins for the pSRAM (if needed).

4. Refer to Application Note on pinout subsets to match the package size offerings.

5. Ball B5 is shared between Flash RDY and RAM WAIT# signals.

11

S71WS256/128/064J_CSA0 October 27, 2004

A d v a n c e I n f o r m a t i o n

Input/Output Descriptions

A22-A0

DQ15-DQ0

OE#

=

Address inputs

Data input/output

Output Enable input. Asynchronous relative to CLK

for the Burst mode.

WE#

V_SS

NC

=

Write Enable input.

Ground

No Connect; not connected internally

Ready output. Indicates the status of the Burst read

(shared with WAIT# pin of RAM).

RDY

CLK

=

Clock input. In burst mode, after the initial word is

output, subsequent active edges of CLK increment

the internal address counter. Should be at V_ILor V_IH

while in asynchronous mode

AVD#

=

Address Valid input. Indicates to device that the

valid address is present on the address inputs.

Low = for asynchronous mode, indicates valid

address; for burst mode, causes starting address to

be latched.

High = device ignores address inputs

F-RST#

F-WP#

=

Hardware reset input. Low = device resets and

returns to reading array data

Hardware write protect input. At V_IL, disables

program and erase functions in the four outermost

sectors. Should be at V_IHfor all other conditions.

F-ACC

=

Accelerated input. At V_HH, accelerates

programming; automatically places device in unlock

bypass mode. At V_IL, disables all program and erase

functions. Should be at V_IHfor all other conditions.

R-CE1#

F1-CE#

=

Chip-enable input for pSRAM.

Chip-enable input for Flash 1. Asynchronous relative

to CLK for Burst Mode.

R-CRE

=

Control Register Enable (Only for MCPs with

CellularRAM pSRAM).

F-V_CC

R-V_CC

R-UB#

R-LB#

F2-CE#

=

Flash 1.8 Volt-only single power supply.

pSRAM Power Supply.

Upper Byte Control (pSRAM).

Lower Byte Control (pSRAM).

Chip-enable input for Flash 2. Asynchronous relative

to CLK for burst mode (needed only for

S71WS256J).

DNU

R-CE2

=

Do not use. Reserved for future Spansion products.

Chip-enable input for pSRAM

October 27, 2004 S71WS256/128/064J_CSA0

12

A d v a n c e I n f o r m a t i o n

Ordering Information

The order number is formed by a valid combinations of the following:

S71WS 256

J

C0 BA

W

A

K

0

PACKING TYPE

0

2

3

=

Tray

7” Tape and Reel

13” Tape and Reel

MODEL NUMBER

CosmoRAM 1, 66MHz

Y

=

PACKAGE MODIFIER

A

T

2

=

8 x 11.6 mm, 1.2 mm height, 84 balls, FBGA (128)

8 x 11.6 mm, 1.4 mm height, 84 balls, FBGA

7 x 9 mm, 1.2 mm height, 80 balls, FBGA

TEMPERATURE RANGE

W

I

=

Wireless (-25

Industrial (-40

°

C to +85

°

C)

°C to +85

°

PACKAGE TYPE

BA

BF

=

Very-thin Fine-pitch BGA Lead (Pb)-free compliant package

Very-thin Fine-pitch BGA Lead (Pb)-free package

pSRAM DENSITY

C0

B0

A0

=

64 Mb pSRAM

32 Mb pSRAM

16 Mb pSRAM

PROCESS TECHNOLOGY

110 nm, Floating Gate Technology

J

=

FLASH DENSITY

256

128

064

=

256Mb

128Mb

64Mb

PRODUCT FAMILY

S71WS Multi-chip Product (MCP)

1.8-volt Simultaneous Read/Write, Burst Mode Flash Memory and pRAM

S71WS064JB0 Valid Combinations (WS064J Flash + 16Mb pSRAM)

Base Ordering

Part Number

Temperature

Range

Package Marking

Burst Speed

Material Set

Supplier

S71WS064JA0BAW2Y

S71WS064JA0BAI2Y

S71WS064JA0BFW2Y

S71WS064JA0BFI2Y

71WS064JA0BAW2Y

71WS064JA0BAI2Y

71WS064JA0BFW2Y

71WS064JA0BFI2Y

-25°C to +85°C

40°C to +85°C

-25°C to +85°C

40°C to +85°C

Pb-free compliant

66 MHz

CosmoRAM

Pb-free

Notes:

Valid Combinations

1. Type 0 is standard. Specify other options as required.

2. BGA package marking omits leading “S” and packing type

designator from ordering part number.

Valid Combinations list configurations planned to be supported in vol-

ume for this device. Consult your local sales office to confirm avail-

ability of specific valid combinations and to check on newly released

combinations.

13

S71WS256/128/064J_CSA0 October 27, 2004

A d v a n c e I n f o r m a t i o n

S71WS064JB0 Valid Combinations (WS064J Flash + 32Mb pSRAM)

Base Ordering

Part Number

Temperature

Range

Package Marking

Burst Speed

Material Set

Supplier

S71WS064JB0BAW2Y

S71WS064JB0BAI2Y

S71WS064JB0BFW2Y

S71WS064JB0BFI2Y

71WS064JB0BAW2Y

71WS064JB0BAI2Y

71WS064JB0BFW2Y

71WS064JB0BFI2Y

-25°C to +85°C

40°C to +85°C

-25°C to +85°C

40°C to +85°C

Pb-free compliant

66 MHz

CosmoRAM

Pb-free

Notes:

Valid Combinations

1. Type 0 is standard. Specify other options as required.

2. BGA package marking omits leading “S” and packing type

designator from ordering part number.

Valid Combinations list configurations planned to be supported in vol-

ume for this device. Consult your local sales office to confirm avail-

ability of specific valid combinations and to check on newly released

combinations.

S71WS128JB0 Valid Combinations (WS128J Flash + 16Mb pSRAM)

Base Ordering

Part Number

Temperature

Range

Package Marking

Burst Speed

Material Set

Supplier

S71WS128JA0BAWAY

S71WS128JA0BAIAY

S71WS128JA0BFWAY

S71WS128JA0BFIAY

71WS128JA0BAWAY

71WS128JA0BAIAY

71WS128JA0BFWAY

71WS128JA0BFIAY

-25°C to +85°C

-40°C to +85°C

-25°C to +85°C

-40°C to +85°C

Pb-free compliant

66 MHz

CosmoRAM

Pb-free

Notes:

Valid Combinations

1. Type 0 is standard. Specify other options as required.

2. BGA package marking omits leading “S” and packing type

designator from ordering part number.

Valid Combinations list configurations planned to be supported in vol-

ume for this device. Consult your local sales office to confirm avail-

ability of specific valid combinations and to check on newly released

combinations.

S71WS128JB0 Valid Combinations (WS128J Flash + 32Mb pSRAM)

Base Ordering

Part Number

Temperature

Range

Package Marking

Burst Speed

Material Set

Supplier

S71WS128JB0BAWAY

S71WS128JB0BAIAY

S71WS128JB0BFWAY

S71WS128JB0BFIAY

71WS128JB0BAWAY

71WS128JB0BAIAY

71WS128JB0BFWAY

71WS128JB0BFIAY

-25°C to +85°C

-40°C to +85°C

-25°C to +85°C

-40°C to +85°C

Pb-free compliant

66 MHz

CosmoRAM

Pb-free

Notes:

Valid Combinations

1. Type 0 is standard. Specify other options as required.

2. BGA package marking omits leading “S” and packing type

designator from ordering part number.

Valid Combinations list configurations planned to be supported in vol-

ume for this device. Consult your local sales office to confirm avail-

ability of specific valid combinations and to check on newly released

combinations.

S71WS128JC0 Valid Combinations (WS128J Flash + 64Mb pSRAM)

Base Ordering

Part Number

Temperature

Range

Package Marking

Burst Speed

Material Set

Supplier

S71WS128JC0BAWAY

S71WS128JC0BAIAY

S71WS128JC0BFWAY

S71WS128JC0BFIAY

71WS128JC0BAWAY

71WS128JC0BAIAY

71WS128JC0BFWAY

71WS128JC0BFIAY

-25°C to +85°C

-40°C to +85°C

-25°C to +85°C

-40°C to +85°C

Pb-free compliant

66 MHz

CosmoRAM

Pb-free

Notes:

Valid Combinations

1. Type 0 is standard. Specify other options as required.

2. BGA package marking omits leading “S” and packing type

designator from ordering part number.

Valid Combinations list configurations planned to be supported in vol-

ume for this device. Consult your local sales office to confirm avail-

ability of specific valid combinations and to check on newly released

combinations.

October 27, 2004 S71WS256/128/064J_CSA0

14

A d v a n c e I n f o r m a t i o n

S71WS256JC0 Valid Combinations (2 x WS128J Flash + 64Mb pSRAM)

Base Ordering

Part Number

Temperature

Range

Package Marking

Burst Speed

Material Set

Supplier

S71WS256JC0BAWTY

S71WS256JC0BAITY

S71WS256JC0BFWTY

S71WS256JC0BFITY

71WS256JC0BAWTY

71WS256JC0BAITY

71WS256JC0BFWTY

71WS256JC0BFITY

-25°C to +85°C

-40°C to +85°C

-25°C to +85°C

-40°C to +85°C

Pb-free compliant

66 MHz

CosmoRAM

Pb-free

Notes:

Valid Combinations

1. Type 0 is standard. Specify other options as required.

2. BGA package marking omits leading “S” and packing type

designator from ordering part number.

Valid Combinations list configurations planned to be supported in vol-

ume for this device. Consult your local sales office to confirm avail-

ability of specific valid combinations and to check on newly released

combinations.

15

S71WS256/128/064J_CSA0 October 27, 2004

A d v a n c e I n f o r m a t i o n

Physical Dimensions

TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package

A

D1

D

eD

0.15

(2X)

C

10

9

8

SE

7

6

E

B

E1

5

4

3

2

1

eE

J

H

G

F

E

D

C

B

A

M

L K

INDEX MARK

10

PIN A1

CORNER

PIN A1

CORNER

7

SD

0.15

(2X)

C

TOP VIEW

BOTTOM VIEW

0.20

C

A2

A

0.08

C

A1

SIDE VIEW

6

84X

b

0.15

0.08

M

C

A

B

M

NOTES:

PACKAGE

JEDEC

TLA 084

N/A

1. DIMENSIONING AND TOLERANCING METHODS PER

ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

D x E

11.60 mm x 8.00 mm

PACKAGE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.

SYMBOL

MIN

---

NOM

---

MAX

NOTE

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

1.20

---

PROFILE

5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"

DIRECTION.

0.17

0.81

---

BALL HEIGHT

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE

"E" DIRECTION.

A2

---

0.97

BODY THICKNESS

BODY SIZE

D

11.60 BSC.

8.00 BSC.

8.80 BSC.

7.20 BSC.

12

n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS

FOR MATRIX SIZE MD X ME.

E

BODY SIZE

D1

MATRIX FOOTPRINT

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

E1

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER

BALL IN THE OUTER ROW.

MD

ME

n

MATRIX SIZE D DIRECTION

MATRIX SIZE E DIRECTION

BALL COUNT

10

84

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE

OUTER ROW SD OR SE = 0.000.

Ø b

eE

0.35

0.40

0.45

BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE

OUTER ROW, SD OR SE = e/2

0.80 BSC.

0.80 BSC

0.40 BSC.

BALL PITCH

eD

BALL PITCH

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

SD / SE

SOLDER BALL PLACEMENT

A2,A3,A4,A5,A6,A7,A8,A9

B1,B10,C1,C10,D1,D10,

E1,E10,F1,F10,G1,G10,

H1,H10,J1,J10,K1,K10,L1,L10,

M2,M3,M4,M5,M6,M7,M8,M9

DEPOPULATED SOLDER BALLS

9. N/A

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

3372-2 \ 16-038.22a

October 27, 2004 S71WS256/128/064J_CSA0

16

A d v a n c e I n f o r m a t i o n

FTA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package

A

D1

D

eD

0.15

(2X)

C

10

9

8

SE

7

6

E

B

E1

5

4

3

2

1

eE

J

H

G

F

E

D

C

B

A

M

L K

INDEX MARK

10

PIN A1

CORNER

PIN A1

CORNER

7

SD

0.15

(2X)

C

TOP VIEW

BOTTOM VIEW

0.20

0.08

C

A2

A

C

A1

SIDE VIEW

6

84X

b

0.15

M

C

A

B

0.08

M

NOTES:

PACKAGE

JEDEC

FTA 084

N/A

1. DIMENSIONING AND TOLERANCING METHODS PER

ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

D x E

11.60 mm x 8.00 mm

PACKAGE

NOTE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.

SYMBOL

MIN

---

NOM

---

MAX

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

1.40

---

PROFILE

5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"

DIRECTION.

0.17

1.02

---

BALL HEIGHT

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE

"E" DIRECTION.

A2

---

1.17

BODY THICKNESS

BODY SIZE

D

11.60 BSC.

8.00 BSC.

8.80 BSC.

7.20 BSC.

12

n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS

FOR MATRIX SIZE MD X ME.

E

BODY SIZE

D1

E1

MATRIX FOOTPRINT

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER

BALL IN THE OUTER ROW.

MD

ME

n

MATRIX SIZE D DIRECTION

MATRIX SIZE E DIRECTION

BALL COUNT

10

84

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE

OUTER ROW SD OR SE = 0.000.

φb

0.35

0.40

0.45

BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE

OUTER ROW, SD OR SE = e/2

eE

0.80 BSC.

0.80 BSC

0.40 BSC.

BALL PITCH

eD

SD / SE

BALL PITCH

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

SOLDER BALL PLACEMENT

A2,A3,A4,A5,A6,A7,A8,A9

B1,B10,C1,C10,D1,D10,E1,E10

F1,F10,G1,G10,H1,H10

DEPOPULATED SOLDER BALLS

9. N/A

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

J1,J10,K1,K10,L1,L10

M2,M3,M4,M5,M6,M7,M8,M9

3388 \ 16-038.21a

17

S71WS256/128/064J_CSA0 October 27, 2004

A d v a n c e I n f o r m a t i o n

TLC080—80-ball Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm Package

D1

A

D

eD

0.15

(2X)

C

8

7

SE

7

6

5

4

3

2

E

B

E1

eE

1

K

J

H

G

F

E

D

C

B

A

INDEX MARK

10

PIN A1

CORNER

PIN A1

CORNER

7

SD

0.15

(2X)

C

TOP VIEW

BOTTOM VIEW

0.20

0.08

C

A2

A

C

A1

SIDE VIEW

6

80X

b

0.15

0.08

M

C

A

B

NOTES:

PACKAGE

JEDEC

TLC 080

N/A

1. DIMENSIONING AND TOLERANCING METHODS PER

ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

D x E

9.00 mm x 7.00 mm

PACKAGE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.

SYMBOL

MIN

NOM

---

MAX

NOTE

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

---

1.20

---

PROFILE

5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"

DIRECTION.

0.17

0.81

---

BALL HEIGHT

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE

"E" DIRECTION.

A2

---

0.97

BODY THICKNESS

BODY SIZE

D

9.00 BSC.

7.00 BSC.

7.20 BSC.

5.60 BSC.

10

n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS

FOR MATRIX SIZE MD X ME.

E

BODY SIZE

D1

E1

MATRIX FOOTPRINT

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER

BALL IN THE OUTER ROW.

MD

ME

n

MATRIX SIZE D DIRECTION

MATRIX SIZE E DIRECTION

BALL COUNT

8

80

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE

OUTER ROW SD OR SE = 0.000.

φb

0.35

0.40

0.45

BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE

OUTER ROW, SD OR SE = e/2

eE

0.80 BSC.

0.80 BSC

0.40 BSC.

BALL PITCH

eD

SD / SE

BALL PITCH

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

SOLDER BALL PLACEMENT

DEPOPULATED SOLDER BALLS

9. N/A

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

3430 \ 16-038.22 \ 10.15.04

October 27, 2004 S71WS256/128/064J_CSA0

18

S29WS128/064J

Flash Family for Multi-Chip Products (MCP)

128/64 Megabit (8/4 M x 16-Bit) CMOS 1.8 Volt-only

Simultaneous Read/Write, Burst Mode Flash Memory

ADVANCE

INFORMATION

Distinctive Characteristics

— Asynchronous random access times of 45/55 ns (at

30 pF)

Power dissipation (typical values, C_L= 30 pF)

— Burst Mode Read: 10 mA @ 80Mhz

— Simultaneous Operation: 25 mA @ 80Mhz

— Program/Erase: 15 mA

Architectural Advantages

Single 1.8 volt read, program and erase (1.65 to

1.95 volt)

Manufactured on 0.11 µm process technology

VersatileIO™ (V_IO) Feature

— Device generates data output voltages and tolerates

data input voltages as determined by the voltage on

the V_IOpin

— Standby mode: 0.2 µA

Hardware Features

— 1.8V compatible I/O signals (1.65-1.95 V)

Handshaking feature available

— Provides host system with minimum possible latency

by monitoring RDY

Simultaneous Read/Write operation

— Data can be continuously read from one bank while

executing erase/program functions in other bank

— Zero latency between read and write operations

— Four bank architecture: WS128J: 16Mb/48Mb/48Mb/

16Mb, WS064J: 8Mb/24Mb/24Mb/8Mb

Hardware reset input (RESET#)

— Hardware method to reset the device for reading

array data

WP# input

Programable Burst Interface

— Write protect (WP#) function allows protection of

four outermost boot sectors, regardless of sector

protect status

— 2 Modes of Burst Read Operation

— Linear Burst: 8, 16, and 32 words with wrap-around

— Continuous Sequential Burst

Persistent Sector Protection

— A command sector protection method to lock

combinations of individual sectors and sector groups

to prevent program or erase operations within that

sector

SecSi™ (Secured Silicon) Sector region

— 128 words accessible through a command sequence,

64words for the Factory SecSi™ Sector and 64words

for the Customer SecSi™ Sector.

Sector Architecture

4 Kword x 16 boot sectors, eight at the top of the address

range, and eight at the bottom of the address range

— Sectors can be locked and unlocked in-system at V_CC

level

Password Sector Protection

—

WS128J: 4 Kword X 16, 32 Kword x 254 sectors

— A sophisticated sector protection method to lock

combinations of individual sectors and sector groups

to prevent program or erase operations within that

sector using a user-defined 64-bit password

Bank A: 4 Kword x 8, 32 Kword x 31 sectors

Bank B: 32 Kword x 96 sectors

Bank C: 32 Kword x 96 sectors

ACC input: Acceleration function reduces

programming time; all sectors locked when ACC =

V_IL

Bank D: 4 Kword x 8, 32 Kword x 31 sectors

—

WS064J: 4 Kword x 16, 32 Kword x 126 sectors.

Bank A: 4 Kword x 8, 32 Kword x 15 sectors

CMOS compatible inputs, CMOS compatible outputs

Low V_CCwrite inhibit

Bank B: 32 Kword x 48 sectors

Bank C: 32 Kword x 48 sectors

Bank D: 4 Kword x 8, 32 Kword x 15 sectors

Software Features

Cycling Endurance: 100,000 cycles per sector

typical

Data retention: 20-years typical

Supports Common Flash Memory Interface (CFI)

Software command set compatible with JEDEC

42.4 standards

— Backwards compatible with AMD Am29BDS,

AMD Am29BDD, AMD Am29BL, andFujitsu MBM29BS

families

Performance Characteristics

Read access times at 80/66 MHz

— Burst access times of 9.1/11.2 ns @ 30 pF at

industrial temperature range

— Synchronous latency of 46/56 ns (at 30 pF)

Data# Polling and toggle bits

— Provides a software method of detecting program

and erase operation completion

Publication Number S29WS128_064J_MCP_00 Revision A Amendment 0 Issue Date May 5, 2004

This document contains information on a product under development at FASL, LLC. The information is intended to help you evaluate this product. Do not design in this

product without contacting the factory. FASL reserves the right to change or discontinue work on this proposed product without notice.

Erase Suspend/Resume

Unlock Bypass Program command

— Suspends an erase operation to read data from, or

program data to, a sector that is not being erased,

then resumes the erase operation

— Reduces overall programming time when issuing

multiple program command sequences

21

S29WS128/064J

May 5, 2004

General Description

The S29WS128/064J_MCP/S29WS064J is a 128/64 Mbit, 1.8 Volt-only, simultaneous

Read/Write, Burst Mode Flash memory device, organized as 8,388,608/4,194,304 words

of 16 bits each. This device uses a single V_CCof 1.65 to 1.95 V to read, program, and

erase the memory array. A 12.0-volt V_HHon ACC may be used for faster program perfor-

mance if desired. The device can also be programmed in standard EPROM programmers.

At 80 MHz, the device provides a burst access of 9.1 ns at 30 pF with a latency of 46 ns

at 30 pF. At 66 MHz, the device provides a burst access of 11.2 ns at 30 pF with a latency

of 56 ns at 30 pF. The device operates within the industrial temperature range of -40°C to

+85°C and the wireless temperature range of -25°C to +85°C. The device is offered in

Various FBGA packages.

The Simultaneous Read/Write architecture provides simultaneous operation by divid-

ing the memory space into four banks. The device can improve overall system perfor-

mance by allowing a host system to program or erase in one bank, then immediately and

simultaneously read from another bank, with zero latency. This releases the system from

waiting for the completion of program or erase operations.

The device is divided as shown in the following table:

Quantity

Bank

128Mb

64 Mb

8

Size

8

4 Kwords

32 Kwords

4 Kwords

A

31

96

31

8

15

48

15

8

B

C

D

The VersatileIO™ (V_IO) control allows the host system to set the voltage levels that the

device generates at its data outputs and the voltages tolerated at its data inputs to the

same voltage level that is asserted on the V_IOpin.

The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Out-

put Enable (OE#) to control asynchronous read and write operations. For burst opera-

tions, the device additionally requires Ready (RDY), and Clock (CLK). This

implementation allows easy interface with minimal glue logic to a wide range of micropro-

cessors/microcontrollers for high performance read operations.

The burst read mode feature gives system designers flexibility in the interface to the de-

vice. The user can preset the burst length and wrap through the same memory space, or

read the flash array in continuous mode.

The clock polarity feature provides system designers a choice of active clock edges, either

rising or falling. The active clock edge initiates burst accesses and determines when data

will be output.

The device is entirely command set compatible with the JEDEC 42.4 single-power-

supply Flash standard. Commands are written to the command register using standard

microprocessor write timing. Register contents serve as inputs to an internal state-ma-

chine that controls the erase and programming circuitry. Write cycles also internally latch

addresses and data needed for the programming and erase operations. Reading data out

of the device is similar to reading from other Flash or EPROM devices.

The Erase Suspend/Erase Resume feature enables the user to put erase or program

on hold for any period of time to read data from, or program data to, any sector that is

not selected for erasure. True background erase can thus be achieved. If a read is needed

from the SecSi™ Sector area (One Time Program area) after an erase suspend, then the

user must use the proper command sequence to enter and exit this region. Program sus-

pend is also offered.

The hardware RESET# pin terminates any operation in progress and resets the internal

state machine to reading array data. The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the device, enabling the system microproces-

sor to read boot-up firmware from the Flash memory device.

May 5, 2004

S29WS128/064J

22

The host system can detect whether a program or erase operation is complete by using

the device status bit DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or

erase cycle has been completed, the device automatically returns to reading array data.

The sector erase architecture allows memory sectors to be erased and reprogrammed

without affecting the data contents of other sectors. The device is fully erased when

shipped from the factory.

Hardware data protection measures include a low V_CCdetector that automatically in-

hibits write operations during power transitions. The device also offers two types of data

protection at the sector level. When at V_IL, WP# locks the four outermost boot sectors.

The device offers two power-saving features. When addresses have been stable for a

specified amount of time, the device enters the automatic sleep mode. The system can

also place the device into the standby mode. Power consumption is greatly reduced in

both modes.

Spansion™ Flash memory products combine years of Flash memory manufacturing expe-

rience to produce the highest levels of quality, reliability and cost effectiveness. The de-

vice electrically erases all bits within a sector simultaneously via Fowler-Nordheim

tunnelling. The data is programmed using hot electron injection.

23

S29WS128/064J

May 5, 2004

Product Selector Guide

S29WS128/064J_MCP/S29WS064J

Synchronous/Burst Asynchronous

Part

Number

2

66

80*

66

80*

Speed Option

MHz MHz

Max Latency, ns (t_IACC

Max Burst Access Time, ns (t_BACC

Max OE# Access, ns (t_OE

)

56

46

Max Access Time, ns (t_ACC

)

55

45

V

=

IO

1.65 –

1.95 V

)

11.2

9.1 Max CE# Access, ns (t_CE)

)

9.1 Max OE# Access, ns (t_OE

)

11.2

9.1

Block Diagram

V_CC

V_SS

DQ15–DQ0

V_SSIO

V_IO

RDY

Buffer

RDY

Erase Voltage

Generator

Input/Output

Buffers

WE#

RESET#

WP#

State

Control

ACC

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

CE#

OE#

Y-Decoder

Y-Gating

V_CC

Detector

Timer

Cell Matrix

X-Decoder

Burst

State

Control

Burst

Address

Counter

AVD#

CLK

Amax–A0

Amax: WS064J (A21), WS128J (A22)

May 5, 2004

S29WS128/064J

24

Block Diagram of Simultaneous Operation Circuit

V

CC

V

SS

IO

V

SSIO

Bank A Address

DQ15–DQ0

Bank A

Amax–A0

X-Decoder

OE#

Bank B Address

DQ15–DQ0

Bank B

WP#

ACC

X-Decoder

Amax–A0

STATE

CONTROL

&

COMMAND

REGISTER

RESET#

WE#

DQ15–DQ0

Status

CE#

AVD#

RDY

Control

Amax–A0

DQ15–DQ0

X-Decoder

Bank C

DQ15–DQ0

Bank C Address

Amax–A0

X-Decoder

Bank D

Bank D Address

DQ15–DQ0

Amax: WS064J (A21), WS128J (A22)

25

S29WS128/064J

May 5, 2004

Input/Output Descriptions

Amax-A0

DQ15-DQ0

CE#

=

Address inputs

Data input/output

Chip Enable input. Asynchronous relative to CLK for

the Burst mode.

OE#

=

Output Enable input. Asynchronous relative to CLK

for the Burst mode.

WE#

V_CC

=

Write Enable input.

Device Power Supply

(1.65 – 1.95 V).

V_IO

=

Input & Output Buffer Power Supply

(1.65 – 1.95 V).

V_SS

NC

RDY

=

Ground

No Connect; not connected internally

Ready output;

In Synchronous Mode, indicates the status of the

Burst read.

Low = data not valid at expected time. High = data

valid.

In Asynchronous Mode, indicates the status of the

internal program and erase function.

Low = program/erase in progress.

High Impedance = program/erase completed.

CLK is not required in asynchronous mode. In burst

mode, after the initial word is output, subsequent

active edges of CLK increment the internal address

counter.

Address Valid input. Indicates to device that the valid

address is present on the address inputs (Amax-A0).

Low = for asynchronous mode, indicates valid

address; for burst mode, causes starting address to

be latched.

CLK

=

AVD#

High = device ignores address inputs

Hardware reset input. Low = device resets and

returns to reading array data

Hardware write protect input. At V_IL, disables

program and erase functions in the four outermost

sectors. Should be at V_IHfor all other conditions.

At V_HH, accelerates programming; automatically

places device in unlock bypass mode. At V_IL, locks all

sectors. Should be at V_IHfor all other conditions.

RESET#

WP#

=

ACC

=

Note:

1. Amax = A22 (WS128J), A21 (WS064J)

May 5, 2004

S29WS128/064J

26

Device Bus Operations

This section describes the requirements and use of the device bus operations,

which are initiated through the internal command register. The command register

itself does not occupy any addressable memory location. The register is com-

posed of latches that store the commands, along with the address and data

information needed to execute the command. The contents of the register serve

as inputs to the internal state machine. The state machine outputs dictate the

function of the device. Table 1 lists the device bus operations, the inputs and con-

trol levels they require, and the resulting output. The following subsections

describe each of these operations in further detail.

Table 1. Device Bus Operations

CLK

(See

Operation

CE#

OE#

WE#

A22–0

Addr In

HIGH Z

DQ15–0 RESET# Note) AVD#

Asynchronous Read - Addresses Latched

Asynchronous Read - Addresses Steady State

Asynchronous Write

L

H

L

I/O

H

L

X

L

H

X

I/O

Synchronous Write

L

I/O

Standby (CE#)

H

X

HIGH Z

X

Hardware Reset

Burst Read Operations

Load Starting Burst Address

L

X

L

H

Addr In

HIGH Z

X

H

Advance Burst to next address with

appropriate Data presented on the Data Bus

Burst

Data Out

H

Terminate current Burst read cycle

H

X

H

HIGH Z

H

L

X

Terminate current Burst read cycle via RESET#

X

Terminate current Burst read cycle and start

new Burst read cycle

L

X

H

HIGH Z

I/O

H

Legend: L = Logic 0, H = Logic 1, X = Don’t Care

Note: Default active edge of CLK is the rising edge.

VersatileIO™ (V_IO) Control

The VersatileIO (V_IO) control allows the host system to set the voltage levels that

the device generates at its data outputs and the voltages tolerated at its data in-

puts to the same voltage level that is asserted on the V_IOpin.

Requirements for Asynchronous Read Operation (Non-Burst)

To read data from the memory array, the system must first assert a valid address

on Amax–A0(A22-A0 for WS128J and A21-A0 for WS064J), while driving AVD#

and CE# to V_IL. WE# should remain at V_IH. The rising edge of AVD# latches the

address. The data will appear on DQ15–DQ0. Since the memory array is divided

into four banks, each bank remains enabled for read access until the command

register contents are altered.

Address access time (t_ACC) is equal to the delay from stable addresses to valid

output data. The chip enable access time (t_CE) is the delay from the stable ad-

27

S29WS128/064J

May 5, 2004

dresses and stable CE# to valid data at the outputs. The output enable access

time (t_OE) is the delay from the falling edge of OE# to valid data at the output.

The internal state machine is set for reading array data in asynchronous mode

upon device power-up, or after a hardware reset. This ensures that no spurious

alteration of the memory content occurs during the power transition.

Requirements for Synchronous (Burst) Read Operation

The device is capable of continuous sequential burst operation and linear burst

operation of a preset length. When the device first powers up, it is enabled for

asynchronous read operation.

Prior to entering burst mode, the system should determine how many wait states

are desired for the initial word (t_IACC) of each burst access, what mode of burst

operation is desired, which edge of the clock will be the active clock edge, and

how the RDY signal will transition with valid data. The system would then write

the configuration register command sequence. See “Set Configuration Register

Command Sequence” section on page 64 and “Command Definitions” section on

page 64 for further details.

Once the system has written the “Set Configuration Register” command se-

quence, the device is enabled for synchronous reads only.

The initial word is output t_IACCafter the active edge of the first CLK cycle. Sub-

sequent words are output t_BACCafter the active edge of each successive clock

cycle, which automatically increments the internal address counter. Note that the

device has a fixed internal address boundary that occurs every 64 words, starting

at address 00003Fh.

During the time the device is outputting data at this fixed internal address bound-

ary (address 00003Fh, 00007Fh, 0000BFh, etc.), a two cycle latency occurs

before data appears for the next address (address 000040h, 000080h, 0000C0h,

etc.).

Additionally, when the device is read from an odd address, 1 wait state is inserted

when the address pointer crosses the first boundary that occurs every 16 words.

For instance, if the device is read from 00001Ah (odd), 1 wait state is inserted

before the data of 000020h is output. This wait states is inserted at only the first

16 words boundary. Then, if the device is read from the odd address within the

last 16 words of 64 word boundary (address 000031h, 000033h,..., 00003Eh), a

three cycle latency occurs before data appears for the next address (address

000040h).

The RDY output indicates this condition to the system by pulsing deactive (low).

See Figure 34, “Latency with Boundary Crossing,” on page 111.

The device will continue to output sequential burst data, wrapping around to ad-

dress 000000h after it reaches the highest addressable memory location, until

the system drives CE# high, RESET# low, or AVD# low in conjunction with a new

address. See Table 1, “Device Bus Operations,” on page 27.

If the host system crosses the bank boundary while reading in burst mode, and

the device is not programming or erasing, a two-cycle latency will occur as de-

scribed above in the subsequent bank. If the host system crosses the bank

boundary while the device is programming or erasing, the device will provide read

status information. The clock will be ignored. After the host has completed status

reads, or the device has completed the program or erase operation, the host can

restart a burst operation using a new address and AVD# pulse.

May 5, 2004

S29WS128/064J

28

8-, 16-, and 32-Word Linear Burst with Wrap Around

The remaining three burst read modes are of the linear wrap around design, in

which a fixed number of words are read from consecutive addresses. In each of

these modes, the burst addresses read are determined by the group within which

the starting address falls. The groups are sized according to the number of words

read in a single burst sequence for a given mode (see Table 2.)

Table 2. Burst Address Groups

Mode

8-word

16-word

32-word

Group Size

8 words

Group Address Ranges

0-7h, 8-Fh, 10-17h,...

16 words

32 words

0-Fh, 10-1Fh, 20-2Fh,...

00-1Fh, 20-3Fh, 40-5Fh,...

As an example: if the starting address in the 8-word mode is 39h, the address

range to be read would be 38-3Fh, and the burst sequence would be 39-3A-3B-

3C-3D-3E-3F-38h-etc. The burst sequence begins with the starting address writ-

ten to the device, but wraps back to the first address in the selected group. In a

similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst

sequence on the starting address written to the device, and then wrap back to

the first address in the selected address group. Note that in these three burst

read modes the address pointer does not cross the boundary that occurs

every 128 or 64 words; thus, no wait states are inserted (except during

the initial access).

The RDY pin indicates when data is valid on the bus.

Configuration Register

The device uses a configuration register to set the various burst parameters:

number of wait states, burst read mode, active clock edge, RDY configuration,

and synchronous mode active.

Handshaking

The device is equipped with a handshaking feature that allows the host system

to simply monitor the RDY signal from the device to determine when the initial

word of burst data is ready to be read. The host system should use the program-

mable wait state configuration to set the number of wait states for optimal burst

mode operation. The initial word of burst data is indicated by the active edge of

RDY after OE# goes low.

For optimal burst mode performance, the host system must set the appropriate

number of wait states in the flash device depending on clock frequency. See “Set

Configuration Register Command Sequence” section on page 64 for more

information.

29

S29WS128/064J

May 5, 2004

Simultaneous Read/Write Operations with Zero Latency

This device is capable of reading data from one bank of memory while program-

ming or erasing in another bank of memory. An erase operation may also be

suspended to read from or program to another location within the same bank (ex-

cept the sector being erased). Figure 37, “Back-to-Back Read/Write Cycle

Timings,” on page 114 shows how read and write cycles may be initiated for si-

multaneous operation with zero latency. Refer to the DC Characteristics table for

read-while-program and read-while-erase current specifications.

Writing Commands/Command Sequences

The device has the capability of performing an asynchronous or synchronous

write operation. While the device is configured in Asynchronous read mode, it is

able to perform Asynchronous write operations only. CLK is ignored in the Asyn-

chronous programming mode. When in the Synchronous read mode

configuration, the device is able to perform both Asynchronous and Synchronous

write operations. CLK and WE# address latch is supported in the Synchronous

programming mode. During a synchronous write operation, to write a command

or command sequence (which includes programming data to the device and eras-

ing sectors of memory), the system must drive AVD# and CE# to V_IL, and OE#

to V_IHwhen providing an address to the device, and drive WE# and CE# to V_IL,

and OE# to V_IH. when writing commands or data. During an asynchronous write

operation, the system must drive CE# and WE# to V_ILand OE# to V_IHwhen pro-

viding an address, command, and data. Addresses are latched on the last falling

edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#.

The asynchronous and synchronous programing operation is independent of the

Set Device Read Mode bit in the Configuration Register (see Table 17, “Configu-

ration Register,” on page 68).

The device features an Unlock Bypass mode to facilitate faster programming.

Once the device enters the Unlock Bypass mode, only two write cycles are re-

quired to program a word, instead of four.

An erase operation can erase one sector, multiple sectors, or the entire device.

Table 12, “WS128J Sector Address Table,” on page 50 and Table 13, “WS064J

Sector Address Table,” on page 58 indicate the address space that each sector oc-

cupies. The device address space is divided into four banks. A “bank address” is

the address bits required to uniquely select a bank. Similarly, a “sector address”

is the address bits required to uniquely select a sector.

I_CC2in the “DC Characteristics” section on page 90 represents the active current

specification for the write mode. The AC Characteristics section contains timing

specification tables and timing diagrams for write operations.

Accelerated Program Operation

The device offers accelerated program operations through the ACC function. ACC

is primarily intended to allow faster manufacturing throughput at the factory.

If the system asserts V_HHon this input, the device automatically enters the afore-

mentioned Unlock Bypass mode and uses the higher voltage on the input to

reduce the time required for program operations. The system would use a two-

cycle program command sequence as required by the Unlock Bypass mode. Re-

moving V_HHfrom the ACC input returns the device to normal operation. Note that

sectors must be unlocked prior to raising ACC to V_HH. Note that the ACC pin must

not be at V_HHfor operations other than accelerated programming, or device dam-

age may result. In addition, the ACC pin must not be left floating or unconnected;

inconsistent behavior of the device may result.

When at V_IL, ACC locks all sectors. ACC should be at V_IHfor all other conditions.

May 5, 2004

S29WS128/064J

30

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sec-

tor protection verification, through identifier codes output from the internal

register (which is separate from the memory array) on DQ15–DQ0. This mode is

primarily intended for programming equipment to automatically match a device

to be programmed with its corresponding programming algorithm. However, the

autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires V_IDon ad-

dress pin A9. Address pins must be as shown in Table 3, “Autoselect Codes (High

Voltage Method),” on page 32. In addition, when verifying sector protection, the

sector address must appear on the appropriate highest order address bits (see

Table 4, “S29WS128/064J_MCP Boot Sector/Sector Block Addresses for Protec-

tion/Unprotection,” on page 32 and Table 5, “S29WS064J Boot Sector/Sector

Block Addresses for Protection/Unprotection,” on page 34). Table 3 shows the

remaining address bits that are don’t care. When all necessary bits have been

set as required, the programming equipment may then read the corresponding

identifier code on DQ15–DQ0. However, the autoselect codes can also be ac-

cessed in-system through the command register, for instances when the device

is erased or programmed in a system without access to high voltage on the A9

pin. The command sequence is illustrated in Table 18, “Command Definitions,”

on page 78. Note that if a Bank Address (BA) on address bits A22, A21, and A20

for the WS128J (A21:A19 for the WS064J) is asserted during the third write

cycle of the autoselect command, the host system can read autoselect data that

bank and then immediately read array data from the other bank, without exiting

the autoselect mode.

To access the autoselect codes in-system, the host system can issue the autose-

lect command via the command register, as shown in Table 18, “Command

Definitions,” on page 78. This method does not require V_ID. Autoselect mode

may only be entered and used when in the asynchronous read mode. Refer to

the “Autoselect Command Sequence” section on page 68 for more information.

31

S29WS128/064J

May 5, 2004

Table 3. Autoselect Codes (High Voltage Method)

Ama

x

to

A11

to

A5

to

WE

#

DQ15

to DQ0

Description

CE# OE#

RESET# A12 A10 A9 A8 A7 A6 A4 A3 A2 A1 A0

Manufacturer ID

FASL

:

V_ID

L

H

X

L

X

L

H

L

0001h

227Eh

Read Cycle 1

Read Cycle 2

2218h (WS128J)

221Eh (WS064J)

H

2200h (WS128J)

2201h (WS064J)

Read Cycle 3

H

L

H

L

H

L

Sector Protection

Verification

0001h (protected),

0000h (unprotected)

SA

DQ15 - DQ8 = 0

DQ7 - Factory Lock Bit

1 = Locked, 0 = Not Locked

DQ6 -Customer Lock Bit

1 = Locked, 0 = Not Locked

DQ5 = Handshake Bit

1 = Reserved, 0 = Standard

Handshake

V_ID

Indicator Bits

L

H

X

L

X

L

H

L

DQ4 & DQ3 - Boot Code

DQ2 - DQ0 = 001

Hardware Sector

Group Protection

0001h (protected),

0000h (unprotected)

V_ID

SA

X

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, BA = Bank Address, SA = Sector Address, X = Don’t care.

Notes:

1. The autoselect codes may also be accessed in-system via command sequences.

2. PPB Protection Status is shown on the data bus

Sector/Sector Block Protection and Unprotection

The hardware sector protection feature disables both programming and erase op-

erations in any sector. The hardware sector unprotection feature re-enables both

program and erase operations in previously protected sectors. Sector protection/

unprotection can be implemented via two methods.

(Note: For the following discussion, the term “sector” applies to both sectors and

sector blocks. A sector block consists of two or more adjacent sectors that are

protected or unprotected at the same time (see Table 4, “S29WS128/064J_MCP

Boot Sector/Sector Block Addresses for Protection/Unprotection,” on page 32 and

Table 5, “S29WS064J Boot Sector/Sector Block Addresses for Protection/Unpro-

tection,” on page 34).)

Table 4. S29WS128/064J_MCP Boot Sector/Sector Block Addresses for Protection/Unprotection

Sector/

Sector

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

A22–A12

Sector Block Size

00000000000

00000000001

00000000010

00000000011

00000000100

00000000101

00000000110

00000000111

4 Kwords

May 5, 2004

S29WS128/064J

32

Sector/

Sector

A22–A12

Sector Block Size

SA8

00000001XXX,

00000010XXX,

00000011XXX,

000001XXXXX

000010XXXXX

000011XXXXX

000100XXXXX

000101XXXXX

000110XXXXX

000111XXXXX

001000XXXXX

001001XXXXX

001010XXXXX

001011XXXXX

001100XXXXX

001101XXXXX

001110XXXXX

001111XXXXX

010000XXXXX

010001XXXXX

010010XXXXX

010011XXXXX

010100XXXXX

010101XXXXX

010110XXXXX

010111XXXXX

011000XXXXX

011001XXXXX

011010XXXXX

011011XXXXX

011100XXXXX

011101XXXXX

011110XXXXX

011111XXXXX

100000XXXXX

100001XXXXX

100010XXXXX

100011XXXXX

100100XXXXX

100101XXXXX

100110XXXXX

100111XXXXX

101000XXXXX

101001XXXXX

101010XXXXX

101011XXXXX

101100XXXXX

101101XXXXX

32 Kwords

SA9

32 Kwords

SA10

32 Kwords

SA11–SA14

SA15–SA18

SA19–SA22

SA23-SA26

SA27-SA30

SA31-SA34

SA35-SA38

SA39-SA42

SA43-SA46

SA47-SA50

SA51–SA54

SA55–SA58

SA59–SA62

SA63–SA66

SA67–SA70

SA71–SA74

SA75–SA78

SA79–SA82

SA83–SA86

SA87–SA90

SA91–SA94

SA95–SA98

SA99–SA102

SA103–SA106

SA107–SA110

SA111–SA114

SA115–SA118

SA119–SA122

SA123–SA126

SA127–SA130

SA131-SA134

SA135-SA138

SA139-SA142

SA143-SA146

SA147-SA150

SA151–SA154

SA155–SA158

SA159–SA162

SA163–SA166

SA167–SA170

SA171–SA174

SA175–SA178

SA179–SA182

SA183–SA186

SA187–SA190

128 (4x32) Kwords

33

S29WS128/064J

May 5, 2004

Sector/

Sector

SA191–SA194

SA195–SA198

SA199–SA202

SA203–SA206

SA207–SA210

SA211–SA214

SA215–SA218

SA219–SA222

SA223–SA226

SA227–SA230

SA231–SA234

SA235–SA238

SA239–SA242

SA243–SA246

SA247–SA250

SA251–SA254

SA255–SA258

SA259

A22–A12

Sector Block Size

101110XXXXX

101111XXXXX

110000XXXXX

110001XXXXX

110010XXXXX

110011XXXXX

110100XXXXX

110101XXXXX

110110XXXXX

110111XXXXX

111000XXXXX

111001XXXXX

111010XXXXX

111011XXXXX

111100XXXXX

111101XXXXX

111110XXXXX

11111100XXX

11111101XXX

11111110XXX

11111111000

11111111001

11111111010

11111111011

11111111100

11111111101

11111111110

11111111111

128 (4x32) Kwords

32 Kwords

SA260

32 Kwords

SA261

32 Kwords

SA262

4 Kwords

SA263

4 Kwords

SA264

4 Kwords

SA265

4 Kwords

SA266

4 Kwords

SA267

4 Kwords

SA268

4 Kwords

SA269

4 Kwords

Table 5. S29WS064J Boot Sector/Sector Block Addresses for Protection/Unprotection

Sector/

Sector

SA0

A21–A12

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

0000001XXX

0000010XXX

0000011XXX

00001XXXXX

00010XXXXX

00011XXXXX

00100XXXXX

00101XXXXX

Sector Block Size

4 Kwords

SA1

4 Kwords

SA2

4 Kwords

SA3

4 Kwords

SA4

4 Kwords

SA5

4 Kwords

SA6

4 Kwords

SA7

4 Kwords

SA8

32 Kwords

SA9

32 Kwords

SA10

32 Kwords

SA11–SA14

SA15–SA18

SA19–SA22

SA23-SA26

SA27-SA30

128 (4x32) Kwords

May 5, 2004

S29WS128/064J

34

Sector/

Sector

SA31-SA34

SA35-SA38

SA39-SA42

SA43-SA46

SA47-SA50

SA51–SA54

SA55–SA58

SA59–SA62

SA63–SA66

SA67–SA70

SA71–SA74

SA75–SA78

SA79–SA82

SA83–SA86

SA87–SA90

SA91–SA94

SA95–SA98

SA99–SA102

SA103–SA106

SA107–SA110

SA111–SA114

SA115–SA118

SA119–SA122

SA123–SA126

SA127–SA130

SA131

A21–A12

Sector Block Size

00110XXXXX

00111XXXXX

01000XXXXX

01001XXXXX

01010XXXXX

01011XXXXX

01100XXXXX

01101XXXXX

01110XXXXX

01111XXXXX

10000XXXXX

10001XXXXX

10010XXXXX

10011XXXXX

10100XXXXX

10101XXXXX

10110XXXXX

10111XXXXX

11000XXXXX

11001XXXXX

11010XXXXX

11011XXXXX

11100XXXXX

11101XXXXX

11110XXXXX

1111100XXX

1111101XXX

1111110XXX

1111111000

1111111001

1111111010

1111111011

1111111100

1111111101

1111111110

1111111111

128 (4x32) Kwords

32 Kwords

SA132

32 Kwords

SA133

32 Kwords

SA134

4 Kwords

SA135

4 Kwords

SA136

4 Kwords

SA137

4 Kwords

SA138

4 Kwords

SA139

4 Kwords

SA140

4 Kwords

SA141

4 Kwords

35

S29WS128/064J

May 5, 2004

Sector Protection

The device features several levels of sector protection, which can disable both the

program and erase operations in certain sectors or sector groups:

Persistent Sector Protection

A command sector protection method that replaces the old 12 V controlled pro-

tection method.

Password Sector Protection

A highly sophisticated protection method that requires a password before

changes to certain sectors or sector groups are permitted

WP# Hardware Protection

A write protect pin that can prevent program or erase operations in the outer-

most sectors.

All parts default to operate in the Persistent Sector Protection mode. The cus-

tomer must then choose if the Persistent or Password Protection method is most

desirable. There are two one-time programmable non-volatile bits that define

which sector protection method will be used. If the customer decides to continue

using the Persistent Sector Protection method, they must set the Persistent

Sector Protection Mode Locking Bit. This will permanently set the part to op-

erate only using Persistent Sector Protection. If the customer decides to use the

password method, they must set the Password Mode Locking Bit. This will

permanently set the part to operate only using password sector protection.

It is important to remember that setting either the Persistent Sector Protec-

tion Mode Locking Bit or the Password Mode Locking Bit permanently

selects the protection mode. It is not possible to switch between the two meth-

ods once a locking bit has been set. It is important that one mode is

explicitly selected when the device is first programmed, rather than re-

lying on the default mode alone. This is so that it is not possible for a system

program or virus to later set the Password Mode Locking Bit, which would cause

an unexpected shift from the default Persistent Sector Protection Mode into the

Password Protection Mode.

The WP# Hardware Protection feature is always available, independent of the

software managed protection method chosen.

The device is shipped with all sectors unprotected. Optional Spansion™ pro-

gramming services enable programming and protecting sectors at the factory

prior to shipping the device. Contact your local sales office for Details.

It is possible to determine whether a sector is protected or unprotected. See

“Autoselect Command Sequence” section on page 68 for details.

Persistent Sector Protection

The Persistent Sector Protection method replaces the old 12 V controlled protec-

tion method while at the same time enhancing flexibility by providing three

different sector protection states:

Persistently Locked—A sector is protected and cannot be changed.

Dynamically Locked—The sector is protected and can be changed by a sim-

ple command

Unlocked—The sector is unprotected and can be changed by a simple com-

mand

In order to achieve these states, three types of “bits” are going to be used:

May 5, 2004

S29WS128/064J

36

Persistent Protection Bit (PPB)

A single Persistent (non-volatile) Protection Bit is assigned to a maximum of four

sectors (“S29WS128/064J_MCP Boot Sector/Sector Block Addresses for Protec-

tion/Unprotection” section on page 32, “S29WS064J Boot Sector/Sector Block

Addresses for Protection/Unprotection” section on page 34). All 4 Kbyte boot-

block sectors have individual sector Persistent Protection Bits (PPBs) for greater

flexibility. Each PPB is individually modifiable through the PPB Program

Command.

Note: If a PPB requires erasure, all of the sector PPBs must first be prepro-

grammed prior to PPB erasing. All PPBs erase in parallel, unlike programming

where individual PPBs are programmable. It is the responsibility of the user to

perform the preprogramming operation. Otherwise, an already erased sector

PPBs has the potential of being over-erased. There is no hardware mechanism to

prevent sector PPBs over-erasure.

Persistent Protection Bit Lock (PPB Lock)

A global volatile bit. When set to “1”, the PPBs cannot be changed. When cleared

(“0”), the PPBs are changeable. There is only one PPB Lock bit per device. The

PPB Lock is cleared after power-up or hardware reset. There is no command se-

quence to unlock the PPB Lock.

Dynamic Protection Bit (DYB)

A volatile protection bit is assigned for each sector. After power-up or hardware

reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through

the DPB Write Command.

When the parts are first shipped, the PPBs are cleared (“0”). The DPBs and PPB

Lock are defaulted to power up in the cleared state – meaning the PPBs are

changeable.

When the device is first powered on, the DYBs power up in the cleared state

(sectors not protected). The Protection State for each sector is determined by

the logical OR of the PPB and the DPB related to that sector. For the sectors that

have the PPBs cleared, the DPBs control whether or not the sector is protected

or unprotected. By issuing the DPB Write command sequences, the DPBs will be

set or cleared, thus placing each sector in the protected or unprotected state.

These are the so-called Dynamic Locked or Unlocked states. They are called

dynamic states because it is very easy to switch back and forth between the

protected and unprotected conditions. This allows software to easily protect sec-

tors against inadvertent changes yet does not prevent the easy removal of

protection when changes are needed. The DPBs maybe set or cleared as often

as needed.

The PPBs allow for a more static, and difficult to change, level of protection. The

PPBs retain their state across power cycles because they are Non-Volatile. Indi-

vidual PPBs are set with a command but must all be cleared as a group through

a complex sequence of program and erasing commands. The PPBs are also lim-

ited to 100 erase cycles.

The PBB Lock bit adds an additional level of protection. Once all PPBs are pro-

grammed to the desired settings, the PPB Lock may be set to “1”. Setting the

PPB Lock disables all program and erase commands to the Non-Volatile PPBs. In

effect, the PPB Lock Bit locks the PPBs into their current state. The only way to

clear the PPB Lock is to go through a power cycle. System boot code can deter-

mine if any changes to the PPB are needed e.g. to allow new system code to be

downloaded. If no changes are needed then the boot code can set the PPB Lock

to disable any further changes to the PPBs during system operation.

37

S29WS128/064J

May 5, 2004

The WP# write protect pin adds a final level of hardware protection to the four

outermost 4 Kbytes sectors (SA0 - SA3 for a bottom boot, WS128J: SA266 -

SA269, WS064J: SA138 - SA141, or SA0 - SA3 & WS128J: SA266 - SA269,

WS064J: SA138 - SA141 for a dual boot). When this pin is low it is not possible

to change the contents of these four sectors. These sectors generally hold sys-

tem boot code. So, the WP# pin can prevent any changes to the boot code that

could override the choices made while setting up sector protection during sys-

tem initialization.

It is possible to have sectors that have been persistently locked, and sectors

that are left in the dynamic state. The sectors in the dynamic state are all un-

protected. If there is a need to protect some of them, a simple DPB Write

command sequence is all that is necessary. The DPB write command for the dy-

namic sectors switch the DPBs to signify protected and unprotected,

respectively. If there is a need to change the status of the persistently locked

sectors, a few more steps are required. First, the PPB Lock bit must be disabled

by either putting the device through a power-cycle, or hardware reset. The PPBs

can then be changed to reflect the desired settings. Setting the PPB lock bit once

again will lock the PPBs, and the device operates normally again.

Note: to achieve the best protection, it’s recommended to execute the PPB lock

bit set command early in the boot code, and protect the boot code by holding

WP# = V_IL.

Table 6. Sector Protection Schemes

DPB

PPB

PPB Lock

Sector State

0

1

0

1

0

1

0

Unprotected—PPB and DPB are changeable

Protected—PPB and DPB are changeable

Unprotected—PPB not changeable, DPB is

changeable

0

1

0

1

0

1

Protected—PPB not changeable, DPB is

changeable

Protected—PPB not changeable, DPB is

changeable

Protected—PPB not changeable, DPB is

changeable

Table 6 contains all possible combinations of the DPB, PPB, and PPB lock relating

to the status of the sector.

In summary, if the PPB is set, and the PPB lock is set, the sector is protected and

the protection can not be removed until the next power cycle clears the PPB

lock. If the PPB is cleared, the sector can be dynamically locked or unlocked. The

DPB then controls whether or not the sector is protected or unprotected.

If the user attempts to program or erase a protected sector, the device ignores

the command and returns to read mode. A program command to a protected

sector enables status polling for approximately 1 µs before the device returns to

read mode without having modified the contents of the protected sector. An

erase command to a protected sector enables status polling for approximately

May 5, 2004

S29WS128/064J

38

50 µs after which the device returns to read mode without having erased the

protected sector.

The programming of the DPB, PPB, and PPB lock for a given sector can be veri-

fied by writing a DPB/PPB/PPB lock verify command to the device.

Persistent Sector Protection Mode Locking Bit

Like the password mode locking bit, a Persistent Sector Protection mode locking

bit exists to guarantee that the device remain in software sector protection.

Once set, the Persistent Sector Protection locking bit prevents programming of

the password protection mode locking bit. This guarantees that a hacker could

not place the device in password protection mode.

Password Protection Mode

The Password Sector Protection Mode method allows an even higher level of se-

curity than the Persistent Sector Protection Mode. There are two main

differences between the Persistent Sector Protection and the Password Sector

Protection Mode:

When the device is first powered on, or comes out of a reset cycle, the PPB

Lock bit is set to the locked state, rather than cleared to the unlocked state.

The only means to clear the PPB Lock bit is by writing a unique 64-bit Pass-

word to the device.

The Password Sector Protection method is otherwise identical to the Persistent

Sector Protection method.

A 64-bit password is the only additional tool utilized in this method.

The password is stored in a the SecSi™ (Secured Silicon) region of the flash

memory. Once the Password Mode Locking Bit is set, the password is perma-

nently set with no means to read, program, or erase it. The password is used to

clear the PPB Lock bit. The Password Unlock command must be written to the

flash, along with a password. The flash device internally compares the given

password with the pre-programmed password. If they match, the PPB Lock bit is

cleared, and the PPBs can be altered. If they do not match, the flash device does

nothing. There is a built-in 2 µs delay for each “password check.” This delay is

intended to thwart any efforts to run a program that tries all possible combina-

tions in order to crack the password.

Password and Password Mode Locking Bit

In order to select the Password sector protection scheme, the customer must first

program the password. FASL recommends that the password be somehow corre-

lated to the unique Electronic Serial Number (ESN) of the particular flash device.

Each ESN is different for every flash device; therefore each password should be

different for every flash device. While programming in the password region, the

customer may perform Password Verify operations.

Once the desired password is programmed in, the customer must then set the

Password Mode Locking Bit. This operation achieves two objectives:

1. It permanently sets the device to operate using the Password Protection

Mode. It is not possible to reverse this function.

2. It also disables all further commands to the password region. All program,

and read operations are ignored.

Both of these objectives are important, and if not carefully considered, may lead

to unrecoverable errors. The user must be sure that the Password Protection

method is desired when setting the Password Mode Locking Bit. More impor-

tantly, the user must be sure that the password is correct when the Password

39

S29WS128/064J

May 5, 2004

Mode Locking Bit is set. Due to the fact that read operations are disabled, there

is no means to verify what the password is afterwards. If the password is lost

after setting the Password Mode Locking Bit, there will be no way to clear the

PPB Lock bit.

The Password Mode Locking Bit, once set, prevents reading the 64-bit password

on the DQ bus and further password programming. The Password Mode Locking

Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persis-

tent Sector Protection Locking Bit is disabled from programming, guaranteeing

that no changes to the protection scheme are allowed.

64-bit Password

The 64-bit Password is located in its own memory space and is accessible

through the use of the Password Program and Verify commands (see “Password

Program Command” section on page 74 and “Password Verify Command” sec-

tion on page 74). The password function works in conjunction with the Password

Mode Locking Bit, which when set, prevents the Password Verify command from

reading the contents of the password on the pins of the device.

Persistent Protection Bit Lock

The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of

the Password Mode Locking Bit after power-up reset. If the Password Mode Lock

Bit is also set, after a hardware reset (RESET# asserted) or a power-up reset

the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to

issue the Password Unlock command. Successful execution of the Password Un-

lock command clears the PPB Lock Bit, allowing for sector PPBs modifications.

Asserting RESET#, taking the device through a power-on reset, or issuing the

PPB Lock Bit Set command sets the PPB Lock Bit to a “1”.

If the Password Mode Locking Bit is not set, including Persistent Protection

Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB

Lock Bit is setable by issuing the PPB Lock Bit Set command. Once set the only

means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset.

The Password Unlock command is ignored in Persistent Protection Mode.

High Voltage Sector Protection

Sector protection and unprotection may also be implemented using programming

equipment. The procedure requires high voltage (VID) to be placed on the RE-

SET# pin. Refer to Figure 2, “In-System Sector Protection/Sector Unprotection

Algorithms,” on page 43 for details on this procedure. Note that for sector unpro-

tect, all unprotected sectors must be first protected prior to the first sector write

cycle. Once the Password Mode Locking bit or Persistent Protection Locking bit are

set, the high voltage sector protect/unprotect capability is disabled.

Standby Mode

When the system is not reading or writing to the device, it can place the device

in the standby mode. In this mode, current consumption is greatly reduced, and

the outputs are placed in the high impedance state, independent of the OE#

input.

The device enters the CMOS standby mode when the CE# and RESET# inputs are

both held at V_CC± 0.2 V. The device requires standard access time (t_CE) for read

access, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws ac-

tive current until the operation is completed.

May 5, 2004

S29WS128/064J

40

I_CC3in the “DC Characteristics” section on page 90 represents the standby cur-

rent specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. While in

asynchronous mode, the device automatically enables this mode when addresses

remain stable for t_ACC+ 60 ns. The automatic sleep mode is independent of the

CE#, WE#, and OE# control signals. Standard address access timings provide

new data when addresses are changed. While in sleep mode, output data is

latched and always available to the system. Based on the implementation by

design, the Auto Power Down feature is disabled in synchronous mode

and enabled in asynchronous mode. As a result, in synchronous mode,

the device can be in Auto Power Down Mode only by deselecting the CE#.

Note that a new burst operation is required to provide new data.

I_CC6in the “DC Characteristics” section on page 90 represents the automatic

sleep mode current specification.

RESET#: Hardware Reset Input

The RESET# input provides a hardware method of resetting the device to reading

array data. When RESET# is driven low for at least a period of t_RP, the device im-

mediately terminates any operation in progress, tristates all outputs, resets the

configuration register, and ignores all read/write commands for the duration of

the RESET# pulse. The device also resets the internal state machine to reading

array data. The operation that was interrupted should be reinitiated once the de-

vice is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held

at V_SS± 0.2 V, the device draws CMOS standby current (I_CC4). If RESET# is held

at V_ILbut not within V_SS± 0.2 V, the standby current will be greater.

RESET# may be tied to the system reset circuitry. A system reset would thus also

reset the Flash memory, enabling the system to read the boot-up firmware from

the Flash memory.

If RESET# is asserted during a program or erase operation, the device requires

a time of t_READY(during Embedded Algorithms) before the device is ready to read

data again. If RESET# is asserted when a program or erase operation is not ex-

ecuting, the reset operation is completed within a time of t_READY(not during

Embedded Algorithms). The system can read data t_RHafter RESET# returns to

V_IH.

Refer to the “AC Characteristics” section on page 99 for RESET# parameters and

to Figure 21, “Reset Timings,” on page 99 for the timing diagram.

41

S29WS128/064J

May 5, 2004

Output Disable Mode

When the OE# input is at V_IH, output from the device is disabled. The outputs are

placed in the high impedance state.

START

RESET# = V_ID

(Note 1)

Perform Erase or

Program Operations

RESET# = V_IH

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected (If WP# = V_IL, outermost boot sectors will remain protected).

2. All previously protected sectors are protected once again.

Figure 1. Temporary Sector Unprotect Operation

May 5, 2004

S29WS128/064J

42

START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

PLSCNT = 1

RESET# = V_ID

unprotected sectors

prior to issuing the

first sector

Wait 1 µs

unprotect address

No

First Write

Cycle = 60h?

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

address

Sector Unprotect:

Wait 150 µs

Write 60h to sector

address with

A7:A0 =

Verify Sector

Protect: Write 40h

to sector address

with A7:A0 =

01000010

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 1.5 ms

00000010

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector address

with A6 = 1,

Data = 01h?

Yes

A1 = 1, A0 = 0

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

Sector Unprotect

Algorithm

from RESET#

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

Figure 2. In-System Sector Protection/Sector Unprotection Algorithms

43

S29WS128/064J

May 5, 2004

SecSi™ (Secured Silicon) Sector Flash Memory Region

The SecSi™ (Secured Silicon) Sector feature provides a Flash memory region

that enables permanent part identification through an Electronic Serial Number

(ESN). The SecSi™ Sector is 128 words in length and located at addresses

000000h-000007h. The Factory Indicator Bit (DQ7) is used to indicate whether

or not the Factory SecSi™ Sector is locked when shipped from the factory. The

Customer Indicator Bit (DQ6) is used to indicate whether or not the Customer

SecSi™ Sector is locked when shipped from the factory. These bits are perma-

nently set at the factory and cannot be changed, in order to prevent cloning of a

factory locked part. This ensures the security of the ESN and customer code

once the product is shipped to the field.

FASL™ offers the device with a 64 word Factory SecSi™ Sector that is locked

when the part is shipped and a 64 words Customer SecSi™ Sector that is either

locked or is lockable. The Factory SecSi™ Sector is always protected when

shipped from the factory, and has the Factory Indicator Bit (DQ7) permanently

set to a “1”. The Customer SecSi™ Sector is shipped unprotected with the Cus-

tomer Indicator Bit (DQ6) set to “0”, allowing customers to utilize that sector in

any manner they choose. Once the Customer SecSi™ Sector area is protected,

the Customer Indicator Bit will be permanently set to “1.”

The system accesses the SecSi™ Sector through a command sequence (see

“Enter SecSi™ Sector/Exit SecSi™ Sector Command Sequence”). After the sys-

tem has written the Enter SecSi™ Sector command sequence, it may read the

SecSi™ Sector by using the addresses normally occupied by the memory array.

This mode of operation continues until the system issues the Exit SecSi™ Sector

command sequence, or until power is removed from the device. While SecSi™

Sector access is enabled, Memory Array read access, program operations, and

erase operations to all sectors other than SA0 are also available. On power-up,

or following a hardware reset, the device reverts to sending commands to the

normal address space.

Factory Locked: Factor SecSi™ Sector Programmed and Protected At the

Factory

In a factory sector locked device, the Factory SecSi™ Sector is protected when

the device is shipped from the factory whether or not the area was programmed

at the factory. The Factory SecSi™ Sector cannot be modified in any way. Op-

tional Spansion™ programming service can preprogram a random ESN, a

customer-defined code, or any combination of the two. The Factory SecSi™ Sec-

tor is located at addresses 000000h–00003Fh.

The device is available preprogrammed with one of the following:

A random, secure ESN only within the Factor SecSi™ Sector

Customer code within the Customer SecSi™ Sector through the Spansion

programming service

Both a random, secure ESN and customer code through the Spansion pro-

gramming service.

Table 7. SecSi™ Sector Addresses

Sector

Customer

Factory

Sector Size

64 words

Address Range

000040h-00007Fh

000000h-00003Fh

64 words

Customers may opt to have their code programmed by FASL through the Span-

sion programming service. FASL programs the customer’s code, with or without

the random ESN. The devices are then shipped from FASL’s factory with the Fac-

May 5, 2004

S29WS128/064J

44

tory SecSi™ Sector and Customer SecSi™ Sector permanently locked. Contact

the local sales office for details on using Spansion programming services.

Customer SecSi™ Sector

The customer lockable area is shipped unprotected, which allows the customer

to program and optionally lock the area as appropriate for the application. secu-

rity feature is not required, the Customer SecSi™ Sector can be treated as an

additional Flash memory space. The Customer SecSi™ Sector can be read any

number of times, but can be programmed and locked only once. Note that the

accelerated programming (ACC) and unlock bypass functions are not available

when programming the Customer SecSi™ Sector, but reading in Banks A, B, and

C is available. The Customer SecSi™ Sector is located at addresses 000040h–

00007Fh.

The Customer SecSi™ Sector area can be protected using one of the following

procedures:

Write the three-cycle Enter SecSi™ Sector Region command sequence, and

then follow the in-system sector protect algorithm as shown in Figure 2, “In-

System Sector Protection/Sector Unprotection Algorithms,” on page 43 ex-

cept that RESET# may be at either V_IHor V_ID. This allows in-system protec-

tion of the Customer SecSi™ Sector Region without raising any device pin to

a high voltage. Note that this method is only applicable to the SecSi™ Sector.

Write the SecSi™ Sector Protection Bit Lock command sequence.

Once the Customer SecSi™ Sector is locked and verified, the system must write

the Exit SecSi™ Sector Region command sequence to return to reading and

writing the remainder of the array.

The Customer SecSi™ Sector lock must be used with caution since, once locked,

there is no procedure available for unlocking the Customer SecSi™ Sector area

and none of the bits in the Customer SecSi™ Sector memory space can be mod-

ified in any way.

SecSi™ Sector Protection Bit

The Customer SecSi™ Sector Protection Bit prevents programming of the Cus-

tomer SecSi™ Sector memory area. Once set, the Customer SecSi™ Sector

memory area contents are non-modifiable.

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing

provides data protection against inadvertent writes (refer to Table 18, “Command

Definitions,” on page 78 for command definitions).

The device offers two types of data protection at the sector level:

The PPB and DPB associated command sequences disables or re-enables both

program and erase operations in any sector or sector group.

When WP# is at V_IL, the four outermost sectors are locked.

When ACC is at V_IL, all sectors are locked.

The following hardware data protection measures prevent accidental erasure or

programming, which might otherwise be caused by spurious system level signals

during V_CCpower-up and power-down transitions, or from system noise.

Write Protect (WP#)

The Write Protect feature provides a hardware method of protecting the four

outermost sectors. This function is provided by the WP# pin and overrides the

previously discussed Sector Protection/Unprotection method.

45

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May 5, 2004

If the system asserts V_ILon the WP# pin, the device disables program and erase

functions in the four “outermost” 4 Kword boot sectors. The four outermost 4

Kword boot sectors are the four sectors containing the lowest addresses (SA0 -

SA3), or the four sectors containing the highest addresses (WS128J: SA266 -

SA269, WS064J: SA138 - SA141) or both the lower four (SA0 - SA3) and upper

four sectors (WS128J: SA266 - SA269, WS064J: SA138 - SA141) in a dual-boot-

configured device.

If the system asserts V_IHon the WP# pin, the device reverts to whether the

upper and/or lower four sectors were last set to be protected or unprotected.

That is, sector protection or unprotection for these sectors depends on whether

they were last protected or unprotected using the method described in “PPB Pro-

gram Command” section on page 76.

Note that the WP# pin must not be left floating or unconnected; inconsistent be-

havior of the device may result.

Low V

Write Inhibit

CC

When V_CCis less than V_LKO, the device does not accept any write cycles. This pro-

tects data during V_CCpower-up and power-down. The command register and all

internal program/erase circuits are disabled, and the device resets to reading

array data. Subsequent writes are ignored until V_CCis greater than V_LKO. The sys-

tem must provide the proper signals to the control inputs to prevent unintentional

writes when V_CCis greater than V_LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write

cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = V_IL, CE# = V_IHor WE# =

V_IH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a

logical one.

Power-Up Write Inhibit

If WE# = CE# = RESET# = V_ILand OE# = V_IHduring power up, the device does

not accept commands on the rising edge of WE#. The internal state machine is

automatically reset to the read mode on power-up.

May 5, 2004

S29WS128/064J

46

Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification outlines device and host system

software interrogation handshake, which allows specific vendor-specified soft-

ware algorithms to be used for entire families of devices. Software support can

then be device-independent, JEDEC ID-independent, and forward- and back-

ward-compatible for the specified flash device families. Flash vendors can

standardize their existing interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query

command, 98h, to address 55h any time the device is ready to read array data.

The system can read CFI information at the addresses given in Tables 8-11. To

terminate reading CFI data, the system must write the reset command.

The system can also write the CFI query command when the device is in the au-

toselect mode. The device enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 8-11. The system must write the reset

command to return the device to the autoselect mode.

For further information, please refer to the CFI Specification and CFI Publication

100, available via the FASL site at the following URL:

http://www.amd.com/us-en/FlashMemory/TechnicalResources/

0,,37_1693_1780_1834^1955,00.html. Alternatively, contact an FASL represen-

tative for copies of these documents.

Table 8. CFI Query Identification String

Addresses

Data

Description

10h

11h

12h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

Primary OEM Command Set

13h

14h

0002h

0000h

15h

16h

0040h

0000h

Address for Primary Extended Table

17h

18h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

0000h

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May 5, 2004

Table 9. System Interface String

Addresses

Data

Description

V_CCMin. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Bh

0017h

V_CCMax. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch

0019h

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

0000h

0003h

0000h

0009h

0000h

0004h

0000h

0004h

0000h

V_PPMin. voltage (00h = no V_PPpin present)

V_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^Nµs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

Table 10. Device Geometry Definition

Addresses

Data

Description

0018h (WS128J)

0017h (WS064J)

27h

Device Size = 2^Nbyte

28h

29h

0001h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

0000h

Max. number of bytes in multi-byte write = 2^N

(00h = not supported)

2Ch

0003h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

00FDh (WS128J)

007Dh (WS064J)

31h

Erase Block Region 2 Information

32h

33h

34h

0000h

0001h

35h

36h

37h

38h

0007h

0000h

0020h

0000h

Erase Block Region 3 Information

Erase Block Region 4 Information

39h

3Ah

3Bh

3Ch

0000h

May 5, 2004

S29WS128/064J

48

Table 11. Primary Vendor-Specific Extended Query

Addresses

Data

Description

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

0031h

0033h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

45h

000Ch

Silicon Technology (Bits 5-2) 0011 = 0.13 µm

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46h

47h

48h

49h

0002h

0001h

0007h

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

07 = Advanced Sector Protection

00E7h (WS128J)

0077h (WS064J)

Simultaneous Operation

Number of Sectors in all banks except boot block

4Ah

Burst Mode Type

00 = Not Supported, 01 = Supported

4Bh

4Ch

0001h

0000h

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word Page

ACC (Acceleration) Supply Minimum

4Dh

4Eh

4Fh

00B5h

00C5h

0001h

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag

01h = Dual Boot Device, 02h = Bottom Boot Device, 03h = Top Boot Device

50h

57h

0000h

0004h

Program Suspend. 00h = not supported

Bank Organization: X = Number of banks

0027h (WS128J)

0017h (WS064J)

58h

59h

5Ah

5Bh

Bank A Region Information. X = Number of sectors in bank

Bank B Region Information. X = Number of sectors in bank

Bank C Region Information. X = Number of sectors in bank

Bank D Region Information. X = Number of sectors in bank

0060h (WS128J)

0030h (WS064J)

0060h (WS128J)

0030h (WS064J)

0027h (WS128J)

0017h (WS064J)

49

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May 5, 2004

Table 12. WS128J Sector Address Table

Bank

Sector

SA0

Sector Size

4 Kwords

(x16) Address Range

000000h-000FFFh

001000h-001FFFh

002000h-002FFFh

003000h-003FFFh

004000h-004FFFh

005000h-005FFFh

006000h-006FFFh

007000h-007FFFh

008000h-00FFFFh

010000h-017FFFh

018000h-01FFFFh

020000h-027FFFh

028000h-02FFFFh

030000h-037FFFh

038000h-03FFFFh

040000h-047FFFh

048000h-04FFFFh

050000h-057FFFh

058000h-05FFFFh

060000h-067FFFh

068000h-06FFFFh

070000h-077FFFh

078000h-07FFFFh

080000h-087FFFh

088000h-08FFFFh

090000h-097FFFh

098000h-09FFFFh

0A0000h-0A7FFFh

0A8000h-0AFFFFh

0B0000h-0B7FFFh

0B8000h-0BFFFFh

0C0000h-0C7FFFh

0C8000h-0CFFFFh

0D0000h-0D7FFFh

0D8000h-0DFFFFh

0E0000h-0E7FFFh

0E8000h-0EFFFFh

0F0000h-0F7FFFh

0F8000h-0FFFFFh

SA1

4 Kwords

SA2

4 Kwords

SA3

4 Kwords

SA4

4 Kwords

SA5

4 Kwords

SA6

4 Kwords

SA7

4 Kwords

SA8

32 Kwords

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

Bank D

May 5, 2004

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50

Table 12. WS128J Sector Address Table (Continued)

Bank

Sector

Sector Size

32 Kwords

(x16) Address Range

100000h-107FFFh

108000h-10FFFFh

110000h-117FFFh

118000h-11FFFFh

120000h-127FFFh

128000h-12FFFFh

130000h-137FFFh

138000h-13FFFFh

140000h-147FFFh

148000h-14FFFFh

150000h-157FFFh

158000h-15FFFFh

160000h-167FFFh

168000h-16FFFFh

170000h-177FFFh

178000h-17FFFFh

180000h-187FFFh

188000h-18FFFFh

190000h-197FFFh

198000h-19FFFFh

1A0000h-1A7FFFh

1A8000h-1AFFFFh

1B0000h-1B7FFFh

1B8000h-1BFFFFh

1C0000h-1C7FFFh

1C8000h-1CFFFFh

1D0000h-1D7FFFh

1D8000h-1DFFFFh

1E0000h-1E7FFFh

1E8000h-1EFFFFh

1F0000h-1F7FFFh

1F8000h-1FFFFFh

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

Bank C

51

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May 5, 2004

Table 12. WS128J Sector Address Table (Continued)

Bank

Sector

Sector Size

32 Kwords

(x16) Address Range

200000h-207FFFh

208000h-20FFFFh

210000h-217FFFh

218000h-21FFFFh

220000h-227FFFh

228000h-22FFFFh

230000h-237FFFh

238000h-23FFFFh

240000h-247FFFh

248000h-24FFFFh

250000h-257FFFh

258000h-25FFFFh

260000h-267FFFh

268000h-26FFFFh

270000h-277FFFh

278000h-27FFFFh

280000h-287FFFh

288000h-28FFFFh

290000h-297FFFh

298000h-29FFFFh

2A0000h-2A7FFFh

2A8000h-2AFFFFh

2B0000h-2B7FFFh

2B8000h-2BFFFFh

2C0000h-2C7FFFh

2C8000h-2CFFFFh

2D0000h-2D7FFFh

2D8000h-2DFFFFh

2E0000h-2E7FFFh

2E8000h-2EFFFFh

2F0000h-2F7FFFh

2F8000h-2FFFFFh

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

Bank C

May 5, 2004

S29WS128/064J

52

Table 12. WS128J Sector Address Table (Continued)

Bank

Sector

Sector Size

32 Kwords

(x16) Address Range

300000h-307FFFh

308000h-30FFFFh

310000h-317FFFh

318000h-31FFFFh

320000h-327FFFh

328000h-32FFFFh

330000h-337FFFh

338000h-33FFFFh

340000h-347FFFh

348000h-34FFFFh

350000h-357FFFh

358000h-35FFFFh

360000h-367FFFh

368000h-36FFFFh

370000h-377FFFh

378000h-37FFFFh

380000h-387FFFh

388000h-38FFFFh

390000h-397FFFh

398000h-39FFFFh

3A0000h-3A7FFFh

3A8000h-3AFFFFh

3B0000h-3B7FFFh

3B8000h-3BFFFFh

3C0000h-3C7FFFh

3C8000h-3CFFFFh

3D0000h-3D7FFFh

3D8000h-3DFFFFh

3E0000h-3E7FFFh

3E8000h-3EFFFFh

3F0000h-3F7FFFh

3F8000h-3FFFFFh

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

Bank C

53

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Table 12. WS128J Sector Address Table (Continued)

Bank

Sector

Sector Size

32 Kwords

(x16) Address Range

400000h-407FFFh

408000h-40FFFFh

410000h-417FFFh

418000h-41FFFFh

420000h-427FFFh

428000h-42FFFFh

430000h-437FFFh

438000h-43FFFFh

440000h-447FFFh

448000h-44FFFFh

450000h-457FFFh

458000h-45FFFFh

460000h-467FFFh

468000h-46FFFFh

470000h-477FFFh

478000h-47FFFFh

480000h-487FFFh

488000h-48FFFFh

490000h-497FFFh

498000h-49FFFFh

4A0000h-4A7FFFh

4A8000h-4AFFFFh

4B0000h-4B7FFFh

4B8000h-4BFFFFh

4C0000h-4C7FFFh

4C8000h-4CFFFFh

4D0000h-4D7FFFh

4D8000h-4DFFFFh

4E0000h-4E7FFFh

4E8000h-4EFFFFh

4F0000h-4F7FFFh

4F8000h-4FFFFFh

SA135

SA136

SA137

SA138

SA139

SA140

SA141

SA142

SA143

SA144

SA145

SA146

SA147

SA148

SA149

SA150

SA151

SA152

SA153

SA154

SA155

SA156

SA157

SA158

SA159

SA160

SA161

SA162

SA163

SA164

SA165

SA166

Bank B

May 5, 2004

S29WS128/064J

54

Table 12. WS128J Sector Address Table (Continued)

Bank

Sector

Sector Size

32 Kwords

(x16) Address Range

500000h-507FFFh

508000h-50FFFFh

510000h-517FFFh

518000h-51FFFFh

520000h-527FFFh

528000h-52FFFFh

530000h-537FFFh

538000h-53FFFFh

540000h-547FFFh

548000h-54FFFFh

550000h-557FFFh

558000h-55FFFFh

560000h-567FFFh

568000h-56FFFFh

570000h-577FFFh

578000h-57FFFFh

580000h-587FFFh

588000h-58FFFFh

590000h-597FFFh

598000h-59FFFFh

5A0000h-5A7FFFh

5A8000h-5AFFFFh

5B0000h-5B7FFFh

5B8000h-5BFFFFh

5C0000h-5C7FFFh

5C8000h-5CFFFFh

5D0000h-5D7FFFh

5D8000h-5DFFFFh

5E0000h-5E7FFFh

5E8000h-5EFFFFh

5F0000h-5F7FFFh

5F8000h-5FFFFFh

SA167

SA168

SA169

SA170

SA171

SA172

SA173

SA174

SA175

SA176

SA177

SA178

SA179

SA180

SA181

SA182

SA183

SA184

SA185

SA186

SA187

SA188

SA189

SA190

SA191

SA192

SA193

SA194

SA195

SA196

SA197

SA198

Bank B

55

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Table 12. WS128J Sector Address Table (Continued)

Bank

Sector

Sector Size

32 Kwords

(x16) Address Range

600000h-607FFFh

608000h-60FFFFh

610000h-617FFFh

618000h-61FFFFh

620000h-627FFFh

628000h-62FFFFh

630000h-637FFFh

638000h-63FFFFh

640000h-647FFFh

648000h-64FFFFh

650000h-657FFFh

658000h-65FFFFh

660000h-667FFFh

668000h-66FFFFh

670000h-677FFFh

678000h-67FFFFh

680000h-687FFFh

688000h-68FFFFh

690000h-697FFFh

698000h-69FFFFh

6A0000h-6A7FFFh

6A8000h-6AFFFFh

6B0000h-6B7FFFh

6B8000h-6BFFFFh

6C0000h-6C7FFFh

6C8000h-6CFFFFh

6D0000h-6D7FFFh

6D8000h-6DFFFFh

6E0000h-6E7FFFh

6E8000h-6EFFFFh

6F0000h-6F7FFFh

6F8000h-6FFFFFh

SA199

SA200

SA201

SA202

SA203

SA204

SA205

SA206

SA207

SA208

SA209

SA210

SA211

SA212

SA213

SA214

SA215

SA216

SA217

SA218

SA219

SA220

SA221

SA222

SA223

SA224

SA225

SA226

SA227

SA228

SA229

SA230

Bank B

May 5, 2004

S29WS128/064J

56

Table 12. WS128J Sector Address Table (Continued)

Bank

Sector

Sector Size

32 Kwords

4 Kwords

(x16) Address Range

700000h-707FFFh

708000h-70FFFFh

710000h-717FFFh

718000h-71FFFFh

720000h-727FFFh

728000h-72FFFFh

730000h-737FFFh

738000h-73FFFFh

740000h-747FFFh

748000h-74FFFFh

750000h-757FFFh

758000h-75FFFFh

760000h-767FFFh

768000h-76FFFFh

770000h-777FFFh

778000h-77FFFFh

780000h-787FFFh

788000h-78FFFFh

790000h-797FFFh

798000h-79FFFFh

7A0000h-7A7FFFh

7A8000h-7AFFFFh

7B0000h-7B7FFFh

7B8000h-7BFFFFh

7C0000h-7C7FFFh

7C8000h-7CFFFFh

7D0000h-7D7FFFh

7D8000h-7DFFFFh

7E0000h-7E7FFFh

7E8000h-7EFFFFh

7F0000h-7F7FFFh

7F8000h-7F8FFFh

7F9000h-7F9FFFh

7FA000h-7FAFFFh

7FB000h-7FBFFFh

7FC000h-7FCFFFh

7FD000h-7FDFFFh

7FE000h-7FEFFFh

7FF000h-7FFFFFh

SA231

SA232

SA233

SA234

SA235

SA236

SA237

SA238

SA239

SA240

SA241

SA242

SA243

SA244

SA245

SA246

SA247

SA248

SA249

SA250

SA251

SA252

SA253

SA254

SA255

SA256

SA257

SA258

SA259

SA260

SA261

SA262

SA263

SA264

SA265

SA266

SA267

SA268

SA269

Bank A

4 Kwords

57

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May 5, 2004

Table 13. WS064J Sector Address Table

Bank

Sector

SA0

Sector Size

4 Kwords

32 Kwords

(x16) Address Range

000000h-000FFFh

001000h-001FFFh

002000h-002FFFh

003000h-003FFFh

004000h-004FFFh

005000h-005FFFh

006000h-006FFFh

007000h-007FFFh

008000h-00FFFFh

010000h-017FFFh

018000h-01FFFFh

020000h-027FFFh

028000h-02FFFFh

030000h-037FFFh

038000h-03FFFFh

040000h-047FFFh

048000h-04FFFFh

050000h-057FFFh

058000h-05FFFFh

060000h-067FFFh

068000h-06FFFFh

070000h-077FFFh

078000h-07FFFFh

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

Bank D

May 5, 2004

S29WS128/064J

58

Table 13. WS064J Sector Address Table (Continued)

Bank

Sector

Sector Size

32 Kwords

(x16) Address Range

080000h-087FFFh

088000h-08FFFFh

090000h-097FFFh

098000h-09FFFFh

0A0000h-0A7FFFh

0A8000h-0AFFFFh

0B0000h-0B7FFFh

0B8000h-0BFFFFh

0C0000h-0C7FFFh

0C8000h-0CFFFFh

0D0000h-0D7FFFh

0D8000h-0DFFFFh

0E0000h-0E7FFFh

0E8000h-0EFFFFh

0F0000h-0F7FFFh

0F8000h-0FFFFFh

100000h-107FFFh

108000h-10FFFFh

110000h-117FFFh

118000h-11FFFFh

120000h-127FFFh

128000h-12FFFFh

130000h-137FFFh

138000h-13FFFFh

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

Bank C

59

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May 5, 2004

Table 13. WS064J Sector Address Table (Continued)

Bank

Sector

Sector Size

32 Kwords

(x16) Address Range

140000h-147FFFh

148000h-14FFFFh

150000h-157FFFh

158000h-15FFFFh

160000h-167FFFh

168000h-16FFFFh

170000h-177FFFh

178000h-17FFFFh

180000h-187FFFh

188000h-18FFFFh

190000h-197FFFh

198000h-19FFFFh

1A0000h-1A7FFFh

1A8000h-1AFFFFh

1B0000h-1B7FFFh

1B8000h-1BFFFFh

1C0000h-1C7FFFh

1C8000h-1CFFFFh

1D0000h-1D7FFFh

1D8000h-1DFFFFh

1E0000h-1E7FFFh

1E8000h-1EFFFFh

1F0000h-1F7FFFh

1F8000h-1FFFFFh

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

Bank C

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Table 13. WS064J Sector Address Table (Continued)

Bank

Sector

Sector Size

32 Kwords

(x16) Address Range

200000h-207FFFh

208000h-20FFFFh

210000h-217FFFh

218000h-21FFFFh

220000h-227FFFh

228000h-22FFFFh

230000h-237FFFh

238000h-23FFFFh

240000h-247FFFh

248000h-24FFFFh

250000h-257FFFh

258000h-25FFFFh

260000h-267FFFh

268000h-26FFFFh

270000h-277FFFh

278000h-27FFFFh

280000h-287FFFh

288000h-28FFFFh

290000h-297FFFh

298000h-29FFFFh

2A0000h-2A7FFFh

2A8000h-2AFFFFh

2B0000h-2B7FFFh

2B8000h-2BFFFFh

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

Bank B

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Table 13. WS064J Sector Address Table (Continued)

Bank

Sector

Sector Size

32 Kwords

(x16) Address Range

2C0000h-2C7FFFh

2C8000h-2CFFFFh

2D0000h-2D7FFFh

2D8000h-2DFFFFh

2E0000h-2E7FFFh

2E8000h-2EFFFFh

2F0000h-2F7FFFh

2F8000h-2FFFFFh

300000h-307FFFh

308000h-30FFFFh

310000h-317FFFh

318000h-31FFFFh

320000h-327FFFh

328000h-32FFFFh

330000h-337FFFh

338000h-33FFFFh

340000h-347FFFh

348000h-34FFFFh

350000h-357FFFh

358000h-35FFFFh

360000h-367FFFh

368000h-36FFFFh

370000h-377FFFh

378000h-37FFFFh

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

Bank B

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Table 13. WS064J Sector Address Table (Continued)

Bank

Sector

Sector Size

32 Kwords

4 Kwords

(x16) Address Range

380000h-387FFFh

388000h-38FFFFh

390000h-397FFFh

398000h-39FFFFh

3A0000h-3A7FFFh

3A8000h-3AFFFFh

3B0000h-3B7FFFh

3B8000h-3BFFFFh

3C0000h-3C7FFFh

3C8000h-3CFFFFh

3D0000h-3D7FFFh

3D8000h-3DFFFFh

3E0000h-3E7FFFh

3E8000h-3EFFFFh

3F0000h-3F7FFFh

3F8000h-3F8FFFh

3F9000h-3F9FFFh

3FA000h-3FAFFFh

3FB000h-3FBFFFh

3FC000h-3FCFFFh

3FD000h-3FDFFFh

3FE000h-3FEFFFh

3FF000h-3FFFFFh

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

Bank A

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Command Definitions

Writing specific address and data commands or sequences into the command

register initiates device operations. Table 18, “Command Definitions,” on page 78

defines the valid register command sequences. Writing incorrect address and

data values or writing them in the improper sequence may place the device in an

unknown state. The system must write the reset command to return the device

to reading array data. Refer to the AC Characteristics section for timing diagrams.

Reading Array Data

The device is automatically set to reading array data after device power-up. No

commands are required to retrieve data in asynchronous mode. Each bank is

ready to read array data after completing an Embedded Program or Embedded

Erase algorithm.

After the device accepts an Erase Suspend command, the corresponding bank

enters the erase-suspend-read mode, after which the system can read data from

any non-erase-suspended sector within the same bank. After completing a pro-

gramming operation in the Erase Suspend mode, the system may once again

read array data from any non-erase-suspended sector within the same bank. See

the “Erase Suspend/Erase Resume Commands” section on page 73 for more

information.

The system must issue the reset command to return a bank to the read (or erase-

suspend-read) mode if DQ5 goes high during an active program or erase opera-

tion, or if the bank is in the autoselect mode. See the “Reset Command” section

on page 68 for more information.

See also “Requirements for Asynchronous Read Operation (Non-Burst)” section

on page 27 and “Requirements for Synchronous (Burst) Read Operation” section

on page 28 for more information. The Asynchronous Read and Synchronous/

Burst Read tables provide the read parameters, and Figure 14, “CLK Synchronous

Burst Mode Read (rising active CLK),” on page 94, Figure 16, “Synchronous Burst

Mode Read,” on page 95, and Figure 19, “Asynchronous Mode Read with Latched

Addresses,” on page 98 show the timings.

Set Configuration Register Command Sequence

The device uses a configuration register to set the various burst parameters:

number of wait states, burst read mode, active clock edge, RDY configuration,

and synchronous mode active. The configuration register must be set before the

device will enter burst mode.

The configuration register is loaded with a three-cycle command sequence. The

first two cycles are standard unlock sequences. On the third cycle, the data

should be C0h, address bits A11–A0 should be 555h, and address bits A19–A12

set the code to be latched. The device will power up or after a hardware reset

with the default setting, which is in asynchronous mode. The register must be set

before the device can enter synchronous mode. The configuration register can

not be changed during device operations (program, erase, or sector lock).

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Power-up/

Hardware Reset

Asynchronous Read

Mode Only

Set Burst Mode

Configuration Register

Command for

Set Burst Mode

Configuration Register

Command for

Synchronous Mode

(D15 = 0)

Asynchronous Mode

(D15 = 1)

Synchronous Read

Mode Only

Figure 3. Synchronous/Asynchronous State Diagram

Read Mode Setting

On power-up or hardware reset, the device is set to be in asynchronous read

mode. This setting allows the system to enable or disable burst mode during sys-

tem operations. Address A19 determines this setting: “1’ for asynchronous mode,

“0” for synchronous mode.

Programmable Wait State Configuration

The programmable wait state feature informs the device of the number of clock

cycles that must elapse after AVD# is driven active before data will be available.

This value is determined by the input frequency of the device. Address bits A14–

A12 determine the setting (see Table 14, “Programmable Wait State Settings,” on

page 66).

The wait state command sequence instructs the device to set a particular number

of clock cycles for the initial access in burst mode. The number of wait states that

should be programmed into the device is directly related to the clock frequency.

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Table 14. Programmable Wait State Settings

A14

0

A13

0

A12

0

Total Initial Access Cycles

2

0

1

3

0

1

0

4

5

0

1

0

6

1

0

1

7 (default)

Reserved

1

0

1

Notes:

1. Upon power-up or hardware reset, the default setting is seven wait states.

2. RDY will default to being active with data when the Wait State Setting is set to a total initial access cycle of 2.

It is recommended that the wait state command sequence be written, even if the

default wait state value is desired, to ensure the device is set as expected. A

hardware reset will set the wait state to the default setting.

Standard wait-state Handshaking Option

The host system must set the appropriate number of wait states in the flash de-

vice depending upon the clock frequency. The host system should set address bits

A14–A12 to 010 for a clock frequency of 66/80 MHz.

Table 15 describes the typical number of clock cycles (wait states) for various

conditions.

Table 15. Wait States for Standard wait-state Handshaking

Typical No. of Clock Cycles after AVD# Low

Burst Mode

8-Word or 16-Word or Continuous

32-Word

Conditions

V_IO= 1.8 V

66/80 MHz

4

5

* In the 8-, 16- and 32-word burst read modes, the address pointer does not cross 64-word boundaries (addresses

which are multiples of 3Fh).

The host system must set the appropriate number of wait states in the flash de-

vice depending upon the clock frequency. The autoselect function allows the host

system to determine whether the flash device is enabled for handshaking. See

the “Autoselect Command Sequence” section on page 68 for more information.

Read Mode Configuration

The device supports four different read modes: continuous mode, and 8, 16, and

32 word linear wrap around modes. A continuous sequence begins at the starting

address and advances the address pointer until the burst operation is complete.

If the highest address in the device is reached during the continuous burst read

mode, the address pointer wraps around to the lowest address.

For example, an eight-word linear read with wrap around begins on the starting

address written to the device and then advances to the next 8 word boundary.

The address pointer then returns to the 1st word after the previous eight word

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boundary, wrapping through the starting location. The sixteen- and thirty-two lin-

ear wrap around modes operate in a fashion similar to the eight-word mode.

Table 16 shows the address bits and settings for the four read modes.

Table 16. Read Mode Settings

Address Bits

Burst Modes

A16

0

A15

0

Continuous

8-word linear wrap around

16-word linear wrap around

32-word linear wrap around

0

1

0

1

Note: Upon power-up or hardware reset the default setting is continuous.

Burst Active Clock Edge Configuration

By default, the device will deliver data on the rising edge of the clock after the

initial synchronous access time. Subsequent outputs will also be on the following

rising edges, barring any delays. The device can be set so that the falling clock

edge is active for all synchronous accesses. Address bit A17 determines this set-

ting; “1” for rising active, “0” for falling active.

RDY Configuration

By default, the device is set so that the RDY pin will output V_OHwhenever there

is valid data on the outputs. The device can be set so that RDY goes active one

data cycle before active data. Address bit A18 determines this setting; “1” for

RDY active with data, “0” for RDY active one clock cycle before valid data. In

asynchronous mode, RDY is an open-drain output.

Configuration Register

Table 17 shows the address bits that determine the configuration register settings

for various device functions.

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Table 17. Configuration Register

Settings (Binary)

Address Bit

Function

Set Device

Read Mode

0 = Synchronous Read (Burst Mode) Enabled

1 = Asynchronous Mode (default)

A19

0 = RDY active one clock cycle before data

1 = RDY active with data (default)

A18

RDY

0 = Burst starts and data is output on the falling edge of CLK

1 = Burst starts and data is output on the rising edge of CLK (default)

A17

A16

Clock

Synchronous Mode

00 = Continuous (default)

Read Mode

01 = 8-word linear with wrap around

10 = 16-word linear with wrap around

11 = 32-word linear with wrap around

A15

A14

A13

000 = Data is valid on the 2nd active CLK edge after AVD# transition to V_IH

001 = Data is valid on the 3rd active CLK edge after AVD# transition to V_IH

010 = Data is valid on the 4th active CLK edge after AVD# transition to V_IH

011 = Data is valid on the 5th active CLK edge after AVD# transition to V_IH

100 = Data is valid on the 6th active CLK edge after AVD# transition to V_IH

101 = Data is valid on the 7th active CLK edge after AVD# transition to V_IH(default)

Programmable

Wait State

A12

110 = Reserved

111 = Reserved

Note: Device will be in the default state upon power-up or hardware reset.

Reset Command

Writing the reset command resets the banks to the read or erase-suspend-read

mode. Address bits are don’t cares for this command.

The reset command may be written between the sequence cycles in an erase

command sequence before erasing begins. This resets the bank to which the sys-

tem was writing to the read mode. Once erasure begins, however, the device

ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program

command sequence before programming begins (prior to the third cycle). This re-

sets the bank to which the system was writing to the read mode. If the program

command sequence is written to a bank that is in the Erase Suspend mode, writ-

ing the reset command returns that bank to the erase-suspend-read mode. Once

programming begins, however, the device ignores reset commands until the op-

eration is complete.

The reset command may be written between the sequence cycles in an autoselect

command sequence. Once in the autoselect mode, the reset command must be

written to return to the read mode. If a bank entered the autoselect mode while

in the Erase Suspend mode, writing the reset command returns that bank to the

erase-suspend-read mode.

If DQ5 goes high during a program or erase operation, writing the reset command

returns the banks to the read mode (or erase-suspend-read mode if that bank

was in Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manu-

facturer and device codes, and determine whether or not a sector is protected.

Table 18, “Command Definitions,” on page 78 shows the address and data re-

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68

quirements. The autoselect command sequence may be written to an address

within a bank that is either in the read or erase-suspend-read mode. The autose-

lect command may not be written while the device is actively programming or

erasing in the other bank.

The autoselect command sequence is initiated by first writing two unlock cycles.

This is followed by a third write cycle that contains the bank address and the au-

toselect command. The bank then enters the autoselect mode. No subsequent

data will be made available if the autoselect data is read in synchronous mode.

The system may read at any address within the same bank any number of times

without initiating another autoselect command sequence. Read commands to

other banks will return data from the array. The following table describes the ad-

dress requirements for the various autoselect functions, and the resulting data.

BA represents the bank address, and SA represents the sector address. The de-

vice ID is read in three cycles.

Description

Manufacturer ID

Device ID, Word 1

Address

(BA) + 00h

(BA) + 01h

Read Data

0001h

227Eh

2218h (WS128J)

221Eh (WS064J)

Device ID, Word 2

Device ID, Word 3

(BA) + 0Eh

2200h (WS128J)

2201h (WS064J)

(BA) + 0Fh

(SA) + 02h

Sector Protection

Verification

0001 (locked),

0000 (unlocked)

DQ15 - DQ8 = 0

DQ7 - Factory Lock Bit

1 = Locked, 0 = Not Locked

DQ6 -Customer Lock Bit

1 = Locked, 0 = Not Locked

DQ5 - Handshake Bit

1 = Reserved,

Indicator Bits

(BA) + 03h

0 = Standard Handshake

DQ4 & DQ3 - Boot Code

00 = Dual Boot Sector,

01 = Top Boot Sector,

10 = Bottom Boot Sector

DQ2 - DQ0 = 001

The system must write the reset command to return to the read mode (or erase-

suspend-read mode if the bank was previously in Erase Suspend).

Enter SecSi™ Sector/Exit SecSi™ Sector Command Sequence

The SecSi™ Sector region provides a secured data area containing a random,

eight word electronic serial number (ESN). The system can access the SecSi™

Sector region by issuing the three-cycle Enter SecSi™ Sector command se-

quence. The device continues to access the SecSi™ Sector region until the

system issues the four-cycle Exit SecSi™ Sector command sequence. The Exit

SecSi™ Sector command sequence returns the device to normal operation. The

SecSi™ Sector is not accessible when the device is executing an Embedded Pro-

gram or embedded Erase algorithm. Table 18, “Command Definitions,” on

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page 78 shows the address and data requirements for both command

sequences.

The following commands are not allowed when the SecSi™ is accessible.

— CFI

— Unlock Bypass Entry

— Unlock Bypass Program

— Unlock Bypass Reset

— Erase Suspend/Resume

— Chip Erase

Program Command Sequence

Programming is a four-bus-cycle operation. The program command sequence is

initiated by writing two unlock write cycles, followed by the program set-up com-

mand. The program address and data are written next, which in turn initiate the

Embedded Program algorithm. The system is not required to provide further con-

trols or timings. The device automatically provides internally generated program

pulses and verifies the programmed cell margin. Table 18, “Command Defini-

tions,” on page 78 shows the address and data requirements for the program

command sequence.

When the Embedded Program algorithm is complete, that bank then returns to

the read mode and addresses are no longer latched. The system can determine

the status of the program operation by monitoring DQ7 or DQ6/DQ2. Refer to the

“Write Operation Status” section on page 81 for information on these status bits.

Any commands written to the device during the Embedded Program Algorithm

are ignored. Note that a hardware reset immediately terminates the program op-

eration. The program command sequence should be reinitiated once that bank

has returned to the read mode, to ensure data integrity.

Programming is allowed in any sequence and across sector boundaries. A bit can-

not be programmed from “0” back to a “1.” Attempting to do so may cause that

bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bit to indicate the oper-

ation was successful. However, a succeeding read will show that the data is still

“0.” Only erase operations can convert a “0” to a “1.”

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to primarily program to a array

faster than using the standard program command sequence. The unlock bypass

command sequence is initiated by first writing two unlock cycles. This is followed

by a third write cycle containing the unlock bypass command, 20h. The device

then enters the unlock bypass mode. A two-cycle unlock bypass program com-

mand sequence is all that is required to program in this mode. The first cycle in

this sequence contains the unlock bypass program command, A0h; the second

cycle contains the program address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial two unlock cycles required

in the standard program command sequence, resulting in faster total program-

ming time. The host system may also initiate the chip erase and sector erase

sequences in the unlock bypass mode. The erase command sequences are four

cycles in length instead of six cycles. Table 18, “Command Definitions,” on

page 78 shows the requirements for the unlock bypass command sequences.

During the unlock bypass mode, only the Read, Unlock Bypass Program, Unlock

Bypass Sector Erase, Unlock Bypass Chip Erase, and Unlock Bypass Reset com-

mands are valid. To exit the unlock bypass mode, the system must issue the two-

cycle unlock bypass reset command sequence. The first cycle must contain the

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bank address and the data 90h. The second cycle need only contain the data 00h.

The array then returns to the read mode.

The device offers accelerated program operations through the ACC input. When

the system asserts V_HHon this input, the device automatically enters the Unlock

Bypass mode. The system may then write the two-cycle Unlock Bypass program

command sequence. The device uses the higher voltage on the ACC input to ac-

celerate the operation.

Figure 4, “Program Operation,” on page 71 illustrates the algorithm for the pro-

gram operation. Refer to the Erase/Program Operations table in the AC

Characteristics section for parameters, and Figure 22, “Asynchronous Program

Operation Timings: AVD# Latched Addresses,” on page 101 and Figure 24, “Syn-

chronous Program Operation Timings: WE# Latched Addresses,” on page 103 for

timing diagrams.

START

Write Program

Command Sequence

Data Poll

from System

Embedded

Program

algorithm

in progress

Verify Data?

No

Yes

No

Increment Address

Last Address?

Yes

Programming

Completed

Note: See Table 18 for program command sequence.

Figure 4. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is ini-

tiated by writing two unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the chip erase command,

which in turn invokes the Embedded Erase algorithm. The device does not require

the system to preprogram prior to erase. The Embedded Erase algorithm auto-

matically preprograms and verifies the entire memory for an all zero data pattern

prior to electrical erase. The system is not required to provide any controls or tim-

ings during these operations. Table 18, “Command Definitions,” on page 78

shows the address and data requirements for the chip erase command sequence.

When the Embedded Erase algorithm is complete, that bank returns to the read

mode and addresses are no longer latched. The system can determine the status

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of the erase operation by using DQ7 or DQ6/DQ2. Refer to the “Write Operation

Status” section on page 81 for information on these status bits.

Any commands written during the chip erase operation are ignored. However,

note that a hardware reset immediately terminates the erase operation. If that

occurs, the chip erase command sequence should be reinitiated once that bank

has returned to reading array data, to ensure data integrity.

The host system may also initiate the chip erase command sequence while the

device is in the unlock bypass mode. The command sequence is two cycles in

length instead of six cycles. See Table 18, “Command Definitions,” on page 78 for

details on the unlock bypass command sequences.

Figure 5, “Erase Operation,” on page 74 illustrates the algorithm for the erase op-

eration. Refer to the Erase/Program Operations table in the AC Characteristics

section for parameters and timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is

initiated by writing two unlock cycles, followed by a set-up command. Two addi-

tional unlock cycles are written, and are then followed by the address of the

sector to be erased, and the sector erase command. Table 18, “Command Defi-

nitions,” on page 78 shows the address and data requirements for the sector

erase command sequence.

The device does not require the system to preprogram prior to erase. The Em-

bedded Erase algorithm automatically programs and verifies the entire memory

for an all zero data pattern prior to electrical erase. The system is not required to

provide any controls or timings during these operations.

After the command sequence is written, a sector erase time-out of no less than

50 µs occurs. During the time-out period, additional sector addresses and sector

erase commands may be written. Loading the sector erase buffer may be done

in any sequence, and the number of sectors may be from one sector to all sectors.

The time between these additional cycles must be less than 50 µs, otherwise era-

sure may begin. Any sector erase address and command following the exceeded

time-out may or may not be accepted. It is recommended that processor inter-

rupts be disabled during this time to ensure all commands are accepted. The

interrupts can be re-enabled after the last Sector Erase command is written. Any

command other than Sector Erase or Erase Suspend during the time-out period

resets that bank to the read mode. The system must rewrite the command se-

quence and any additional addresses and commands.

The system can monitor DQ3 to determine if the sector erase timer has timed out

(See “DQ3: Sector Erase Timer” section on page 86.) The time-out begins from

the rising edge of the final WE# pulse in the command sequence.

When the Embedded Erase algorithm is complete, the bank returns to reading

array data and addresses are no longer latched. Note that while the Embedded

Erase operation is in progress, the system can read data from the non-erasing

bank. The system can determine the status of the erase operation by reading

DQ7 or DQ6/DQ2 in the erasing bank. Refer to the “Write Operation Status” sec-

tion on page 81 for information on these status bits.

Once the sector erase operation has begun, only the Erase Suspend command is

valid. All other commands are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that occurs, the sector erase

command sequence should be reinitiated once that bank has returned to reading

array data, to ensure data integrity.

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72

The host system may also initiate the sector erase command sequence while the

device is in the unlock bypass mode. The command sequence is four cycles cycles

in length instead of six cycles.

Figure 5, “Erase Operation,” on page 74 illustrates the algorithm for the erase op-

eration. Refer to the Erase/Program Operations table in the Figure , “AC

Characteristics,” on page 100 for parameters and timing diagrams.

Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the system to interrupt a sector erase

operation and then read data from, or program data to, any sector not selected

for erasure. The bank address is required when writing this command. This com-

mand is valid only during the sector erase operation, including the minimum 50

µs time-out period during the sector erase command sequence. The Erase Sus-

pend command is ignored if written during the chip erase operation or Embedded

Program algorithm.

When the Erase Suspend command is written during the sector erase operation,

the device requires a maximum of 35 µs to suspend the erase operation. How-

ever, when the Erase Suspend command is written during the sector erase time-

out, the device immediately terminates the time-out period and suspends the

erase operation.

After the erase operation has been suspended, the bank enters the erase-sus-

pend-read mode. The system can read data from or program data to any sector

not selected for erasure. (The device “erase suspends” all sectors selected for

erasure.) Reading at any address within erase-suspended sectors produces sta-

tus information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2

together, to determine if a sector is actively erasing or is erase-suspended. Refer

to the Figure , “Write Operation Status,” on page 81 for information on these sta-

tus bits.

After an erase-suspended program operation is complete, the bank returns to the

erase-suspend-read mode. The system can determine the status of the program

operation using the DQ7 or DQ6 status bits, just as in the standard program op-

eration. Refer to the “Write Operation Status” section on page 81 for more

information.

In the erase-suspend-read mode, the system can also issue the autoselect com-

mand sequence. Refer to the “Autoselect Mode” section on page 31 and

“Autoselect Command Sequence” section on page 68 for details.

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To resume the sector erase operation, the system must write the Erase Resume

command. The bank address of the erase-suspended bank is required when writ-

ing this command. Further writes of the Resume command are ignored. Another

Erase Suspend command can be written after the chip has resumed erasing.

START

Write Erase

Command Sequence

Data Poll

from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

Notes:

1. See Table 18 for erase command sequence.

2. See the section on DQ3 for information on the sector erase timer.

Figure 5. Erase Operation

Password Program Command

The Password Program Command permits programming the password that is

used as part of the hardware protection scheme. The actual password is 64-bits

long. 4 Password Program commands are required to program the password.

The user must enter the unlock cycle, password program command (38h) and

the program address/data for each portion of the password when programming.

There are no provisions for entering the 2-cycle unlock cycle, the password pro-

gram command, and all the password data. There is no special addressing order

required for programming the password. Also, when the password is undergoing

programming, Simultaneous Operation is disabled. Read operations to any

memory location will return the programming status except DQ7. Once pro-

gramming is complete, the user must issue a SecSi™ Exit command to return

the device to normal operation. Once the Password is written and verified, the

Password Mode Locking Bit must be set in order to prevent verification. The

Password Program Command is only capable of programming “0”s. Program-

ming a “1” after a cell is programmed as a “0” results in a time-out by the

Embedded Program Algorithm™ with the cell remaining as a “0”. The password

is all F’s when shipped from the factory. All 64-bit password combinations are

valid as a password.

Password Verify Command

The Password Verify Command is used to verify the Password. The Password is

verifiable only when the Password Mode Locking Bit is not programmed. If the

May 5, 2004

S29WS128/064J

74

Password Mode Locking Bit is programmed and the user attempts to verify the

Password, the device will always drive all F’s onto the DQ data bus.

Also, the device will not operate in Simultaneous Operation when the Password

Verify command is executed. Only the password is returned regardless of the

bank address. The lower two address bits (A1–A0) are valid during the Password

Verify. Writing the SecSi™ Exit command returns the device back to normal

operation.

Password Protection Mode Locking Bit Program Command

The Password Protection Mode Locking Bit Program Command programs the

Password Protection Mode Locking Bit, which prevents further verifies or up-

dates to the password. Once programmed, the Password Protection Mode

Locking Bit cannot be erased and the Persistent Protection Mode Locking Bit pro-

gram circuitry is disabled, thereby forcing the device to remain in the Password

Protection Mode. After issuing “PL/68h” at the fourth bus cycle, the device re-

quires a time out period of approximately 150 µs for programming the Password

Protection Mode Locking Bit. Then by writing “PL/48h” at the fifth bus cycle, the

device outputs verify data at DQ0. If DQ0 = 1, then the Password Protection

Mode Locking Bit is programmed. If not, the system must repeat this program

sequence from the fourth cycle of “PL/68h”. Exiting the Password Protection

Mode Locking Bit Program command is accomplished by writing the SecSi Sector

command.

Persistent Sector Protection Mode Locking Bit Program Command

The Persistent Sector Protection Mode Locking Bit Program Command programs

the Persistent Sector Protection Mode Locking Bit, which prevents the Password

Mode Locking Bit from ever being programmed. By disabling the program cir-

cuitry of the Password Mode Locking Bit, the device is forced to remain in the

Persistent Sector Protection mode of operation, once this bit is set. After issuing

“SMPL/68h” at the fourth bus cycle, the device requires a time out period of ap-

proximately 150 µs for programming the Persistent Protect ion Mode Locking Bit.

Then by writing “SMPL/48h” at the fifth bus cycle, the device outputs verify data

at DQ0. If DQ0 = 1, then the Persistent Protection Mode Locking Bit is pro-

grammed. If not, the system must repeat this program sequence from the

fourth cycle of “PL/68h”. Exiting the Persistent Protection Mode Locking Bit Pro-

gram command is accomplished by writing the SecSi Sector Exit command.

SecSi™ Sector Protection Bit Program Command

To protect the SecSi Sector, write the SecSi Sector Protect command sequence

while in the SecSi Sector mode. After issuing “OPBP/48h” at the fourth bus cycle,

the device requires a time out period of approximately 150 µs to protect the SecSi

Sector. Then, by writing “OPBP/48” at the fifth bus cycle, the device outputs verify

data at DQ0. If DQ0 = 1, then the SecSi Sector is protected. If not, then the sys-

tem must repeat this program sequence from the fourth cycle of “OPBP/48h”.

PPB Lock Bit Set Command

The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared ei-

ther at reset or if the Password Unlock command was successfully executed.

There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot

be cleared unless the device is taken through a power-on clear or the Password

Unlock command is executed. Upon setting the PPB Lock Bit, the PPBs are

latched into the DPBs. If the Password Mode Locking Bit is set, the PPB Lock Bit

status is reflected as set, even after a power-on reset cycle. Exiting the PPB Lock

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May 5, 2004

Bit Set command is accomplished by writing the SecSi™ Exit command, only

while in the Persistent Sector Protection Mode.

DPB Write/Erase/Status Command

The DPB Write command is used to set or clear a DPB for a given sector. The

high order address bits (Amax–A11) are issued at the same time as the code

01h or 00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data

write cycle. The DPBs are modifiable at any time, regardless of the state of the

PPB or PPB Lock Bit. If the PPB is set, the sector is protected regardless of the

value of the DPB. If the PPB is cleared, setting the DPB to a 1 protects the sector

from programs or erases. Since this is a volatile bit, removing power or resetting

the device will clear the DPBs. The programming of the DPB for a given sector

can be verified by writing a DPB Status command to the device. Exiting the DPB

Write/Erase command is accomplished by writing the Read/Reset command. Ex-

iting the DPB Status command is accomplished by writing the SecSi™ Sector

Exit command

Password Unlock Command

The Password Unlock command is used to clear the PPB Lock Bit so that the

PPBs can be unlocked for modification, thereby allowing the PPBs to become ac-

cessible for modification. The exact password must be entered in order for the

unlocking function to occur. This command cannot be issued any faster than 2 µs

at a time to prevent a hacker from running through the all 64-bit combinations

in an attempt to correctly match a password. If the command is issued before

the 2 µs execution window for each portion of the unlock, the command will be

ignored.

The Password Unlock function is accomplished by writing Password Unlock com-

mand and data to the device to perform the clearing of the PPB Lock Bit. The

password is 64 bits long, so the user must write the Password Unlock command

4 times. A1 and A0 are used for matching. Writing the Password Unlock com-

mand is not address order specific. The lower address A1–A0= 00, the next

Password Unlock command is to A1–A0= 01, then to A1–A0= 10, and finally to

A1–A0= 11.

Once the Password Unlock command is entered for all four words, the RDY pin

goes LOW indicating that the device is busy. Also, reading the Bank D results in

the DQ6 pin toggling, indicating that the Password Unlock function is in

progress. Reading the other bank returns actual array data. Approximately 1µs

is required for each portion of the unlock. Once the first portion of the password

unlock completes (RDY is not driven and DQ6 does not toggle when read), the

Password Unlock command is issued again, only this time with the next part of

the password. Four Password Unlock commands are required to successfully

clear the PPB Lock Bit. As with the first Password Unlock command, the RDY sig-

nal goes LOW and reading the device results in the DQ6 pin toggling on

successive read operations until complete. It is the responsibility of the micro-

processor to keep track of the number of Password Unlock commands, the order,

and when to read the PPB Lock bit to confirm successful password unlock. In

order to re lock the device into the Password Mode, the PPB Lock Bit Set com-

mand can be re-issued.

PPB Program Command

The PPB Program command is used to program, or set, a given PPB. Each PPB is

individually programmed (but is bulk erased with the other PPBs). The specific

sector address (Amax–A12) are written at the same time as the program com-

mand 60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set

May 5, 2004

S29WS128/064J

76

for the sector, the PPB Program command will not execute and the command will

time-out without programming the PPB.

After programming a PPB, two additional cycles are needed to determine whether

the PPB has been programmed with margin. After 4th cycle, the device requires

approximately 150 µs time out period for programming the PPB. And then after

5th cycle, the device outputs verify data at DQ0.

The PPB Program command does not follow the Embedded Program algorithm.

Writing the SecSi™ Sector Exit command returns the device back to normal

operation.

All PPB Erase Command

The All PPB Erase command is used to erase all PPBs in bulk. There is no means

for individually erasing a specific PPB. Unlike the PPB program, no specific sector

address is required. However, when the PPB erase command is written (60h)

and A6 = 1, all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the

ALL PPB Erase command will not execute and the command will time-out with-

out erasing the PPBs.

After erasing the PPBs, two additional cycles are needed to determine whether

the PPB has been erased with margin. After 4th cycle, the device requires ap-

proximately 1.5 ms time out period for erasing the PPB. And then after 5th

cycle, the device outputs verify data at DQ0.

It is the responsibility of the user to preprogram all PPBs prior to issuing the All

PPB Erase command. If the user attempts to erase a cleared PPB, over-erasure

may occur making it difficult to program the PPB at a later time. Also note that

the total number of PPB program/erase cycles is limited to 100 cycles. Cycling

the PPBs beyond 100 cycles is not guaranteed. Writing the SecSi™ Sector Exit

command returns the device back to normal operation.

PPB Status Command

The programming of the PPB for a given sector can be verified by writing a PPB

status verify command to the device.

PPB Lock Bit Status Command

The programming of the PPB Lock Bit for a given sector can be verified by writ-

ing a PPB Lock Bit status verify command to the device.

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Command Definitions

Table 18. Command Definitions

Bus Cycles (Notes 1–6)

Third Fourth Fifth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Command Sequence

(Note 1)

First

Second

Sixth

Seventh

Asynchronous Read (Note 7)

Reset (Note 8)

1

RA

RD

F0

XXX

(BA)

555

(BA)

X00

Manufacturer ID

4

6

4

555

AA

2AA

55

90

0001

227E

(BA)

555

(BA)

X01

(BA)X (Note (BA) (Not

Device ID (Note 10)

0E

10)

X0F e 10)

(SA)

555

(SA) 0000/

X02

Sector Lock Verify

(Note 11)

0001

(BA)

555

(BA)

X03

(Note

12)

Indicator Bits

Program

4

6

1

555

BA

AA

B0

30

2AA

55

555

A0

80

PA

Data

AA

Chip Erase

555

2AA

55

555

SA

10

30

Sector Erase

AA

Erase Suspend (Note 15)

Erase Resume (Note 16)

BA

(CR)

555

Set Configuration Register (Note 17)

3

555

AA

2AA

55

C0

20

CFI Query (Note 18)

1

55

98

Unlock Bypass Entry

3

555

AA

2AA

PA

55

PD

555

Unlock Bypass

Program (Notes 13,

14)

2

XX

A0

Unlock Bypass

Unlock

Sector Erase (Notes

2

XX

80

90

SA

30

Bypass

13, 14)

Mode

Unlock Bypass Erase

(Notes 13, 14)

XXX 10

XXX 00

Unlock Bypass Reset

(Notes 13, 14)

Sector Protection Command Definitions

SecSi™ Sector Entry

3

4

555

AA

2AA

55

555

88

90

SecSi™ Sector Exit

SecSi™

XX

00

68

Sector

SecSi™ Protection

Bit Program (Notes

19, 20, 22)

RD

(0)

6

555

AA

2AA

55

555

60

OW

48

OW

XX0

XX1

XX2

XX3

XX0

XX1

XX2

XX3

PD0

PD1

PD2

PD3

PD0

PD1

PD2

PD3

Password Program

(Notes 19, 24)

4

555

AA

2AA

55

555

38

Password

Protection

Password Verify

4

7

555

AA

2AA

55

555

C8

28

Password Unlock

(Note 24)

XX0

PD0 XX1 PD1 XX2 PD2 XX3 PD3

May 5, 2004

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78

Bus Cycles (Notes 1–6)

Third Fourth Fifth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Command Sequence

(Note 1)

First

Second

Sixth

Seventh

(SA)

+ WP

RD

(0)

PPB Program (Notes

(SA)

6

555

AA

2AA

55

555

60

68

60

48

40

XX

19, 20, 22)

+ WP

RD

(0)

PPB

All PPB Erase (Notes

Commands 19, 20, 23, 25)

(SA)

WP

(SA)

555

(SA)

X02

RD

(0)

PPB Status (Note 26)

4

3

4

555

AA

2AA

55

90

78

58

PPB Lock Bit Set

555

PPB Lock

Bit

(BA)

555

RD

(1)

PPB Lock Bit Status

(Note 20)

BA

DPB Write

DPB Erase

4

555

AA

2AA

55

555

48

SA

X1

X0

DPB

(BA)

555

RD

(0)

DPB Status

4

6

555

AA

2AA

55

58

60

SA

PL

Password Protection Mode

Locking Bit Program (Notes 19,

20, 22)

RD

(0)

555

68

PL

SL

48

PL

SL

Persistent Protection Mode

Locking Bit Program (Notes 19,

20, 22)

RD

(0)

6

555

AA

2AA

55

60

SL

Legend:

X = Don’t care

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses latch on the rising edge of the AVD# pulse or active edge of

CLK which ever comes first.

PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits Amax–A12 uniquely select any sector.

BA = Address of the bank (WS128J: A22, A21, A20, WS064J: A21, A20, A19) that is being switched to autoselect mode, is in

bypass mode, or is being erased.

SLA = Address of the sector to be locked. Set sector address (SA) and either A6 = 1 for unlocked or A6 = 0 for locked.

CR = Configuration Register address bits A19–A12.

OW = Address (A7–A0) is (00011010).

PD3–PD0 = Password Data. PD3–PD0 present four 16 bit combinations that represent the 64-bit Password

PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity.

PWD = Password Data.

PL = Address (A7-A0) is (00001010)

RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 1, if unprotected, DQ0 = 0.

RD(1) = DQ1 protection indicator bit. If protected, DQ1 = 1, if unprotected, DQ1 = 0.

SL = Address (A7-A0) is (00010010)

WD= Write Data. See “Configuration Register” definition for specific write data

WP = Address (A7-A0) is (00000010)

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands,

fourth cycle of the configuration register verify and password verify commands, and any cycle reading at RD(0) and RD(1).

4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD, WD, PWD, and PD3-PD0.

5. Unless otherwise noted, address bits Amax–A12 are don’t cares.

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May 5, 2004

6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown

state. The system must write the reset command to return the device to reading array data.

7. No unlock or command cycles required when bank is reading array data.

8. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase

Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or

performing sector lock/unlock.

9. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address. See the

Autoselect Command Sequence section for more information.

10. (BA)X0Fh = 2200h (WS128J), (BA)X0Eh = 2218h (WS128J), (BA)X0Fh = 221Eh (WS064J), (BA)X0Eh = 2201h (WS064J)

11. The data is 0000h for an unlocked sector and 0001h for a locked sector

12. DQ15 - DQ8 = 0, DQ7 - Factory Lock Bit (1 = Locked, 0 = Not Locked), DQ6 -Customer Lock Bit (1 = Locked, 0 = Not

Locked), DQ5 = Handshake Bit (1 = Reserved, 0 = Standard Handshake)8, DQ4 & DQ3 - Boot Code (00= Dual Boot Sector,

01= Top Boot Sector, 10= Bottom Boot Sector, 11=No Boot Sector), DQ2 - DQ0 = 001

13. The Unlock Bypass command sequence is required prior to this command sequence.

14. The Unlock Bypass Reset command is required to return to reading array data.

15. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase operation, and requires the bank address.

16. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address.

17. See “Set Configuration Register Command Sequence” for details.

18. Command is valid when device is ready to read array data or when device is in autoselect mode.

19. The Reset command returns the device to reading the array.

20. Regardless of CLK and AVD# interaction or Control Register bit 15 setting, command mode verifies are always asynchronous

read operations.

21. ACC must be at V_HHduring the entire operation of this command

22. The fourth cycle programs the addressed locking bit. The fifth and sixth cycles are used to validate whether the bit has been

fully programmed. If DQ0 (in the sixth cycle) reads 0, the program command must be issued and verified again.

23. The fourth cycle erases all PPBs. The fifth and sixth cycles are used to validate whether the bits have been fully erased. If

DQ0 (in the sixth cycle) reads 1, the erase command must be issued and verified again.

24. The entire four bus-cycle sequence must be entered for each portion of the password.

25. Before issuing the erase command, all PPBs should be programmed in order to prevent over-erasure of PPBs.

26. In the fourth cycle, 01h indicates PPB set; 00h indicates PPB not set.

May 5, 2004

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80

Write Operation Status

The device provides several bits to determine the status of a program or erase

operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 20, “Write Operation Status,”

on page 87 and the following subsections describe the function of these bits. DQ7

and DQ6 each offers a method for determining whether a program or erase op-

eration is complete or in progress.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded

Program or Erase algorithm is in progress or completed, or whether a bank is in

Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse

in the command sequence.

During the Embedded Program algorithm, the device outputs on DQ7 the com-

plement of the datum programmed to DQ7. This DQ7 status also applies to

programming during Erase Suspend. When the Embedded Program algorithm is

complete, the device outputs the datum programmed to DQ7. The system must

provide the program address to read valid status information on DQ7. If a pro-

gram address falls within a protected sector, Data# Polling on DQ7 is active for

approximately 1 µs, then that bank returns to the read mode.

During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.

When the Embedded Erase algorithm is complete, or if the bank enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide

an address within any of the sectors selected for erasure to read valid status in-

formation on DQ7.

After an erase command sequence is written, if all sectors selected for erasing

are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the

bank returns to the read mode. If not all selected sectors are protected, the Em-

bedded Erase algorithm erases the unprotected sectors, and ignores the selected

sectors that are protected. However, if the system reads DQ7 at an address within

a protected sector, the status may not be valid.

Just prior to the completion of an Embedded Program or Erase operation, DQ7

may change asynchronously with DQ6–DQ0 while Output Enable (OE#) is as-

serted low. That is, the device may change from providing status information to

valid data on DQ7. Depending on when the system samples the DQ7 output, it

may read the status or valid data. Even if the device has completed the program

or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may

be still invalid. Valid data on DQ7-D00 will appear on successive read cycles.

Table 20, “Write Operation Status,” on page 87 shows the outputs for Data# Poll-

ing on DQ7. Figure 6, “Data# Polling Algorithm,” on page 82 shows the Data#

Polling

algorithm.

Figure 28,

“Data#

Polling

Timings

(During Embedded Algorithm),” on page 107 in the AC Characteristics section

shows the Data# Polling timing diagram.

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May 5, 2004

START

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

No

PASS

FAIL

Notes:

1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within

the sector being erased. During chip erase, a valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

Figure 6. Data# Polling Algorithm

May 5, 2004

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82

RDY: Ready

The RDY is a dedicated output that, when the device is configured in the Synchro-

nous mode, indicates (when at logic low) the system should wait 1 clock cycle

before expecting the next word of data. The RDY pin is only controlled by CE#.

Using the RDY Configuration Command Sequence, RDY can be set so that a logic

low indicates the system should wait 2 clock cycles before expecting valid data.

The following conditions cause the RDY output to be low: during the initial access

(in burst mode), and after the boundary that occurs every 64 words beginning

with the 64th address, 3Fh.

When the device is configured in Asynchronous Mode, the RDY is an open-drain

output pin which indicates whether an Embedded Algorithm is in progress or

completed. The RDY status is valid after the rising edge of the final WE# pulse in

the command sequence.

If the output is low (Busy), the device is actively erasing or programming. (This

includes programming in the Erase Suspend mode.) If the output is in high im-

pedance (Ready), the device is in the read mode, the standby mode, or in the

erase-suspend-read mode. Table 20, “Write Operation Status,” on page 87 shows

the outputs for RDY.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm

is in progress or complete, or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address in the same bank, and is valid

after the rising edge of the final WE# pulse in the command sequence (prior to

the program or erase operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm operation, successive read cy-

cles to any address cause DQ6 to toggle. When the operation is complete, DQ6

stops toggling.

After an erase command sequence is written, if all sectors selected for erasing

are protected, DQ6 toggles for approximately 100 µs, then returns to reading

array data. If not all selected sectors are protected, the Embedded Erase algo-

rithm erases the unprotected sectors, and ignores the selected sectors that are

protected.

The system can use DQ6 and DQ2 together to determine whether a sector is ac-

tively erasing or is erase-suspended. When the device is actively erasing (that is,

the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en-

ters the Erase Suspend mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-

natively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).

If a program address falls within a protected sector, DQ6 toggles for approxi-

mately 1 ms after the program command sequence is written, then returns to

reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling

once the Embedded Program algorithm is complete.

See the following for additional information: Figure 7, “Toggle Bit Algorithm,” on

page 84, “DQ6: Toggle Bit I” on page 83, Figure 29, “Toggle Bit Timings

(During Embedded Algorithm),” on page 107 (toggle bit timing diagram), and

Table 19, “DQ6 and DQ2 Indications,” on page 85.

Toggle Bit I on DQ6 requires either OE# or CE# to be deasserteed and reasserted

to show the change in state.

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S29WS128/064J

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START

Read Byte

(DQ0-DQ7)

Address = VA

Read Byte

(DQ0-DQ7)

Address = VA

No

DQ6 = Toggle?

Yes

No

DQ5 = 1?

Yes

Read Byte Twice

(DQ 0-DQ7)

Adrdess = VA

No

DQ6 = Toggle?

Yes

FAIL

PASS

Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to

“1.” See the subsections on DQ6 and DQ2 for more information.

Figure 7. Toggle Bit Algorithm

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular

sector is actively erasing (that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit II is valid after the rising

edge of the final WE# pulse in the command sequence.

DQ2 toggles when the system reads at addresses within those sectors that have

been selected for erasure. But DQ2 cannot distinguish whether the sector is ac-

tively erasing or is erase-suspended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but cannot distinguish which

sectors are selected for erasure. Thus, both status bits are required for sector and

May 5, 2004

S29WS128/064J

84

mode information. Refer to Table 19, “DQ6 and DQ2 Indications,” on page 85 to

compare outputs for DQ2 and DQ6.

See the following for additional information: Figure 7, “Toggle Bit Algorithm,” on

page 84, “DQ6: Toggle Bit I” on page 83, Figure 29, “Toggle Bit Timings

(During Embedded Algorithm),” on page 107, and Table 19, “DQ6 and DQ2 Indi-

cations,” on page 85.

Table 19. DQ6 and DQ2 Indications

If device is

and the system reads

then DQ6

and DQ2

programming,

at any address,

toggles,

does not toggle.

at an address within a sector

selected for erasure,

toggles,

also toggles.

does not toggle.

toggles.

actively erasing,

erase suspended,

at an address within sectors not

selected for erasure,

at an address within a sector

selected for erasure,

does not toggle,

returns array data,

toggles,

at an address within sectors not

returns array data. The system can read

from any sector not selected for erasure.

selected for erasure,

programming in

erase suspend

at any address,

is not applicable.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 7, “Toggle Bit Algorithm,” on page 84 for the following discussion.

Whenever the system initially begins reading toggle bit status, it must read DQ7–

DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typi-

cally, the system would note and store the value of the toggle bit after the first

read. After the second read, the system would compare the new value of the tog-

gle bit with the first. If the toggle bit is not toggling, the device has completed

the program or erase operation. The system can read array data on DQ7–DQ0 on

the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle

bit is still toggling, the system also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should then determine again

whether the toggle bit is toggling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer toggling, the device has suc-

cessfully completed the program or erase operation. If it is still toggling, the

device did not completed the operation successfully, and the system must write

the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit

is toggling and DQ5 has not gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles, determining the status as de-

scribed in the previous paragraph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the beginning of the algo-

rithm when it returns to determine the status of the operation (Figure 7, “Toggle

Bit Algorithm,” on page 84).

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DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified inter-

nal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that

the program or erase cycle was not successfully completed.

The device may output a “1” on DQ5 if the system tries to program a “1” to a

location that was previously programmed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the device halts the operation,

and when the timing limit has been exceeded, DQ5 produces a “1.”

Under both these conditions, the system must write the reset command to return

to the read mode (or to the erase-suspend-read mode if a bank was previously

in the erase-suspend-program mode).

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to de-

termine whether or not erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional sectors are selected for erasure,

the entire time-out also applies after each additional sector erase command.

When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the

time between additional sector erase commands from the system can be as-

sumed to be less than 50 µs, the system need not monitor DQ3. See also “Sector

Erase Command Sequence” on page 72.

After the sector erase command is written, the system should read the status of

DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase

algorithm has begun; all further commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the device will accept addi-

tional sector erase commands. To ensure the command has been accepted, the

system software should check the status of DQ3 prior to and following each sub-

sequent sector erase command. If DQ3 is high on the second status check, the

last command might not have been accepted.

Table 20 shows the status of DQ3 relative to the other status bits.

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Table 20. Write Operation Status

DQ7

DQ5

DQ2

RDY

Status

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

(Note 5)

Embedded Program Algorithm

No toggle

(Note 6)

DQ7#

0

Toggle

0

Standard

Mode

Embedded Erase Algorithm

Erase

Toggle

No toggle

(Note 6)

High

Impedance

1

0

N/A

Suspended Sector

Erase-Suspend-

Read (Note 4)

Erase

Suspend

Mode

Non-Erase

Suspended Sector

High

Impedance

Data

0

Data

N/A

Data

N/A

Erase-Suspend-Program

DQ7#

Toggle

0

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing

limits. Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for

further details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded

Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.

4. The system may read either asynchronously or synchronously (burst) while in erase suspend.

5. The RDY pin acts a dedicated output to indicate the status of an embedded erase or program operation is in progress.

This is available in the Asynchronous mode only.

6. When the device is set to Asynchronous mode, these status flags should be read by CE# toggle.

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Absolute Maximum Ratings

Storage Temperature, Plastic Packages ................................. –65°C to +150°C

Ambient Temperature with Power Applied.............................. –65°C to +125°C

Voltage with Respect to Ground:

All Inputs and I/Os except as noted below (Note 1) ................ –0.5 V to V_IO+ 0.5 V

V_CC(Note 1)................................................................. –0.5 V to +2.5 V

V_IO............................................................................. –0.5 V to +2.5 V

A9, RESET#, ACC (Note 1) ............................................. –0.5 V to +12.5 V

Output Short Circuit Current (Note 3) ................................... 100 mA

Notes:

1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may undershoot V_SSto –

2.0 V for periods of up to 20 ns. See Figure 8. Maximum DC voltage on input or I/Os is V_CC+ 0.5 V. During voltage

transitions outputs may overshoot to V_CC+ 2.0 V for periods up to 20 ns. See Figure 9.

2. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater

than one second.

3. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is

a stress rating only; functional operation of the device at these or any other conditions above those indicated in the

operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions

for extended periods may affect device reliability.

20 ns

+0.8 V

–0.5 V

–2.0 V

20 ns

Figure 8. Maximum Negative Overshoot Waveform

20 ns

V_CC

+2.0 V

V_CC

+0.5 V

1.0 V

20 ns

Figure 9. Maximum Positive Overshoot Waveform

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Operating Ranges

Commercial (C) Devices

Ambient Temperature (T_A)0°C to +70°C

Industrial (I) Devices

Ambient Temperature (T_A)................................................... –40°C to +85°C

Supply Voltages

V_CCSupply Voltages........................................................... +1.65 V to +1.95 V

V_IOSupply Voltages: .......................................................... +1.65 V to +1.95 V

V_CC>= V_IO- 100mV

Operating ranges define those limits between which the functionality of the device is guaranteed.

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DC Characteristics

CMOS Compatible

Parameter

Description

Test Conditions Notes: 1 & 2

V_IN= V_SSto V_CC, V_CC= V_CCmax

V_OUT= V_SSto V_CC, V_CC= V_CCmax

Min

Typ

Max

±1

30

Unit

µA

I_LI

Input Load Current

I_LO

Output Leakage Current

µA

CE# = V_IL, OE# = V_IH

,

66 MHz

80 MHz

66 MHz

80 MHz

66 MHz

80 MHz

15

18

15

18

15

18

mA

WE# = V_IH, burst length =

8

36

CE# = V_IL, OE# = V_IH

,

30

WE# = V_IH, burst length =

16

36

I_CCB

V_CCActive burst Read Current

CE# = V_IL, OE# = V_IH

,

30

WE# = V_IH, burst length =

Continuous

36

CE# = V_IL, OE# = V_IH, WE# = V_IH

burst length = 8

,

50

200

µA

I_IO1

V_IONon-active Output

OE# = V_IH

0.2

20

12

3.5

15

0.2

22

25

0.2

7

10

30

µA

mA

µA

10 MHz

5 MHz

1 MHz

V_CCActive Asynchronous Read Current

(Note 3)

CE# = V_IL, OE# = V_IH

WE# = V_IH

,

I_CC1

16

5

I_CC2

I_CC3

I_CC4

V_CCActive Write Current (Note 4)

V_CCStandby Current (Note 5)

V_CCReset Current

CE# = V_IL, OE# = V_IH, ACC = V_IH

CE# = RESET# = V_CC± 0.2 V

RESET# = V_IL,CLK = V_IL

40

50

µA

66 MHz

54

mA

µA

V_CCActive Current

(Read While Write)

I_CC5

I_CC6

I_ACC

CE# = V_IL, OE# = V_IH

80 MHz

60

V_CCSleep Current

50

V_ACC

V_CC

15

mA

V

Accelerated Program Current

(Note 6)

CE# = V_IL, OE# = V_IH,

V_ACC= 12.0 ± 0.5 V

5

10

V_IL

V_IH

V_OL

V_OH

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

V_IO= 1.8 V

–0.5

0.4

V_IO+ 0.4

0.1

V_IO– 0.4

I_OL= 100 µA, V_CC= V_{CC min}= V_IO

I_OH= –100 µA, V_CC= V_{CC min}= V_IO

V

V_IO– 0.1

11.5

Voltage for Autoselect and Temporary

Sector Unprotect

V_ID

V_CC= 1.8 V

12.5

V

V_HH

Voltage for Accelerated Program

Low V_CCLock-out Voltage

11.5

1.0

12.5

1.4

V

V_LKO

Notes:

1. Maximum I_CCspecifications are tested with V_CC= V_CCmax.

2. V_CC= V_IO

3. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at V_IH

.

4. I_CCactive while Embedded Erase or Embedded Program is in progress.

5. Device enters automatic sleep mode when addresses are stable for t_ACC+ 60 ns. Typical sleep mode current is equal

to I_CC3

6. Total current during accelerated programming is the sum of V_ACCand V_CCcurrents.

.

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90

Test Conditions

Device

Under

Test

C

L

Figure 10. Test Setup

Table 21. Test Specifications

Test Condition

All Speed Options

Unit

Output Load Capacitance, C_L

(including jig capacitance)

30

pF

Input Rise and Fall Times

2.5 - 3

0.0–V_IO

V_IO/2

ns

V

Input Pulse Levels

Input timing measurement reference levels

Output timing measurement reference levels

V

V_IO/2

V

Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

Switching Waveforms

V_IO

All Inputs and Outputs

V_IO/2

Input

Measurement Level

Output

0.0 V

Figure 11. Input Waveforms and Measurement Levels

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AC Characteristics

V_CCPower-up

Parameter

t_VCS

Description

V_CCSetup Time

V_IOSetup Time

Test Setup

Min

Speed

50

Unit

µs

t_VIOS

Min

50

µs

t_RSTH

Notes:

RESET# Low Hold Time

Min

50

µs

1. V_CC>= V_IO- 100mV and V_CCramp rate is > 1V / 100µs

2. V_CCramp rate <1V / 100µs, a Hardware Reset will be required.

t_VCS

V_CC

t_VIOS

V_IO

RESET#

Figure 12.

V

Power-up Diagram

CC

CLK Characterization

Parameter

Description

66 MHz

66

80 MHz

80

Unit

f_CLK

t_CLK

t_CKH

t_CKL

t_CR

CLK Frequency

Max

Min

MHz

ns

CLK Period

15

12.5

CLK High Time

CLK Low Time

CLK Rise Time

CLK Fall Time

Min

7.0

3

5

ns

Max

2.5

t_CF

t

CLK

t

CL

CH

CLK

t

CF

CR

Figure 13. CLK Characterization

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92

AC Characteristics

Synchronous/Burst Read @ V_IO= 1.8 V

Parameter

JEDEC Standard Description

66 MHz 80 MHz Unit

Latency (Standard wait-state Handshake mode) for 8-Word

and 16-Word Burst

t_IACC

Max

56

46

ns

Latency (Standard wait-state Handshake mode) for 32-

Word and Continuous Burst

t_IACC

71

58.5

9.1

t_BACC

t_ACS

t_ACH

t_BDH

t_CR

Burst Access Time Valid Clock to Output Delay

Address Setup Time to CLK (Note 1)

Address Hold Time from CLK (Note 1)

Data Hold Time from Next Clock Cycle

Chip Enable to RDY Valid

Output Enable to Output Valid

Chip Enable to High Z

Max

Min

Max

Min

Max

Min

Max

Min

11.2

ns

4

5.5

2

11.2

9.1

t_OE

t_CEZ

t_OEZ

t_CES

t_RDYS

t_RACC

t_AAS

t_AAH

t_CAS

t_AVC

t_AVD

t_ACC

t_CKA

t_CKZ

t_OES

8

4

Output Enable to High Z

CE# Setup Time to CLK

RDY Setup Time to CLK

Ready Access Time from CLK

Address Setup Time to AVD# (Note 1)

Address Hold Time to AVD# (Note 1)

CE# Setup Time to AVD#

AVD# Low to CLK

11.2

9.1

4

5.5

0

4

AVD# Pulse

10

Access Time

55

45

CLK to access resume

11.2

9.1

CLK to High Z

8

4

Output Enable Setup Time

Note:

1. Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.

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AC CHaracteristics

t_CEZ

t_CES

7 cycles for initial access shown.

CE#

CLK

1

2

3

4

5

6

7

t_AVC

AVD#

t_AVD

t_ACS

t_BDH

Addresses

Data

Aa

t_BACC

t_ACH

Hi-Z

t_IACC

t_ACC

Da

Da + 1

Da + n

t_OEZ

OE#

RDY

t_CR

t_RACC

t_OE

Hi-Z

t_RDYS

Notes:

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed

from two cycles to seven cycles.

2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.

3. The device is in synchronous mode.

Figure 14. CLK Synchronous Burst Mode Read (rising active CLK)

t_CEZ

4 cycles for initial access shown.

t_CES

CE#

1

2

3

4

5

CLK

t_AVC

AVD#

t_AVD

t_ACS

t_BDH

Aa

Addresses

Data

t_BACC

t_ACH

Hi-Z

t_IACC

Da

Da + 1

Da + n

t_ACC

t_OEZ

OE#

RDY

t_RACC

t_OE

t_CR

Hi-Z

t_RDYS

Notes:

1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from

two cycles to seven cycles. Clock is set for active falling edge.

2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.

3. The device is in synchronous mode.

Figure 15. CLK Synchronous Burst Mode Read (Falling Active Clock)

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94

AC Characteristics

t_CEZ

7 cycles for initial access shown.

t_CAS

CE#

CLK

1

2

3

4

5

6

7

t_AVC

AVD#

t_AVD

t_AAS

Addresses

Data

Aa

t_BACC

t_AAH

Hi-Z

t_IACC

Da

Da + 1

Da + n

t_ACC

t_BDH

t_OEZ

OE#

RDY

t_RACC

t_CR

t_OE

Hi-Z

t_RDYS

Notes:

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed

from two cycles to seven cycles. Clock is set for active rising edge.

2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.

3. The device is in synchronous mode.

Figure 16. Synchronous Burst Mode Read

7 cycles for initial access shown.

t_CES

CE#

1

2

3

4

5

6

7

CLK

t_AVC

AVD#

t_AVD

t_ACS

AC

Addresses

Data

t_BACC

t_ACH

t_IACC

DC

DD

DE

DF

D8

DB

t_BDH

OE#

RDY

t_CR

t_RACC

t_OE

t_RACC

Hi-Z

t_RDYS

Notes:

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed

from two cycles to seven cycles. Clock is set for active rising edge.

2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.

3. The device is in synchronous mode with wrap around.

4. D0-D7 in data waveform indicates the order the data within a given 8-word address range, from lowest to highest.

Starting address in figure is the 4th address in range (AC)

Figure 17. 8-word Linear Burst with Wrap Around

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AC Characteristics

t_CEZ

6 wait cycles for initial access shown.

t_CES

CE#

1

2

3

4

5

6

CLK

t_AVC

AVD#

t_AVD

t_ACS

Aa

Addresses

Data

t_BACC

t_ACH

Hi-Z

t_IACC

Da

Da+1

Da+2

Da+3

Da + n

t_BDH

t_OEZ

t_RACC

OE#

RDY

t_CR

t_OE

Hi-Z

t_RDYS

Notes:

1. Figure assumes 6 wait states for initial access and synchronous read.

2. The Set Configuration Register command sequence has been written with A18=0; device will output RDY one cycle

before valid data.

Figure 18. Linear Burst with RDY Set One Cycle Before Data

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96

AC Characteristics

Asynchronous Mode Read @ V_IO= 1.8 V

Parameter

66

80

JEDEC Standard Description

MHz

Unit

ns

t_CE

t_ACC

Access Time from CE# Low

Max

Min

Max

Min

Max

Min

55

45

Asynchronous Access Time (Note 1)

AVD# Low Time

t_AVDP

t_AAVDS

t_AAVDH

t_OE

10

4

Address Setup Time to Rising Edge of AVD

Address Hold Time from Rising Edge of AVD

Output Enable to Output Valid

5.5

11.2

9.1

Read

0

8

0

t_OEH

Output Enable Hold Time

Toggle and Data# Polling

t_OEZ

t_CAS

Output Enable to High Z (Note 2)

CE# Setup Time to AVD#

Notes:

1. Asynchronous Access Time is from the last of either stable addresses or the falling edge of AVD#.

2. Not 100% tested.

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AC Characteristics

CE#

t_OE

OE#

t_OEH

WE#

Data

t_CE

t_OEZ

Valid RD

t_ACC

RA

Addresses

AVD#

t_AAVDH

t_CAS

t_AVDP

t_AAVDS

Note: RA = Read Address, RD = Read Data.

Figure 19. Asynchronous Mode Read with Latched Addresses

CE#

OE#

t_OE

t_OEH

WE#

Data

t_CE

t_OEZ

Valid RD

t_ACC

RA

Addresses

AVD#

Note: RA = Read Address, RD = Read Data.

Figure 20. Asynchronous Mode Read

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AC Characteristics

Hardware Reset (RESET#)

Parameter

All Speed

Options

JEDEC

Std

Description

Unit

RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note)

t_Ready

Max

35

µs

RESET# Pin Low (NOT During Embedded Algorithms)

to Read Mode (See Note)

t_Ready

500

ns

t_RP

t_RH

RESET# Pulse Width

Min

500

200

20

ns

µs

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

t_RPD

Note: Not 100% tested.

CE#, OE#

t_RH

RESET#

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

CE#, OE#

RESET#

t_Ready

t_RP

Figure 21. Reset Timings

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AC Characteristics

Erase/Program Operations @ V_IO= 1.8 V

Parameter

JEDEC Standard Description

66 MHz 80 MHz Unit

t_AVAV

t_WC

Write Cycle Time (Note 1)

Min

45

4

ns

Synchronous

Asynchronous

Synchronous

Asynchronous

Address Setup Time (Notes

2, 3)

t_AVWL

t_AS

ns

0

5.5

15

10

20

0

Address Hold Time (Notes

2, 3)

t_WLAX

t_AH

Min

ns

t_AVDP

t_DS

AVD# Low Time

Data Setup Time

Data Hold Time

Min

Typ

ns

µs

t_DVWH

t_WHDX

t_GHWL

t_DH

t_GHWL

t_CAS

t_CH

Read Recovery Time Before Write

CE# Setup Time to AVD#

CE# Hold Time

0

t_WHEH

t_WLWH

t_WHWL

t_WP

Write Pulse Width

20

0

t_WPH

t_SR/W

Write Pulse Width High

Latency Between Read and Write Operations

t_WHWH1

t_WHWH1Programming Operation (Note 4)

<7

<4

<0.2

<104

500

1

t_WHWH1Accelerated Programming Operation (Note 4)

Sector Erase Operation (Notes 4, 5)

t_WHWH2

Typ

sec

Chip Erase Operation (Notes 4, 5)

t_VID

t_VIDS

t_VCS

V_ACCRise and Fall Time

Min

ns

µs

ns

V_ACCSetup Time (During Accelerated Programming)

V_CCSetup Time

50

0

t_ELWL

t_CS

CE# Setup Time to WE#

AVD# Setup Time to WE#

AVD# Hold Time to WE#

AVD# Hold Time to CLK

t_AVSW

t_AVHW

t_AVHC

t_CSW

4

Clock Setup Time to WE#

5

Notes:

1. Not 100% tested.

2. Asynchronous mode allows both Asynchronous and Synchronous program operation. Synchronous mode allows both

Asynchronous and Synchronous program operation.

3. In asynchronous program operation timing, addresses are latched on the falling edge of WE# or rising edge of AVD#.

In synchronous program operation timing, addresses are latched on the first of either the rising edge of AVD# or the

active edge of CLK.

4. See the “Erase and Programming Performance” section for more information.

5. Does not include the preprogramming time.

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AC Characteristics

Program Command Sequence (last two cycles)

Read Status Data

V

IH

CLK

V

IL

t_AVDP

AVD#

t_AH

t_AS

PA

VA

Addresses

Data

555h

In

Complete

A0h

PD

t_DS

t_DH

Progress

CE#

t_CH

OE#

WE#

t_WP

t_WHWH1

t_CS

t_WPH

t_WC

t_VCS

V_CC

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. A22–A12 are don’t care during command sequence unlock cycles.

4. CLK can be either V_ILor V_IH

.

5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Reg-

ister.

Figure 22. Asynchronous Program Operation Timings: AVD# Latched Addresses

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AC Characteristics

Program Command Sequence (last two cycles)

Read Status Data

CLK

t_ACS

t_CSW

AVD#

t_AVDP

Addresses

555h

PA

VA

In

Data

t_CAS

Complete

A0h

PD

t_DS

t_DH

Progress

t_AVSW

CE#

t_CH

OE#

t_AH

t_WP

WE#

t_WHWH1

t_WPH

t_WC

t_VCS

V_CC

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. A22–A12 are don’t care during command sequence unlock cycles.

4. CLK can be either V_ILor V_IH

.

5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Reg-

ister.

Figure 23. Asynchronous Program Operation Timings: WE# Latched Addresses

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AC Characteristics

Program Command Sequence (last two cycles)

t_AVCH

Read Status Data

CLK

t_ACS

t_CSW

AVD#

t_AVDP

Addresses

555h

PA

VA

In

Data

t_CAS

Complete

A0h

PD

t_DS

t_DH

Progress

t_AVSW

CE#

t_CH

OE#

t_AH

t_WP

WE#

t_WHWH1

t_WPH

t_WC

t_VCS

V_CC

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. A22–A12 are don’t care during command sequence unlock cycles.

4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.

5. Either CE# or AVD# is required to go from low to high in between programming command sequences.

6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register.

The Configuration Register must be set to the Synchronous Read Mode.

Figure 24. Synchronous Program Operation Timings: WE# Latched Addresses

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AC Characteristics

Program Command Sequence (last two cycles)

t_AVCH

Read Status Data

CLK

t_AS

t_AH

t_AVSC

AVD#

t_AVDP

Addresses

555h

PA

VA

In

Data

Complete

A0h

PD

t_DS

t_DH

Progress

t_CAS

CE#

t_CH

OE#

WE#

t_CSW

t_WP

t_WHWH1

t_WPH

t_WC

t_VCS

V_CC

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. A22–A12 are don’t care during command sequence unlock cycles.

4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.

5. Either CE# or AVD# is required to go from low to high in between programming command sequences.

6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register.

The Configuration Register must be set to the Synchronous Read Mode.

Figure 25. Synchronous Program Operation Timings: CLK Latched Addresses

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104

AC Characteristics

Erase Command Sequence (last two cycles)

Read Status Data

V

IH

CLK

V

IL

t_AVDP

AVD#

t_AH

t_AS

SA

555h for

chip erase

VA

Addresses

Data

2AAh

10h for

chip erase

In

Complete

55h

30h

Progress

t_DS

t_DH

CE#

t_CH

OE#

WE#

t_WP

t_WHWH2

t_CS

t_WPH

t_WC

t_VCS

V_CC

Figure 26. Chip/Sector Erase Command Sequence

Notes:

1. SA is the sector address for Sector Erase.

2. Address bits A22–A12 are don’t cares during unlock cycles in the command sequence.

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AC Characteristics

CE#

AVD#

WE#

Addresses

Data

PA

Don't Care

A0h

Don't Care

PD

Don't Care

OE#

t_VIDS

1 µs

V

ID

ACC

t_VID

or V

IL

IH

Note: Use setup and hold times from conventional program operation.

Figure 27. Accelerated Unlock Bypass Programming Timing

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106

AC Characteristics

AVD#

t_CEZ

t_CE

CE#

t_OEZ

t_CH

t_OE

OE#

t_OEH

WE#

t_ACC

VA

Addresses

VA

Status Data

Data

Notes:

1. Status reads in figure are shown as asynchronous.

2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is

complete, and Data# Polling will output true data.

3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.

Figure 28. Data# Polling Timings (During Embedded Algorithm)

AVD#

t_CEZ

t_CE

CE#

t_OEZ

t_CH

t_OE

OE#

WE#

t_OEH

t_ACC

Addresses

Data

VA

Status Data

Notes:

1. Status reads in figure are shown as asynchronous.

2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is

complete, the toggle bits will stop toggling.

3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.

Figure 29. Toggle Bit Timings (During Embedded Algorithm)

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AC Characteristics

CE#

CLK

AVD#

Addresses

OE#

VA

t_IACC

Data

Status Data

RDY

Notes:

1. The timings are similar to synchronous read timings.

2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is

complete, the toggle bits will stop toggling.

3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is

active one clock cycle before data.

Figure 30. Synchronous Data Polling Timings/Toggle Bit Timings

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

WE#

Erase

Erase Suspend

Suspend

Program

Complete

Read

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#

to toggle DQ2 and DQ6.

Figure 31. DQ2 vs. DQ6

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108

AC Characteristics

Temporary Sector Unprotect

Parameter

JEDEC

Std

t_VIDR

t_VHH

Description

All Speed Options

Unit

ns

V_IDRise and Fall Time (See Note)

V_HHRise and Fall Time (See Note)

Min

500

250

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

Min

4

µs

RESET# Hold Time from RDY High for

Temporary Sector Unprotect

t_RRB

Note: Not 100% tested.

V_ID

RESET#

V_ILor V_IH

t_VIDR

Program or Erase Command Sequence

CE#

WE#

RDY

t_RRB

t_RSP

Figure 32. Temporary Sector Unprotect Timing Diagram

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AC Characteristics

V

ID

V

IH

RESET#

SA, A6,

A1, A0

Valid*

Status

Sector Protect/Unprotect

Verify

40h

Data

60h

Sector Protect: 150 µs

Sector Unprotect: 1.5 ms

1 µs

CE#

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 33. Sector/Sector Block Protect and Unprotect Timing Diagram

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110

AC Characteristics

Address boundary occurs every 64 words, beginning at address

00003Fh: 00007Fh, 0000BFh, etc. Address 000000h is also a boundary crossing.

C60

C61

3D

C62

3E

C63

3F

C63

3F

C63

3F

C64

40

C65

41

C66

42

C67

43

CLK

3C

Address (hex)

(stays high)

AVD#

RDY

t_RACC

(Note 1)

(Note 2)

latency

t_RACC

latency

Data

D60

D61

D62

D63

D64

D65

D66

D67

Notes:

1. RDY active with data (A18 = 0 in the Configuration Register).

2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register).

3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device not

crossing a bank in the process of performing an erase or program.

4. If the starting address latched in is either 3Eh or 3Fh (or some 64 multiple of either), there is no additional 2 cycle

latency at the boundary crossing.

Figure 34. Latency with Boundary Crossing

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AC Characteristics

Address boundary occurs every 64 words, beginning at address

00003Fh: 00007Fh, 0000BFh, etc. Address 000000h is also a boundary crossing.

C60

C61

3D

C62

3E

C63

3F

C63

3F

C63

3F

C64

40

CLK

3C

Address (hex)

(stays high)

AVD#

RDY

t_RACC

(Note 1)

(Note 2)

latency

t_RACC

latency

Data

Invalid

D60

D61

D62

D63

Read Status

OE#,

CE#

(stays low)

Notes:

1. RDY active with data (A18 = 0 in the Configuration Register).

2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register).

3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device

crossing a bank in the process of performing an erase or program.

Figure 35. Latency with Boundary Crossing into Program/Erase Bank

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AC Characteristics

Data

D0

D1

Rising edge of next clock cycle

following last wait state triggers

next burst data

AVD#

OE#

total number of clock cycles

following addresses being latched

1

2

0

3

1

4

5

6

4

7

5

CLK

2

3

number of clock cycles

programmed

Wait State Decoding Addresses:

A14, A13, A12 = “111” ⇒ Reserved

A14, A13, A12 = “110” ⇒ Reserved

A14, A13, A12 = “101” ⇒ 5 programmed, 7 total

A14, A13, A12 = “100” ⇒ 4 programmed, 6 total

A14, A13, A12 = “011” ⇒ 3 programmed, 5 total

A14, A13, A12 = “010” ⇒ 2 programmed, 4 total

A14, A13, A12 = “001” ⇒ 1 programmed, 3 total

A14, A13, A12 = “000” ⇒ 0 programmed, 2 total

Note: Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to “101”.

Figure 36. Example of Wait States Insertion

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AC Characteristics

Last Cycle in

Program or

Sector Erase

Read status (at least two cycles) in same bank

and/or array data from other bank

Begin another

write or program

command sequence

Command Sequence

t_WC

t_RC

t_WC

CE#

OE#

t_OE

t_OEH

t_GHWL

WE#

Data

t_WPH

t_OEZ

t_WP

t_DS

t_ACC

t_OEH

t_DH

PD/30h

RD

AAh

t_SR/W

RA

Addresses

AVD#

PA/SA

t_AS

RA

555h

t_AH

Note: Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” while checking the

status of the program or erase operation in the “busy” bank. The system should read status twice to ensure valid information.

Figure 37. Back-to-Back Read/Write Cycle Timings

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114

Erase and Programming Performance

Parameter

Typ (Note 1)

Max (Note 2)

Unit

Comments

32 Kword

4 Kword

128J

<0.4

<2

Sector Erase Time

s

<0.2

Excludes 00h programming

prior to erasure (Note 4)

<103

Chip Erase Time

s

064J

<53

Excludes system level

overhead (Note 5)

Word Programming Time

<6

<100

<67

µs

Accelerated Word Programming Time

<4

128J

<50.4

<25.2

<33

Chip Programming Time

(Note 3)

Excludes system level

overhead (Note 5)

s

064J

128J

Accelerated Chip

Programming Time

064J

<17

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 1.8 V V_CC, 100,000 cycles. Additionally,

programming typicals assumes a checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 1.65 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed.

4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program

command. See Table 18, “Command Definitions,” on page 78 for further information on command definitions.

6. The device has a minimum cycling endurance of 100,000 cycles per sector.

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P r e l i m i n a r y

CosmoRAM

32Mbit (2M word x 16-bit)

64Mbit (4M word x 16-bit)

Features

Asynchronous SRAM Interface

Fast Access Time

— t_CE= t_AA= 70ns max

8 words Page Access Capability

— t_PAA= 20ns max

Low Voltage Operating Condition

— V_DD= +1.65V to +1.95V (32M)

— +1.70V to +1.95V (64M)

Wide Operating Temperature

— TA = -30°C to +85°C

Byte Control by LB# and UB#

Low Power Consumption

— I_DDA1= 30mA max (32M), TBDmA max (64M)

— I_DDS1= 80mA max (32M), TBDmA max (64M)

Various Power Down mode

— Sleep, 4M-bit Partial or 8M-bit Partial (32M)

— Sleep, 8M-bit Partial or 16M-bit Partial (64M)

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116

P r e l i m i n a r y

Pin Description (32M)

Pin Name

A₂₁to A₀

CE1#

CE2

Description

Address Input: A₂₀to A₀for 32M, A₂₁to A₀for 64M

Chip Enable (Low Active)

Chip Enable (High Active)

Write Enable (Low Active)

Output Enable (Low Active)

Upper Byte Control (Low Active)

Lower Byte Control (Low Active)

Clock Input

WE#

OE#

UB#

LB#

CLK

ADV#

WAIT#

Address Valid Input (Low Active)

Wait Signal Output

DQ_{16 9}

-

Upper Byte Data Input/Output

Lower Byte Data Input/Output

Power Supply

DQ₈-₁

V_DD

V_SS

Ground

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P r e l i m i n a r y

Functional Description

Asynchronous Operation (Page Mode)

Mode

Standby (Deselect)

Output Disable (Note 1)

Output Disable (No Read)

Read (Upper Byte)

Read (Lower Byte)

Read (Word)

CE2 CE1# CLK

H

ADV#

WE#

OE#

X

LB# UB# A_21-0

DQ_8-1

High-Z

DQ_16-9

High-Z

WAIT#

High-Z

H

L

X

H

X

H

Note 5

Valid

X

High-Z

H

L

H

L

High-Z

Output Valid

High-Z

H

L

H

L

Output Valid

L

Output Valid Output Valid

L

(Note 3)

Page Read

L/H

H

L

L/H

H

L

Note 6

Invalid

Note 6

Invalid

No Write

Write (Upper Byte)

Write (Lower Byte)

Write (Word)

Invalid

Input Valid

Invalid

H

L

(Note 4)

H

L

Input Valid

High-Z

L

Input Valid

High-Z

Power Down (Note 2)

X

Legend:L = V_IL, H = V_IH, X can be either V_ILor V_IH, High-Z = High Impedance.

Notes:

1. Should not be kept at this logic condition longer than 1µs.

2. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the

selection of Partial Size. Refer to the "Power Down" section in the Functional Description for details.

3. “L” for address pass through and “H” for address latch on the rising edge of ADV#.

4. OE# can be V_ILduring Write operation if the following conditions are satisfied:

(1) Write pulse is initiated by CE1# (refer to CE1# Controlled Write timing), or cycle time of the previous operation cycle is

satisfied.

(2) OE# stays V_ILduring Write cycle

5. Can be either V_ILor V_IHbut must be valid before Read or Write.

6. Output is either Valid or High-Z depending on the level of UB# and LB# input.

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118

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Functional Description

Synchronous Operation (Burst Mode)

Mode

CE2 CE1#

CLK

ADV#

WE#

OE#

LB#

UB#

A_21-0

DQ_8-1

DQ_16-9

WAIT#

Standby (Deselect)

H

X

High-Z

Start Address

Latch

(Note 1)

VE

(Note 3)

X

Valid

(Note 7)

High-Z

(Note 8)

High-Z

(Note 8) (Note 11)

High-Z

PELP

(Note 4) (Note 4)

Advance Burst

Read to Next

Address (Note 1)

Output

Valid

(Note 9)

Output

Valid

(Note 9)

VE

(Note 3)

L

Valid

H

Burst Read

Suspend

(Note 1)

VE

High

High-Z

L

H

High-Z

(Note 3)

(Note 12)

H

X

Input

Advance Burst

Write to Next

Address (Note 1)

(Note 6) (Note 6)

Input

Valid

(Note 10)

VE

(Note 3)

L

(Note 5)

H

Valid

(Note

10)

High

H

X

(Note 13)

Burst Write

Suspend (Note 1)

VE

(Note 3)

H

Iput

Invalid

Iput

Invalid

High

(Note 12)

(Note 5)

Terminate Burst

Read

VE

X

H

X

H

X

High-Z

Terminate Burst

Write

Power Down

(Note 2)

L

X

Legend:L = V_IL, H = V_IH, X can be either V_ILor V_IH, VE = Valid Edge, PELP = Positive Edge of Low Pulse, High-

Z = High Impedance.

Notes:

1. Should not be kept this logic condition longer than the specified time of 8µs for 32M and 4µs for 64M.

2. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the

selection of Partial Size. Refer to the "Power Down" section for details.F

3. Valid clock edge shall be set on either positive or negative edge through CR Set. CLK must be started and stable prior to

memory access.

4. Can be either V_ILor V_IHexcept for the case the both of OE# and WE# are V_IL. It is prohibited to bring the both of OE# and

WE# to V_IL

.

5. When device is operating in “WE# Single Clock Pulse Control” mode, WE# is don’t care once write operation is determined by

WE# Low Pulse at the beginning of write access together with address latching. Write suspend feature is not supported in

“WE# Single Clock Pulse Control” mode.

6. Can be either V_ILor V_IHbut must be valid before Read or Write is determined. And once UB# and LB# inputs are

determined, they must not be changed until the end of burst.

7. Once valid address is determined, input address must not be changed during ADV#=L.

8. If OE#=L, output is either Invalid or High-Z depending on the level of UB# and LB# input. If WE#=L, Input is Invalid. If

OE#=WE#=H, output is High-Z.

9. Output is either Valid or High-Z depending on the level of UB# and LB# input.

10. Input is either Valid or Invalid depending on the level of UB# and LB# input.

11. Output is either High-Z or Invalid depending on the level of OE# and WE# input.

12. Keep the level from previous cycle except for suspending on last data. Refer to “WAIT# Output Function” for details.

13. WAIT# output is driven in High level during write operation.

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CosmoRAM_00_A0 October 5, 2004

P r e l i m i n a r y

State Diagrams

Initial/Standby State

Asynchronous Operation

(Page Mode)

Power Up

Synchronous Operation

(Burst Mode)

Common State

CR Set

Pause Time

Power

Down

Power

Down

@M=1

@M=0

CE2=L

CE2=H

@RP=1

Standby

(64M Only)

CE2=H

@RP=0

Figure 38. Initial Standby State Diagram

Asynchronous Operation State

CE2=CE1# = H

Standby

CE1# = L

CE1# = H

CE1# = L &

WE# = L

CE1# = L &

OE# =

L

CE1#= H

Output

CE1# = H

Disable

WE# = H

OE# =

H

L

OE# =

WE# = L

Address Change

or Byte Control

Write

Read

Byte Control

Byte Control @OE# = L

Figure 39. Asynchronous Operation State Diagram

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120

P r e l i m i n a r y

Synchronous Operation State

CE2 = CE1# = H

Standby

CE1# = H

Write

Read

Suspend

OE# = H

WE# = H

CE1# = L

OE# = L

ADV# Low Pulse

& WE# = L

ADV# Low Pulse

& OE# = L

WE# = L

Write

Read

ADV# Low Pulse

(@BL = 8 or 16, and after burst

operation is completed)

Figure 40. Synchronous Operation Diagram

Notes:

1. Assumes all the parameters specified in the "AC Characteristics" section are satisfied. Refer to the "Functional Description"

section, "AC Characteristics" section, and the "Timing Diagrams" section for details. RP (Reset to Page) mode is available

only for 64M.

Functional Description

This device supports asynchronous page read & normal write operation and syn-

chronous burst read & burst write operation for faster memory access and

features three kinds of power down modes for power saving as a user config-

urable option.

Power-up

It is required to follow the power-up timing to start executing proper device op-

eration. Refer to POWER-UP Timing. After Power-up, the device defaults to

asynchronous page read & normal write operation mode with sleep power down

feature.

Configuration Register

The Configuration Register (CR) is used to configure the type of device function

among optional features. Each selection of features is set through CR Set se-

quence after Power-up. If CR Set sequence is not performed after power-up, the

device is configured for asynchronous operation with sleep power down feature

as default configuration.

CR Set Sequence

The CR Set requires total 6 read/write operations with unique address. Between

each read/write operation requires the device to be in standby mode. The follow-

ing table shows the detail sequence.

Cycle #

1st

Operation

Read

Address

3FFFFFh (MSB)

3FFFFFh

Data

Read Data (RDa)

RDa

2nd

Write

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CosmoRAM_00_A0 October 5, 2004

P r e l i m i n a r y

Cycle #

3rd

Operation

Write

Address

3FFFFFh

Data

RDa

4th

Write

3FFFFFh

X

5th

Write

3FFFFFh

X

6th

Read

Address Key

Read Data (RDb)

The first cycle is to read from most significant address (MSB).

The second and third cycle are to write to MSB. If the second or third cycle is writ-

ten into the different address, the CR Set is cancelled and the data written by the

second or third cycle is valid as a normal write operation. It is recommended to

write back the data (RDa) read by first cycle to MSB in order to secure the data.

The forth and fifth cycle is to write to MSB. The data of forth and fifth cycle is

don’t-care. If the forth or fifth cycle is written into different address, the CR Set

is also cancelled but write data may not be written as normal write operation.

The last cycle is to read from specific address key for mode selection. And read

data (RDb) is invalid.

Once this CR Set sequence is performed from an initial CR set to the other new

CR set, the written data stored in memory cell array may be lost. So, CR Set se-

quence should be performed prior to regular read/write operation if necessary to

change from default configuration.

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122

P r e l i m i n a r y

Address Key

The address key has the following format.

Description

Note

Address

Register

Name

Function

Key

32M

64M

Unused bits muse be 1

16M Partial

A21

—

1

—

1

00

01

10

11

8M Partial

4M Partial

8M Partial

A20-A19

PS

Partial Size

Reserved for future use

Sleep [Default]

2

000 to 001 Reserved for future use

010

011

8 words

A18-A16

BL

M

Burst Length

16 words

100 to 110 Reserved for future use

2

111

0

Continuous

Synchronous Mode (Burst Read / Write)

3

4

2

A15

Mode

1

Asynchronous Mode [Default] (Page Read / Normal Write)

000

001

010

011

100

Reserved for future use

3 clocks

4 clocks

A14-A12

RL

Read Latency

5 clocks

Reserved for future use

6 clocks

101 to 111 Reserved for future use

2

0

1

0

1

0

1

0

1

Reserved for future use

Sequential

Burst

A11

A10

A9

BS

SW

VE

Sequence

Burst Read & Burst Write

Burst Read & Single Write

Falling Clock Edge

Single Write

5

Valid Clock

Edge

Rising Clock Edge

Reset to Page mode

6

5

1

A8

RP

Reset to Page

Unused bits must be 1

Remain the previous mode

WE# Single Clock Pulse Control without Write Suspend

Function

0

A7

WC

—

Write Control

—

1

WE# Level Control with Write Suspend Function

Unused bits muse be 1

A6-A0

Notes:

1. A21 and A6 to A0 must be all “1” in any case.

2. It is prohibited to apply this key.

3. If M=0, all the registers must be set with appropriate Key input at the same time.

4. If M=1, PS must be set with appropriate Key input at the same time. Except for PS, all the other key inputs must be “1”.

5. Burst Read & Single Write is not supported at WE# Single Clock Pulse Control.

6. Effective only when PS=11. RP (Reset to Page) mode is available only for 64M.

123

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Power Down

The Power Down is low power idle state controlled by CE2. CE2 Low drives the

device in power down mode and maintains low power idle state as long as CE2 is

kept Low. CE2 High resumes the device from power down mode. These devices

have three power down mode. These can be programmed by series of read/write

operations. Each mode has following features.

32M

Data Retention Size

No

64M

Data Retention Size

No

Mode

Retention Address

N/A

Mode

Retention Address

N/A

Sleep (default)

4M Partial

Sleep (default)

8M Partial

4M bit

000000h to 03FFFFh

000000h to 07FFFFh

8M bit

000000h to 07FFFFh

000000h to 0FFFFFh

8M Partial

8M bit

16M Partial

16M bit

The default state is Sleep and it is the lowest power consumption but all data will

be lost once CE2 is brought to Low for Power Down. It is not required to program

to Sleep mode after power-up.

64M supports Reset to Page (RP) mode. When RP=0, Power Down comprehends

a function to reset the device to default configuration (asynchronous mode). After

resuming from power down mode, the device is back in default configurations.

This is effective only when PS is set on Sleep mode. When Partial mode is se-

lected, RP=0 is not effective.

Burst Read/Write Operation

Synchronous burst read/write operation provides faster memory access that syn-

chronized to microcontroller or system bus frequency. Configuration Register Set

is required to perform burst read & write operation after power-up. Once CR Set

sequence is performed to select synchronous burst mode, the device is config-

ured to synchronous burst read/write operation mode with corresponding RL and

BL that is set through CR Set sequence together with operation mode. In order

to perform synchronous burst read & write operation, it is required to control new

signals, CLK, ADV# and WAIT# that Low Power SRAMs don’t have.

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CLK

ADDRESS

Valid

ADV#

CE1#

OE#

High

WE#

DQ

RL

High-Z

Q1

QBL

Q2

BL

WAIT#

Figure 41. Burst Read Operation

CLK

ADDRESS

Valid

ADV#

CE1#

High

OE#

WE#

DQ

RL-1

High-Z

D1

DBL

D2

BL

WAIT#

Figure 42. Burst Write Operation

CLK Input Function

The CLK is input signal to synchronize memory to microcontroller or system bus

frequency during synchronous burst read & write operation. The CLK input incre-

ments device internal address counter and the valid edge of CLK is referred for

latency counts from address latch, burst write data latch, and burst read data out.

During synchronous operation mode, CLK input must be supplied except for

standby state and power down state. CLK is don’t care during asynchronous

operation.

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ADV# Input Function

The ADV# is input signal to indicate valid address presence on address inputs. It

is applicable to synchronous operation as well as asynchronous operation. ADV#

input is active during CE1#=L and CE1#=H disables ADV# input. All addresses

are determined on the positive edge of ADV#.

During synchronous burst read/write operation, ADV#=H disables all address in-

puts. Once ADV# is brought to High after valid address latch, it is inhibited to

bring ADV# Low until the end of burst or until burst operation is terminated.

ADV# Low pulse is mandatory for synchronous burst read/write operation mode

to latch the valid address input.

During asynchronous operation, ADV#=H also disables all address inputs. ADV#

can be tied to Low during asynchronous operation and it is not necessary to con-

trol ADV# to High.

WAIT# Output Function

The WAIT# is output signal to indicate data bus status when the device is oper-

ating in synchronous burst mode.

During burst read operation, WAIT# output is enabled after specified time dura-

tion from OE#=L or CE1#=L whichever occurs last. WAIT# output Low indicates

data out at next clock cycle is invalid, and WAIT# output becomes High one clock

cycle prior to valid data out. During OE# read suspend, WAIT# output doesn’t

indicate data bus status but carries the same level from previous clock cycle (kept

High) except for read suspend on the final data output. If final read data out is

suspended, WAIT# output become high impedance after specified time duration

from OE#=H.

In case of continuous burst read operation of 32M, an additional output delay may

occur when a burst sequence crosses it’s device-row boundary. The WAIT# out-

put indicates this delay. Refer to the "Burst Length" section for the additional

delay cycles in details.

During burst write operation, WAIT# output is enabled to High level after speci-

fied time duration from WE#=L or CE1#=L whichever occurs last and kept High

for entire write cycles including WE# write suspend. The actual write data latch-

ing starts on the appropriate clock edge with respect to Valid Clock Edge, Read

Latency and Burst Length. During WE# write suspend, WAIT# output doesn’t in-

dicate data bus status but carries the same level from previous clock cycle (kept

High) except for write suspend on the final data input. If final write data in is sus-

pended, WAIT# output become high impedance after specified time duration

from WE#=H.

The burst write operation of 32M and the both burst read/write operation of 64M

are always started after fixed latency with respect to Read Latency set in CR.

When the device is operating in asynchronous mode, WAIT# output is always in

High Impedance.

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Latency

Read Latency (RL) is the number of clock cycles between the address being

latched and first read data becoming available during synchronous burst read op-

eration. It is set through CR Set sequence after power-up. Once specific RL is set

through CR Set sequence, write latency, that is the number of clock cycles be-

tween address being latched and first write data being latched, is automatically

set to RL-1.The burst operation is always started after fixed latency with respect

to Read Latency set in CR. RL=6 is available only for 64M.

CLK

0

3

4

5

6

1

2

ADDRESS

ADV#

Valid

CE1#

OE# or WE#

RL=3

DQ [Out]

WAIT#

Q1

Q2

Q3

Q4

Q5

D5

High-Z

DQ [In]

WAIT#

D1

D2

D3

D4

D5

High-Z

RL=4

DQ [Out]

WAIT#

Q1

D2

Q2

D3

Q3

D4

Q4

D5

High-Z

DQ [In]

WAIT#

D1

High-Z

RL=5

DQ [Out]

WAIT#

Q1

D2

Q2

D3

Q3

D4

High-Z

DQ [In]

WAIT#

D1

High-Z

RL=6

DQ [Out]

WAIT#

Q1

D2

Q2

D3

High-Z

DQ [In]

WAIT#

D1

High-Z

Figure 43. Read Latency Diagram

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Address Latch by ADV#

The ADV# indicates valid address presence on address inputs. During synchro-

nous burst read/write operation mode, all the address are determined on the

positive edge of ADV# when CE1#=L. The specified minimum value of ADV#=L

setup time and hold time against valid edge of clock where RL count begin must

be satisfied for appropriate RL counts. Valid address must be determined with

specified setup time against either the negative edge of ADV# or negative edge

of CE1# whichever comes late. And the determined valid address must not be

changed during ADV#=L period.

Burst Length

Burst Length is the number of word to be read or write during synchronous burst

read/write operation as the result of a single address latch cycle. It can be set on

8, 16 words boundary or continuous for entire address through CR Set sequence.

The burst type is sequential that is incremental decoding scheme within a bound-

ary address. Starting from initial address being latched, device internal address

counter assign +1 to the previous address until reaching the end of boundary ad-

dress and then wrap round to least significant address (=0). After completing

read data out or write data latch for the set burst length, operation automatically

ended except for continuous burst length. When continuous burst length is set,

read/write is endless unless it is terminated by the positive edge of CE1#.

During continuous burst read of 32M, an additional output delay may occur when

a burst sequence cross it’s device-row boundary. This is the case when A0 to A6

of starting address is either 7Dh, 7Eh, or 7Fh as shown in the following table. The

WAIT# signal indicates this delay. The 64M device has no additional output delay.

Read Address Sequence

Start Address

(A6-A0)

00h

01h

02h

03h

...

BL = 8

BL = 16

Continuous

00-01-02-03-04-...

01-02-03-04-05-...

02-03-04-05-06-...

03-04-05-06-07-...

...

00-01-02-...-06-07

01-02-03-...-07-00

02-03-...-07-00-01

03-...-07-00-01-02

...

00-01-02-...-0E-0F

01-02-03-...-0F-00

02-03-...-0F-00-01

03-...-0F-00-01-02

...

7Ch

7Dh

7Eh

7Fh

7C-...-7F-78-...-7B

7D-7E-7F-78-...-7C

7E-7F-78-79-...-7D

7F-78-79-7A-...-7E

7C-...-7F-70-...-7B

7D-7E-7F-70-...-7C

7E-7F-70-71-...-7D

7F-70-71-72-...-7E

7C-7D-7E-7F-80-81-...

7D-7E-7F-WAIT-80-81-...

7E-7F-WAIT-WAIT-80-81-...

7F-WAIT WAIT

-

-WAIT-80-81

Note: Read address in Hexadecimal.

Single Write

Single Write is synchronous write operation with Burst Length =1. The device can

be configured either to “Burst Read & Single Write” or to “Burst Read & Burst

Write” through CR set sequence. Once the device is configured to “Burst Read &

Single Write” mode, the burst length for synchronous write operation is always

fixed 1 regardless of BL values set in CR, while burst length for read is in accor-

dance with BL values set in CR.

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Write Control

The device has two types of WE# signal control method, “WE# Level Control” and

“WE# Single Clock Pulse Control”, for synchronous write operation. It is config-

ured through CR set sequence.

CLK

0

3

4

5

6

1

2

ADDRESS

Valid

ADV#

CE1#

RL=5

WE# Level Control

WE#

tWLD

DQ [In]

WAIT#

D1

D2

D3

D4

tWLTH

High-Z

WE# Single Clock Pulse Control

tWSCK

WE#

tCKWH

DQ [In]

D1

D2

D3

D4

tCLTH

tWLTH

WAIT#

High-Z

Figure 44. Write Controls

Burst Read Suspend

Burst read operation can be suspended by OE# High pulse. During burst read op-

eration, OE# brought to High suspends burst read operation. Once OE# is

brought to High with the specified set up time against clock where the data being

suspended, the device internal counter is suspended, and the data output be-

come high impedance after specified time duration. It is inhibited to suspend the

first data out at the beginning of burst read.

OE# brought to Low resumes burst read operation. Once OE# is brought to Low,

data output become valid after specified time duration, and internal address

counter is reactivated. The last data out being suspended as the result of OE#=H

and first data out as the result of OE#=L are from the same address.

In order to guarantee to output last data before suspension and first data after

resumption, the specified minimum value of OE#=L hold time and setup time

against clock edge must be satisfied respectively.

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CLK

OE#

tCKOH tOSCK

tAC

tOHZ

Q2

tAC

Q2

tAC

Q3

Q1

DQ

Q4

tCKQX

tOLZ

tCKQX

tCKTV

WAIT#

Figure 45. Burst Read Suspend Diagram

Burst Write Suspend

Burst write operation can be suspended by WE# High pulse. During burst write

operation, WE# brought to High suspends burst write operation. Once WE# is

brought to High with the specified set up time against clock where the data being

suspended, device internal counter is suspended, data input is ignored. It is in-

hibited to suspend the first data input at the beginning of burst write.

WE# brought to Low resumes burst write operation. Once WE# is brought to Low,

data input become valid after specified time duration, and internal address

counter is reactivated. The write address of the cycle where data being sus-

pended and the first write address as the result of WE#=L are the same address.

In order to guarantee to latch the last data input before suspension and first data

input after resumption, the specified minimum value of WE#=L hold time and

setup time against clock edge must be satisfied respectively. Burst write suspend

function is available when the device is operating in WE# level controlled burst

write only.

CLK

tCKWH tWSCK

WE#

tDSCK

DQ

D1

D2

D3

D4

tDHCK

High

Figure 46. Burst Write Suspend Diagram

WAIT#

Burst Read Termination

Burst read operation can be terminated by CE1# brought to High. If BL is set on

Continuous, burst read operation is continued endless unless terminated by

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CE1#=H. It is inhibited to terminate burst read before first data out is completed.

In order to guarantee last data output, the specified minimum value of CE1#=L

hold time from clock edge must be satisfied. After termination, the specified min-

imum recovery time is required to start new access.

CLK

ADDRESS

Valid

ADV#

CE1#

tTRB

tCKCLH

tCKOH

tCHZ

tOHZ

OE#

WAIT#

DQ

High-Z

tCHTZ

tCKQX

tAC

Q1

Q2

Figure 47. Burst Read Termination Diagram

Burst Write Termination

Burst write operation can be terminated by CE1# brought to High. If BL is set on

Continuous, burst write operation is continued endless unless terminated by

CE1#=H. It is inhibited to terminate burst write before first data in is completed.

In order to guarantee last write data being latched, the specified minimum values

of CE1#=L hold time from clock edge must be satisfied. After termination, the

specified minimum recovery time is required to start new access.

CLK

ADDRESS

Valid

ADV#

CE1#

tTRB

tCKCLH

tCKWH

tCHCK

WE#

WAIT#

DQ

tCHTZ

High-Z

tDSCK

D1

D2

tDHCK

Figure 48. Burst Write Termination Diagram

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Absolute Maximum Ratings

Item

Voltage of V_DDSupply Relative to V_SS

Voltage at Any Pin Relative to V_SS

Short Circuit Output Current

Storage temperature

Symbol

V_DD

Value

Unit

V

-0.5 to +3.6

±50

V_IN, V_OUT

I_OUT

V

mA

°C

T_STG

-55 to +125

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,

etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Recommended Operating Conditions (See Warning Below)

32M

64M

Parameter

Symbol

V_DD

V_SS

V_IH

Min

1.65

0

Max

1.95

Min

1.7

Max

1.95

Unit

V

Supply Voltage

0

V

High Level Input Voltage (Note 1)

High Level Input Voltage (Note 2)

Ambient Temperature

V_DDx 0.8

-0.3

V_DD+0.2

V_DDx 0.2

85

V_DDx 0.8

-0.3

V_DD+0.2

V_DDx 0.2

85

V

V_IL

V

T_A

-30

°C

Notes:

1. Maximum DC voltage on input and I/O pins are V_DD+0.2V. During voltage transitions, inputs may positive overshoot to

_DD+1.0V for periods of up to 5 ns.

V

2. Minimum DC voltage on input or I/O pins are -0.3V. During voltage transitions, inputs may negative overshoot V_SSto -1.0V

for periods of up to 5ns.

WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the de-

vice’s electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may

adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.

Package Pin Capacitance

Test conditions: T_A= 25°C, f = 1.0 MHz

Symbol

Description

Te s t S e tup

V_IN= 0V

V_IO= 0V

Typ

—

Max

5

Unit

pF

C_IN1

C_IN2

C_IO

Address Input Capacitance

Control Input Capacitance

Data Input/Output Capacitance

—

5

pF

—

8

pF

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DC Characteristics

(Under Recommended Conditions Unless Otherwise Noted)

32M

64M

Parameter

Symbol

Test Conditions

Unit

Min.

Max.

Min.

Max.

Input Leakage

Current

I_LI

V_IN= V_SSto V_DD

-1.0

+1.0

-1.0

+1.0

µA

V

Output Leakage

Current

I_LO

V_OUT= V_SSto V_DD, Output Disable

V_DD= V_DD(min), I_OH= –0.5mA

I_OL= 1mA

-1.0

2.4

—

+1.0

—

-1.0

2.4

+1.0

—

Output High Voltage

Level

V_OH

Output Low Voltage

Level

V_OL

0.4

—

0.4

V

I_DDPS

I_DDP4

I_DDP8

I_DDP16

SLEEP

—

10

40

50

TBD

µA

4M Partial

8M Partial

16M Partial

N/A

V_DD= V_DDmax.,

V_DDPower Down

Current

V_IN= V_IHor V_IL

CE2 ≤ 0.2V

,

—

TBD

N/A

V_DD= V_DDmax.,

_IN(including CLK)= V_IHor V_IL

I_DDS

V

,

—

1.5

—

TBD

mA

CE1# = CE2 = V_IH

V_DD= V_DDmax.,

TA ≤ +85°C

TA ≤ +40°C

—

80

—

TBD

µA

V_DDStandby

Current

V

_IN(including CLK) ≤ 0.2V or

I_DDS1

_IN(including CLK) ≥ V_DD– 0.2V,

CE1# = CE2 ≥ V_DD– 0.2V

V_DD= V_DDmax., t_CK=min.

V_IN≤ 0.2V or V_IN≥ V_DD– 0.2V,

CE1# = CE2 ≥ V_DD– 0.2V

—

200

—

TBD

µA

t_RC/ t_WC

=

I_DDA1

—

30

3

—

35

5

mA

V_DD= V_DDmax.,

minimum

V_IN= V_IHor V_IL

,

V

_DDActive Current

CE1# = V_ILand CE2= V_IH

I_OUT=0mA

,

t_RC/ t_WC

=

I_DDA2

1µs

V_DD= V_DDmax., V_IN= V_IHor V_IL

CE1# = V_ILand CE2= V_IH

I_OUT=0mA, t_PRC= min.

,

V_DDPage Read

Current

I_DDA3

,

—

10

15

—

TBD

mA

V_DD= V_DDmax., V_IN= V_IHor V_IL

CE1# = V_ILand CE2= V_IH

t_CK= t_CKmin., BL = Continuous,

_OUT=0mA

,

V

_DDBurst Access

,

I_DDA4

Current

I

Notes:

1. All voltages are referenced to V_SS

.

2. DC Characteristics are measured after following POWER-UP timing.

3. I_OUTdepends on the output load conditions.

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AC Characteristics

(Under Recommended Operating Conditions Unless Otherwise Noted)

Read Operation

32M

64M

Parameter

Symbol

t_RC

Min.

70

—

Max.

1000

70

40

70

30

20

1000

—

Min.

70

—

Max.

1000

70

40

70

30

20

1000

—

Unit

ns

Notes

Read Cycle Time

CE1# Access Time

OE# Access Time

1, 2

t_CE

3

t_OE

—

3

Address Access Time

t_AA

—

3, 5

ADV# Access Time

t_AV

3

LB# / UB# Access Time

t_BA

—

20

5

—

20

5

3

Page Address Access Time

Page Read Cycle Time

t_PAA

t_PRC

t_OH

3,6

1, 6, 7

Output Data Hold Time

3

4

3

CE1# Low to Output Low-Z

OE# Low to Output Low-Z

LB# / UB# Low to Output Low-Z

CE1# High to Output High-Z

OE# High to Output High-Z

LB# / UB# High to Output High-Z

Address Setup Time to CE1# Low

Address Setup Time to OE# Low

ADV# Low Pulse Width

t_CLZ

t_OLZ

t_BLZ

t_CHZ

t_OHZ

t_BHZ

t_ASC

t_ASO

t_VPL

t_VPH

t_ASV

t_AHV

t_AX

5

—

5

—

10

0

—

0

—

0

—

–5

10

15

5

20

—

–5

10

15

5

20

—

8

ADV# High Pulse Width

—

Address Setup Time to ADV High

Address Hold Time from ADV# High

Address Invalid Time

—

10

—

–5

15

—

5

—

10

—

–5

25

15

10

—

5, 9

10

Address Hold Time from CE1# High

Address Hold Time from OE# High

WE# High to OE# Low Time for Read

CE1# High Pulse Width

t_CHAH

t_OHAH

t_WHOL

t_CP

—

10

1000

—

1000

—

11

Notes:

1. Maximum value is applicable if CE#1 is kept at Low without change of address input of A3 to A21.

2. Address should not be changed within minimum t_RC

3. The output load 50pF with 50ohm termination to V_DD*0.5 V.

.

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4. The output load 5pF without any other load.

5. Applicable to A3 to A21 when CE1# is kept at Low.

6. Applicable only to A0, A1 and A2 when CE1# is kept at Low for the page address access.

7. In case Page Read Cycle is continued with keeping CE1# stays Low, CE1# must be brought to High within 4µs. In other

words, Page Read Cycle must be closed within 4µs.

8. t_VPLis specified from the negative edge of either CE1# or ADV# whichever comes late. The sum of t_VPLand t_VPHmust be

equal or greater than tRC for each access.

9. Applicable to address access when at least two of address inputs are switched from previous state.

10. t_RC(min) and t_PRC(min) must be satisfied.

11. If actual value of t_WHOLis shorter than specified minimum values, the actual t_AAof following Read may become longer by the

amount of subtracting actual value from specified minimum value.

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Write Operation

32M

64M

Parameter

Symbol

t_WC

t_AS

Min.

70

0

Max.

1000

—

Min.

70

0

Max.

1000

—

Unit

ns

Notes

1, 2

3

Write Cycle Time

Address Setup Time

ADV# Low Pulse Width

t_VPL

t_VPH

t_ASV

t_AHV

t_CW

t_WP

10

15

5

—

10

15

5

—

4

ADV# High Pulse Width

Address Setup Time to ADV# High

Address Hold Time from ADV# High

CE1# Write Pulse Width

WE# Write Pulse Width

LB# / UB# Write Pulse Width

LB# / UB# Byte Mask Setup Time

LB# / UB# Byte Mask Hold Time

CE1# Write Recovery Time

Write Recovery Time

—

10

45

-5

15

0

—

5

—

45

-5

15

0

—

3

5

6

7

—

t_BW

t_BS

—

t_BH

—

t_WRC

t_WR

t_CP

—

1000

—

1000

—

CE1# High Pulse Width

WE# High Pulse Width

t_WHP

t_BHP

t_DS

1000

—

1000

—

LB# / UB# High Pulse Width

Data Setup Time

Data Hold Time

t_DH

—

OE# High to CE1# Low Setup Time for Write

OE# High to Address Setup Time for Write

LB# / UB# Write Pulse Overlap

t_OHCL

t_OES

-5

0

—

-5

0

—

8

9

—

t_BWO

30

—

30

—

Notes:

1. Maximum value is applicable if CE1# is kept at Low without any address change.

2. Minimum value must be equal or greater than the sum of write pulse (t_CW, t_WPor t_BW) and write recovery time (t_WR).

3. Write pulse is defined from High to Low transition of CE1#, WE#, or LB# / UB#, whichever occurs last.

4.

t

_VPLis specified from the negative edge of either CE#1 or ADV# whichever comes late. The sum of t_VPLand t_VPHmust be

equal or greater than t_WCfor each access.

5. Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1# or WE# whichever

occurs last.

6. Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1# or WE# whichever

occurs first.

7. Write recovery is defined from Low to High transition of CE1#, WE#, or LB# / UB#, whichever occurs first.

8. If OE# is Low after minimum t_OHCL, read cycle is initiated. In other words, OE# must be brought to High within 5ns after

CE1# is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum t_RCis met.

9. If OE# is Low after new address input, read cycle is initiated. In other word, OE# must be brought to High at the same time

or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum t_RCis met and data

bus is in High-Z.

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Synchronous Operation - Clock Input (Burst Mode)

32M

64M

Parameter

Symbol

Min.

Max.

Min.

13

15

18

30

4

Max.

—

Unit

ns

Notes

RL = 6

RL = 5

RL = 4

RL = 3

N/A

15

20

30

5

—

3

—

Clock Period

t_CK

1

—

Clock High Time

Clock Low Time

Clock Rise/Fall Time

Notes:

t_CKH

t_CKL

t_CKT

—

3

5

4

—

2

1. Clock period is defined between valid clock edges.

2. Clock rise/fall time is defined between V_IHMin. and V_ILMax.

Synchronous Operation - Address Latch (Burst Mode)

32M

64M

Parameter

Symbol

t_ASVL

t_ASCL

t_AHV

Min.

-5

Max.

—

Min.

-5

5

Max.

Unit

Notes

Address Setup Time to ADV# Low

Address Setup Time to CE1# Low

Address Hold Time from ADV# High

ADV# Low Pulse Width

—

ns

1

2

-5

—

10

—

t_VPL

—

10

5

3

4

RL = 6, 5

—

ADV# Low Setup Time to CLK

t_VSCK

7

RL = 4, 3

RL = 6, 5

RL = 4, 3

—

7

—

5

CE1 Low Setup Time to CLK

t_CLCK

—

7

ADV# Low Hold Time from CLK

t_CKVH

t_VHVL

1

—

1

Burst End ADV# High Hold Time from CLK

15

—

13

Notes:

1. t_ASCLis applicable if CE1# is brought to Low after ADV# is brought to Low.

2.

t

_ASVLis applicable if ADV# is brought to Low after CE1# is brought to Low.

3.

t

_VPLis specified from the negative edge of either CE1# or ADV# whichever comes late.

4. Applicable to the 1st valid clock edge.

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Synchronous Read Operation (Burst Mode)

32M

64M

Parameter

Burst Read Cycle Time

Symbol

Min.

Max.

Min.

—

3

Max.

4000

10

12

—

Unit

ns

Notes

t_RCB

—

8000

RL = 6, 5

RL = 4, 3

1

CLK Access Time

t_AC

—

12

Output Hold Time from CLK

CE1# Low to WAIT# Low

t_CKQX

t_CLTL

t_OLTL

t_VLTL

t_CKTV

t_CKTX

t_CLZ

3

5

0

—

20

1

5

20

10

—

1

OE# Low to WAIT# Low

0

1, 2

1

ADV# Low to WAIT# Low

N/A

0

CLK to WAIT# Valid Time

—

3

12

—

14

20

—

3

1, 3

1

WAIT# Valid Hold Time from CLK

CE1# Low to Output Low-Z

OE# Low to Output Low-Z

LB#, UB# Low to Output Low-Z

CE1# High to Output High-Z

OE# High to Output High-Z

LB#, UB# High to Output High-Z

CE1# High to WAIT High-Z

OE# High to WAIT High-Z

OE# Low Setup Time to 1st Data-out

5

—

4

t_OLZ

10

0

10

0

—

4

t_BLZ

—

4

t_CHZ

—

30

5

—

30

26

5

20

—

1

t_OHZ

t_BHZ

1

t_CHTZ

t_OHTZ

t_OLQ

1

UB#, LB# Setup Time to 1st Data-out

OE# Setup Time to CLK

t_BLQ

—

5

t_OSCK

t_CKOH

t_CKCLH

t_CKBH

—

OE# Hold Time from CLK

5

—

Burst End CE1# Low Hold Time from CLK

Burst End UB#, LB# Hold Time from CLK

5

—

5

—

BL=8, 16

BL=Continuous

30

70

26

70

—

6

Burst Terminate Recovery Time

t_TRB

—

Notes:

1. The output load 50pF with 50ohm termination to V_DD*0.5 V.

2. WAIT# drives High at the beginning depending on OE# falling edge timing.

3. t_CKTVis guaranteed after t_OLTL(max) from OE# falling edge and t_OSCKmust be satisfied.

4. The output load is 5pF without any other load.

5. Once they are determined, they must not be changed until the end of burst.

6. Defined from the Low to High transition of CE1# to the High to Low transition of either ADV# or CE1# whichever occurs late.

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Synchronous Write Operation (Burst Mode)

32M

64M

Parameter

Burst Write Cycle Time

Symbol

t_WCB

Min.

—

7

Max.

8000

—

Min.

—

5

Max.

4000

—

Unit

ns

Notes

Data Setup Time to Clock

t_DSCK

t_DHCK

t_WLD

Data Hold Time from CLK

3

—

3

—

WE# Low Setup Time to 1st Data In

UB#, LB# Setup Time for Write

WE# Setup Time to CLK

30

-5

5

—

30

-5

5

—

t_BS

—

1

t_WSCK

t_CKWH

t_CLTH

t_WLTH

t_CHTZ

t_WHTZ

t_CKCLH

t_CHCK

t_CKBH

t_WRB

—

WE# Hold Time from CLK

5

—

5

—

CE1# Low to WAIT# High

5

20

—

5

20

—

2

WE# Low to WAIT# High

0

CE1# High to WAIT# High-Z

WE# High to WAIT# High-Z

—

5

—

5

Burst End CE1# Low Hold Time from CLK

Burst End CE1# High Setup Time to next CLK

Burst End UB#, LB# Hold Time from CLK

Burst Write Recovery Time

5

—

5

—

5

—

5

—

30

70

26

70

BL=8, 16

Burst Terminate Recovery Time

BL=Continuous

t_TRB

—

3

4

t_TRB

Notes:

1. Defined from the valid input edge to the High to Low transition of either ADV#, CE1#, or WE#, whichever occurs last. And

once they are determined, they must not be changed until the end of burst.

2. The output load 50pF with 50ohm termination to V_DD*0.5 V.

3. Defined from the valid clock edge where last data-in being latched at the end of burst write to the High to Low transition of

either ADV# or CE1# whichever occurs late for the next access.

4. Defined from the Low to High transition of CE1# to the High to Low transition of either ADV# or CE1# whichever occurs late

for the next access.

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Power Down Parameters

32M

64M

Parameter

Symbol

t_CSP

Min.

20

Max.

—

Min.

10

Max.

—

Unit

ns

Notes

CE2 Low Setup Time for Power Down Entry

CE2 Low Hold Time after Power Down Entry

CE2 Low Hold Time for Reset to Asynchronous Mode

t_C2LP

70

—

70

—

ns

t_C2LPR

N/A

50

—

µs

1

2

CE1# High Hold Time following CE2 High after Power

Down Exit [SLEEP mode only]

t_CHH

t_CHHP

t_CHS

300

70

0

—

300

70

0

—

µs

ns

CE1# High Hold Time following CE2 High after Power

Down Exit [not in SLEEP mode]

3

2

CE1# High Setup Time following CE2 High after Power

Down Exit

Notes:

1. Applicable when RP=0 (Reset to Page mode). RP (Reset to Page) mode is available only for 64M.

2. Applicable also to power-up.

3. Applicable when Partial mode is set.

Other Timing Parameters

32M

64M

Parameter

CE1 High to OE Invalid Time for Standby Entry

CE1 High to WE Invalid Time for Standby Entry

CE2 Low Hold Time after Power-up

CE1 High Hold Time following CE2 High after Power-up

Input Transition Time

Symbol

t_CHOX

t_CHWX

t_C2LH

t_CHH

Min.

10

50

300

1

Max.

—

Min.

10

50

300

1

Max.

—

Unit

ns

Notes

—

ns

1

—

µs

—

µs

t_T

25

ns

2

Notes:

1. Some data might be written into any address location if t_CHWX(min) is not satisfied.

2. Except for clock input transition time.

3. The Input Transition Time (t_T) at AC testing is 5ns for Asynchronous operation and 3ns for Synchronous operation

respectively. If actual t_Tis longer than 5ns or 3ns specified as AC test condition, it may violate AC specification of some

timing parameters. See the "AC Test Conditions" section

AC Test Conditions

Symbol

V_IH

Description

Te s t S e tu p

Value

V_DD* 0.8

V_DD* 0.2

V_DD* 0.5

5

Unit

V

Note

Input High Level

Input Low Level

V_IL

V

V_REF

Input Timing Measurement Level

V

Async.

Sync.

ns

t_T

Input Transition Time

Between V_ILand V_IH

3

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AC Measurement Output Load Circuit

V_DD*0.5V

50ohm

V_DD

DEVICE

UNDER

TEST

OUT

0.1µF

V_SS

50pF

Figure 49. Output Load Circuit

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Timing Diagrams

tRC

ADDRESS VALID

ADDRESS

ADV#

CE1#

Low

tASC

tCE

tCHAH

tASC

tCP

tCHZ

tOE

OE#

tOHZ

tBHZ

tBA

LB# / UB#

tBLZ

tOLZ

DQ

(Output)

VALID DATA OUTPUT

Figure 50. Asynchronous Read Timing #1-1 (Basic Timing)

tOH

Note: This timing diagram assumes CE2=H and WE#=H.

tRC

ADDRESS VALID

ADDRESS

ADV#

tAHV

tAV

tVPL

tASC

tCE

CE1#

tCP

tOE

tCHZ

OE#

tOHZ

tBHZ

tBA

LB# / UB#

tBLZ

tOLZ

DQ

(Output)

VALID DATA OUTPUT

Figure 51. Asynchronous Read Timing #1-2 (Basic Timing)

tOH

Note: This timing diagram assumes CE2=H and WE#=H.

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tAX

tRC

ADDRESS

CE1#

ADDRESS VALID

tAA

tOHAH

Low

tASO

tOE

OE#

LB# / UB#

tOLZ

tOH

tOHZ

tOH

DQ

(Output)

VALID DATA OUTPUT

Figure 52. Asynchronous Read Timing #2 (OE# & Address Access)

VALID DATA OUTPUT

Note: This timing diagram assumes CE2=H, ADV#=L and WE#=H.

tAX

tRC

tAX

ADDRESS

ADDRESS VALID

tAA

Low

CE1#, OE#

LB#

tBA

UB#

tBHZ

tOH

tBHZ

tOH

tBLZ

DQ1-8

(Output)

VALID DATA

OUTPUT

tBHZ

VALID DATA

OUTPUT

tOH

tBLZ

DQ9-16

(Output)

VALID DATA OUTPUT

Figure 53. Asynchronous Read Timing #3 (LB# / UB# Byte Access)

Note: This timing diagram assumes CE2=H, ADV#=L and WE#=H.

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tRC

ADDRESS

(A21-A3)

ADDRESS VALID

tRC

tPRC

ADDRESS

(A2-A0)

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS VALID

tPAA

tASC

tCHAH

ADV#

CE1#

tCHZ

tCE

OE#

LB# / UB#

tOH

tCLZ

tOH

DQ

(Output)

VALID DATA OUTPUT

(Page Access)

VALID DATA OUTPUT

(Normal Access)

Figure 54. Asynchronous Read Timing #4 (Page Address Access after CE1# Control Access)

Note: This timing diagram assumes CE2=H and WE#=H.

tRC

tAX

tRC

tAX

ADDRESS

(A21-A3)

ADDRESS VALID

tRC

tPRC

tRC

tPRC

ADDRESS

(A2-A0)

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

tAA

tPAA

tAA

tPAA

CE1#

Low

tASO

tOE

OE#

tBA

LB# / UB#

tOLZ

tBLZ

tOH

DQ

(Output)

VALID DATA OUTPUT

(Page Access)

VALID DATA OUTPUT

(Normal Access)

Figure 55. Asynchronous Read Timing #5 (Random and Page Address

Access)

Notes:

1. This timing diagram assumes CE2=H, ADV#=L and WE#=H.

2. Either or both LB# and UB# must be Low when both CE1# and OE# are Low.

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tWC

ADDRESS

ADV#

ADDRESS VALID

Low

tAS

tCW

tWP

tBW

tWRC

tWR

tBR

tAS

CE1#

tAS

WE#

tAS

LB#, UB#

tOHCL

OE#

tDS

tDH

DQ

(Input)

VALID DATA INPUT

Figure 56. Asynchronous Write Timing #1-1 (Basic Timing)

Note: This timing diagram assumes CE2=H and ADV#=L.

tWC

ADDRESS

ADV#

ADDRESS VALID

tVPL

tAHV

tCW

tAS

tWRC

tWR

tBR

tAS

CE1#

tAS

tWP

tAS

WE#

tAS

tBW

tAS

LB#, UB#

tOHCL

OE#

tDS

tDH

DQ

(Input)

VALID DATA INPUT

Figure 57. Asynchronous Write Timing #1-2 (Basic Timing)

Note: This timing diagram assumes CE2=H.

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tWC

ADDRESS VALID

ADDRESS

CE1#

tOHAH

Low

tAS

tWP

tWR

tAS

tWP

tWR

WE#

UB#, LB#

OE#

tOES

tOHZ

tDS

tDH

tDS

tDH

DQ

(Input)

VALID DATA INPUT

Figure 58. Asynchronous Write Timing #2 (WE# Control)

Note: This timing diagram assumes CE2=H and ADV#=L.

tWC

ADDRESS VALID

ADDRESS

CE1#

Low

tAS

tWP

tAS

tWP

WE#

LB#

UB#

tBH

tBR

tBS

tBR

tBS

tBH

tDS

tDH

DQ1-8

(Input)

VALID DATA INPUT

tDS

tDH

DQ9-16

(Input)

VALID DATA INPUT

Figure 59. Asynchronous Write Timing #3-1 (WE# / LB# / UB# Byte Write Control)

Note: This timing diagram assumes CE2=H, ADV#=L and OE#=H.

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tWC

ADDRESS VALID

ADDRESS

CE1#

Low

tWR

WE#

LB#

UB#

tAS

tBW

tBS

tBH

tAS

tBW

tBH

tBS

tDS

tDH

DQ1-8

(Input)

VALID DATA INPUT

tDS

tDH

DQ9-16

(Input)

VALID DATA INPUT

Figure 60. Asynchronous Write Timing #3-2 (WE# / LB# / UB# Byte Write Control)

Note: This timing diagram assumes CE2=H, ADV#=L and OE#=H.

tWC

ADDRESS VALID

ADDRESS

CE1#

Low

WE#

LB#

UB#

tAS

tBW

tBR

tBS

tBH

tAS

tBW

tBR

tBS

tBH

tDS

tDH

DQ1-8

(Input)

VALID DATA INPUT

tDS

tDH

DQ9-16

(Input)

VALID DATA INPUT

Figure 61. Asynchronous Write Timing #3-3 (WE# / LB# / UB# Byte Write Control)

Note: This timing diagram assumes CE2=H, ADV#=L and OE#=H.

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tWC

ADDRESS VALID

ADDRESS

CE1#

Low

WE#

LB#

tAS

tBW

tBR

tAS

tBW

tBR

tBWO

tDH

tDS

tDH

tDS

DQ1-8

(Input)

VALID

DATA INPUT

VALID

DATA INPUT

tAS

tBW

tBR

tAS

tBR

tBWO

tBW

UB#

tDS

tDH

tDS

tDH

DQ9-16

(Input)

VALID

DATA INPUT

VALID

DATA INPUT

Figure 62. Asynchronous Write Timing #3-4 (WE# / LB# / UB# Byte Write Control)

Note: This timing diagram assumes CE2=H, ADV#=L and OE#=H.

tWC

tRC

ADDRESS

CE1#

WRITE ADDRESS

READ ADDRESS

tCHAH

tAS

tCW

tWRC

tASC

tCE

tCHAH

tCP

WE#

UB#, LB#

OE#

tOHCL

tCHZ

tOH

tDS

tDH

tCLZ

tOH

DQ

READ DATA OUTPUT

WRITE DATA INPUT

Figure 63. Asynchronous Read / Write Timing #1-1 (CE1# Control)

Notes:

1. This timing diagram assumes CE2=H and ADV#=L.

2. Write address is valid from either CE1# or WE# of last falling edge.

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tWC

tRC

ADDRESS

CE1#

WRITE ADDRESS

READ ADDRESS

tCHAH

tAS

tWR

tASC

tCE

tCHAH

tCP

tWP

WE#

UB#, LB#

OE

tOHCL

tOE

tCHZ

tOH

tDS

tDH

tOLZ

tOH

DQ

READ DATA OUTPUT

WRITE DATA INPUT

READ DATA OUTPUT

Figure 64. Asynchronous Read / Write Timing #1-2 (CE1# / WE# / OE# Control)

Notes:

1. This timing diagram assumes CE2=H and ADV#=L.

2. OE# can be fixed Low during write operation if it is CE1# controlled write at Read-Write-Read Sequence.

tWC

tRC

ADDRESS

CE1#

WRITE ADDRESS

READ ADDRESS

tOHAH

tAA

Low

tAS

tWR

tWP

WE#

tOES

UB#, LB#

OE#

tASO

tOE

tOHZ

tOH

tOHZ

tOH

tDS

tDH

tOLZ

DQ

READ DATA OUTPUT

WRITE DATA INPUT

Figure 65. Asynchronous Read / Write Timing #2 (OE#, WE# Control)

Notes:

1. This timing diagram assumes CE2=H and ADV#=L.

2. CE1# can be tied to Low for WE# and OE# controlled operation.

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tWC

tRC

ADDRESS

CE1#

WRITE ADDRESS

READ ADDRESS

tAA

tOHAH

Low

WE#

tOES

tAS

tBW

tBR

tBA

UB#, LB#

OE#

tBHZ

tASO

tBHZ

tOH

tDS

tDH

tBLZ

tOH

DQ

READ DATA OUTPUT

WRITE DATA INPUT

Figure 66. Asynchronous Read / Write Timing #3 (OE,# WE#, LB#, UB# Control)

Notes:

1. This timing diagram assumes CE2=H and ADV#=L.

2. CE1# can be tied to Low for WE# and OE# controlled operation.

tCK

CLK

tCK

tCKH

tCKL

tCKT

Figure 67. Clock Input Timing

Notes:

1. Stable clock input must be required during CE1#=L.

2.

t

_CKis defined between valid clock edges.

3.

t

_CKTis defined between V_IHMin. and V_ILMax

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Case #1

Case #2

CLK

ADDRESS

Valid

tASCL

tCKVH

tAHV

tVSCK

tCKVH

tAHV

tASVL

tVSCK

ADV#

CE1#

tVPL

tVLCL

tCLCK

Low

Figure 68. Address Latch Timing (Synchronous Mode)

Notes:

1. Case #1 is the timing when CE1# is brought to Low after ADV# is brought to Low. Case #2 is the timing when ADV# is

brought to Low after CE1# is brought to Low.

2.

t

_VPLis specified from the negative edge of either CE1# or ADV# whichever comes late. At least one valid clock edge must be

input during ADV#=L.

3. t_VSCKand t_CLCKare applied to the 1st valid clock edge during ADV#=L.

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RL=5

CLK

tRCB

ADDRESS

Valid

tASVL

tAHV

tCKVH

tASVL

tVSCK

tCKVH

ADV#

CE1#

tVPL

tVHVL

tVPL

tASCL

tCLCK

tCKOH

tCP

OE#

WE#

tOLQ

High

tCKBH

tBLQ

LB#, UB#

WAIT#

DQ

tOHTZ

tCKTV

High-Z

tOHZ

tOLTL

tCKTX

tAC

tCKTX

QBL

Q1

tOLZ

tCKQX

Figure 69. 32M Synchronous Read Timing #1 (OE# Control)

Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.

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RL=5

CLK

tRCB

ADDRESS

Valid

tASVL

tAHV

tCKVH

tASVL

tAHV

tCKVH

tVSCK

ADV#

tVPL

tVHVL

tVPL

tASCL

CE1#

tCP

tCLCK

tCKCLH

tCLCK

OE#

WE#

High

tCKBH

LB#, UB#

WAIT#

DQ

tCKTV

tCHTZ

tCLTL

tCLZ

tCLTL

tCKTX

tAC

tCKTX

tCHZ

Q1

QBL

tCLZ

tCKQX

Figure 70. 32M Synchronous Read Timing #2 (CE1# Control)

Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.

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RL=5

CLK

tRCB

ADDRESS

Valid

tASVL

tAHV

tASVL

tAHV

tCKVH

tVSCK

tCKVH

ADV#

tVPL

tVHVL

tVPL

CE1#

Low

OE#

WE#

Low

High

LB#, UB#

WAIT#

DQ

tCKTV

tCKTX

tAC

tCKTX

QBL

Q1

tCKQX

Figure 71. 32M Synchronous Read Timing #3 (ADV# Control)

Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.

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RL=5

CLK

ADDRESS

XXX7Fh

tASVL

tAHV

tCKVH

tVSCK

ADV#

CE1#

OE#

tVPL

tASCL

tCLCK

tOLQ

High

WE#

tBLQ

LB#, UB#

WAIT#

DQ

tCKTV

High-Z

tCKTX

tOLTL

tCKTX

tAC

tCKTX

tAC

Q1

Q2

Q3

tOLZ

tCKQX

Figure 72. Synchronous Read - WAIT# Output Timing (Continuous Read)

Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.

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P r e l i m i n a r y

RL=5

CLK

tRCB

ADDRESS

Valid

tASVL

tAHV

tCKVH

tASVL

tVSCK

tCKVH

ADV#

CE1#

tVPL

tVHVL

tVPL

tASCL

tCLCK

tCKOH

tCP

OE#

WE#

tOLQ

High

tCKBH

tBLQ

LB#, UB#

tCKTV

tOHTZ

tOHZ

WAIT#

DQ

High-Z

tOLTL

tCKTX

tAC

Q1

QBL

tOLZ

tCKQX

Figure 73. 64M Synchronous Read Timing #1 (OE# Control)

Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.

October 5, 2004 CosmoRAM_00_A0

CosmoRAM

156

P r e l i m i n a r y

RL=5

CLK

tRCB

ADDRESS

Valid

tASVL

tAHV

tCKVH

tASVL

tAHV

tCKVH

tVSCK

ADV#

CE1#

tVPL

tVHVL

tVPL

tASCL

tCP

tCLCK

tCKCLH

tCLCK

OE#

WE#

High

tCKBH

LB#, UB#

tCKTV

tCHTZ

tCLTL

WAIT#

DQ

tCLZ

tCLTL

tCKTX

tAC

tCHZ

Q1

QBL

tCLZ

tCKQX

Figure 74. 64M Synchronous Read Timing #2 (CE1# Control)

Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.

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P r e l i m i n a r y

RL=5

CLK

tRCB

ADDRESS

Valid

tASVL

tAHV

tCKVH

tASVL

tAHV

tCKVH

tVSCK

ADV#

tVPL

tVHVL

tVPL

CE1#

Low

OE#

WE#

Low

High

LB#, UB#

WAIT#

DQ

tCKTV

tVLTL

tCKTX

tAC

Q1

QBL

tCKQX

Figure 75. 64M Synchronous Read Timing #3 (ADV# Control)

Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.

October 5, 2004 CosmoRAM_00_A0

CosmoRAM

158

P r e l i m i n a r y

RL=5

CLK

tWCB

ADDRESS

Valid

tASVL

tAHV

tCKVH

tASVL

tAHV

tCKVH

tVSCK

tVHVL

tWRB

ADV#

CE1#

tVPL

tCLCK

tASCL

tCLCK

tCP

High

OE#

WE#

tWLD

tCKWH

tBS

tCKBH

tBS

LB#, UB#

WAIT#

DQ

High-Z

tWLTH

tDSCK

tWHTZ

D1

D2

DBL

tDHCK

Figure 76. Synchronous Write Timing #1 (WE# Level Control)

Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.

159

CosmoRAM

CosmoRAM_00_A0 October 5, 2004

P r e l i m i n a r y

RL=5

CLK

tWCB

ADDRESS

Valid

tASVL

tAHV

tCKVH

tASVL

tAHV

tCKVH

tVSCK

tVHVL

tWRB

ADV#

CE1#

tVPL

tCLCK

tASCL

tCLCK

tCP

tCKCLH

High

OE#

WE#

tWSCK

tCKWH

tWSCK

tCKWH

tBS

tCKBH

tBS

LB#, UB#

WAIT#

High-Z

tWLTH

tDSCK

tCHTZ

tWLTH

D1

D2

DBL

DQ

tDHCK

Figure 77. Synchronous Write Timing #2 (WE# Single Clock Pulse Control)

Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.

October 5, 2004 CosmoRAM_00_A0

CosmoRAM

160

P r e l i m i n a r y

RL=5

CLK

tWCB

ADDRESS

Valid

tASVL

tAHV

tCKVH

tASVL

tAHV

tCKVH

tVSCK

ADV#

CE1#

tVHVL

tVPL

tWRB

High

OE#

WE#

tBS

tCKBH

tBS

LB#, UB#

WAIT#

DQ

High

tDSCK

D1

D2

DBL

tDHCK

Figure 78. Synchronous Write Timing #3 (ADV# Control)

Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.

161

CosmoRAM

CosmoRAM_00_A0 October 5, 2004

P r e l i m i n a r y

RL=5

CLK

tWCB

ADDRESS

Valid

tASVL

tAHV

tCKVH

tASVL

tAHV

tCKVH

tVSCK

tVHVL

tWRB

ADV#

CE1#

tVPL

tCLCK

tASCL

tCLCK

tCP

High

OE#

WE#

tWLD

tCKWH

tBS

tCKBH

tBS

LB#, UB#

WAIT#

DQ

High-Z

tWLTH

tDSCK

tWHTZ

tWLTH

D1

tDHCK

Figure 79. Synchronous Write Timing #4 (WE# Level Control, Single Write)

Notes:

1. This timing diagram assumes CE2=H, the valid clock edge on rising edge and single write operation.

2. Write data is latched on the valid clock edge.

October 5, 2004 CosmoRAM_00_A0

CosmoRAM

162

P r e l i m i n a r y

RL=5

CLK

tWCB

ADDRESS

Valid

tASVL

tVHVL

tAHV

tCKVH

tVSCK

ADV#

CE1#

tVPL

tCLCK

tCKCLH

tASCL

tCP

OE#

WE#

LB#, UB#

WAIT#

DQ

tCKBH

tBS

tCKBH

tCHTZ

tCKTV

tCHZ

tCLTH

tAC

tCKTX

QBL

tDSCK

QBL-1

D1

D2

D3

DBL

tDHCK

tCKQX

Figure 80. 32M Synchronous Read to Write Timing #1(CE1# Control)

Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.

163

CosmoRAM

CosmoRAM_00_A0 October 5, 2004

P r e l i m i n a r y

RL=5

CLK

ADDRESS

Valid

tASVL

tAHV

tVSCK

tCKVH

ADV#

CE1#

tVPL

tVHVL

tCKOH

OE#

tWLD

tCKWH

WE#

tCKBH

tBS

tCKBH

LB#, UB#

tOHTZ

tCKTV

WAIT#

DQ

tOHZ

tAC

tCKTX

tWLTH

tDSCK

QBL-1

QBL

D1

D2

D3

DBL

tDHCK

tCKQX

Figure 81. 32M Synchronous Read to Write Timing #2(ADV# Control)

Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.

October 5, 2004 CosmoRAM_00_A0

CosmoRAM

164

P r e l i m i n a r y

RL=5

CLK

tWCB

ADDRESS

Valid

tASVL

tAHV

tCKVH

tVSCK

ADV#

tVHVL

tASCL

tVPL

tCLCK

tCKCLH

CE1#

tCP

OE#

WE#

tCKBH

tBS

tCKBH

LB#, UB#

WAIT#

DQ

tCHTZ

tCHZ

tAC

tCLTH

tDSCK

QBL-1

QBL

D1

D2

D3

DBL

tDHCK

tCKQX

Figure 82. 64M Synchronous Read to Write Timing #1(CE1# Control)

Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.

165

CosmoRAM

CosmoRAM_00_A0 October 5, 2004

P r e l i m i n a r y

RL=5

CLK

ADDRESS

Valid

tASVL

tAHV

tVSCK

tCKVH

ADV#

tVPL

tVHVL

CE1#

tCKOH

OE#

WE#

tWLD

tCKWH

tCKBH

tBS

tCKBH

LB#, UB#

WAIT#

DQ

tOHTZ

tOHZ

tAC

tWLTH

tDSCK

QBL-1

QBL

D1

D2

D3

DBL

tDHCK

tCKQX

Figure 83. 64M Synchronous Read to Write Timing #2(ADV# Control)

Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.

October 5, 2004 CosmoRAM_00_A0

CosmoRAM

166

P r e l i m i n a r y

RL=5

CLK

tCKT

ADDRESS

Valid

tASVL

tAHV

tVSCK

tCKVH

ADV#

CE1#

tVPL

tASCL

tCKCLH

tCP

tCLCK

tWRB

OE#

WE#

tCKBH

LB#, UB#

tCKTV

High-Z

WAIT#

tDSCK

tCHTZ

tCLTL

tCKTX

tAC

DBL-1

DBL

Q1

Q2

DQ

tDHCK

tCLZ

tCKQX

Figure 84. Synchronous Write to Read Timing #1 (CE1# Control)

Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.

167

CosmoRAM

CosmoRAM_00_A0 October 5, 2004

P r e l i m i n a r y

RL=5

CLK

tCKT

ADDRESS

Valid

tASVL

tVSCK

tAHV

tCKVH

ADV#

CE1#

tVPL

tWRB

Low

OE#

WE#

tOLQ

tCKWH

tCKBH

tBLQ

LB#, UB#

WAIT#

tCKTV

High-Z

tDSCK

tWHTZ

tOLTL

tCKTX

tAC

DBL-1

DBL

Q1

Q2

DQ

tDHCK

tOLZ

tCKQX

Figure 85. Synchronous Write to Read Timing #2 (ADV# Control)

Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.

October 5, 2004 CosmoRAM_00_A0

CosmoRAM

168

P r e l i m i n a r y

CE1#

CE2

tCHS

tC2LH

tCHH

V

DD

VDD min

0V

Figure 86. Power-up Timing #1

Note: The t_C2LHspecifies after V_DDreaches specified minimum level.

CE1#

tCHH

CE2

VDD

VDD min

0V

Figure 87. Power-up Timing #2

Note: The t_CHHspecifies after V_DDreaches specified minimum level and applicable to both CE1# and CE2.

CE1#

tCHS

CE2

tCSP

tC2LP

tCHH (tCHHP)

High-Z

DQ

Power Down Entry

Power Down Mode

Power Down Exit

Figure 88. Power Down Entry and Exit Timing

Note: This Power Down mode can be also used as a reset timing if the POWER-UP timing above could not be satisfied

and Power-Down program was not performed prior to this reset.

169

CosmoRAM

CosmoRAM_00_A0 October 5, 2004

P r e l i m i n a r y

CE1#

OE#

tCHOX

tCHWX

WE#

Active (Read)

Standby

Active (Write)

Standby

Figure 89. Standby Entry Timing after Read or Write

Note: Both t_CHOXand t_CHWXdefine the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes

t_RC(min) period for Standby mode from CE1# Low to High transition.

tRC

tWC

tRC

MSB*¹

Key*²

ADDRESS

CE1#

tCP*³

(tRC)

tCP

OE#

WE#

LB#, UB#

DQ*³

RDa

Cycle #1

RDa

Cycle #2

RDa

Cycle #3

X

RDb

Cycle #6

Cycle #4

Cycle #5

Figure 90. Configuration Register Set Timing #1 (Asynchronous Operation)

Notes:

1. The all address inputs must be High from Cycle #1 to #5.

2. The address key must confirm the format specified in the "Functional Description" section. If not, the operation and data are

not guaranteed.

3. After t_CPor t_RCfollowing Cycle #6, the Configuration Register Set is completed and returned to the normal operation. t_CPand

t

_RCare applicable to returning to asynchronous mode and to synchronous mode respectively.

4. Byte read or write is available in addition to Word read or write. At least one byte control signal (LB# or UB#) need to be

Low.

October 5, 2004 CosmoRAM_00_A0

CosmoRAM

170

P r e l i m i n a r y

CLK

ADDRESS

MSB

Key

tRCB

tWCB

tRCB

ADV#

CE1#

tTRB

OE#

WE#

LB#, UB#

WAIT#

RL

RL-1

RDa

Cycle#2

RL-1

RDa

Cycle#3

RL-1

RL

RDa

X

RDb

Cycle#6

DQ

Cycle#1

Cycle#4

Cycle#5

Figure 91. Configuration Register Set Timing #2 (Synchronous Operation)

Notes:

1. The all address inputs must be High from Cycle #1 to #5.

2. The address key must confirm the format specified in the "Functional Description" section. If not, the operation and data are

not guaranteed.

3. After t_TRBfollowing Cycle #6, the Configuration Register Set is completed and returned to the normal operation.

4. Byte read or write is available in addition to Word read or write. At least one byte control signal (LB# or UB#) need to be

Low.

171

CosmoRAM

CosmoRAM_00_A0 October 5, 2004

A d v a n c e I n f o r m a t i o n

Revision Summary

Revision A (October 27, 2004)

Initial release.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary

industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that

includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal

injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,

medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and

artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-men-

tioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other

abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under

the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-

thorization by the respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by

Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided

ìas isî without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement

of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the

use of the information in this document.

sion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective compa-

nies.

October 27, 2004 S71WS256/128/064J_CSA0

Revision Summary

172


型号：	S71WS128JB0BAIAY2
厂家：	CYPRESS
描述：	Memory IC,
文件：	总171页 (文件大小：4450K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S71WS128JB0BAIAY2 [CYPRESS]

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