W161H [CYPRESS]
Processor Specific Clock Generator, 133MHz, CMOS, PDSO48, 0.300 INCH, MO-118AA, SSOP-48;
| 型号： | W161H |
| 厂家： | 
CYPRESS |
| 描述： | Processor Specific Clock Generator, 133MHz, CMOS, PDSO48, 0.300 INCH, MO-118AA, SSOP-48 光电二极管 |
| 文件： | 总10页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
W161
133-MHz Spread Spectrum FTG for Pentium® II Platforms
Spread Spectrum Modulation:..................................... –0.5%
Features
CPU to 3V66 Output Offset:............. 0.0–1.5 ns (CPU leads)
• Maximized EMI Suppression using Cypress’s Spread
Spectrum Technology
3V66 to PCI Output Offset:.............. 1.5–3.0 ns (3V66 leads)
CPU to IOAPIC Output Offset: ......... 1.5–4.0 ns (CPU leads)
• Three copies of CPU outputs at 100 or 133 MHz
• Three copies of 66-MHz output at 3.3V
• Ten copies of PCI clocks at 33 MHz, 3.3V
• Two copies of 14.318-MHz reference output at 3.3V
• One copy of 48-MHz USB clock
• One copy of CPU-divide-by-2 output as reference input
to Direct Rambus™ Clock Generator (Cypress W134)
• Available in 48-pin SSOP (300 mils)
Table 1. Pin Selectable Frequency
SEL133/100# SEL1 SEL0
Function
All outputs Three-State
(Reserved)
0
0
0
0
0
1
0
1
0
Active 100-MHz, 48-MHz
PLL inactive
0
1
1
Active 100-MHz, 48-MHz
PLL active
Key Specifications
Supply Voltages:...................................... VDDQ2 = 2.5V±5%
VDDQ3 = 3.3V±5%
1
1
1
0
0
1
0
1
0
Test Mode
(Reserved)
CPU, CPUdiv2 Output Jitter:....................................... 250 ps
CPU, CPUdiv2 Output Skew:...................................... 175 ps
IOAPIC, 3V66 Output Skew:....................................... 250 ps
PCI0:9 Output Skew: .................................................. 500 ps
Duty Cycle: ................................................................... 45/55
Active 133-MHz, 48-MHz
PLL inactive
1
1
1
Active 133-MHz, 48-MHz
PLL active
Pin Configuration[1]
Block Diagram
2
X1
XTAL
OSC
GND
REF0
REF1
VDDQ3
X1
X2
GND
PCI0
PCI1
VDDQ3
PCI2
PCI3
PCI4
PCI5
GND
PCI6
PCI7
VDDQ3
PCI8
PCI9
GND
3V66_0
3V66_1
3V66_2
VDDQ3
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF_[0:1]
X2
2
VDDQ2
IOAPIC
GND
VDDQ2
CPUdiv2
GND
VDDQ2
CPU2
GND
VDDQ2
CPU1
CPU0
GND
VDDQ3
GND
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
3
CPU_[0:2]
÷2
CPUdiv2
SPREAD#
SEL0
PLL 1
SEL1
3
SEL133/100#
3V66_[0:2]
÷2/÷1.5
PWRDWN#*
SPREAD#*
SEL1*
9
SEL0*
÷2
PCI_[0:9]
IOAPIC
PWRDWN#
VDDQ3
48MHz
GND
SEL133/100#
Power
Down
Logic
÷2
Note:
1. Internal 250-kΩ pull-up resistors present on inputs marked with *.
Design should not rely solely on internal pull-up resistor to set I/O
pins HIGH.
Three-state
Logic
PLL2
48MHz
Pentium is a registered trademark of Intel Corporation. Direct Rambus is a trademark of Rambus, Inc.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07162 Rev. **
Revised September 25, 2001
PRELIMINARY
W161
Pin Definitions
Pin
No.
Pin
Type
Pin Name
Pin Description
CPU0:2
36, 37, 40
O
O
CPU Clock Outputs 0 through 2: CPU clock outputs. Their output voltage
swing is controlled by voltage applied to VDDQ2.
PCI0:9
7, 8, 10, 11, 12,
13, 15, 16, 18,
19
PCI Clock Outputs 0 through 9: Output voltage swing is controlled by voltage
applied to VDDQ3.
CPUdiv2
43
O
CPU-Divide-By-2 Output: This serves as a reference input signal for Direct
Rambus Clock Generator (Cypress W134). The output voltage is determined
by VDDQ2.
3V66_0:2
IOAPIC
21, 22, 23
46
O
O
66-MHz Clock Outputs 0 through 2: Output voltage swing is controlled by
voltage applied to VDDQ3.
I/O APIC Clock Output: Provides an output synchronous to CPU clock. See
Table 1 for their relation to other system clock outputs.
48 MHz
27
31
O
I
48-MHz Output: Fixed clock output at 48 MHz.
SPREAD#
Spread Spectrum Enable: This input enables spread spectrum modulation
on the PLL1 generated frequency outputs of the W161. Modulation range is
–0.5%.
PWRDWN#
REF0:1
32
I
I
Power Down Control
1, 2
Fixed 14.318-MHz Output 0 and 1: Output voltage swing is controlled by
voltage applied to VDDQ3.
SEL0:1
SEL133/100#
X1
29, 30
25
I
I
I
Mode Select Input 0 through 1: 3.3V LVTTL-compatible input for selecting
clock output modes. As shown in Table 1.
Frequency Selection Input: 3.3V LVTTL-compatible input that selects CPU
output frequency as shown in Table 1.
4
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It can be used as an external 14.318-MHz crystal connection
or as an external reference frequency input.
X2
5
I
Crystal Connection: An input connection for an external 14.318-MHz crystal.
If using an external reference, this pin must be left unconnected.
VDDQ2
VDDQ3
38, 41, 44, 47
P
P
Power Connection: Connected to 2.5V power supply.
Power Connection: Connected to 3.3V power supply.
3, 9, 17, 24, 28,
34
GND
6, 14, 20, 26,
33, 35, 39, 42,
45, 48
G
Ground Connection: Connect all ground pins to the common system ground
plane.
Crystal Oscillator
Overview
The W161 requires one input reference clock to synthesize all
The W161, a motherboard clock synthesizer, provides 2.5V
CPU clock outputs for advanced CPU and a CPU-divide-by-2
reference frequency for Direct Rambus Clock Generator (such
Cypress W134) interface. Fixed output frequencies are provid-
ed for other system functions.
output frequencies. The reference clock can be either an ex-
ternally generated clock signal or the clock generated by the
internal crystal oscillator. When using an external clock signal,
pin X1 is used as the clock input and pin X2 is left open.
The internal crystal oscillator is used in conjunction with a
quartz crystal connected to device pins X1 and X2. This forms
a parallel resonant crystal oscillator circuit. The W161 incorpo-
rates the necessary feedback resistor and crystal load capac-
itors. Including typical stray circuit capacitance, the total load
presented to the crystal is approximately 18 pF. For optimum
frequency accuracy without the addition of external capacitors,
a parallel-resonant mode crystal specifying a load of 18 pF
should be used. This will typically yield reference frequency
accuracies within ±100 ppm.
CPU Frequency Selection
CPU frequency is selected with input pins 25, 29, and 30
(SEL133/100#, SEL0, and SEL1, respectively). Refer to Table
1 for details.
Output Buffer Configuration
Clock Outputs
All clock outputs are designed to drive serial terminated clock
lines. The W161 outputs are CMOS-type, which provide
rail-to-rail output swing.
Document #: 38-07162 Rev. **
Page 2 of 10
PRELIMINARY
W161
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
Spread Spectrum Feature
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 1.
The output clock is modulated with a waveform depicted in
Figure 2. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is –0.5% downspread. Figure
2 details the Cypress spreading pattern. Cypress does offer
options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
As shown in Figure 1, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is
dB = 6.5 + 9*log10(P) + 9*log10(F)
EMI Reduction
Spread
Spectrum
Enabled
Non-
Spread
Spectrum
Figure 1. Typical Clock and SSFTG Comparison
100%
80%
60%
40%
20%
0%
–20%
–40%
–60%
–80%
–100%
Time
Figure 2. Typical Modulation Profile
Document #: 38-07162 Rev. **
Page 3 of 10
PRELIMINARY
W161
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
only. Operation of the device at these or any other conditions
.
Parameter
VDD, VIN
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
–0.5 to +7.0
–65 to +150
0 to +70
Unit
V
TSTG
TA
°C
°C
°C
kV
Operating Temperature
TB
Ambient Temperature under Bias
Input ESD Protection
–55 to +125
2 (min.)
ESDPROT
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Supply Current
IDD-3.3V
IDD-2.5
Combined 3.3V Supply Current
Combined 2.5V Supply Current
CPU0:3 =133 MHz[2]
CPU0:3 =133 MHz[2]
160
90
mA
mA
Logic Inputs (All referenced to VDDQ3 = 3.3V)
VIL
Input Low Voltage
GND –
0.3
0.8
V
V
VIH
Input High Voltage
2.0
VDD
0.3
+
IIL
IIH
IIL
IIH
Input Low Current[3]
Input High Current[3]
Input Low Current, SEL133/100#[3]
Input High Current, SEL133/100#[3]
–25
10
–5
5
µA
µA
µA
µA
Clock Outputs
CPU, CPUdiv2, IOAPIC (Referenced to VDDQ2
)
Test Condition
IOL = 1 mA
Min.
Typ.
Max.
Unit
mV
V
VOL
VOH
IOL
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
50
IOH = –1 mA
VOL = 1.25V
VOH = 1.25V
Test Condition
IOL = 1 mA
2.2
45
65
65
100
100
Max.
50
mA
mA
Unit
mV
V
IOH
45
48MHz, REF (Referenced to VDDQ3
)
Min.
Typ.
VOL
VOH
IOL
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
IOH = –1 mA
VOL = 1.5V
3.1
45
65
65
100
100
Max.
50
mA
mA
Unit
mV
V
IOH
VOH = 1.5V
45
PCI, 3V66 (Referenced to VDDQ3
)
Test Condition
IOL = 1 mA
Min.
Typ.
VOL
VOH
IOL
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
IOH = –1 mA
VOL = 1.5V
3.1
70
65
100
95
145
135
mA
mA
IOH
VOH = 1.5V
Notes:
2. All clock outputs loaded with 6" 60Ω transmission lines with 20-pF capacitors.
3. W161 logic inputs have internal pull-up devices, except SEL133/100# (pull-ups not CMOS level).
Document #: 38-07162 Rev. **
Page 4 of 10
PRELIMINARY
W161
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5% (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Crystal Oscillator
VTH
X1 Input threshold Voltage[4]
1.65
18
V
CLOAD
Load Capacitance, Imposed on
External Crystal[5]
pF
CIN,X1
X1 Input Capacitance[6]
Pin X2 unconnected
Except X1 and X2
28
pF
Pin Capacitance/Inductance
CIN
Input Pin Capacitance
5
6
7
pF
pF
nH
COUT
LIN
Output Pin Capacitance
Input Pin Inductance
3.3V AC Electrical Characteristics
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%,VDDQ2 = 2.5V± 5%, fXTL = 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.[7]
3V66 Clock Outputs, 3V66_0:3 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Frequency
Test Condition/Comments
Min.
Typ.
Max.
Unit
MHz
V/ns
V/ns
%
f
Note 8
66.6
tR
tF
tD
fST
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Measured from 0.4V to 2.4V
1
1
4
4
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
45
55
3
Frequency Stabilization
Assumes full supply voltage reached within
ms
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior
to frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition.
Used for determining series termination
value.
15
Ω
Notes:
4. X1 input threshold voltage (typical) is VDD/2.
5. The W161 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF;
this includes typical stray capacitance of short PCB traces to crystal.
6. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
7. Period, jitter, offset, and skew measured on rising edge at 1.5V.
8. 3V66 is CPU/2 for CPU =133 MHz and (2 x CPU)/3 for CPU = 100 MHz.
Document #: 38-07162 Rev. **
Page 5 of 10
PRELIMINARY
W161
PCI Clock Outputs, PCI0:9 (Lump Capacitance Test Load = 30 pF
Parameter
Description
Period
Test Condition/Comments
Measured on rising edge at 1.5V[9]
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
Min.
30
12
12
1
Typ.
Max.
Unit
ns
tP
tH
tL
High Time
ns
Low Time
ns
tR
tF
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
4
4
V/ns
V/ns
%
Measured from 2.4V to 0.4V
1
tD
tJC
Measured on rising and falling edge at 1.5V
45
55
500
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
ps
difference of cycle time between two adjacent cycles.
tSK
tO
Output Skew
Measured on rising edge at 1.5V.
500
3
ps
ns
3V66 to PCI Clock Skew Covers all 3V66/PCI outputs. Measured on rising
edge at 1.5V. 3V66 leads PCI output.
1.5
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
15
Ω
REF Clock Outputs, REF0:1 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.4V
Min.
Typ.
Max. Unit
f
14.318
tR
0.5
0.5
45
2
2
V/ns
V/ns
%
tF
Measured from 2.4V to 0.4V
tD
Measured on rising and falling edge at 1.5V
55
3
fST
FrequencyStabilizationfrom Assumes full supply voltage reached within
ms
Power-up (cold start)
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value duringswitching transition. Used
for determining series termination value.
25
Ω
48-MHZ Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Frequency, Actual
Deviation from 48 MHz
PLL Ratio
Test Condition/Comments
Determined by PLL divider ratio (see m/n below)
(48.008 – 48)/48
Min.
Typ.
48.008
+167
Max. Unit
MHz
f
fD
ppm
m/n
tR
(14.31818 MHz x 57/17 = 48.008 MHz)
Measured from 0.4V to 2.4V
57/17
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
0.5
0.5
45
2
2
V/ns
V/ns
%
tF
Measured from 2.4V to 0.4V
tD
Measured on rising and falling edge at 1.5V
55
3
fST
Frequency Stabilization
Assumes full supply voltage reached within 1 ms
ms
from Power-up (cold start) from power-up. Short cycles exist prior to fre-
quency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
25
Ω
Note:
9. PCI clock is CPU/4 for CPU = 133 MHz and CPU/3 for CPU = 100 MHz.
Document #: 38-07162 Rev. **
Page 6 of 10
PRELIMINARY
W161
2.5V AC Electrical Characteristics
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2= 2.5V±5%
fXTL = 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.[10]
CPU Clock Outputs, CPU0:2 (Lump Capacitance Test Load = 20 pF)
CPU = 133 MHz
CPU = 100 MHz
Parameter
Description
Period
Test Condition/Comments
Measured on rising edge at 1.25V
Duration of clock cycle above 2.0V
Duration of clock cycle below 0.4V
Min. Typ. Max. Min. Typ. Max. Unit
tP
tH
tL
7.5
1.87
1.67
1
7.65
10
3.0
2.8
1
10.2
ns
ns
High Time
Low Time
ns
tR
tF
tD
Output Rise Edge Rate Measured from 0.4V to 2.0V
Output Fall Edge Rate Measured from 2.0V to 0.4V
4
4
4
4
V/ns
V/ns
%
1
1
Duty Cycle
Measured on rising and falling edge at
45
55
45
55
1.25V
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.25V. Max-
imum difference of cycle time between
two adjacent cycles.
250
250
ps
tSK
fST
Output Skew
Measured on rising edge at 1.25V
175
3
175
3
ps
Frequency Stabiliza-
tion from Power-up
(cold start)
Assumes full supply voltage reached
within 1ms from power-up. Short cycles
exist prior to frequency stabilization.
ms
CPUdiv2 Clock Outputs, CPUdiv2 (Lump Capacitance Test Load = 20 pF)
CPU = 133 MHz
CPU = 100 MHz
Parameter
Description
Period
Test Condition/Comments
Measured on rising edge at 1.25V
Duration of clock cycle above 2.0V
Duration of clock cycle below 0.4V
Min. Typ. Max. Min. Typ. Max. Unit
tP
tH
tL
15
5.25
5.05
1
15.3
20
7.5
7.3
1
20.4
ns
ns
High Time
Low Time
ns
tR
tF
tD
Output Rise Edge Rate Measured from 0.4V to 2.0V
Output Fall Edge Rate Measured from 2.0V to 0.4V
4
4
4
4
V/ns
V/ns
%
1
1
Duty Cycle
Measured on rising and falling edge at
45
55
45
55
1.25V
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.25V. Max-
imum difference of cycle time between
two adjacent cycles.
250
250
ps
tSK
fST
Output Skew
Measured on rising edge at 1.25V
175
3
175
3
ps
Frequency Stabiliza-
tion from Power-up
(cold start)
Assumes full supply voltage reached
within1msfrompower-up.Shortcycles
exist prior to frequency stabilization.
ms
Zo
AC Output Impedance Average value during switching transi-
tion. Used for determining series termi-
nation value.
20
20
Ω
Note:
10. Period, Jitter, offset. and skew measured on rising edge at 1.25V.
Document #: 38-07162 Rev. **
Page 7 of 10
PRELIMINARY
W161
IOAPIC Clock Output, IOAPIC (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Frequency
Test Condition/Comments
Min
Typ
Max
Unit
MHz
V/ns
V/ns
%
f
Note 11
16.67
tR
tF
tD
fST
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Measured from 0.4V to 2.0V
1
1
4
4
Measured from 2.0V to 0.4V
Measured on rising and falling edge at 1.25V
45
55
3
Frequency Stabilization
Assumes full supply voltage reached within
ms
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Averagevalueduringswitchingtransition.Used
for determining series termination value.
20
Ω
Note:
11. IOAPIC clock is CPU/8 for CPU = 133 MHz and CPU/6 for CPU = 100 MHz.
Ordering Information
Package
Ordering Code
W161
Name
Package Type
H
48-pin SSOP (300 mils)
Document #: 38-07162 Rev. **
Page 8 of 10
PRELIMINARY
W161
Package Diagram
48-Pin Small Shrink Outline Package (SSOP, 300 mils)
Summary of nominal dimensions in inches:
Body Width: 0.296
Lead Pitch: 0.025
Body Length: 0.625
Body Height: 0.102
Document #: 38-07162 Rev. **
Page 9 of 10
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
W161
Document Title: W161 133-MHz Spread Spectrum FTG for Pentium® II Platforms
Document Number: 38-07162
Issue
ECN NO. Date
Orig. of
Change
REV.
Description of Change
**
110272
10/28/01
SZV
Change from Spec number: 38-00817 to 38-07162
Document #: 38-07162 Rev. **
Page 10 of 10
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