W163 [CYPRESS]
Spread Aware⑩, Zero Delay Buffer; 流传意识到™ ，零延迟缓冲器
| 型号： | W163 |
| 厂家： | 
CYPRESS |
| 描述： | Spread Aware⑩, Zero Delay Buffer |
| 文件： | 总4页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W163
Spread Aware™, Zero Delay Buffer
Features
Key Specifications
• Spread Aware™—designed to work with SSFTG
reference signals
• Outputs may be three-stated
• Available in 8-pin SOIC package
• Extra strength output drive available (-15 version)
Operating Voltage: ................................................3.3V±10%
Operating Range: ................................ 10 < f
< 133 MHz
OUT
Cycle-to-Cycle Jitter: ..................................................200 ps
Output-to-Output Skew: ..............................................250 ps
Device-to-Device Skew:...............................................700 ps
Propagation Delay:......................................................350 ps
• Internal feedback maximized the number of outputs
available in 8-pin package
Block Diagram
Pin Configuration
SOIC
REF
Q0
1
2
3
4
8
7
6
5
QFB
Q3
REF
PLL
QFB
Q0
VDD
Q2
Q1
GND
Q1
Q2
Q3
Spread Aware is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
February 21, 2000, rev. *A
W163
Pin Definitions
Pin
Type
Pin Name
Pin No.
Pin Description
REF
1
I
Reference Input: The output signals Q0:3 will be synchronized to this signal
unless the device is programmed to bypass the PLL.
Q0:3
QFB
VDD
GND
2, 3, 5, 7
O
O
P
P
Outputs: These signals will be synchronous and of equal frequency to the signal
input at pin 1.
8
6
4
Feedback Output: This output signal does not vary from signals Q0:3 in function,
but is noted as the signal used to establish the propagation delay of nearly 0.
Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise
for optimal jitter performance.
Ground Connections: Connect all grounds to the common system ground
plane.
the result is a significant amount of tracking skew which may
cause problems in systems requiring synchronization.
Overview
The W163 products are five-output zero delay buffers. A
Phase-Locked Loop (PLL) is used to take a time-varying signal
and provide five copies of that same signal out. The internal
feedback to the PLL provides outputs in phase with the refer-
ence inputs.
For more details on Spread Spectrum timing technology,
please see the Cypress Application note titled, “EMI Suppres-
sion Techniques with Spread Spectrum Frequency Timing
Generator (SSFTG) ICs.”
Schematic
QFB
Q3
REF
Q0
Ferrite
Bead
Spread Aware
VDD
V
Q1
GND
DD
Many systems being designed now utilize a technology called
Spread Spectrum Frequency Timing Generation. Cypress has
been one of the pioneers of SSFTG development, and we de-
signed this product so as not to filter off the Spread Spectrum
feature of the Reference input, assuming it exists. When a zero
delay buffer is not designed to pass the SS feature through,
0.1
F 10 F
µ µ
Q2
2
W163
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
only. Operation of the device at these or any other conditions
.
Parameter
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
–0.5 to +7.0
–65 to +150
0 to +70
Unit
V
V
, V
DD IN
T
°C
°C
°C
W
STG
T
Operating Temperature
A
T
Ambient Temperature under Bias
Power Dissipation
–55 to +125
0.5
B
P
D
: T =0°C to 70°C, V = 3.3V ±10%
DC Electrical Characteristics
A
DD
Parameter
Description
Supply Current
Test Condition
Min
Typ
Max
Unit
mA
V
I
Unloaded, 100 MHz
40
DD
V
Input Low Voltage
Input High Voltage
Output Low Voltage
0.8
IL
V
V
2.0
2.4
V
IH
OL
I
I
= 12 mA (-15)
= 8 mA (-5)
0.4
V
OL
OL
V
Output High Voltage
I
I
= 12 mA (-15)
= 8 mA (-5)
V
OH
OL
OL
I
I
Input Low Current
Input High Current
V
V
= 0V
50
µA
µA
IL
IN
IN
= V
100
IH
DD
AC Electrical Characteristics: T = 0°C to +70°C, V = 3.3V ±10%
A
DD
Parameter
Description
Input Frequency
Test Condition
Min
10
Typ
Max
133
133
2.5
1.5
2.5
1.5
?
Unit
f
MHz
MHz
ns
IN
[5]
f
t
Output Frequency
15-pF load
10
OUT
R
[1]
Output Rise Time (-05)
Output Rise Time (-15)
2.0 to 0.8V, 15-pF load
2.0 to 0.8V, 20-pF load
2.0 to 0.8V, 15-pF load
2.0 to 0.8V, 20-pF load
[1]
ns
[1]
t
Output Fall Time (-05)
Output Rise Time (-15)
ns
F
[1]
ns
[1]
t
t
t
t
t
Input Clock Rise Time
ns
ICLKR
ICLKF
PD
[1]
Input Clock Fall Time
?
ns
[2, 3]
FBIN to REF Skew
Measured at V /2
–350
–250
–700
0
0
0
350
250
700
ps
DD
Output to Output Skew
Device to Device Skew
All outputs loaded equally
Measured at FBIN pins,
ps
SK
ps
SKDD
V
/2
DD
[4]
t
t
t
Duty Cycle
15-pF load
Power supply stable and
45
50
55
1.0
200
%
ms
ps
D
PLL Lock Time
Jitter, Cycle-to-Cycle
LOCK
JC
Notes:
1. Longer input rise and fall time will degrade skew and jitter performance.
2. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V.
3. Skew is measured at 1.4V on rising edges.
4. Duty cycle is measured at 1.4V.
5. For the higher drive -15, the load is 20 pF.
3
W163
Ordering Information
Package
Name
Ordering Code
Option
Package Type
W163
-05, -15
G
8-pin Plastic SOIC (150-mil)
Document #: 38-00787-*A
Package Diagram
8-Pin Small Outline Integrated Circuit (SOIC, 150-mil)
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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