W162-09H [CYPRESS]

PLL Based Clock Driver, W162 Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, SSOP-16;


型号：	W162-09H
厂家：	CYPRESS
描述：	PLL Based Clock Driver, W162 Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, SSOP-16 驱动光电二极管逻辑集成电路
文件：	总7页 (文件大小：130K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W162

Spread Aware™, Zero Delay Buffer

Features

Table 1. Input Logic

• Spread Aware™—designed to work with SSFTG

reference signals

SEL1 SEL0

QA0:3

QB0:3

PLL

QFB

Three-

State

Three-

State

Shutdown Active

• Two banks of four outputs, plus the fed back output

• Outputs may be three-stated

• Available in 16-pin SOIC or SSOP package

• Extra strength output drive available (-19 version)

• Internal feedback

Active

Three-

State

Active,

Utilized

Active

Shutdown, Active

Bypassed

Key Specifications

Active

Active,

Utilized

Active

Operating Voltage: ............................................... 3.3V±10%

Operating Range: ................................15 < f_OUT< 133 MHz

Cycle-to-Cycle Jitter: .................................................. 250 ps

Output to Output Skew: ............................................. 150 ps

Propagation Delay: ..................................................... 150 ps

Block Diagram

Pin Configuration

QFB

REF

QA0

QA1

VDD

GND

QB0

QB1

SEL1

QFB

QA3

QA2

VDD

GND

QB3

QB2

SEL0

REF

PLL

MUX

QA0

QA1

QA2

SEL0

SEL1

QA3

QB0

QB1

QB2

QB3

Spread Aware is a trademark of Cypress Semiconductor Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07150 Rev. **

Revised November 14, 2001

W162

Pin Definitions

Type

Pin Name

Pin No.

Pin Description

REF

Reference Input: The output signals QA0:3 through QB0:3 will be synchro-

nized to this signal unless the device is programmed to bypass the PLL.

QFB

2, 3, 14, 15

6, 7, 10, 11

4, 13

Feedback Output: This signal is used as the feedback internally to establish

the propagation delay of nearly 0.

QA0:3

QB0:3

VDD

Outputs from Bank A: The frequency of the signals provided by these pins

is equal to the signal connected to REF.

Outputs from Bank B: The frequency of the signals provided by these pins

is equal to the signal connected to REF.

Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise

for optimal jitter performance.

GND

5, 12

Ground Connections: Connect all grounds to the common system ground

plane.

SEL0:1

9, 8

Function Select Inputs: Tie to V_DD(HIGH, 1) or GND (LOW, 0) as desired

per Table 1.

For more details on Spread Spectrum timing technology,

please see the Cypress Application note titled, “EMI Suppres-

Overview

The W162 products are nine-output zero delay buffers. A

Phase-Locked Loop (PLL) is used to take a time-varying signal

and provide eight copies of that same signal out.

sion Techniques with Spread Spectrum Frequency Timing

Generator (SSFTG) ICs.”

Functional Description

Internal feedback is used to maximize the number of output

signals provided in the 16-pin package.

Logic inputs provide the user the ability to turn off one or both

banks of clocks when not in use, as described in Table 1. Dis-

abling a bank of unused outputs will reduce jitter and power

consumption, and will also reduce the amount of EMI generat-

ed by the W162.

Spread Aware

Many systems being designed now utilize a technology called

Spread Spectrum Frequency Timing Generation. Cypress has

been one of the pioneers of SSFTG development, and we de-

signed this product so as not to filter off the Spread Spectrum

feature of the Reference input, assuming it exists. When a zero

delay buffer is not designed to pass the SS feature through,

the result is a significant amount of tracking skew which may

cause problems in systems requiring synchronization.

These same inputs allow the user to bypass the PLL entirely if

so desired. When this is done, the device no longer acts as a

zero delay buffer, it simply reverts to a standard nine-output

clock driver.

Document #: 38-07150 Rev. **

Page 2 of 7

W162

Absolute Maximum Ratings

Stresses greater than those listed in this table may cause per-

manent damage to the device. These represent a stress rating

above those specified in the operating sections of this specifi-

cation is not implied. Maximum conditions for extended peri-

ods may affect reliability

only. Operation of the device at these or any other conditions

Parameter

V_DD, V_IN

Description

Voltage on any pin with respect to GND

Storage Temperature

Rating

–0.5 to +7.0

–65 to +150

0 to +70

Unit

T_STG

T_A

°C

Operating Temperature

T_B

Ambient Temperature under Bias

Power Dissipation

–55 to +125

0.5

P_D

DC Electrical Characteristics: T_A=0°C to 70°C, V_DD= 3.3V ±10%

Parameter

I_DD

Description

Supply Current

Test Condition

Unloaded, 100 MHz

Min

Typ

Max

Unit

V_IL

Input Low Voltage

Input High Voltage

Output Low Voltage

0.8

V_IH

2.0

V_OL

I_OL= 12 mA (-19)

I_OL= 8 mA (-9)

0.4

V_OH

Output High Voltage

I_OL= 12 mA (-19)

2.4

_OL= 8 mA (-9)

I_IL

Input Low Current

Input High Current

V_IN= 0V

–500

µA

I_IH

V_IN= V_DD

AC Electrical Characteristics: T_A= 0°C to +70°C, V_DD= 3.3V ±10%

Parameter

Description

Input Frequency

Test Condition

Min

Typ

Max

133

2.5

Unit

f_IN

MHz

f_OUT

t_R

Output Frequency

15-pF load^[5]

Output Rise Time (-09)^[1]

Output Rise Time (-19)^[1]

Output Fall Time (-09)^[1]

Output Rise Time (-19)^[1]

FBIN to REF Skew^{[2, 3]}

Output to Output Skew

Duty Cycle

2.0 to 0.8V, 15-pF load

2.0 to 0.8V, 20-pF load

2.0 to 0.8V, 15-pF load

2.0 to 0.8V, 20-pF load

Measured at V_DD/2

1.5

t_F

2.5

1.5

t_PD

t_SK

150

All outputs loaded equally

15-pF load^[4]

t_D

t_LOCK

PLL Lock Time

Power supply stable

1.0

t_JC

Jitter, Cycle-to-Cycle

250

Notes:

1. Long input rise and fall time will degrade skew and jitter performance.

2. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V.

3. Skew is measured at V_DD/2 on rising edges.

4. Duty cycle is measured at V_DD/2

5. For the higher drive -19, the load is 20 pF.

Document #: 38-07150 Rev. **

Page 3 of 7

W162

Schematic

Ref In

Output

Power

Ground

Output

Logic In

Output

Power

Ferrite

Bead

Ferrite

Bead

V_DD

0.1µF10µF

10µF 0.1µF

Ground

Output

Logic In

V_DDor GND (for desired operation mode)

Ordering Information

Package

Name

Ordering Code

W162

Option

Package Type

-09, -19

16-pin Plastic SOIC (150-mil)

16-pin Plastic SSOP (150-mil)

Document #: 38-07150 Rev. **

Page 4 of 7

W162

Package Diagrams

16-pin SSOP Small Shrunk Outline Package (SSOP, 150-mil)

Document #: 38-07150 Rev. **

Page 5 of 7

W162

Package Diagrams (continued)

16-Pin Small Outlined Integrated Circuit (SOIC, 150-mil)

Document #: 38-07150 Rev. **

Page 6 of 7

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

W162

Document Title: W162 Spread Aware™. Zero Delay Buffer

Document Number: 38-07150

Issue

Date

Orig. of

Change

REV.

ECN NO.

Description of Change

110590

12/19/01

DSG

Change from Spec number: 38-00788 to 38-07150

Document #: 38-07150 Rev. **

Page 7 of 7

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