W181-53GI [CYPRESS]
Clock Generator, 75MHz, CMOS, PDSO8, 0.150 INCH, PLASTIC, SOIC-8;
| 型号： | W181-53GI |
| 厂家： | 
CYPRESS |
| 描述： | Clock Generator, 75MHz, CMOS, PDSO8, 0.150 INCH, PLASTIC, SOIC-8 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总9页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W181I
Peak Reducing EMI Solution
Features
Table 1. Modulation Width Selection
• Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the out-
put
• Selectable input to output frequency
• Single 1.25% or 3.75% down or center spread output
• Integrated loop filter components
• Operates with a 3.3V or 5V supply
• Low power CMOS design
W181I-01, 02, 03
Output
W181I-51, 52, 53
Output
SS%
0
Fin ≥ Fout ≥ Fin
–
Fin + 0.625% ≥ Fin≥
– 0.625%
1.25%
1
Fin ≥ Fout ≥ Fin
–
Fin + 1.875% ≥ Fin≥
–1.875%
3.75%
Table 2. Frequency Range Selection
W181I Option#
-02, 52
• Available in 8-pin SOIC (Small Outline Integrated
Circuit)
Key Specifications
-01, 51
(MHz)
-03, 53
(MHz)
FS2 FS1
(MHz)
Supply Voltages:...........................................VDD = 3.3V±5%
or VDD = 5V±10%
0
0
1
1
0
1
0
1
28 ≤ FIN ≤ 36 28 ≤ FIN ≤ 36
36 ≤ FIN ≤ 48 36 ≤ FIN ≤ 48
N/A
N/A
Frequency Range: ............................ 28 MHz ≤ Fin ≤ 75 MHz
Crystal Reference Range.................. 28 MHz ≤ Fin ≤ 40 MHz
Cycle to Cycle Jitter: ....................................... 300 ps (max.)
Selectable Spread Percentage:....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: .................................. 5 ns (max.)
46 ≤ FIN ≤ 57
57 ≤ FIN ≤ 75
N/A
N/A
46 ≤ FIN ≤ 57
57 ≤ FIN ≤ 75
Simplified Block Diagram
Pin Configurations
3.3 or 5.0V
SOIC
CLKIN or X1
NC or X2
GND
FS2
1
2
3
4
8
7
6
5
FS1
X1
VDD
XTAL
SS%
CLKOUT
Input
X2
Spread Spectrum
Output
(EMI suppressed)
W181I
40 MHz
Max.
CLKIN or X1
NC or X2
SSON#
FS1
1
2
8
7
GND
SS%
VDD
3
4
6
5
CLKOUT
3.3 or 5.0V
Oscillator or
Reference Input
Spread Spectrum
W181I
Output
(EMI suppressed)
PREMIS is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
Document #: 38-07115 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised September 12, 2001
W181I
Pin Definitions
Pin No.
(SOIC)
Pin
Type
Pin Name
Pin Description
CLKOUT
5
O
I
Output Modulated Frequency: Frequency modulated copy of the un-
modulated input clock (SSON# asserted).
CLKIN or X1
1
Crystal Connection or External Reference Frequency Input: This
pin has dual functions. It may either be connected to an external crystal,
or to an external reference clock.
NC or X2
SSON#
2
I
I
Crystal Connection: If using an external reference, this pin must be left
unconnected.
8(02/03/52/53
)
Spread Spectrum Control (Active LOW): Asserting this signal (active
LOW) turns the internal modulation waveform on. This pin has an inter-
nal pull-down resistor.
FS1:2
SS%
7, 8 (01/51)
4
I
I
Frequency Selection Bit(s) 1 and 2: These pins select the frequency
range of operation. Refer to Table 2. These pins have internal pull-up
resistors.
ModulationWidthSelection:WhenSpreadSpectrumfeatureis turned
on, this pin is used to select the amount of variation and peak EMI
reduction that is desired on the output signal. This pin has an internal
pull-up resistor.
VDD
GND
6
3
P
Power Connection: Connected to 3.3V or 5V power supply.
G
Ground Connection: Connect all ground pins to the common system
ground plane.
Document #: 38-07115 Rev. **
Page 2 of 9
W181I
times the reference frequency. (Note: For the W181I the output
frequency is equal to the input frequency.) The unique feature
of the Spread Spectrum Frequency Timing Generator is that a
modulating waveform is superimposed at the input to the VCO.
This causes the VCO output to be slowly swept across a pre-
determined frequency band.
Overview
The W181I products are one series of devices in the Cypress
PREMIS family. The PREMIS family incorporates the latest
advances in PLL spread spectrum frequency synthesizer tech-
niques. By frequency modulating the output with a low-
frequency carrier, peak EMI is greatly reduced. Use of this
technology allows systems to pass increasingly difficult EMI
testing without resorting to costly shielding or redesign.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro-
cess has little impact on system performance.
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The Sim-
plified Block Diagram on page 1 shows a simple implementa-
tion.
Frequency Selection With SSFTG
In Spread Spectrum Frequency Timing Generation, EMI re-
duction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be varied.
Functional Description
Using frequency select bits (FS1:2 pins), the frequency range
can be set. Spreading percentage is set to be 1.25% or 3.75%
(see Table 1).
The W181I uses a Phase-Locked Loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. The
input reference signal is divided by Q and fed to the phase
detector. A signal from the VCO is divided by P and fed back
to the phase detector also. The PLL will force the frequency of
the VCO output signal to change until the divided output signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q
A larger spreading percentage improves EMI reduction. How-
ever, large spread percentages may either exceed system
maximum frequency ratings or lower the average frequency to
a point where performance is affected. For these reasons,
spreading percentages between 0.5% and 2.5% are most
common.
VDD
Clock Input
CLKOUT
Freq.
Divider
Q
Phase
Detector
Charge
Pump
Post
Dividers
Reference Input
(EMI suppressed)
Σ
VCO
Modulating
Waveform
Feedback
Divider
P
PLL
GND
Figure 1. Functional Block Diagram
Document #: 38-07115 Rev. **
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W181I
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
Spread Spectrum Frequency Timing Genera-
tion
The output clock is modulated with a waveform depicted in
Figure 3. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. Figure
3 details the Cypress spreading pattern. Cypress does offer
options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 2.
As shown in Figure 2, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log10(P) + 9*log10(F)
EMI Reduction
SSFTG
Typical Clock
Spread
Spectrum
Enabled
Non-
Spread
Spectrum
Frequency Span (MHz)
Down Spread
Frequency Span (MHz)
Center Spread
Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX.
MIN.
Figure 3. Typical Modulation Profile
Document #: 38-07115 Rev. **
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W181I
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Parameter
VDD, VIN
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
–0.5 to +7.0
–65 to +150
–40 to +85
–55 to +125
0.5
Unit
V
TSTG
TA
°C
°C
°C
W
Operating Temperature
TB
Ambient Temperature under Bias
Power Dissipation
PD
DC Electrical Characteristics: –40°C < TA < +85°C, VDD = 3.3V ±5%
Parameter
IDD
Description
Supply Current
Test Condition
Min.
Typ.
Max.
Unit
mA
ms
18
32
5
tON
Power-Up Time
First locked clock cycle after Power
Good
VIL
VIH
VOL
VOH
IIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
Output Low Current
Output High Current
Input Capacitance
Input Capacitance
Input Pull-Up Resistor
Clock Output Impedance
0.8
0.4
V
V
2.4
2.4
V
V
Note 1
–100
µA
µA
mA
mA
pF
pF
kΩ
Ω
IIH
Note 1
10
IOL
IOH
CI
@ 0.4V, VDD = 3.3V
@ 2.4V, VDD = 3.3V
All pins except CLKIN
CLKIN pin only
15
15
7
CI
6
10
RP
500
25
ZOUT
Note:
1. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor.
Document #: 38-07115 Rev. **
Page 5 of 9
W181I
DC Electrical Characteristics: –40°C < TA < +85°C, VDD = 5V ±10%
Parameter
IDD
Description
Supply Current
Test Condition
Min.
Typ.
Max.
50
Unit
mA
ms
30
tON
Power-Up Time
First locked clock cycle after
Power Good
5
VIL
VIH
VOL
VOH
IIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
Output Low Current
Output High Current
Input Capacitance
Input Capacitance
Input Pull-Up Resistor
Clock Output Impedance
0.15VDD
0.4
V
V
0.7VDD
2.4
V
V
Note 1
–100
µA
µA
mA
mA
pF
pF
kΩ
Ω
IIH
Note 1
10
IOL
IOH
CI
@ 0.4V, VDD = 5V
@ 2.4V, VDD = 5V
All pins except CLKIN
CLKIN pin only
24
24
7
CI
6
10
RP
500
25
ZOUT
AC Electrical Characteristics: TA = –40°C < TA < +85°C, VDD = 3.3V ±5% or 5V±10%
Parameter
fIN
fOUT
tR
Description
Input Frequency
Test Condition
Input Clock
Min.
28
Typ.
Max.
Unit
MHz
MHz
ns
75
75
5
Output Frequency
Output Rise Time
Output Fall Time
Output Duty Cycle
Input Duty Cycle
Jitter, Cycle-to-Cycle
Harmonic Reduction
Spread Off
28
VDD, 15-pF load 0.8V–2.4V
VDD, 15-pF load 2.4V–0.8V
15-pF load
2
2
tF
5
ns
tOD
tID
40
40
60
60
300
%
%
tJCYC
250
ps
fout = 40 MHz, third harmonic
measured, reference board,
15-pF load
8
dB
Document #: 38-07115 Rev. **
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W181I
creased trace inductance will negate its decoupling capability.
The 10-µF decoupling capacitor shown should be a tantalum
type. For further EMI protection, the VDD connection can be
made via a ferrite bead, as shown.
Application Information
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in Figure 4 should be used.
Recommended Board Layout
VDD decoupling is important to both reduce phase jitter and
EMI radiation. The 0.1-µF decoupling capacitor should be
placed as close to the VDD pin as possible, otherwise the in-
Figure 5 shows a recommended 2-layer board layout.
Reference Input
1
2
3
4
8
7
6
5
NC
GND
Clock
Output
R1
C1
µF
0.1
3.3 or 5V System Supply
FB
C2
10
µF Tantalum
Figure 4. Recommended Circuit Configuration
C1 =
C2 =
High frequency supply decoupling
µF recommended).
capacitor (0.1-
Common supply low frequency
µF tantalum
decoupling capacitor (10-
recommended).
R1 =
Match value to line impedance
Ferrite Bead
FB
=
G
Via To GND Plane
=
Reference Input
NC
C1
G
G
Clock Output
R1
G
C2
Power Supply Input
FB
(3.3 or 5V)
Figure 5. Recommended Board Layout (2-Layer Board)
Ordering Information
Freq. Mask
Package
Name
Ordering Code
Code
Package Type
Temperature Range
W181I
01, 02, 03
51, 52, 53
G
8-pin Plastic SOIC (150-mil) I = Industrial (-40°C to +85°C)
Document #: 38-07115 Rev. **
Page 7 of 9
W181I
Package Diagram
8-Pin Small Outline Integrated Circuit (SOIC, 150 mils)
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
W181I
Document Title: W181I Peak Reducing EMI Solution
Document Number: 38-07115
REV.
ECN NO.
Issue Date
Orig. of Change
Description of Change
**
108762
09/14/01
IKA
New spec.
Document #: 38-07115 Rev. **
Page 9 of 9
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