W218H [CYPRESS]
Processor Specific Clock Generator, 133MHz, CMOS, PDSO56, 0.300 INCH, SSOP-56;
| 型号： | W218H |
| 厂家： | 
CYPRESS |
| 描述： | Processor Specific Clock Generator, 133MHz, CMOS, PDSO56, 0.300 INCH, SSOP-56 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总17页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W218
FTG for Integrated Core Logic with 133-MHz FSB
CPU, 3V66 Output Skew:............................................175 ps
Features
PCI Output Skew:........................................................500 ps
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Three copies of CPU clock at 66/100/133 MHz
• Nine copies of 100-MHz SDRAM clocks
• Seven copies of PCI clock
CPU to SDRAM Skew (@ 133 MHz):.........................±0.5 ns
CPU to SDRAM Skew (@ 100 MHz):.................4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz): .......................7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead):..........................1.5 to 3.5 ns
PCI to APIC Skew: .....................................................±0.5 ns
• Two copies of APIC clock at 33 MHz, synchronous to
CPU clock
• Two copies of 48-MHz clock (non-spread spectrum) op-
timized for USB reference input and video dot clock
Table 1. Pin Selectable Functions
• Three copies of 3V 66-MHz fixed clock
• One copy of 14.31818-MHz reference clock
• Power down control
Tristate# FSEL0 FSEL1
CPU
SDRAM
0
0
1
1
1
1
0
1
0
1
0
1
x
x
0
0
1
1
Three-state Three-state
Test
Test
• SMBus interface for turning off unused clocks
66 MHz
100 MHz
133 MHz
133 MHz
100 MHz
100 MHz
133 MHz
100 MHz
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter:.............. 250 ps
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter:................................................... 500 ps
APIC, SDRAM Output Skew:...................................... 250 ps
Pin Configuration[1]
Block Diagram
VDDQ3
*REF0/FSEL1
VDDQ3
X1
1
56
GND
2
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
APIC0
APIC1
VDDQ2
CPU0
VDDQ2
CPU1
3
REF0/FSEL1
X1
X2
XTAL
OSC
X2
4
GND
GND
5
PLL REF FREQ
6
7
8
9
VDDQ2
CPU0:1
3V66_0
3V66_1
3V66_AGP
VDDQ3
VDDQ3
PCI0_ICH
PCI1
CPU2_ITP
Divider,
Delay,
and
Phase
Control
Logic
GND
I2C
Logic
2
SDATA
SCLK
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
CPU2_ITP
APIC0:1
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
2
2
GND
PCI2
VDDQ3
FSEL0:1
VDDA
PCI3
PLL 1
3V66_0:1
3V66_AGP
PCI0_ICH
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
GND
PCI4
PCI5
PCI6
VDDQ3
VDDA
GNDA
GND
USB
DOT
VDDQ3
FSEL0
PCI1:6
Tristate#
7
8
DCLK
VDDQ3
PWR_DWN#
SCLK
DCLK
25
26
27
28
PWR_DWN#
SDRAM0:7
SDATA
Tristate#
Note:
VDDQ3
VDDA
1. Internal pull-down resistors present on input marked with *.
Design should not solely rely on internal pull-down resister to
set I/O pin LOW.
USB
PLL2
DOT
Intel is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07221 Rev. *A
Revised December 21, 2002
W218
Pin Definitions
Pin
Type
Pin Name
Pin No.
Pin Description
REF0/FSEL1
1
I/O
I
Reference Clock: 3.3V 14.318-MHz clock output. This pin also serves as a strap
option for CPU frequency selection. See Table 1 for detailed descriptions.
X1
X2
3
4
Crystal Input: This pin has dual functions. It can be used as an external
14.318-MHz crystal connection or as an external reference frequency input.
O
O
O
Crystal Output: A connection for an external 14.318-MHz crystal. If using an ex-
ternal reference, this pin must be left unconnected.
PCI0_ICH,
PCI1:6
12, 13, 15, 16,
18, 19, 20
PCI Clock 0 through 6: 3.3V 33-MHz PCI clock outputs. PCI1:7 can be individually
turned off via SMBus interface.
3V66_0:1/
3V66_AGP
7, 8, 9
66-MHz Clock Output: 3.3V fixed 66-MHz clock.
USB
DOT
25
26
O
O
I
USB Clock Output: 3.3V fixed 48-MHz, non-spread spectrum USB clock output.
Dot Clock Output: 3.3V 48-MHz, non-spread spectrum signal.
FSEL0,
Tristate#
28, 29
Clock Function Selection pins: LVTTL-compatible input to select device func-
tions. See Table 1 for detailed descriptions.
PWR_DWN#
32
I
Power-Down Control: LVTTL-compatible asynchronous input that places the de-
vice in power-down mode when held LOW. This input can be used as the
VTT_PWRGD input to support Intel VRM 8.5 implementation.
CPU2_ITP,
CPU0:1
49,52,50
O
O
O
CPU Clock Outputs: Clock outputs for the host bus interface and integrated test
port. Output frequencies run at 66 MHz, 100 MHz, or 133 MHz depending on the
configuration of SEL0:1 and SEL133. Voltage swing set by VDDQ2
.
SDRAM0:7,
DCLK
46, 45, 43, 42,
40, 39, 37, 36,
34
SDRAM Clock Outputs: 3.3V outputs running at 100 MHz. SDRAM0:7 can be
individually turned off via SMBus interface.
APIC0:1
55, 54
Synchronous APIC Clock Outputs: Clock outputs running synchronous with the
PCI clock outputs (33 MHz). Voltage swing set by VDDQ2
.
SDATA
SCLK
30
31
I/O
I
Data pin for SMBus circuitry.
Clock pin for SMBus circuitry.
VDDQ3
2, 10, 11, 21, 27,
33, 38, 44
P
3.3V Power Connection: Power supply for SDRAM output buffers, PCI output
buffers, 3V66 output buffers, reference output buffers, and 48-MHz output buffers.
Connect to 3.3V.
VDDA
VDDQ2
GND
22
P
P
G
3.3V Power Connection: Power supply for core logic, PLL circuitry. Connect to
3.3V.
51, 53
2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Con-
nect to 2.5V or 3.3V.
5, 6, 14, 17, 24,
35, 41, 47, 48,
56
Ground Connections: Connect all ground pins to the common system ground
plane.
GNDA
23
G
Ground Connections: Ground for core logic, PLL circuitry.
Document #: 38-07221 Rev. *A
Page 2 of 17
W218
V
DD
Output Strapping Resistor
Series Termination Resistor
10 k
Ω
(Load Option 1)
Clock Load
W218
Output
Buffer
Power-on
Reset
Timer
Hold
Output
Low
Output Three-state
10 k
Ω
(Load Option 0)
Q
D
Data
Latch
Figure 1. Input Logic Selection Through Resistor Load Option
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
is delivered on the pins. If the power supply has not yet
reached full value, output frequency initially may be below tar-
get but will increase to target once supply voltage has stabi-
lized. In either case, a short output clock cycle may be pro-
duced from the CPU clock outputs when the outputs are
enabled.
Overview
The W218 is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel® architec-
ture platform using graphics integrated core logic.
Functional Description
I/O Pin Operation
Pin Selectable Functions
REF0/FSEL1is a dual-purpose l/O pin. Upon power-up the pin
acts as a logic input. If the pin is strapped to a HIGH state
externally, CPU clock outputs will run at 133 MHz. If it is
strapped LOW, CPU clock outputs will be determined by the
status of FSEL input pin. An external 10-kΩ strapping resistor
should be used. Figure 1 shows a suggested method for strap-
ping resistor connections.
Table 1 outlines the device functions selectable through
Threestate#, FSEL0 and FSEL1. Specific outputs available at
each pin are detailed in Table 2 below. The SEL0 pin requires
a 220Ω pull-up resistor to 3.3V for the W218 to sense the max-
imum host bus frequency of the processor and configure itself
accordingly. Also note that FSEL0, Threestate# input levels
should be stable within 500 µs of the later of VDDQ3, VDDQ2
,
PWR_DWN# rising edge.
Table 2. CK Whitney Truth Table
Notes
2
Tristate#
FSEL0
FSEL1
CPU
Hi-Z
SDRAM
Hi-Z
3V66
PCI
48 MHz
Hi-Z
REF
Hi-Z
APIC
Hi-Z
0
0
1
1
1
1
0
1
0
1
0
1
X
X
0
0
1
1
Hi-Z
Hi-Z
TCLK/4
66 MHz
TCLK/4
TCLK/6 TCLK/12
TCLK/2
TCLK
TCLK/12
4, 5
100 MHz 66 MHz
33 MHz
33 MHz
33 MHz
33 MHz
48 MHz 14.318 MHz 33 MHz
48 MHz 14.318 MHz 33 MHz
48 MHz 14.318 MHz 33 MHz
48 MHz 14.318 MHz 33 MHz
3, 6, 7
3, 6, 7
3, 6, 7
3, 6, 7
100 MHz 100 MHz 66 MHz
133 MHz 133 MHz 66 MHz
133 MHz 100 MHz 66 MHz
Notes:
2. Provided for board-level “bed of nails” testing.
3. “Normal” mode of operation.
4. TCLK is a test clock overdriven on the XTAL_IN input during test mode.
5. Required for DC output impedance verification.
6. Range of reference frequency allowed is min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz.
7. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
Document #: 38-07221 Rev. *A
Page 3 of 17
W218
How to use PD# input to support VTT_PWRGD
the start of the PLL, keep all the multiplexed I/O pins as input
and keep all the output inactive. The functionality of PD# will
allow system designer to use this input to support the
VTT_PWRGD output from the VRM 8.5 module. Please refer
to the Figure 2 for power up sequence details.
The PD# input can be used to support the VTT_PWRGD sig-
nal specified in the Intel
VRM 8.5 specification. The
VTT_PWRGD is used to indicated that the frequency select
output pins (BSEL[0:1]) from the CPU are valid and the clock
generator can use them to determine the CPU FSB frequency.
The assertion of PD# input pin during initial power up will delay
3.3V & 2.5V
PD# (connected to
VTT_PWRGD)
PLL & Output
Synchronization
Outputs
Input Latch
(pin 4 & pin21)
1 ms
Figure 2. Power up sequence with PD# (VTT_PWRGD) hold LOW
Document #: 38-07221 Rev. *A
Page 4 of 17
W218
Offsets Among Clock Signal Groups
spectively. It should be noted that when CPU clock is operating
at 100 MHz, CPU clock output is 180 degrees out of phase
with SDRAM clock outputs.
Figure 3 and Figure 4 represent the phase relationship among
the different groups of clock outputs from W218 when it is pro-
viding a 66-MHz CPU clock and a 100-MHz CPU clock, re-
10 ns
20 ns
30 ns
40 ns
0 ns
Cycle Repeat
CPU 66-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 3. Group Offset Waveforms (66-MHz CPU/100-MHZ SDRAM Clock)
0 ns
10 ns
20 ns
30 ns
40 ns
Cycle Repeat
CPU 100-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC 33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 4. Group Offset Waveforms (100-MHz CPU/100-MHZ SDRAM Clock)
Document #: 38-07221 Rev. *A
Page 5 of 17
W218
0 ns
10 ns
20 ns
30 ns
40 ns
Cycle Repeats
CPU 133-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC 33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 5. Group Offset Waveforms (133-MHz CPU/100-MHz SDRAM Clock)
0 ns
10 ns
20 ns
30 ns
40 ns
Cycle Repeat
CPU 100-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC 33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 6. Group Offset Waveforms (133-MHz CPU/133-MHz SDRAM Clock)
Document #: 38-07221 Rev. *A
Page 6 of 17
W218
Power Down Control
W218 provides one PWRDWN# signal to place the device in
low-power mode. In low-power mode, the PLLs are turned off
and all clock outputs are driven LOW.
0 ns
25 ns
50 ns
2
75 ns
Center
1
VCO Internal
CPU 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC 33-MHz
PwrDwn
SDRAM 100-MHz
REF 14.318-MHz
USB 48-MHz
Figure 7. W218 PWRDWN# Timing Diagram[8, 9, 10, 11]
Table 3. W218 Maximum Allowed Current
Max. 2.5V supply consumption
Max. discrete cap loads,
VDDQ2 = 2.625V
Max. 3.3V supply consumption
Max. discrete cap loads
VDDQ3 = 3.465V
W218
Condition
All static inputs = VDDQ3 or VSS
All static inputs = VDDQ3 or VSS
Powerdown Mode
(PWRDWN# = 0)
10 µA
70 mA
100 mA
TBD
10 µA
280 mA
280 mA
TBD
Full Active 66 MHz
FSEL1:0 = 00 (PWRDWN# =1)
Full Active 100 MHz
FSEL1:0 = 01 (PWRDWN# =1)
Full Active 133 MHz
FSEL1:0 = 11 (PWRDWN# =1)
Notes:
8. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU, clocks of interest will be held LOW on the next HIGH-to-LOW transition.
9. PWRDWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W218.
10. The shaded sections on the SDRAM, REF, and USB clocks indicate “Don’t Care” states.
11. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
Document #: 38-07221 Rev. *A
Page 7 of 17
W218
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
Spread Spectrum Frequency Timing
Generation
The output clock is modulated with a waveform depicted in
Figure 9. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin, produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is –0.5% of the selected fre-
quency. Figure 9 details the Cypress spreading pattern.
Cypress does offer options with more spread and greater EMI
reduction. Contact your local Sales representative for details
on these devices.
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 8.
As shown in Figure 8, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
Spread Spectrum clocking is activated or deactivated by se-
lecting the appropriate value for bit 3 in data byte 0 of the I2C
data stream. Refer to page 10 for more details.
dB = 6.5 + 9*log10(P) + 9*log10(F)
EMI Reduction
Spread
Non-
Spread
Spectrum
Spectrum
Enabled
Figure 8. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX.
MIN.
Figure 9. Typical Modulation Profile
Document #: 38-07221 Rev. *A
Page 8 of 17
W218
1 bit
7 bits
1
1
8 bits
1
Start bit
Slave Address
R/W
Ack
Command Code
Ack
Byte Count = N
Ack
1 bit
Data Byte 1
8 bits
Ack
Data Byte 2
8 bits
Ack
1
...
Data Byte N
8 bits
Ack
1
Stop
1
1
Figure 10. An Example of a Block Write[12]
Serial Data Interface
transfer a maximum of 32 data bytes. The slave receiver ad-
dress for W218 is 11010010. Figure 10 shows an example of
a block write.
The W218 features a two-pin, serial data interface that can be
used to configure internal register settings that control partic-
ular device functions.
The command code and the byte count bytes are required as
the first two bytes of any transfer. W218 expects a command
code of 0000 0000. The byte count byte is the number of ad-
ditional bytes required for the transfer, not counting the com-
mand code and byte count bytes. Additionally, the byte count
byte is required to be a minimum of 1 byte and a maximum of
32 bytes to satisfy the above requirement. Table 4 shows an
example of a possible byte count value.
Data Protocol
The clock driver serial protocol accepts only block writes from
the controller. The bytes must be accessed in sequential order
from lowest to highest byte with the ability to stop after any
complete byte has been transferred. Indexed bytes are not
allowed.
A transfer is considered valid after the acknowledge bit corre-
sponding to the byte count is read by the controller. The com-
mand code and byte count bytes are ignored by the W218.
However, these bytes must be included in the data write se-
quence to maintain proper byte allocation.
A block write begins with a slave address and a write condition.
After the command code the core logic issues a byte count
which describes how many more bytes will follow in the mes-
sage. If the host had 20 bytes to send, the first byte would be
the number 20 (14h), followed by the 20 bytes of data. The
byte count may not be 0. A block write command is allowed to
Table 4. Example of Possible Byte Count Value
Byte Count Byte
Notes
MSB
0000
0000
0000
0000
0000
0000
0000
0000
0010
LSB
0000
0001
0010
0011
0100
0101
0110
0111
0000
Not allowed. Must have at least one byte
Data for functional and frequency select register (currently byte 0 in spec)
Reads first two bytes of data (byte 0 then byte 1)
Reads first three bytes (byte 0, 1, 2 in order)
Reads first four bytes (byte 0, 1, 2, 3 in order)
Reads first five bytes (byte 0, 1, 2, 3, 4 in order)[13]
Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)[13]
Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order)
Max. byte count supported = 32
Table 5. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Output Disable
Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
Unused outputs are disabled to reduce EMI and sys-
tem power. Examples are clock outputs to unused
PCI slots.
Spread Spectrum
Enabling
Enables or disables spread spectrum clocking.
For EMI reduction.
(Reserved)
Reservedfunction for future device revision or pro- No user application. Register bit must be written as 0.
duction device testing.
Notes:
12. The acknowledgment bit is returned by the slave/receiver (W218).
13. Data Bytes 3 to 7 are reserved.
Document #: 38-07221 Rev. *A
Page 9 of 17
W218
2. All unused register bits (reserved and N/A) should be writ-
ten to a “0” level.
W218 Serial Configuration Map
1. The serial bits willbereadby theclock driver inthe following
order:
3. All register bits labeled “Initialize to 0" must be written to
zero during initialization. Failure to do so may result in high-
er than normal operating current.
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
4. Only Byte 0, 1 and 2 are defined in W218. Byte 3 to Byte 7
are reserved and must be written to “zero.”
Byte 0: Control Register (1 = Enable, 0 = Disable) [14]
Bit
Pin#
Name
Pin Description
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
Reserved
Reserved
Reserved
Reserved
(Active/Inactive)
-
(Active/Inactive)
-
(Active/Inactive)
-
Spread Spectrum (1 = On/0 = Off) (Disabled/Enabled)
26
25
49
DOT
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
USB
CPU2_ITP
Byte 1: Control Register (1 = Enable, 0 = Disable) [14]
Bit
Pin#
36
37
39
40
42
43
45
46
Name
Pin Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Byte 2: Control Register (1 = Enable, 0 = Disable) [14]
Bit
Pin#
9
Name
Pin Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
3V66_AGP
PCI6
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Reserved
20
19
18
16
15
13
--
PCI5
PCI4
PCI3
PCI2
PCI1
Bit 0
Note:
Reserved
14. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be
configured during the normal modes of operation.
Document #: 38-07221 Rev. *A
Page 10 of 17
W218
Byte 3: Reserved Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Reserved Drive to ’0’
Pin Description
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
Reserved Drive to ’0’
Reserved Drive to ’0’
Reserved Drive to ’0’
Reserved Drive to ’0’
Reserved Drive to ’0’
Reserved Drive to ’0’
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Disabled/Enabled)
-
SDRAM 133-MHz Mode Enable
Default is Disabled = ’0’, Enabled = ’1’
Byte 4: Reserved Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Reserved Drive to ’0’
Pin Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Reserved Drive to ’0’
Reserved Drive to ’0’
Reserved Drive to ’0’
Reserved Drive to ’0’
Reserved Drive to ’0’
Reserved Drive to ’0’
Reserved Drive to ’0’
-
Document #: 38-07221 Rev. *A
Page 11 of 17
W218
DC Electrical Characteristics[15]
Absolute Maximum DC Power Supply
Parameter
Description
Min.
–0.5
–0.5
–0.5
–65
Max.
4.6
Unit
V
VDD3
VDDQ2
VDDQ3
TS
3.3V Core Supply Voltage
2.5V I/O Supply Voltage
3.6
V
3.3V Supply Voltage
Storage Temperature
4.6
V
150
°C
Absolute Maximum DC I/O
Parameter
Description
Min.
–0.5
–0.5
2000
Max.
Unit
V
Vih3
3.3V Input High Voltage
3.3V Input Low Voltage
Input ESD Protection
4.6
Vil3
V
ESD prot.
V
DC Operating Requirements
Parameter
Description
Condition
3.3V±5%
3.3V±5%
2.5V±5%
Min.
Max.
Unit
V
VDD3
3.3V Core Supply Voltage
3.3V I/O Supply Voltage
2.5V I/O Supply Voltage
3.135
3.135
2.375
3.465
3.465
2.625
VDDQ3
V
VDDQ2
V
VDD3 = 3.3V±5%
Vih3
3.3V Input High Voltage
3.3V Input Low Voltage
Input Leakage Current[16]
VDD3
2.0
VSS – 0.3
–5
VDD + 0.3
0.8
V
V
Vil3
Iil
0<Vin<VDD3
+5
µA
VDDQ2 = 2.5V±5%
Voh2
2.5V Output High Voltage
2.5V Output Low Voltage
Ioh=(–1 mA)
2.0
2.4
2.4
V
V
Vol2
Iol=(1 mA)
0.4
0.4
VDDQ3 = 3.3V±5%
Voh3
3.3V Output High Voltage
3.3V Output Low Voltage
Ioh=(–1 mA)
V
V
Vol3
Iol=(1 mA)
VDDQ3 = 3.3V±5%
Vpoh3
PCI Bus Output High Voltage
PCI Bus Output Low Voltage
Ioh=(–1 mA)
V
V
Vpol3
Iol=(1 mA)
0.55
Cin
Input Pin Capacitance
Xtal Pin Capacitance
Output Pin Capacitance
Pin Inductance
5
22.5
6
pF
pF
pF
nH
°C
Cxtal
Cout
Lpin
13.5
0
0
7
Ta
Ambient Temperature
No Airflow
70
Note:
15. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
16. Input Leakage Current does not include inputs with pull-up or pull-down resistors.
Document #: 38-07221 Rev. *A
Page 12 of 17
W218
AC Electrical Characteristics[15]
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2= 2.5V±5%
fXTL = 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.[17]
AC Electrical Characteristics
66.6-MHz Host
100-MHz Host
133-MHz Host
Parameter
TPeriod
THIGH
Description
Host/CPUCLK Period
Min.
15.0
5.2
Max.
15.5
N/A
N/A
1.6
Min.
10.0
3.0
Max.
10.5
N/A
N/A
1.6
Min.
7.5
Max.
8.0
Unit Notes
ns
ns
ns
ns
ns
17
20
Host/CPUCLK High Time
Host/CPUCLK Low Time
Host/CPUCLK Rise Time
Host/CPUCLK Fall Time
1.87
1.67
0.4
N/A
N/A
1.6
TLOW
5.0
2.8
TRISE
0.4
0.4
21
21
TFALL
0.4
1.6
0.4
1.6
0.4
1.6
TPeriod
THIGH
TLOW
TRISE
TFALL
SDRAM CLK Period (100-MHz)
SDRAM CLK High Time (100-MHz)
SDRAM CLK Low Time (100-MHz)
SDRAM CLK Rise Time (100-MHz)
SDRAM CLK Fall Time (100-MHz)
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
ns
ns
ns
ns
ns
17
20
21
21
1.6
1.6
1.6
TPeriod
THIGH
TLOW
TRISE
TFALL
SDRAM CLK Period (133-MHz)
SDRAM CLK High Time (133-MHz)
SDRAM CLK Low Time (133-MHz)
SDRAM CLK Rise Time (133-MHz)
SDRAM CLK Fall Time (133-MHz)
7.5
1.87
1.67
0.4
8.0
N/A
N/A
1.6
1.6
7.5
1.87
1.67
0.4
8.0
N/A
N/A
1.6
7.5
1.87
1.67
0.4
8.0
N/A
N/A
1.6
1.6
ns
ns
ns
ns
ns
17
20
21
21
0.4
0.4
1.6
0.4
TPeriod
THIGH
TLOW
TRISE
TFALL
APIC 33-MHz CLK Period
APIC 33-MHz CLK High Time
APIC 33-MHz CLK Low Time
APIC CLK Rise Time
30.0
12.0
12.0
0.4
N/A
N/A
N/A
1.6
30.0
12.0
12.0
0.4
N/A
N/A
N/A
1.6
30.0
12.0
12.0
0.4
N/A
N/A
N/A
1.6
ns
ns
ns
ns
ns
17
20
21
21
APIC CLK Fall Time
0.4
1.6
0.4
1.6
.04
1.6
TPeriod
THIGH
TLOW
TRISE
TFALL
3V66 CLK Period
15.0
5.25
5.05
0.5
16.0
N/A
N/A
2.0
15.0
5.25
5.05
0.5
16.0
N/A
N/A
2.0
15.0
5.25
5.05
0.5
16.0
N/A
N/A
2.0
ns
ns
ns
ns
ns
17, 19
20
3V66 CLK High Time
3V66 CLK Low Time
3V66 CLK Rise Time
3V66 CLK Fall Time
21
21
0.5
2.0
0.5
2.0
0.5
2.0
TPeriod
THIGH
TLOW
TRISE
PCI CLK Period
30.0
12.0
12.0
0.5
N/A
N/A
N/A
2.0
30.0
12.0
12.0
0.5
N/A
N/A
N/A
2.0
30.0
12.0
12.0
0.5
N/A
N/A
N/A
2.0
ns
ns
ns
ns
ns
17, 18
20
PCI CLK High Time
PCI CLK Low Time
PCI CLK Rise Time
PCI CLK Fall Time
21
21
TFALL
0.5
2.0
0.5
2.0
0.5
2.0
Notes:
17. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.
18.
19.
T
T
HIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
LOW is measured at 0.4V for all outputs.
20. The time specified is measured from when VDDQ3 achieves its nominal operating level (typical condition VDDQ3 = 3.3V) until the frequency output is stable
and operating within specification.
21.
TRISE and TFALL are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA) JEDEC specification for 2.5V outputs, and Vol
=
0.4V and Voh = 2.4V for 3.3V.
Document #: 38-07221 Rev. *A
Page 13 of 17
W218
AC Electrical Characteristics (continued)
66.6-MHz Host
100-MHz Host
133-MHz Host
Parameter
tpZL, tpZH
tpLZ, tpZH
tstable
Description
Min.
1.0
Max.
10.0
10.0
3
Min.
1.0
Max.
10.0
10.0
3
Min.
1.0
Max.
10.0
10.0
3
Unit Notes
Output Enable Delay (All outputs)
Output Disable Delay (All outputs)
All Clock Stabilization from Power-Up
ns
1.0
1.0
1.0
ns
ms 20
Group Skew and Jitter Limits
Skew, Jitter
Output Group
CPU
Pin-Pin Skew Max.
Cycle-Cycle Jitter
250 ps
Duty Cycle
45/55
Nom VDD
2.5V
Measure Point
1.25V
1.5V
175 ps
250 ps
250 ps
250 ps
175 ps
500 ps
N/A
SDRAM
APIC
250 ps
45/55
3.3V
500 ps
45/55
2.5V
1.25V
1.5V
48MHz
3V66
500 ps
45/55
3.3V
500 ps
45/55
3.3V
1.5V
PCI
500 ps
45/55
3.3V
1.5V
REF
1000 ps
45/55
3.3V
1.5V
Test Point
Output
Buffer
Test Load
Clock Output Wave
TPERIOD
Duty Cycle
THIGH
2.0
1.25
2.5V Clocking
Interface
0.4
TLOW
TRISE
TFALL
TPERIOD
Duty Cycle
THIGH
2.4
1.5
0.4
3.3V Clocking
Interface
TLOW
TRISE
TFALL
Figure 11. Output Buffer
Ordering Information
Ordering Code
Package Name
Package Type
W218
H
56-pin SSOP (300 mils)
Document #: 38-07221 Rev. *A
Page 14 of 17
W218
Layout Diagram
+2.5V Supply
FB
+3.3V Supply
FB
VDDQ2
VDDQ3
10 µF
0.005 µF C2
G
10 µF
C4 0.005
µ
F
C1
C3
G
G
G
G
1
G 56
G
V
2
3
4
55
G
G
G
54
53
V
G
5
52
V
G
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
51
G
50
49
48
G
G
V
G
G
47
V
46
G
G
V
G
45
G
44
43
42
41
40
39
38
37
G
G
G
G
V
G
G
G
V
G
G
21
22
23
24
25
26
27
28
36
35
34
33
32
31
30
29
Core
V
G
V
G
G
VDDQ3
10
Ω
PLL2
G
G
C5
C6
G
G
FB = Dale ILB1206 - 300 (300Ω @ 100 MHz)
µF
C5 = 47 µF
C6 = 0.1 µF
Ceramic Caps
µF C2 & C4 = 0.005
C1 & C3 = 10–22
G = VIA to GND plane layer
V =VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors
Document #: 38-07221 Rev. *A
Page 15 of 17
W218
Package Diagram
56-Pin Shrink Small Outline Package (SSOP, 300 mils)
Summary of nominal dimensions in inches:
Body Width: 0.296
Lead Pitch: 0.025
Body Length: 0.625
Body Height: 0.102
Document #: 38-07221 Rev. *A
Page 16 of 17
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
W218
Document Title: W218 FTG for Integrated Core Logic with 133-MHz FSB
Document Number: 38-07221
Issue
Orig. of
Change
REV.
**
*A
ECN NO. Date
Description of Change
110486
122838
10/21/01
12/21/02
SZV
RBI
Change from Spec number: 38-00885 to 38-07221
Add Power up Requirements to Electrical Characteristics Information
Document #: 38-07221 Rev. *A
Page 17 of 17
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