W48C55A-61GT [CYPRESS]
Processor Specific Clock Generator, 100MHz, CMOS, PDSO20, 0.300 INCH, PLASTIC, SOIC-20;
| 型号： | W48C55A-61GT |
| 厂家： | 
CYPRESS |
| 描述： | Processor Specific Clock Generator, 100MHz, CMOS, PDSO20, 0.300 INCH, PLASTIC, SOIC-20 光电二极管 |
| 文件： | 总8页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A
W48C54A/55A
Frequency Synthesizers
• Smooth frequency transition of CPU and 2XCPU
outputs
Features
• Proprietary crystal oscillator circuitry provides low
REFOUT jitter, excellent duty cycle
• Compatible with Intel X86 and other high-performance
processors
• Power-ondelayfeatureensuresfullV isreachedprior
• Up to eight outputs for CPU and peripherals
• Supports Green PC and notebook designs
• Custom options available with metal layer change
• High-performance, low-power CMOS
DD
to output activation
• 3.3V and 5V operation supported including the VRE
(Voltage Regulated Extended) specification for
Pentium® processor
• Available in 16- (150-mil) and 20-pin SOIC package
(300-mil)
• Pin and function compatible with AV9154/AV9155
• IntegralPLL loop filter components ensures stable PLL
operation in noisy system environment
Block Diagram
Pin Configurations
VDD
14.318 MHz
NC
X2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
Xtal
X1
X2
47.059MHz
NC
XTAL
X1
14.318 MHz
OSC
VDD
GND
NC
VDD
GND
REF(20MHz)
NC
Fixed
Outputs
PLL1
PLL2
32MHz
GND
PD
OE
2XCPU
CPU
FS0
X2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FS1
CPU
NC
FS2:0
X1
VDD
GND
40MHz
32MHz
GND
VDD
GND
REF(20MHz)
NC
OE
GND
OE
1.843MHz
X2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FS1
FS0
X1
CPU
VDD
GND
14.318MHz
PD
VDD
GND
24MHz
12MHz
GND
OE
1.843MHz
X2
1
2
20
19
18
17
16
15
14
13
12
11
FS0
FS1
X1
3
CPUCLK
2XCPUCLK
VDD
VDD
4
GND
16MHz
24MHz
12MHz
GND
0E
5
6
GND
7
14.318MHz
14.318MHz
PD
8
9
10
FS2
Intel and Pentium are registered trademarks of Intel Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
September 28 1999, rev. **
W48C54A/55A
Pin Definitions
Pin
Pin #
Pin #
-08
Pin #
-59
Pin #
-61
Pin Name
1.843MHz
12MHz
16MHz
REF
Type -05, -09
Pin Description
O
O
O
O
O
O
O
O
O
O
N/A
N/A
N/A
11
N/A
N/A
N/A
11
1
1
8
6
Fixed 1.843-MHz output for serial I/O clock application
Fixed 12-MHz output for keyboard clock application
Fixed 16-MHz output for APIC or bus clock application
7
N/A
11
13, 14 Fixed Reference output.
24MHz
32MHz
40MHz
47.059MHz
2XCPU
CPU
N/A
7
N/A
7
6
7
Fixed 24-MHz output for floppy drive or super I/O application
N/A
N/A
N/A
N/A
14
N/A
N/A
N/A
17
Fixed 32-MHz output for ISA or PCI bus clock application
Fixed 40-MHz output for SCSI clock application
Fixed 47.059-MHz output
6
N/A
15
N/A
N/A
15
N/A
N/A
2X Clock Output (refer to Frequency Selection table)
Clock Output (refer to Frequency Selection table)
No Connect
18
NC
10, 14
1, 6, 10,
14, 16
N/A
N/A
OE
PD
I
I
9
9
9
10
12
Output Enable, puts all outputs in high-impedance state
when LOW
N/A
N/A
10
Power Down input, puts device in power-down mode when
LOW
FS0
FS1
FS2
VDD
GND
X1
I
I
1
N/A
N/A
15
16
20
19
Frequency Selection input, LSB
Frequency Selection input
Frequency Selection input
Power supply connection
16
I
N/A
4, 13
N/A
N/A
4, 13
11
P
G
I
4, 13
4, 16
5, 8, 12 5, 8, 12 5, 8, 12 5, 9, 15 Ground connection
3
2
3
2
3
2
3
2
Crystal connection or external clock frequency input
X2
O
Crystal connection, leave unconnected when driving X1 with
external clock
2
W48C54A/55A
can best be used by power management systems where it is
frequently necessary to slow down the clock to conserve pow-
er. By controlling the rate of frequency transition, both devices
are designed to be compatible with Intel® cycle-to-cycle pro-
cessor timing specifications.
Overview
The W48C54A and W48C55A are general-purpose clock gen-
erator ICs. Some of the standard device options described in
this document are designed for PC motherboard and embed-
ded applications. Backward compatible with the W48C54 and
W48C55, these dual-PLL clock devices incorporate an im-
proved crystal oscillator as well as other refinements. On-chip
loop filter components ensure stable operation even with the
noise typical of a digital system. Device functionality, including
input/output options and frequency selection is determined by
a single metal mask that allows quick-turn customization ca-
pability. Both 3.3- and 5-volt operation are supported.
Power down capability is available in selected versions of the
W48C54A and W48C55A. When PD is active (LOW), the de-
vice is placed in a standby mode during which power dissipa-
tion is at its minimum; all clock outputs are forced LOW. Partial
power is also an available option, wherein selected outputs are
disabled or enabled according to a logic input.
Table 1. Frequency Selection for W48C54A
The improved crystal oscillator of the W48C54A and
W48C55A most notably provides improved duty cycle at the
reference output(s). With this new design, duty cycle is not
affected by varying operating conditions such as with the ad-
dition of external crystal load capacitors. Clock jitter from the
14.318-MHz output(s) is also improved, as is the crystal oscil-
lation frequency accuracy.
-05
-09
-59
FS1
0
FS0
0
CPU (MHz) CPU (MHz) CPU (MHz)
47.000
47.000
27.000
36.000
20
54.000
18.800
27.000
36.000
20
50.113
40.568
66.817
33.409
14.318
0
1
1
0
Like the W48C54 and W48C55, the W48C54A and W48C55A
have a unique power-on delay circuit. This feature allows com-
patibility with certain microprocessor devices that cannot with-
stand clock input toggling until full supply voltage is reached.
1
1
Input/REF
Upon application of power to the V pins, the W48C54A/55A
output clocks are delayed (held LOW) for approximately 15 ms,
after which they assume normal operation.
DD
Table 2. Frequency Selection for W48C55A
-61
2XCPU
(MHz)
CPU
Functional Description
FS2
0
FS1
0
FS0
0
(MHz)
The Functional Block Diagram shows the reference clock
source can be a crystal connected across the X1 and X2 input
pins, alternatively input clock connected to the X1 input pin. In
the latter case, the X2 pin is left open. With either source as
reference, both the W48C54A and W48C55A generate all nec-
essary clocks at their respective frequencies to drive the spec-
ified clocks. To provide the broadest possible range of frequen-
cies typically required for CPU mother-board designs, the
target frequencies can be selected via up to four select inputs.
Consult the appropriate tables for the clock selection range. In
addition, the W48C54A/55A can provide rebuffered reference
clock outputs.
8
16
4
8
0
0
1
0
1
0
32
16
0
1
1
40
20
1
0
0
50
25
1
0
1
66.66
80
33.33
40
1
1
0
[1]
[1]
1
1
1
100
50
Note:
1. Not guaranteed when VDD < 4.5V.
Both the W48C54A and W48C55A offer smooth transitions
when changing CPU/2XCPU output frequency. This feature
3
W48C54A/55A
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Parameter
Description
referenced to GND
Rating
7.0
Unit
V
V
V
DD
DD
T
Storage Temperature
Operating Temperature
V on I/O ref to GND
Power Dissipation
–40 to +150
0 to +70
°C
°C
V
STG
T
A
V
GND–5.0 to V +5.0
IN
D
DD
P
0.5
W
Electrical Characteristics
)
(0°C < T < 70°C, V = 5.0V±10%)
5.0V DC Characteristics
A
DD
Parameter Description
Test Condition
= 5.0V
Min
Typ
Max
Unit
V
V
Input Low Voltage
Input High Voltage
V
V
V
V
0.8
IL
DD
DD
V
= 5.0V
= 0V
2.0
V
IH
[2]
I
I
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Output High Voltage
–100
10
µA
µA
V
IL
IH
IN
IN
= V
DD
V
V
V
I
I
I
= 4 mA
0.4
OL
OH
OH
OL
OH
OH
= –1 mA, V =5V
V
V
–0.4
V
DD
DD
DD
= –4 mA, V =5V
–0.8
V
DD
[3]
I
Supply Current
No load
25
0.002
40
40
mA
%
DD
[4]
F
Output Frequency Change
Short Circuit Current
Over supply and temperature
Each output clock
0.01
D
I
25
mA
µA
SC
DDSTBY
I
Supply Current, Power
300
[5]
Down
C
C
R
Input Capacitance
Load Capacitance
Pull-up Resistor Value
Except pins X1, X2
Pins X1 and X2
Except X1, X2
10
pF
pF
kΩ
IN
L
20
250
P
Notes:
2. Includes pull-up resistor.
3. No output load capacitance, CPU or 2XCPU running at 50 MHz. Power supply current can change with different mask configuration.
4. Consideration of reference crystal shift only.
5. With full chip power-down pin LOW.
4
W48C54A/55A
(0°C < T < 70°C, V = 5.0V ±10%)
5.0V AC Characteristics
Parameter
A
DD
Description
Conditions
Min
Typ
Max
20
20
2
Unit
ns
T
Input Clock Rise Time
ICR
ICF
R
T
T
T
T
T
Input Clock Fall Time
ns
Output Rise Time, 0.8 to 2.0V
25-pF load
1
ns
Rise Time, 20% to 80% V
25-pF load
2
1
4
ns
R
DD
Output Fall Time, 2.0 to 0.8V
25-pF load
2
ns
F
Fall Time, 80% to 20% V
Duty Cycle, All Outputs
Jitter, Absolute
25-pF load
2
4
ns
F
DD
D
25-pF load
40/60
50/50
60/40
700
%
T
T
F
T
16–100 MHz clocks
ps
JAB
I
Input Frequency
14.318
40
MHz
ns
Clock Skew between CPU and
2XCPU outputs
1.0
50
SK
T
Frequency Transition Time
From 8–100 MHz
ms
FT
(0°C < T < 70°C, V = 3.3V±10%)
3.3V DC Characteristics
A
DD
Parameter Description
Test Condition
= 3.3V
Min
Typ
Max
0.15*V
DD
Unit
V
V
Input Low Voltage
Input High Voltage
V
IL
DD
DD
V
V
V
V
= 3.3V
= 0V
0.7*V
V
IH
DD
[2]
I
I
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
–100
10
µA
µA
V
IL
IH
IN
IN
= V
DD
V
I
I
= 4 mA
0.4
OL
OL
OH
V
= –4 mA, V =3.3V
2.4
25
V
OH
DD
[3]
I
Supply Current
No load
20
0.002
40
35
mA
%
DD
[4]
F
Output Frequency Change
Short Circuit Current
Input Capacitance
Over supply and temperature
Each output clock
Except pins X1, X2
Pins X1 and X2
0.01
D
I
mA
pF
pF
kΩ
SC
C
C
R
10
IN
L
Load Capacitance
20
Pull-up Resistor Value
Except X1, X2
250
P
(0°C < T < 70°C, V = 3.3V ±10%)
3.3V AC Characteristics
Parameter
A
DD
Description
Conditions
Min
Typ
Max
20
Unit
ns
T
T
T
T
Input Clock Rise Time
Input Clock Fall Time
Rise Time, 20% to 80% V
ICR
ICF
R
20
ns
15-pF load
2
2
4
ns
DD
Fall Time, 80% to 20% V
Duty Cycle, All Outputs
Jitter, Absolute
15-pF load
4
ns
F
DD
D
15-pF load
40/60
50/50
60/40
700
%
T
T
F
T
16–80 MHz clocks
ps
JAB
I
Input Frequency
14.318
40
MHz
ns
Clock Skew between CPU and
2XCPU outputs
1.0
50
SK
T
Frequency Transition Time
From 8–100 MHz
ms
FT
5
W48C54A/55A
V
decoupling is important to both reduce phase jitter and
Recommended Board Layout: W48C54A/55A
DD
EMI radiation. The 0.1-µF decoupling capacitors should be
For optimum performance in system applications, the power
supply decoupling scheme shown in Figure 1 should be used.
All GND pins are connected to the ground plane.
placed as close to the V pins as possible, otherwise the
increased trace inductance will negate its decoupling capabil-
ity. the 10-µF decoupling capacitor shown should be a tanta-
DD
lum type. For further EMI protection, the V
be made via a ferrite bead, as shown.
connection can
DD
V
DD
Optional
Ferrite Bead
10 µF
VDD
VDD
GND
0.1 µF
GND
GND
0.1 µF
Figure 1. Recommended Circuit Configuration
Ordering Information
Freq. Mask
Package
Name
Ordering Code
W48C54A
Code
05, 08, 09, 59
61
Package Type
G
G
16-pin Plastic SOIC (150-mil)
20-pin Plastic SOIC (300-mil)
W48C55A
Document #: 38-00803
6
W48C54A/55A
Package Diagrams
20-Pin Small Outline Integrated Circuit (SOIC, 300-mil)
7
W48C54A/55A
Package Diagrams (continued)
16-Pin Small Outline Integrated Circuit (SOIC, 150-mil)
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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